1 /* 2 * Copyright (C) 2012 Samsung Electronics Co.Ltd 3 * Authors: 4 * Eunchul Kim <chulspro.kim@samsung.com> 5 * Jinyoung Jeon <jy0.jeon@samsung.com> 6 * Sangmin Lee <lsmin.lee@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/clk.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/of_device.h> 21 #include <linux/regmap.h> 22 23 #include <drm/drmP.h> 24 #include <drm/exynos_drm.h> 25 #include "regs-gsc.h" 26 #include "exynos_drm_drv.h" 27 #include "exynos_drm_iommu.h" 28 #include "exynos_drm_ipp.h" 29 30 /* 31 * GSC stands for General SCaler and 32 * supports image scaler/rotator and input/output DMA operations. 33 * input DMA reads image data from the memory. 34 * output DMA writes image data to memory. 35 * GSC supports image rotation and image effect functions. 36 */ 37 38 39 #define GSC_MAX_CLOCKS 8 40 #define GSC_MAX_SRC 4 41 #define GSC_MAX_DST 16 42 #define GSC_RESET_TIMEOUT 50 43 #define GSC_BUF_STOP 1 44 #define GSC_BUF_START 2 45 #define GSC_REG_SZ 16 46 #define GSC_WIDTH_ITU_709 1280 47 #define GSC_SC_UP_MAX_RATIO 65536 48 #define GSC_SC_DOWN_RATIO_7_8 74898 49 #define GSC_SC_DOWN_RATIO_6_8 87381 50 #define GSC_SC_DOWN_RATIO_5_8 104857 51 #define GSC_SC_DOWN_RATIO_4_8 131072 52 #define GSC_SC_DOWN_RATIO_3_8 174762 53 #define GSC_SC_DOWN_RATIO_2_8 262144 54 #define GSC_CROP_MAX 8192 55 #define GSC_CROP_MIN 32 56 #define GSC_SCALE_MAX 4224 57 #define GSC_SCALE_MIN 32 58 #define GSC_COEF_RATIO 7 59 #define GSC_COEF_PHASE 9 60 #define GSC_COEF_ATTR 16 61 #define GSC_COEF_H_8T 8 62 #define GSC_COEF_V_4T 4 63 #define GSC_COEF_DEPTH 3 64 #define GSC_AUTOSUSPEND_DELAY 2000 65 66 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev)) 67 #define gsc_read(offset) readl(ctx->regs + (offset)) 68 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) 69 70 /* 71 * A structure of scaler. 72 * 73 * @range: narrow, wide. 74 * @pre_shfactor: pre sclaer shift factor. 75 * @pre_hratio: horizontal ratio of the prescaler. 76 * @pre_vratio: vertical ratio of the prescaler. 77 * @main_hratio: the main scaler's horizontal ratio. 78 * @main_vratio: the main scaler's vertical ratio. 79 */ 80 struct gsc_scaler { 81 bool range; 82 u32 pre_shfactor; 83 u32 pre_hratio; 84 u32 pre_vratio; 85 unsigned long main_hratio; 86 unsigned long main_vratio; 87 }; 88 89 /* 90 * A structure of gsc context. 91 * 92 * @regs_res: register resources. 93 * @regs: memory mapped io registers. 94 * @gsc_clk: gsc gate clock. 95 * @sc: scaler infomations. 96 * @id: gsc id. 97 * @irq: irq number. 98 * @rotation: supports rotation of src. 99 */ 100 struct gsc_context { 101 struct exynos_drm_ipp ipp; 102 struct drm_device *drm_dev; 103 struct device *dev; 104 struct exynos_drm_ipp_task *task; 105 struct exynos_drm_ipp_formats *formats; 106 unsigned int num_formats; 107 108 struct resource *regs_res; 109 void __iomem *regs; 110 const char **clk_names; 111 struct clk *clocks[GSC_MAX_CLOCKS]; 112 int num_clocks; 113 struct gsc_scaler sc; 114 int id; 115 int irq; 116 bool rotation; 117 }; 118 119 /** 120 * struct gsc_driverdata - per device type driver data for init time. 121 * 122 * @limits: picture size limits array 123 * @clk_names: names of clocks needed by this variant 124 * @num_clocks: the number of clocks needed by this variant 125 */ 126 struct gsc_driverdata { 127 const struct drm_exynos_ipp_limit *limits; 128 int num_limits; 129 const char *clk_names[GSC_MAX_CLOCKS]; 130 int num_clocks; 131 }; 132 133 /* 8-tap Filter Coefficient */ 134 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = { 135 { /* Ratio <= 65536 (~8:8) */ 136 { 0, 0, 0, 128, 0, 0, 0, 0 }, 137 { -1, 2, -6, 127, 7, -2, 1, 0 }, 138 { -1, 4, -12, 125, 16, -5, 1, 0 }, 139 { -1, 5, -15, 120, 25, -8, 2, 0 }, 140 { -1, 6, -18, 114, 35, -10, 3, -1 }, 141 { -1, 6, -20, 107, 46, -13, 4, -1 }, 142 { -2, 7, -21, 99, 57, -16, 5, -1 }, 143 { -1, 6, -20, 89, 68, -18, 5, -1 }, 144 { -1, 6, -20, 79, 79, -20, 6, -1 }, 145 { -1, 5, -18, 68, 89, -20, 6, -1 }, 146 { -1, 5, -16, 57, 99, -21, 7, -2 }, 147 { -1, 4, -13, 46, 107, -20, 6, -1 }, 148 { -1, 3, -10, 35, 114, -18, 6, -1 }, 149 { 0, 2, -8, 25, 120, -15, 5, -1 }, 150 { 0, 1, -5, 16, 125, -12, 4, -1 }, 151 { 0, 1, -2, 7, 127, -6, 2, -1 } 152 }, { /* 65536 < Ratio <= 74898 (~8:7) */ 153 { 3, -8, 14, 111, 13, -8, 3, 0 }, 154 { 2, -6, 7, 112, 21, -10, 3, -1 }, 155 { 2, -4, 1, 110, 28, -12, 4, -1 }, 156 { 1, -2, -3, 106, 36, -13, 4, -1 }, 157 { 1, -1, -7, 103, 44, -15, 4, -1 }, 158 { 1, 1, -11, 97, 53, -16, 4, -1 }, 159 { 0, 2, -13, 91, 61, -16, 4, -1 }, 160 { 0, 3, -15, 85, 69, -17, 4, -1 }, 161 { 0, 3, -16, 77, 77, -16, 3, 0 }, 162 { -1, 4, -17, 69, 85, -15, 3, 0 }, 163 { -1, 4, -16, 61, 91, -13, 2, 0 }, 164 { -1, 4, -16, 53, 97, -11, 1, 1 }, 165 { -1, 4, -15, 44, 103, -7, -1, 1 }, 166 { -1, 4, -13, 36, 106, -3, -2, 1 }, 167 { -1, 4, -12, 28, 110, 1, -4, 2 }, 168 { -1, 3, -10, 21, 112, 7, -6, 2 } 169 }, { /* 74898 < Ratio <= 87381 (~8:6) */ 170 { 2, -11, 25, 96, 25, -11, 2, 0 }, 171 { 2, -10, 19, 96, 31, -12, 2, 0 }, 172 { 2, -9, 14, 94, 37, -12, 2, 0 }, 173 { 2, -8, 10, 92, 43, -12, 1, 0 }, 174 { 2, -7, 5, 90, 49, -12, 1, 0 }, 175 { 2, -5, 1, 86, 55, -12, 0, 1 }, 176 { 2, -4, -2, 82, 61, -11, -1, 1 }, 177 { 1, -3, -5, 77, 67, -9, -1, 1 }, 178 { 1, -2, -7, 72, 72, -7, -2, 1 }, 179 { 1, -1, -9, 67, 77, -5, -3, 1 }, 180 { 1, -1, -11, 61, 82, -2, -4, 2 }, 181 { 1, 0, -12, 55, 86, 1, -5, 2 }, 182 { 0, 1, -12, 49, 90, 5, -7, 2 }, 183 { 0, 1, -12, 43, 92, 10, -8, 2 }, 184 { 0, 2, -12, 37, 94, 14, -9, 2 }, 185 { 0, 2, -12, 31, 96, 19, -10, 2 } 186 }, { /* 87381 < Ratio <= 104857 (~8:5) */ 187 { -1, -8, 33, 80, 33, -8, -1, 0 }, 188 { -1, -8, 28, 80, 37, -7, -2, 1 }, 189 { 0, -8, 24, 79, 41, -7, -2, 1 }, 190 { 0, -8, 20, 78, 46, -6, -3, 1 }, 191 { 0, -8, 16, 76, 50, -4, -3, 1 }, 192 { 0, -7, 13, 74, 54, -3, -4, 1 }, 193 { 1, -7, 10, 71, 58, -1, -5, 1 }, 194 { 1, -6, 6, 68, 62, 1, -5, 1 }, 195 { 1, -6, 4, 65, 65, 4, -6, 1 }, 196 { 1, -5, 1, 62, 68, 6, -6, 1 }, 197 { 1, -5, -1, 58, 71, 10, -7, 1 }, 198 { 1, -4, -3, 54, 74, 13, -7, 0 }, 199 { 1, -3, -4, 50, 76, 16, -8, 0 }, 200 { 1, -3, -6, 46, 78, 20, -8, 0 }, 201 { 1, -2, -7, 41, 79, 24, -8, 0 }, 202 { 1, -2, -7, 37, 80, 28, -8, -1 } 203 }, { /* 104857 < Ratio <= 131072 (~8:4) */ 204 { -3, 0, 35, 64, 35, 0, -3, 0 }, 205 { -3, -1, 32, 64, 38, 1, -3, 0 }, 206 { -2, -2, 29, 63, 41, 2, -3, 0 }, 207 { -2, -3, 27, 63, 43, 4, -4, 0 }, 208 { -2, -3, 24, 61, 46, 6, -4, 0 }, 209 { -2, -3, 21, 60, 49, 7, -4, 0 }, 210 { -1, -4, 19, 59, 51, 9, -4, -1 }, 211 { -1, -4, 16, 57, 53, 12, -4, -1 }, 212 { -1, -4, 14, 55, 55, 14, -4, -1 }, 213 { -1, -4, 12, 53, 57, 16, -4, -1 }, 214 { -1, -4, 9, 51, 59, 19, -4, -1 }, 215 { 0, -4, 7, 49, 60, 21, -3, -2 }, 216 { 0, -4, 6, 46, 61, 24, -3, -2 }, 217 { 0, -4, 4, 43, 63, 27, -3, -2 }, 218 { 0, -3, 2, 41, 63, 29, -2, -2 }, 219 { 0, -3, 1, 38, 64, 32, -1, -3 } 220 }, { /* 131072 < Ratio <= 174762 (~8:3) */ 221 { -1, 8, 33, 48, 33, 8, -1, 0 }, 222 { -1, 7, 31, 49, 35, 9, -1, -1 }, 223 { -1, 6, 30, 49, 36, 10, -1, -1 }, 224 { -1, 5, 28, 48, 38, 12, -1, -1 }, 225 { -1, 4, 26, 48, 39, 13, 0, -1 }, 226 { -1, 3, 24, 47, 41, 15, 0, -1 }, 227 { -1, 2, 23, 47, 42, 16, 0, -1 }, 228 { -1, 2, 21, 45, 43, 18, 1, -1 }, 229 { -1, 1, 19, 45, 45, 19, 1, -1 }, 230 { -1, 1, 18, 43, 45, 21, 2, -1 }, 231 { -1, 0, 16, 42, 47, 23, 2, -1 }, 232 { -1, 0, 15, 41, 47, 24, 3, -1 }, 233 { -1, 0, 13, 39, 48, 26, 4, -1 }, 234 { -1, -1, 12, 38, 48, 28, 5, -1 }, 235 { -1, -1, 10, 36, 49, 30, 6, -1 }, 236 { -1, -1, 9, 35, 49, 31, 7, -1 } 237 }, { /* 174762 < Ratio <= 262144 (~8:2) */ 238 { 2, 13, 30, 38, 30, 13, 2, 0 }, 239 { 2, 12, 29, 38, 30, 14, 3, 0 }, 240 { 2, 11, 28, 38, 31, 15, 3, 0 }, 241 { 2, 10, 26, 38, 32, 16, 4, 0 }, 242 { 1, 10, 26, 37, 33, 17, 4, 0 }, 243 { 1, 9, 24, 37, 34, 18, 5, 0 }, 244 { 1, 8, 24, 37, 34, 19, 5, 0 }, 245 { 1, 7, 22, 36, 35, 20, 6, 1 }, 246 { 1, 6, 21, 36, 36, 21, 6, 1 }, 247 { 1, 6, 20, 35, 36, 22, 7, 1 }, 248 { 0, 5, 19, 34, 37, 24, 8, 1 }, 249 { 0, 5, 18, 34, 37, 24, 9, 1 }, 250 { 0, 4, 17, 33, 37, 26, 10, 1 }, 251 { 0, 4, 16, 32, 38, 26, 10, 2 }, 252 { 0, 3, 15, 31, 38, 28, 11, 2 }, 253 { 0, 3, 14, 30, 38, 29, 12, 2 } 254 } 255 }; 256 257 /* 4-tap Filter Coefficient */ 258 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = { 259 { /* Ratio <= 65536 (~8:8) */ 260 { 0, 128, 0, 0 }, 261 { -4, 127, 5, 0 }, 262 { -6, 124, 11, -1 }, 263 { -8, 118, 19, -1 }, 264 { -8, 111, 27, -2 }, 265 { -8, 102, 37, -3 }, 266 { -8, 92, 48, -4 }, 267 { -7, 81, 59, -5 }, 268 { -6, 70, 70, -6 }, 269 { -5, 59, 81, -7 }, 270 { -4, 48, 92, -8 }, 271 { -3, 37, 102, -8 }, 272 { -2, 27, 111, -8 }, 273 { -1, 19, 118, -8 }, 274 { -1, 11, 124, -6 }, 275 { 0, 5, 127, -4 } 276 }, { /* 65536 < Ratio <= 74898 (~8:7) */ 277 { 8, 112, 8, 0 }, 278 { 4, 111, 14, -1 }, 279 { 1, 109, 20, -2 }, 280 { -2, 105, 27, -2 }, 281 { -3, 100, 34, -3 }, 282 { -5, 93, 43, -3 }, 283 { -5, 86, 51, -4 }, 284 { -5, 77, 60, -4 }, 285 { -5, 69, 69, -5 }, 286 { -4, 60, 77, -5 }, 287 { -4, 51, 86, -5 }, 288 { -3, 43, 93, -5 }, 289 { -3, 34, 100, -3 }, 290 { -2, 27, 105, -2 }, 291 { -2, 20, 109, 1 }, 292 { -1, 14, 111, 4 } 293 }, { /* 74898 < Ratio <= 87381 (~8:6) */ 294 { 16, 96, 16, 0 }, 295 { 12, 97, 21, -2 }, 296 { 8, 96, 26, -2 }, 297 { 5, 93, 32, -2 }, 298 { 2, 89, 39, -2 }, 299 { 0, 84, 46, -2 }, 300 { -1, 79, 53, -3 }, 301 { -2, 73, 59, -2 }, 302 { -2, 66, 66, -2 }, 303 { -2, 59, 73, -2 }, 304 { -3, 53, 79, -1 }, 305 { -2, 46, 84, 0 }, 306 { -2, 39, 89, 2 }, 307 { -2, 32, 93, 5 }, 308 { -2, 26, 96, 8 }, 309 { -2, 21, 97, 12 } 310 }, { /* 87381 < Ratio <= 104857 (~8:5) */ 311 { 22, 84, 22, 0 }, 312 { 18, 85, 26, -1 }, 313 { 14, 84, 31, -1 }, 314 { 11, 82, 36, -1 }, 315 { 8, 79, 42, -1 }, 316 { 6, 76, 47, -1 }, 317 { 4, 72, 52, 0 }, 318 { 2, 68, 58, 0 }, 319 { 1, 63, 63, 1 }, 320 { 0, 58, 68, 2 }, 321 { 0, 52, 72, 4 }, 322 { -1, 47, 76, 6 }, 323 { -1, 42, 79, 8 }, 324 { -1, 36, 82, 11 }, 325 { -1, 31, 84, 14 }, 326 { -1, 26, 85, 18 } 327 }, { /* 104857 < Ratio <= 131072 (~8:4) */ 328 { 26, 76, 26, 0 }, 329 { 22, 76, 30, 0 }, 330 { 19, 75, 34, 0 }, 331 { 16, 73, 38, 1 }, 332 { 13, 71, 43, 1 }, 333 { 10, 69, 47, 2 }, 334 { 8, 66, 51, 3 }, 335 { 6, 63, 55, 4 }, 336 { 5, 59, 59, 5 }, 337 { 4, 55, 63, 6 }, 338 { 3, 51, 66, 8 }, 339 { 2, 47, 69, 10 }, 340 { 1, 43, 71, 13 }, 341 { 1, 38, 73, 16 }, 342 { 0, 34, 75, 19 }, 343 { 0, 30, 76, 22 } 344 }, { /* 131072 < Ratio <= 174762 (~8:3) */ 345 { 29, 70, 29, 0 }, 346 { 26, 68, 32, 2 }, 347 { 23, 67, 36, 2 }, 348 { 20, 66, 39, 3 }, 349 { 17, 65, 43, 3 }, 350 { 15, 63, 46, 4 }, 351 { 12, 61, 50, 5 }, 352 { 10, 58, 53, 7 }, 353 { 8, 56, 56, 8 }, 354 { 7, 53, 58, 10 }, 355 { 5, 50, 61, 12 }, 356 { 4, 46, 63, 15 }, 357 { 3, 43, 65, 17 }, 358 { 3, 39, 66, 20 }, 359 { 2, 36, 67, 23 }, 360 { 2, 32, 68, 26 } 361 }, { /* 174762 < Ratio <= 262144 (~8:2) */ 362 { 32, 64, 32, 0 }, 363 { 28, 63, 34, 3 }, 364 { 25, 62, 37, 4 }, 365 { 22, 62, 40, 4 }, 366 { 19, 61, 43, 5 }, 367 { 17, 59, 46, 6 }, 368 { 15, 58, 48, 7 }, 369 { 13, 55, 51, 9 }, 370 { 11, 53, 53, 11 }, 371 { 9, 51, 55, 13 }, 372 { 7, 48, 58, 15 }, 373 { 6, 46, 59, 17 }, 374 { 5, 43, 61, 19 }, 375 { 4, 40, 62, 22 }, 376 { 4, 37, 62, 25 }, 377 { 3, 34, 63, 28 } 378 } 379 }; 380 381 static int gsc_sw_reset(struct gsc_context *ctx) 382 { 383 u32 cfg; 384 int count = GSC_RESET_TIMEOUT; 385 386 /* s/w reset */ 387 cfg = (GSC_SW_RESET_SRESET); 388 gsc_write(cfg, GSC_SW_RESET); 389 390 /* wait s/w reset complete */ 391 while (count--) { 392 cfg = gsc_read(GSC_SW_RESET); 393 if (!cfg) 394 break; 395 usleep_range(1000, 2000); 396 } 397 398 if (cfg) { 399 DRM_ERROR("failed to reset gsc h/w.\n"); 400 return -EBUSY; 401 } 402 403 /* reset sequence */ 404 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); 405 cfg |= (GSC_IN_BASE_ADDR_MASK | 406 GSC_IN_BASE_ADDR_PINGPONG(0)); 407 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); 408 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); 409 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); 410 411 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 412 cfg |= (GSC_OUT_BASE_ADDR_MASK | 413 GSC_OUT_BASE_ADDR_PINGPONG(0)); 414 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); 415 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); 416 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); 417 418 return 0; 419 } 420 421 static void gsc_handle_irq(struct gsc_context *ctx, bool enable, 422 bool overflow, bool done) 423 { 424 u32 cfg; 425 426 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", 427 enable, overflow, done); 428 429 cfg = gsc_read(GSC_IRQ); 430 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK); 431 432 if (enable) 433 cfg |= GSC_IRQ_ENABLE; 434 else 435 cfg &= ~GSC_IRQ_ENABLE; 436 437 if (overflow) 438 cfg &= ~GSC_IRQ_OR_MASK; 439 else 440 cfg |= GSC_IRQ_OR_MASK; 441 442 if (done) 443 cfg &= ~GSC_IRQ_FRMDONE_MASK; 444 else 445 cfg |= GSC_IRQ_FRMDONE_MASK; 446 447 gsc_write(cfg, GSC_IRQ); 448 } 449 450 451 static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt) 452 { 453 u32 cfg; 454 455 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 456 457 cfg = gsc_read(GSC_IN_CON); 458 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK | 459 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK | 460 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE | 461 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK); 462 463 switch (fmt) { 464 case DRM_FORMAT_RGB565: 465 cfg |= GSC_IN_RGB565; 466 break; 467 case DRM_FORMAT_XRGB8888: 468 case DRM_FORMAT_ARGB8888: 469 cfg |= GSC_IN_XRGB8888; 470 break; 471 case DRM_FORMAT_BGRX8888: 472 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP); 473 break; 474 case DRM_FORMAT_YUYV: 475 cfg |= (GSC_IN_YUV422_1P | 476 GSC_IN_YUV422_1P_ORDER_LSB_Y | 477 GSC_IN_CHROMA_ORDER_CBCR); 478 break; 479 case DRM_FORMAT_YVYU: 480 cfg |= (GSC_IN_YUV422_1P | 481 GSC_IN_YUV422_1P_ORDER_LSB_Y | 482 GSC_IN_CHROMA_ORDER_CRCB); 483 break; 484 case DRM_FORMAT_UYVY: 485 cfg |= (GSC_IN_YUV422_1P | 486 GSC_IN_YUV422_1P_OEDER_LSB_C | 487 GSC_IN_CHROMA_ORDER_CBCR); 488 break; 489 case DRM_FORMAT_VYUY: 490 cfg |= (GSC_IN_YUV422_1P | 491 GSC_IN_YUV422_1P_OEDER_LSB_C | 492 GSC_IN_CHROMA_ORDER_CRCB); 493 break; 494 case DRM_FORMAT_NV21: 495 case DRM_FORMAT_NV61: 496 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | 497 GSC_IN_YUV420_2P); 498 break; 499 case DRM_FORMAT_YUV422: 500 cfg |= GSC_IN_YUV422_3P; 501 break; 502 case DRM_FORMAT_YUV420: 503 case DRM_FORMAT_YVU420: 504 cfg |= GSC_IN_YUV420_3P; 505 break; 506 case DRM_FORMAT_NV12: 507 case DRM_FORMAT_NV16: 508 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | 509 GSC_IN_YUV420_2P); 510 break; 511 } 512 513 gsc_write(cfg, GSC_IN_CON); 514 } 515 516 static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation) 517 { 518 unsigned int degree = rotation & DRM_MODE_ROTATE_MASK; 519 u32 cfg; 520 521 cfg = gsc_read(GSC_IN_CON); 522 cfg &= ~GSC_IN_ROT_MASK; 523 524 switch (degree) { 525 case DRM_MODE_ROTATE_0: 526 if (rotation & DRM_MODE_REFLECT_Y) 527 cfg |= GSC_IN_ROT_XFLIP; 528 if (rotation & DRM_MODE_REFLECT_X) 529 cfg |= GSC_IN_ROT_YFLIP; 530 break; 531 case DRM_MODE_ROTATE_90: 532 cfg |= GSC_IN_ROT_90; 533 if (rotation & DRM_MODE_REFLECT_Y) 534 cfg |= GSC_IN_ROT_XFLIP; 535 if (rotation & DRM_MODE_REFLECT_X) 536 cfg |= GSC_IN_ROT_YFLIP; 537 break; 538 case DRM_MODE_ROTATE_180: 539 cfg |= GSC_IN_ROT_180; 540 if (rotation & DRM_MODE_REFLECT_Y) 541 cfg &= ~GSC_IN_ROT_XFLIP; 542 if (rotation & DRM_MODE_REFLECT_X) 543 cfg &= ~GSC_IN_ROT_YFLIP; 544 break; 545 case DRM_MODE_ROTATE_270: 546 cfg |= GSC_IN_ROT_270; 547 if (rotation & DRM_MODE_REFLECT_Y) 548 cfg &= ~GSC_IN_ROT_XFLIP; 549 if (rotation & DRM_MODE_REFLECT_X) 550 cfg &= ~GSC_IN_ROT_YFLIP; 551 break; 552 } 553 554 gsc_write(cfg, GSC_IN_CON); 555 556 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; 557 } 558 559 static void gsc_src_set_size(struct gsc_context *ctx, 560 struct exynos_drm_ipp_buffer *buf) 561 { 562 struct gsc_scaler *sc = &ctx->sc; 563 u32 cfg; 564 565 /* pixel offset */ 566 cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) | 567 GSC_SRCIMG_OFFSET_Y(buf->rect.y)); 568 gsc_write(cfg, GSC_SRCIMG_OFFSET); 569 570 /* cropped size */ 571 cfg = (GSC_CROPPED_WIDTH(buf->rect.w) | 572 GSC_CROPPED_HEIGHT(buf->rect.h)); 573 gsc_write(cfg, GSC_CROPPED_SIZE); 574 575 /* original size */ 576 cfg = gsc_read(GSC_SRCIMG_SIZE); 577 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK | 578 GSC_SRCIMG_WIDTH_MASK); 579 580 cfg |= (GSC_SRCIMG_WIDTH(buf->buf.width) | 581 GSC_SRCIMG_HEIGHT(buf->buf.height)); 582 583 gsc_write(cfg, GSC_SRCIMG_SIZE); 584 585 cfg = gsc_read(GSC_IN_CON); 586 cfg &= ~GSC_IN_RGB_TYPE_MASK; 587 588 if (buf->rect.w >= GSC_WIDTH_ITU_709) 589 if (sc->range) 590 cfg |= GSC_IN_RGB_HD_WIDE; 591 else 592 cfg |= GSC_IN_RGB_HD_NARROW; 593 else 594 if (sc->range) 595 cfg |= GSC_IN_RGB_SD_WIDE; 596 else 597 cfg |= GSC_IN_RGB_SD_NARROW; 598 599 gsc_write(cfg, GSC_IN_CON); 600 } 601 602 static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id, 603 bool enqueue) 604 { 605 bool masked = !enqueue; 606 u32 cfg; 607 u32 mask = 0x00000001 << buf_id; 608 609 /* mask register set */ 610 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); 611 612 /* sequence id */ 613 cfg &= ~mask; 614 cfg |= masked << buf_id; 615 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); 616 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); 617 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); 618 } 619 620 static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id, 621 struct exynos_drm_ipp_buffer *buf) 622 { 623 /* address register set */ 624 gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id)); 625 gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id)); 626 gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id)); 627 628 gsc_src_set_buf_seq(ctx, buf_id, true); 629 } 630 631 static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt) 632 { 633 u32 cfg; 634 635 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 636 637 cfg = gsc_read(GSC_OUT_CON); 638 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK | 639 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK | 640 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK | 641 GSC_OUT_GLOBAL_ALPHA_MASK); 642 643 switch (fmt) { 644 case DRM_FORMAT_RGB565: 645 cfg |= GSC_OUT_RGB565; 646 break; 647 case DRM_FORMAT_ARGB8888: 648 case DRM_FORMAT_XRGB8888: 649 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff)); 650 break; 651 case DRM_FORMAT_BGRX8888: 652 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP); 653 break; 654 case DRM_FORMAT_YUYV: 655 cfg |= (GSC_OUT_YUV422_1P | 656 GSC_OUT_YUV422_1P_ORDER_LSB_Y | 657 GSC_OUT_CHROMA_ORDER_CBCR); 658 break; 659 case DRM_FORMAT_YVYU: 660 cfg |= (GSC_OUT_YUV422_1P | 661 GSC_OUT_YUV422_1P_ORDER_LSB_Y | 662 GSC_OUT_CHROMA_ORDER_CRCB); 663 break; 664 case DRM_FORMAT_UYVY: 665 cfg |= (GSC_OUT_YUV422_1P | 666 GSC_OUT_YUV422_1P_OEDER_LSB_C | 667 GSC_OUT_CHROMA_ORDER_CBCR); 668 break; 669 case DRM_FORMAT_VYUY: 670 cfg |= (GSC_OUT_YUV422_1P | 671 GSC_OUT_YUV422_1P_OEDER_LSB_C | 672 GSC_OUT_CHROMA_ORDER_CRCB); 673 break; 674 case DRM_FORMAT_NV21: 675 case DRM_FORMAT_NV61: 676 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P); 677 break; 678 case DRM_FORMAT_YUV422: 679 case DRM_FORMAT_YUV420: 680 case DRM_FORMAT_YVU420: 681 cfg |= GSC_OUT_YUV420_3P; 682 break; 683 case DRM_FORMAT_NV12: 684 case DRM_FORMAT_NV16: 685 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | 686 GSC_OUT_YUV420_2P); 687 break; 688 } 689 690 gsc_write(cfg, GSC_OUT_CON); 691 } 692 693 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio) 694 { 695 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst); 696 697 if (src >= dst * 8) { 698 DRM_ERROR("failed to make ratio and shift.\n"); 699 return -EINVAL; 700 } else if (src >= dst * 4) 701 *ratio = 4; 702 else if (src >= dst * 2) 703 *ratio = 2; 704 else 705 *ratio = 1; 706 707 return 0; 708 } 709 710 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor) 711 { 712 if (hratio == 4 && vratio == 4) 713 *shfactor = 4; 714 else if ((hratio == 4 && vratio == 2) || 715 (hratio == 2 && vratio == 4)) 716 *shfactor = 3; 717 else if ((hratio == 4 && vratio == 1) || 718 (hratio == 1 && vratio == 4) || 719 (hratio == 2 && vratio == 2)) 720 *shfactor = 2; 721 else if (hratio == 1 && vratio == 1) 722 *shfactor = 0; 723 else 724 *shfactor = 1; 725 } 726 727 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc, 728 struct drm_exynos_ipp_task_rect *src, 729 struct drm_exynos_ipp_task_rect *dst) 730 { 731 u32 cfg; 732 u32 src_w, src_h, dst_w, dst_h; 733 int ret = 0; 734 735 src_w = src->w; 736 src_h = src->h; 737 738 if (ctx->rotation) { 739 dst_w = dst->h; 740 dst_h = dst->w; 741 } else { 742 dst_w = dst->w; 743 dst_h = dst->h; 744 } 745 746 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio); 747 if (ret) { 748 dev_err(ctx->dev, "failed to get ratio horizontal.\n"); 749 return ret; 750 } 751 752 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio); 753 if (ret) { 754 dev_err(ctx->dev, "failed to get ratio vertical.\n"); 755 return ret; 756 } 757 758 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n", 759 sc->pre_hratio, sc->pre_vratio); 760 761 sc->main_hratio = (src_w << 16) / dst_w; 762 sc->main_vratio = (src_h << 16) / dst_h; 763 764 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", 765 sc->main_hratio, sc->main_vratio); 766 767 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio, 768 &sc->pre_shfactor); 769 770 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor); 771 772 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) | 773 GSC_PRESC_H_RATIO(sc->pre_hratio) | 774 GSC_PRESC_V_RATIO(sc->pre_vratio)); 775 gsc_write(cfg, GSC_PRE_SCALE_RATIO); 776 777 return ret; 778 } 779 780 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio) 781 { 782 int i, j, k, sc_ratio; 783 784 if (main_hratio <= GSC_SC_UP_MAX_RATIO) 785 sc_ratio = 0; 786 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8) 787 sc_ratio = 1; 788 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8) 789 sc_ratio = 2; 790 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8) 791 sc_ratio = 3; 792 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8) 793 sc_ratio = 4; 794 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8) 795 sc_ratio = 5; 796 else 797 sc_ratio = 6; 798 799 for (i = 0; i < GSC_COEF_PHASE; i++) 800 for (j = 0; j < GSC_COEF_H_8T; j++) 801 for (k = 0; k < GSC_COEF_DEPTH; k++) 802 gsc_write(h_coef_8t[sc_ratio][i][j], 803 GSC_HCOEF(i, j, k)); 804 } 805 806 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio) 807 { 808 int i, j, k, sc_ratio; 809 810 if (main_vratio <= GSC_SC_UP_MAX_RATIO) 811 sc_ratio = 0; 812 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8) 813 sc_ratio = 1; 814 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8) 815 sc_ratio = 2; 816 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8) 817 sc_ratio = 3; 818 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8) 819 sc_ratio = 4; 820 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8) 821 sc_ratio = 5; 822 else 823 sc_ratio = 6; 824 825 for (i = 0; i < GSC_COEF_PHASE; i++) 826 for (j = 0; j < GSC_COEF_V_4T; j++) 827 for (k = 0; k < GSC_COEF_DEPTH; k++) 828 gsc_write(v_coef_4t[sc_ratio][i][j], 829 GSC_VCOEF(i, j, k)); 830 } 831 832 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc) 833 { 834 u32 cfg; 835 836 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", 837 sc->main_hratio, sc->main_vratio); 838 839 gsc_set_h_coef(ctx, sc->main_hratio); 840 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio); 841 gsc_write(cfg, GSC_MAIN_H_RATIO); 842 843 gsc_set_v_coef(ctx, sc->main_vratio); 844 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio); 845 gsc_write(cfg, GSC_MAIN_V_RATIO); 846 } 847 848 static void gsc_dst_set_size(struct gsc_context *ctx, 849 struct exynos_drm_ipp_buffer *buf) 850 { 851 struct gsc_scaler *sc = &ctx->sc; 852 u32 cfg; 853 854 /* pixel offset */ 855 cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) | 856 GSC_DSTIMG_OFFSET_Y(buf->rect.y)); 857 gsc_write(cfg, GSC_DSTIMG_OFFSET); 858 859 /* scaled size */ 860 if (ctx->rotation) 861 cfg = (GSC_SCALED_WIDTH(buf->rect.h) | 862 GSC_SCALED_HEIGHT(buf->rect.w)); 863 else 864 cfg = (GSC_SCALED_WIDTH(buf->rect.w) | 865 GSC_SCALED_HEIGHT(buf->rect.h)); 866 gsc_write(cfg, GSC_SCALED_SIZE); 867 868 /* original size */ 869 cfg = gsc_read(GSC_DSTIMG_SIZE); 870 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK); 871 cfg |= GSC_DSTIMG_WIDTH(buf->buf.width) | 872 GSC_DSTIMG_HEIGHT(buf->buf.height); 873 gsc_write(cfg, GSC_DSTIMG_SIZE); 874 875 cfg = gsc_read(GSC_OUT_CON); 876 cfg &= ~GSC_OUT_RGB_TYPE_MASK; 877 878 if (buf->rect.w >= GSC_WIDTH_ITU_709) 879 if (sc->range) 880 cfg |= GSC_OUT_RGB_HD_WIDE; 881 else 882 cfg |= GSC_OUT_RGB_HD_NARROW; 883 else 884 if (sc->range) 885 cfg |= GSC_OUT_RGB_SD_WIDE; 886 else 887 cfg |= GSC_OUT_RGB_SD_NARROW; 888 889 gsc_write(cfg, GSC_OUT_CON); 890 } 891 892 static int gsc_dst_get_buf_seq(struct gsc_context *ctx) 893 { 894 u32 cfg, i, buf_num = GSC_REG_SZ; 895 u32 mask = 0x00000001; 896 897 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 898 899 for (i = 0; i < GSC_REG_SZ; i++) 900 if (cfg & (mask << i)) 901 buf_num--; 902 903 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); 904 905 return buf_num; 906 } 907 908 static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id, 909 bool enqueue) 910 { 911 bool masked = !enqueue; 912 u32 cfg; 913 u32 mask = 0x00000001 << buf_id; 914 915 /* mask register set */ 916 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 917 918 /* sequence id */ 919 cfg &= ~mask; 920 cfg |= masked << buf_id; 921 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); 922 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); 923 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); 924 925 /* interrupt enable */ 926 if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START) 927 gsc_handle_irq(ctx, true, false, true); 928 929 /* interrupt disable */ 930 if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP) 931 gsc_handle_irq(ctx, false, false, true); 932 } 933 934 static void gsc_dst_set_addr(struct gsc_context *ctx, 935 u32 buf_id, struct exynos_drm_ipp_buffer *buf) 936 { 937 /* address register set */ 938 gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id)); 939 gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id)); 940 gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id)); 941 942 gsc_dst_set_buf_seq(ctx, buf_id, true); 943 } 944 945 static int gsc_get_src_buf_index(struct gsc_context *ctx) 946 { 947 u32 cfg, curr_index, i; 948 u32 buf_id = GSC_MAX_SRC; 949 950 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); 951 952 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); 953 curr_index = GSC_IN_CURR_GET_INDEX(cfg); 954 955 for (i = curr_index; i < GSC_MAX_SRC; i++) { 956 if (!((cfg >> i) & 0x1)) { 957 buf_id = i; 958 break; 959 } 960 } 961 962 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, 963 curr_index, buf_id); 964 965 if (buf_id == GSC_MAX_SRC) { 966 DRM_ERROR("failed to get in buffer index.\n"); 967 return -EINVAL; 968 } 969 970 gsc_src_set_buf_seq(ctx, buf_id, false); 971 972 return buf_id; 973 } 974 975 static int gsc_get_dst_buf_index(struct gsc_context *ctx) 976 { 977 u32 cfg, curr_index, i; 978 u32 buf_id = GSC_MAX_DST; 979 980 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); 981 982 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 983 curr_index = GSC_OUT_CURR_GET_INDEX(cfg); 984 985 for (i = curr_index; i < GSC_MAX_DST; i++) { 986 if (!((cfg >> i) & 0x1)) { 987 buf_id = i; 988 break; 989 } 990 } 991 992 if (buf_id == GSC_MAX_DST) { 993 DRM_ERROR("failed to get out buffer index.\n"); 994 return -EINVAL; 995 } 996 997 gsc_dst_set_buf_seq(ctx, buf_id, false); 998 999 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, 1000 curr_index, buf_id); 1001 1002 return buf_id; 1003 } 1004 1005 static irqreturn_t gsc_irq_handler(int irq, void *dev_id) 1006 { 1007 struct gsc_context *ctx = dev_id; 1008 u32 status; 1009 int err = 0; 1010 1011 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); 1012 1013 status = gsc_read(GSC_IRQ); 1014 if (status & GSC_IRQ_STATUS_OR_IRQ) { 1015 dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n", 1016 ctx->id, status); 1017 err = -EINVAL; 1018 } 1019 1020 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) { 1021 int src_buf_id, dst_buf_id; 1022 1023 dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n", 1024 ctx->id, status); 1025 1026 src_buf_id = gsc_get_src_buf_index(ctx); 1027 dst_buf_id = gsc_get_dst_buf_index(ctx); 1028 1029 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n", src_buf_id, 1030 dst_buf_id); 1031 1032 if (src_buf_id < 0 || dst_buf_id < 0) 1033 err = -EINVAL; 1034 } 1035 1036 if (ctx->task) { 1037 struct exynos_drm_ipp_task *task = ctx->task; 1038 1039 ctx->task = NULL; 1040 pm_runtime_mark_last_busy(ctx->dev); 1041 pm_runtime_put_autosuspend(ctx->dev); 1042 exynos_drm_ipp_task_done(task, err); 1043 } 1044 1045 return IRQ_HANDLED; 1046 } 1047 1048 static int gsc_reset(struct gsc_context *ctx) 1049 { 1050 struct gsc_scaler *sc = &ctx->sc; 1051 int ret; 1052 1053 /* reset h/w block */ 1054 ret = gsc_sw_reset(ctx); 1055 if (ret < 0) { 1056 dev_err(ctx->dev, "failed to reset hardware.\n"); 1057 return ret; 1058 } 1059 1060 /* scaler setting */ 1061 memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 1062 sc->range = true; 1063 1064 return 0; 1065 } 1066 1067 static void gsc_start(struct gsc_context *ctx) 1068 { 1069 u32 cfg; 1070 1071 gsc_handle_irq(ctx, true, false, true); 1072 1073 /* enable one shot */ 1074 cfg = gsc_read(GSC_ENABLE); 1075 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK | 1076 GSC_ENABLE_CLK_GATE_MODE_MASK); 1077 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT; 1078 gsc_write(cfg, GSC_ENABLE); 1079 1080 /* src dma memory */ 1081 cfg = gsc_read(GSC_IN_CON); 1082 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); 1083 cfg |= GSC_IN_PATH_MEMORY; 1084 gsc_write(cfg, GSC_IN_CON); 1085 1086 /* dst dma memory */ 1087 cfg = gsc_read(GSC_OUT_CON); 1088 cfg |= GSC_OUT_PATH_MEMORY; 1089 gsc_write(cfg, GSC_OUT_CON); 1090 1091 gsc_set_scaler(ctx, &ctx->sc); 1092 1093 cfg = gsc_read(GSC_ENABLE); 1094 cfg |= GSC_ENABLE_ON; 1095 gsc_write(cfg, GSC_ENABLE); 1096 } 1097 1098 static int gsc_commit(struct exynos_drm_ipp *ipp, 1099 struct exynos_drm_ipp_task *task) 1100 { 1101 struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp); 1102 int ret; 1103 1104 pm_runtime_get_sync(ctx->dev); 1105 ctx->task = task; 1106 1107 ret = gsc_reset(ctx); 1108 if (ret) { 1109 pm_runtime_put_autosuspend(ctx->dev); 1110 ctx->task = NULL; 1111 return ret; 1112 } 1113 1114 gsc_src_set_fmt(ctx, task->src.buf.fourcc); 1115 gsc_src_set_transf(ctx, task->transform.rotation); 1116 gsc_src_set_size(ctx, &task->src); 1117 gsc_src_set_addr(ctx, 0, &task->src); 1118 gsc_dst_set_fmt(ctx, task->dst.buf.fourcc); 1119 gsc_dst_set_size(ctx, &task->dst); 1120 gsc_dst_set_addr(ctx, 0, &task->dst); 1121 gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect); 1122 gsc_start(ctx); 1123 1124 return 0; 1125 } 1126 1127 static void gsc_abort(struct exynos_drm_ipp *ipp, 1128 struct exynos_drm_ipp_task *task) 1129 { 1130 struct gsc_context *ctx = 1131 container_of(ipp, struct gsc_context, ipp); 1132 1133 gsc_reset(ctx); 1134 if (ctx->task) { 1135 struct exynos_drm_ipp_task *task = ctx->task; 1136 1137 ctx->task = NULL; 1138 pm_runtime_mark_last_busy(ctx->dev); 1139 pm_runtime_put_autosuspend(ctx->dev); 1140 exynos_drm_ipp_task_done(task, -EIO); 1141 } 1142 } 1143 1144 static struct exynos_drm_ipp_funcs ipp_funcs = { 1145 .commit = gsc_commit, 1146 .abort = gsc_abort, 1147 }; 1148 1149 static int gsc_bind(struct device *dev, struct device *master, void *data) 1150 { 1151 struct gsc_context *ctx = dev_get_drvdata(dev); 1152 struct drm_device *drm_dev = data; 1153 struct exynos_drm_ipp *ipp = &ctx->ipp; 1154 1155 ctx->drm_dev = drm_dev; 1156 drm_iommu_attach_device(drm_dev, dev); 1157 1158 exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs, 1159 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE | 1160 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT, 1161 ctx->formats, ctx->num_formats, "gsc"); 1162 1163 dev_info(dev, "The exynos gscaler has been probed successfully\n"); 1164 1165 return 0; 1166 } 1167 1168 static void gsc_unbind(struct device *dev, struct device *master, 1169 void *data) 1170 { 1171 struct gsc_context *ctx = dev_get_drvdata(dev); 1172 struct drm_device *drm_dev = data; 1173 struct exynos_drm_ipp *ipp = &ctx->ipp; 1174 1175 exynos_drm_ipp_unregister(drm_dev, ipp); 1176 drm_iommu_detach_device(drm_dev, dev); 1177 } 1178 1179 static const struct component_ops gsc_component_ops = { 1180 .bind = gsc_bind, 1181 .unbind = gsc_unbind, 1182 }; 1183 1184 static const unsigned int gsc_formats[] = { 1185 DRM_FORMAT_ARGB8888, 1186 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888, 1187 DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61, 1188 DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, 1189 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422, 1190 }; 1191 1192 static int gsc_probe(struct platform_device *pdev) 1193 { 1194 struct device *dev = &pdev->dev; 1195 struct gsc_driverdata *driver_data; 1196 struct exynos_drm_ipp_formats *formats; 1197 struct gsc_context *ctx; 1198 struct resource *res; 1199 int ret, i; 1200 1201 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1202 if (!ctx) 1203 return -ENOMEM; 1204 1205 formats = devm_kcalloc(dev, 1206 ARRAY_SIZE(gsc_formats), sizeof(*formats), 1207 GFP_KERNEL); 1208 if (!formats) 1209 return -ENOMEM; 1210 1211 driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev); 1212 ctx->dev = dev; 1213 ctx->num_clocks = driver_data->num_clocks; 1214 ctx->clk_names = driver_data->clk_names; 1215 1216 for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) { 1217 formats[i].fourcc = gsc_formats[i]; 1218 formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE | 1219 DRM_EXYNOS_IPP_FORMAT_DESTINATION; 1220 formats[i].limits = driver_data->limits; 1221 formats[i].num_limits = driver_data->num_limits; 1222 } 1223 ctx->formats = formats; 1224 ctx->num_formats = ARRAY_SIZE(gsc_formats); 1225 1226 /* clock control */ 1227 for (i = 0; i < ctx->num_clocks; i++) { 1228 ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]); 1229 if (IS_ERR(ctx->clocks[i])) { 1230 dev_err(dev, "failed to get clock: %s\n", 1231 ctx->clk_names[i]); 1232 return PTR_ERR(ctx->clocks[i]); 1233 } 1234 } 1235 1236 /* resource memory */ 1237 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1238 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1239 if (IS_ERR(ctx->regs)) 1240 return PTR_ERR(ctx->regs); 1241 1242 /* resource irq */ 1243 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1244 if (!res) { 1245 dev_err(dev, "failed to request irq resource.\n"); 1246 return -ENOENT; 1247 } 1248 1249 ctx->irq = res->start; 1250 ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0, 1251 dev_name(dev), ctx); 1252 if (ret < 0) { 1253 dev_err(dev, "failed to request irq.\n"); 1254 return ret; 1255 } 1256 1257 /* context initailization */ 1258 ctx->id = pdev->id; 1259 1260 platform_set_drvdata(pdev, ctx); 1261 1262 pm_runtime_use_autosuspend(dev); 1263 pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY); 1264 pm_runtime_enable(dev); 1265 1266 ret = component_add(dev, &gsc_component_ops); 1267 if (ret) 1268 goto err_pm_dis; 1269 1270 dev_info(dev, "drm gsc registered successfully.\n"); 1271 1272 return 0; 1273 1274 err_pm_dis: 1275 pm_runtime_dont_use_autosuspend(dev); 1276 pm_runtime_disable(dev); 1277 return ret; 1278 } 1279 1280 static int gsc_remove(struct platform_device *pdev) 1281 { 1282 struct device *dev = &pdev->dev; 1283 1284 pm_runtime_dont_use_autosuspend(dev); 1285 pm_runtime_disable(dev); 1286 1287 return 0; 1288 } 1289 1290 static int __maybe_unused gsc_runtime_suspend(struct device *dev) 1291 { 1292 struct gsc_context *ctx = get_gsc_context(dev); 1293 int i; 1294 1295 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1296 1297 for (i = ctx->num_clocks - 1; i >= 0; i--) 1298 clk_disable_unprepare(ctx->clocks[i]); 1299 1300 return 0; 1301 } 1302 1303 static int __maybe_unused gsc_runtime_resume(struct device *dev) 1304 { 1305 struct gsc_context *ctx = get_gsc_context(dev); 1306 int i, ret; 1307 1308 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1309 1310 for (i = 0; i < ctx->num_clocks; i++) { 1311 ret = clk_prepare_enable(ctx->clocks[i]); 1312 if (ret) { 1313 while (--i > 0) 1314 clk_disable_unprepare(ctx->clocks[i]); 1315 return ret; 1316 } 1317 } 1318 return 0; 1319 } 1320 1321 static const struct dev_pm_ops gsc_pm_ops = { 1322 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1323 pm_runtime_force_resume) 1324 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL) 1325 }; 1326 1327 static const struct drm_exynos_ipp_limit gsc_5250_limits[] = { 1328 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) }, 1329 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) }, 1330 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) }, 1331 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 }, 1332 .v = { (1 << 16) / 16, (1 << 16) * 8 }) }, 1333 }; 1334 1335 static const struct drm_exynos_ipp_limit gsc_5420_limits[] = { 1336 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) }, 1337 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) }, 1338 { IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) }, 1339 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 }, 1340 .v = { (1 << 16) / 16, (1 << 16) * 8 }) }, 1341 }; 1342 1343 static const struct drm_exynos_ipp_limit gsc_5433_limits[] = { 1344 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 2 }, .v = { 16, 8191, 2 }) }, 1345 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) }, 1346 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) }, 1347 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 }, 1348 .v = { (1 << 16) / 16, (1 << 16) * 8 }) }, 1349 }; 1350 1351 static struct gsc_driverdata gsc_exynos5250_drvdata = { 1352 .clk_names = {"gscl"}, 1353 .num_clocks = 1, 1354 .limits = gsc_5250_limits, 1355 .num_limits = ARRAY_SIZE(gsc_5250_limits), 1356 }; 1357 1358 static struct gsc_driverdata gsc_exynos5420_drvdata = { 1359 .clk_names = {"gscl"}, 1360 .num_clocks = 1, 1361 .limits = gsc_5420_limits, 1362 .num_limits = ARRAY_SIZE(gsc_5420_limits), 1363 }; 1364 1365 static struct gsc_driverdata gsc_exynos5433_drvdata = { 1366 .clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"}, 1367 .num_clocks = 4, 1368 .limits = gsc_5433_limits, 1369 .num_limits = ARRAY_SIZE(gsc_5433_limits), 1370 }; 1371 1372 static const struct of_device_id exynos_drm_gsc_of_match[] = { 1373 { 1374 .compatible = "samsung,exynos5-gsc", 1375 .data = &gsc_exynos5250_drvdata, 1376 }, { 1377 .compatible = "samsung,exynos5250-gsc", 1378 .data = &gsc_exynos5250_drvdata, 1379 }, { 1380 .compatible = "samsung,exynos5420-gsc", 1381 .data = &gsc_exynos5420_drvdata, 1382 }, { 1383 .compatible = "samsung,exynos5433-gsc", 1384 .data = &gsc_exynos5433_drvdata, 1385 }, { 1386 }, 1387 }; 1388 MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match); 1389 1390 struct platform_driver gsc_driver = { 1391 .probe = gsc_probe, 1392 .remove = gsc_remove, 1393 .driver = { 1394 .name = "exynos-drm-gsc", 1395 .owner = THIS_MODULE, 1396 .pm = &gsc_pm_ops, 1397 .of_match_table = of_match_ptr(exynos_drm_gsc_of_match), 1398 }, 1399 }; 1400