1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2012 Samsung Electronics Co.Ltd
4  * Authors:
5  *	Eunchul Kim <chulspro.kim@samsung.com>
6  *	Jinyoung Jeon <jy0.jeon@samsung.com>
7  *	Sangmin Lee <lsmin.lee@samsung.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 
19 #include <drm/drm_fourcc.h>
20 #include <drm/drm_print.h>
21 #include <drm/exynos_drm.h>
22 
23 #include "exynos_drm_drv.h"
24 #include "exynos_drm_ipp.h"
25 #include "regs-gsc.h"
26 
27 /*
28  * GSC stands for General SCaler and
29  * supports image scaler/rotator and input/output DMA operations.
30  * input DMA reads image data from the memory.
31  * output DMA writes image data to memory.
32  * GSC supports image rotation and image effect functions.
33  */
34 
35 
36 #define GSC_MAX_CLOCKS	8
37 #define GSC_MAX_SRC		4
38 #define GSC_MAX_DST		16
39 #define GSC_RESET_TIMEOUT	50
40 #define GSC_BUF_STOP	1
41 #define GSC_BUF_START	2
42 #define GSC_REG_SZ		16
43 #define GSC_WIDTH_ITU_709	1280
44 #define GSC_SC_UP_MAX_RATIO		65536
45 #define GSC_SC_DOWN_RATIO_7_8		74898
46 #define GSC_SC_DOWN_RATIO_6_8		87381
47 #define GSC_SC_DOWN_RATIO_5_8		104857
48 #define GSC_SC_DOWN_RATIO_4_8		131072
49 #define GSC_SC_DOWN_RATIO_3_8		174762
50 #define GSC_SC_DOWN_RATIO_2_8		262144
51 #define GSC_CROP_MAX	8192
52 #define GSC_CROP_MIN	32
53 #define GSC_SCALE_MAX	4224
54 #define GSC_SCALE_MIN	32
55 #define GSC_COEF_RATIO	7
56 #define GSC_COEF_PHASE	9
57 #define GSC_COEF_ATTR	16
58 #define GSC_COEF_H_8T	8
59 #define GSC_COEF_V_4T	4
60 #define GSC_COEF_DEPTH	3
61 #define GSC_AUTOSUSPEND_DELAY		2000
62 
63 #define get_gsc_context(dev)	dev_get_drvdata(dev)
64 #define gsc_read(offset)		readl(ctx->regs + (offset))
65 #define gsc_write(cfg, offset)	writel(cfg, ctx->regs + (offset))
66 
67 /*
68  * A structure of scaler.
69  *
70  * @range: narrow, wide.
71  * @pre_shfactor: pre sclaer shift factor.
72  * @pre_hratio: horizontal ratio of the prescaler.
73  * @pre_vratio: vertical ratio of the prescaler.
74  * @main_hratio: the main scaler's horizontal ratio.
75  * @main_vratio: the main scaler's vertical ratio.
76  */
77 struct gsc_scaler {
78 	bool	range;
79 	u32	pre_shfactor;
80 	u32	pre_hratio;
81 	u32	pre_vratio;
82 	unsigned long main_hratio;
83 	unsigned long main_vratio;
84 };
85 
86 /*
87  * A structure of gsc context.
88  *
89  * @regs_res: register resources.
90  * @regs: memory mapped io registers.
91  * @gsc_clk: gsc gate clock.
92  * @sc: scaler infomations.
93  * @id: gsc id.
94  * @irq: irq number.
95  * @rotation: supports rotation of src.
96  */
97 struct gsc_context {
98 	struct exynos_drm_ipp ipp;
99 	struct drm_device *drm_dev;
100 	struct device	*dev;
101 	struct exynos_drm_ipp_task	*task;
102 	struct exynos_drm_ipp_formats	*formats;
103 	unsigned int			num_formats;
104 
105 	struct resource	*regs_res;
106 	void __iomem	*regs;
107 	const char	**clk_names;
108 	struct clk	*clocks[GSC_MAX_CLOCKS];
109 	int		num_clocks;
110 	struct gsc_scaler	sc;
111 	int	id;
112 	int	irq;
113 	bool	rotation;
114 };
115 
116 /**
117  * struct gsc_driverdata - per device type driver data for init time.
118  *
119  * @limits: picture size limits array
120  * @clk_names: names of clocks needed by this variant
121  * @num_clocks: the number of clocks needed by this variant
122  */
123 struct gsc_driverdata {
124 	const struct drm_exynos_ipp_limit *limits;
125 	int		num_limits;
126 	const char	*clk_names[GSC_MAX_CLOCKS];
127 	int		num_clocks;
128 };
129 
130 /* 8-tap Filter Coefficient */
131 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
132 	{	/* Ratio <= 65536 (~8:8) */
133 		{  0,  0,   0, 128,   0,   0,  0,  0 },
134 		{ -1,  2,  -6, 127,   7,  -2,  1,  0 },
135 		{ -1,  4, -12, 125,  16,  -5,  1,  0 },
136 		{ -1,  5, -15, 120,  25,  -8,  2,  0 },
137 		{ -1,  6, -18, 114,  35, -10,  3, -1 },
138 		{ -1,  6, -20, 107,  46, -13,  4, -1 },
139 		{ -2,  7, -21,  99,  57, -16,  5, -1 },
140 		{ -1,  6, -20,  89,  68, -18,  5, -1 },
141 		{ -1,  6, -20,  79,  79, -20,  6, -1 },
142 		{ -1,  5, -18,  68,  89, -20,  6, -1 },
143 		{ -1,  5, -16,  57,  99, -21,  7, -2 },
144 		{ -1,  4, -13,  46, 107, -20,  6, -1 },
145 		{ -1,  3, -10,  35, 114, -18,  6, -1 },
146 		{  0,  2,  -8,  25, 120, -15,  5, -1 },
147 		{  0,  1,  -5,  16, 125, -12,  4, -1 },
148 		{  0,  1,  -2,   7, 127,  -6,  2, -1 }
149 	}, {	/* 65536 < Ratio <= 74898 (~8:7) */
150 		{  3, -8,  14, 111,  13,  -8,  3,  0 },
151 		{  2, -6,   7, 112,  21, -10,  3, -1 },
152 		{  2, -4,   1, 110,  28, -12,  4, -1 },
153 		{  1, -2,  -3, 106,  36, -13,  4, -1 },
154 		{  1, -1,  -7, 103,  44, -15,  4, -1 },
155 		{  1,  1, -11,  97,  53, -16,  4, -1 },
156 		{  0,  2, -13,  91,  61, -16,  4, -1 },
157 		{  0,  3, -15,  85,  69, -17,  4, -1 },
158 		{  0,  3, -16,  77,  77, -16,  3,  0 },
159 		{ -1,  4, -17,  69,  85, -15,  3,  0 },
160 		{ -1,  4, -16,  61,  91, -13,  2,  0 },
161 		{ -1,  4, -16,  53,  97, -11,  1,  1 },
162 		{ -1,  4, -15,  44, 103,  -7, -1,  1 },
163 		{ -1,  4, -13,  36, 106,  -3, -2,  1 },
164 		{ -1,  4, -12,  28, 110,   1, -4,  2 },
165 		{ -1,  3, -10,  21, 112,   7, -6,  2 }
166 	}, {	/* 74898 < Ratio <= 87381 (~8:6) */
167 		{ 2, -11,  25,  96, 25, -11,   2,  0 },
168 		{ 2, -10,  19,  96, 31, -12,   2,  0 },
169 		{ 2,  -9,  14,  94, 37, -12,   2,  0 },
170 		{ 2,  -8,  10,  92, 43, -12,   1,  0 },
171 		{ 2,  -7,   5,  90, 49, -12,   1,  0 },
172 		{ 2,  -5,   1,  86, 55, -12,   0,  1 },
173 		{ 2,  -4,  -2,  82, 61, -11,  -1,  1 },
174 		{ 1,  -3,  -5,  77, 67,  -9,  -1,  1 },
175 		{ 1,  -2,  -7,  72, 72,  -7,  -2,  1 },
176 		{ 1,  -1,  -9,  67, 77,  -5,  -3,  1 },
177 		{ 1,  -1, -11,  61, 82,  -2,  -4,  2 },
178 		{ 1,   0, -12,  55, 86,   1,  -5,  2 },
179 		{ 0,   1, -12,  49, 90,   5,  -7,  2 },
180 		{ 0,   1, -12,  43, 92,  10,  -8,  2 },
181 		{ 0,   2, -12,  37, 94,  14,  -9,  2 },
182 		{ 0,   2, -12,  31, 96,  19, -10,  2 }
183 	}, {	/* 87381 < Ratio <= 104857 (~8:5) */
184 		{ -1,  -8, 33,  80, 33,  -8,  -1,  0 },
185 		{ -1,  -8, 28,  80, 37,  -7,  -2,  1 },
186 		{  0,  -8, 24,  79, 41,  -7,  -2,  1 },
187 		{  0,  -8, 20,  78, 46,  -6,  -3,  1 },
188 		{  0,  -8, 16,  76, 50,  -4,  -3,  1 },
189 		{  0,  -7, 13,  74, 54,  -3,  -4,  1 },
190 		{  1,  -7, 10,  71, 58,  -1,  -5,  1 },
191 		{  1,  -6,  6,  68, 62,   1,  -5,  1 },
192 		{  1,  -6,  4,  65, 65,   4,  -6,  1 },
193 		{  1,  -5,  1,  62, 68,   6,  -6,  1 },
194 		{  1,  -5, -1,  58, 71,  10,  -7,  1 },
195 		{  1,  -4, -3,  54, 74,  13,  -7,  0 },
196 		{  1,  -3, -4,  50, 76,  16,  -8,  0 },
197 		{  1,  -3, -6,  46, 78,  20,  -8,  0 },
198 		{  1,  -2, -7,  41, 79,  24,  -8,  0 },
199 		{  1,  -2, -7,  37, 80,  28,  -8, -1 }
200 	}, {	/* 104857 < Ratio <= 131072 (~8:4) */
201 		{ -3,   0, 35,  64, 35,   0,  -3,  0 },
202 		{ -3,  -1, 32,  64, 38,   1,  -3,  0 },
203 		{ -2,  -2, 29,  63, 41,   2,  -3,  0 },
204 		{ -2,  -3, 27,  63, 43,   4,  -4,  0 },
205 		{ -2,  -3, 24,  61, 46,   6,  -4,  0 },
206 		{ -2,  -3, 21,  60, 49,   7,  -4,  0 },
207 		{ -1,  -4, 19,  59, 51,   9,  -4, -1 },
208 		{ -1,  -4, 16,  57, 53,  12,  -4, -1 },
209 		{ -1,  -4, 14,  55, 55,  14,  -4, -1 },
210 		{ -1,  -4, 12,  53, 57,  16,  -4, -1 },
211 		{ -1,  -4,  9,  51, 59,  19,  -4, -1 },
212 		{  0,  -4,  7,  49, 60,  21,  -3, -2 },
213 		{  0,  -4,  6,  46, 61,  24,  -3, -2 },
214 		{  0,  -4,  4,  43, 63,  27,  -3, -2 },
215 		{  0,  -3,  2,  41, 63,  29,  -2, -2 },
216 		{  0,  -3,  1,  38, 64,  32,  -1, -3 }
217 	}, {	/* 131072 < Ratio <= 174762 (~8:3) */
218 		{ -1,   8, 33,  48, 33,   8,  -1,  0 },
219 		{ -1,   7, 31,  49, 35,   9,  -1, -1 },
220 		{ -1,   6, 30,  49, 36,  10,  -1, -1 },
221 		{ -1,   5, 28,  48, 38,  12,  -1, -1 },
222 		{ -1,   4, 26,  48, 39,  13,   0, -1 },
223 		{ -1,   3, 24,  47, 41,  15,   0, -1 },
224 		{ -1,   2, 23,  47, 42,  16,   0, -1 },
225 		{ -1,   2, 21,  45, 43,  18,   1, -1 },
226 		{ -1,   1, 19,  45, 45,  19,   1, -1 },
227 		{ -1,   1, 18,  43, 45,  21,   2, -1 },
228 		{ -1,   0, 16,  42, 47,  23,   2, -1 },
229 		{ -1,   0, 15,  41, 47,  24,   3, -1 },
230 		{ -1,   0, 13,  39, 48,  26,   4, -1 },
231 		{ -1,  -1, 12,  38, 48,  28,   5, -1 },
232 		{ -1,  -1, 10,  36, 49,  30,   6, -1 },
233 		{ -1,  -1,  9,  35, 49,  31,   7, -1 }
234 	}, {	/* 174762 < Ratio <= 262144 (~8:2) */
235 		{  2,  13, 30,  38, 30,  13,   2,  0 },
236 		{  2,  12, 29,  38, 30,  14,   3,  0 },
237 		{  2,  11, 28,  38, 31,  15,   3,  0 },
238 		{  2,  10, 26,  38, 32,  16,   4,  0 },
239 		{  1,  10, 26,  37, 33,  17,   4,  0 },
240 		{  1,   9, 24,  37, 34,  18,   5,  0 },
241 		{  1,   8, 24,  37, 34,  19,   5,  0 },
242 		{  1,   7, 22,  36, 35,  20,   6,  1 },
243 		{  1,   6, 21,  36, 36,  21,   6,  1 },
244 		{  1,   6, 20,  35, 36,  22,   7,  1 },
245 		{  0,   5, 19,  34, 37,  24,   8,  1 },
246 		{  0,   5, 18,  34, 37,  24,   9,  1 },
247 		{  0,   4, 17,  33, 37,  26,  10,  1 },
248 		{  0,   4, 16,  32, 38,  26,  10,  2 },
249 		{  0,   3, 15,  31, 38,  28,  11,  2 },
250 		{  0,   3, 14,  30, 38,  29,  12,  2 }
251 	}
252 };
253 
254 /* 4-tap Filter Coefficient */
255 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
256 	{	/* Ratio <= 65536 (~8:8) */
257 		{  0, 128,   0,  0 },
258 		{ -4, 127,   5,  0 },
259 		{ -6, 124,  11, -1 },
260 		{ -8, 118,  19, -1 },
261 		{ -8, 111,  27, -2 },
262 		{ -8, 102,  37, -3 },
263 		{ -8,  92,  48, -4 },
264 		{ -7,  81,  59, -5 },
265 		{ -6,  70,  70, -6 },
266 		{ -5,  59,  81, -7 },
267 		{ -4,  48,  92, -8 },
268 		{ -3,  37, 102, -8 },
269 		{ -2,  27, 111, -8 },
270 		{ -1,  19, 118, -8 },
271 		{ -1,  11, 124, -6 },
272 		{  0,   5, 127, -4 }
273 	}, {	/* 65536 < Ratio <= 74898 (~8:7) */
274 		{  8, 112,   8,  0 },
275 		{  4, 111,  14, -1 },
276 		{  1, 109,  20, -2 },
277 		{ -2, 105,  27, -2 },
278 		{ -3, 100,  34, -3 },
279 		{ -5,  93,  43, -3 },
280 		{ -5,  86,  51, -4 },
281 		{ -5,  77,  60, -4 },
282 		{ -5,  69,  69, -5 },
283 		{ -4,  60,  77, -5 },
284 		{ -4,  51,  86, -5 },
285 		{ -3,  43,  93, -5 },
286 		{ -3,  34, 100, -3 },
287 		{ -2,  27, 105, -2 },
288 		{ -2,  20, 109,  1 },
289 		{ -1,  14, 111,  4 }
290 	}, {	/* 74898 < Ratio <= 87381 (~8:6) */
291 		{ 16,  96,  16,  0 },
292 		{ 12,  97,  21, -2 },
293 		{  8,  96,  26, -2 },
294 		{  5,  93,  32, -2 },
295 		{  2,  89,  39, -2 },
296 		{  0,  84,  46, -2 },
297 		{ -1,  79,  53, -3 },
298 		{ -2,  73,  59, -2 },
299 		{ -2,  66,  66, -2 },
300 		{ -2,  59,  73, -2 },
301 		{ -3,  53,  79, -1 },
302 		{ -2,  46,  84,  0 },
303 		{ -2,  39,  89,  2 },
304 		{ -2,  32,  93,  5 },
305 		{ -2,  26,  96,  8 },
306 		{ -2,  21,  97, 12 }
307 	}, {	/* 87381 < Ratio <= 104857 (~8:5) */
308 		{ 22,  84,  22,  0 },
309 		{ 18,  85,  26, -1 },
310 		{ 14,  84,  31, -1 },
311 		{ 11,  82,  36, -1 },
312 		{  8,  79,  42, -1 },
313 		{  6,  76,  47, -1 },
314 		{  4,  72,  52,  0 },
315 		{  2,  68,  58,  0 },
316 		{  1,  63,  63,  1 },
317 		{  0,  58,  68,  2 },
318 		{  0,  52,  72,  4 },
319 		{ -1,  47,  76,  6 },
320 		{ -1,  42,  79,  8 },
321 		{ -1,  36,  82, 11 },
322 		{ -1,  31,  84, 14 },
323 		{ -1,  26,  85, 18 }
324 	}, {	/* 104857 < Ratio <= 131072 (~8:4) */
325 		{ 26,  76,  26,  0 },
326 		{ 22,  76,  30,  0 },
327 		{ 19,  75,  34,  0 },
328 		{ 16,  73,  38,  1 },
329 		{ 13,  71,  43,  1 },
330 		{ 10,  69,  47,  2 },
331 		{  8,  66,  51,  3 },
332 		{  6,  63,  55,  4 },
333 		{  5,  59,  59,  5 },
334 		{  4,  55,  63,  6 },
335 		{  3,  51,  66,  8 },
336 		{  2,  47,  69, 10 },
337 		{  1,  43,  71, 13 },
338 		{  1,  38,  73, 16 },
339 		{  0,  34,  75, 19 },
340 		{  0,  30,  76, 22 }
341 	}, {	/* 131072 < Ratio <= 174762 (~8:3) */
342 		{ 29,  70,  29,  0 },
343 		{ 26,  68,  32,  2 },
344 		{ 23,  67,  36,  2 },
345 		{ 20,  66,  39,  3 },
346 		{ 17,  65,  43,  3 },
347 		{ 15,  63,  46,  4 },
348 		{ 12,  61,  50,  5 },
349 		{ 10,  58,  53,  7 },
350 		{  8,  56,  56,  8 },
351 		{  7,  53,  58, 10 },
352 		{  5,  50,  61, 12 },
353 		{  4,  46,  63, 15 },
354 		{  3,  43,  65, 17 },
355 		{  3,  39,  66, 20 },
356 		{  2,  36,  67, 23 },
357 		{  2,  32,  68, 26 }
358 	}, {	/* 174762 < Ratio <= 262144 (~8:2) */
359 		{ 32,  64,  32,  0 },
360 		{ 28,  63,  34,  3 },
361 		{ 25,  62,  37,  4 },
362 		{ 22,  62,  40,  4 },
363 		{ 19,  61,  43,  5 },
364 		{ 17,  59,  46,  6 },
365 		{ 15,  58,  48,  7 },
366 		{ 13,  55,  51,  9 },
367 		{ 11,  53,  53, 11 },
368 		{  9,  51,  55, 13 },
369 		{  7,  48,  58, 15 },
370 		{  6,  46,  59, 17 },
371 		{  5,  43,  61, 19 },
372 		{  4,  40,  62, 22 },
373 		{  4,  37,  62, 25 },
374 		{  3,  34,  63, 28 }
375 	}
376 };
377 
378 static int gsc_sw_reset(struct gsc_context *ctx)
379 {
380 	u32 cfg;
381 	int count = GSC_RESET_TIMEOUT;
382 
383 	/* s/w reset */
384 	cfg = (GSC_SW_RESET_SRESET);
385 	gsc_write(cfg, GSC_SW_RESET);
386 
387 	/* wait s/w reset complete */
388 	while (count--) {
389 		cfg = gsc_read(GSC_SW_RESET);
390 		if (!cfg)
391 			break;
392 		usleep_range(1000, 2000);
393 	}
394 
395 	if (cfg) {
396 		DRM_DEV_ERROR(ctx->dev, "failed to reset gsc h/w.\n");
397 		return -EBUSY;
398 	}
399 
400 	/* reset sequence */
401 	cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
402 	cfg |= (GSC_IN_BASE_ADDR_MASK |
403 		GSC_IN_BASE_ADDR_PINGPONG(0));
404 	gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
405 	gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
406 	gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
407 
408 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
409 	cfg |= (GSC_OUT_BASE_ADDR_MASK |
410 		GSC_OUT_BASE_ADDR_PINGPONG(0));
411 	gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
412 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
413 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
414 
415 	return 0;
416 }
417 
418 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
419 		bool overflow, bool done)
420 {
421 	u32 cfg;
422 
423 	DRM_DEV_DEBUG_KMS(ctx->dev, "enable[%d]overflow[%d]level[%d]\n",
424 			  enable, overflow, done);
425 
426 	cfg = gsc_read(GSC_IRQ);
427 	cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
428 
429 	if (enable)
430 		cfg |= GSC_IRQ_ENABLE;
431 	else
432 		cfg &= ~GSC_IRQ_ENABLE;
433 
434 	if (overflow)
435 		cfg &= ~GSC_IRQ_OR_MASK;
436 	else
437 		cfg |= GSC_IRQ_OR_MASK;
438 
439 	if (done)
440 		cfg &= ~GSC_IRQ_FRMDONE_MASK;
441 	else
442 		cfg |= GSC_IRQ_FRMDONE_MASK;
443 
444 	gsc_write(cfg, GSC_IRQ);
445 }
446 
447 
448 static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
449 {
450 	u32 cfg;
451 
452 	DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
453 
454 	cfg = gsc_read(GSC_IN_CON);
455 	cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
456 		 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
457 		 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
458 		 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
459 
460 	switch (fmt) {
461 	case DRM_FORMAT_RGB565:
462 		cfg |= GSC_IN_RGB565;
463 		break;
464 	case DRM_FORMAT_XRGB8888:
465 	case DRM_FORMAT_ARGB8888:
466 		cfg |= GSC_IN_XRGB8888;
467 		break;
468 	case DRM_FORMAT_BGRX8888:
469 		cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
470 		break;
471 	case DRM_FORMAT_YUYV:
472 		cfg |= (GSC_IN_YUV422_1P |
473 			GSC_IN_YUV422_1P_ORDER_LSB_Y |
474 			GSC_IN_CHROMA_ORDER_CBCR);
475 		break;
476 	case DRM_FORMAT_YVYU:
477 		cfg |= (GSC_IN_YUV422_1P |
478 			GSC_IN_YUV422_1P_ORDER_LSB_Y |
479 			GSC_IN_CHROMA_ORDER_CRCB);
480 		break;
481 	case DRM_FORMAT_UYVY:
482 		cfg |= (GSC_IN_YUV422_1P |
483 			GSC_IN_YUV422_1P_OEDER_LSB_C |
484 			GSC_IN_CHROMA_ORDER_CBCR);
485 		break;
486 	case DRM_FORMAT_VYUY:
487 		cfg |= (GSC_IN_YUV422_1P |
488 			GSC_IN_YUV422_1P_OEDER_LSB_C |
489 			GSC_IN_CHROMA_ORDER_CRCB);
490 		break;
491 	case DRM_FORMAT_NV21:
492 		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
493 		break;
494 	case DRM_FORMAT_NV61:
495 		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
496 		break;
497 	case DRM_FORMAT_YUV422:
498 		cfg |= GSC_IN_YUV422_3P;
499 		break;
500 	case DRM_FORMAT_YUV420:
501 		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
502 		break;
503 	case DRM_FORMAT_YVU420:
504 		cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
505 		break;
506 	case DRM_FORMAT_NV12:
507 		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
508 		break;
509 	case DRM_FORMAT_NV16:
510 		cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
511 		break;
512 	}
513 
514 	if (tiled)
515 		cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
516 
517 	gsc_write(cfg, GSC_IN_CON);
518 }
519 
520 static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation)
521 {
522 	unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
523 	u32 cfg;
524 
525 	cfg = gsc_read(GSC_IN_CON);
526 	cfg &= ~GSC_IN_ROT_MASK;
527 
528 	switch (degree) {
529 	case DRM_MODE_ROTATE_0:
530 		if (rotation & DRM_MODE_REFLECT_X)
531 			cfg |= GSC_IN_ROT_XFLIP;
532 		if (rotation & DRM_MODE_REFLECT_Y)
533 			cfg |= GSC_IN_ROT_YFLIP;
534 		break;
535 	case DRM_MODE_ROTATE_90:
536 		cfg |= GSC_IN_ROT_90;
537 		if (rotation & DRM_MODE_REFLECT_X)
538 			cfg |= GSC_IN_ROT_XFLIP;
539 		if (rotation & DRM_MODE_REFLECT_Y)
540 			cfg |= GSC_IN_ROT_YFLIP;
541 		break;
542 	case DRM_MODE_ROTATE_180:
543 		cfg |= GSC_IN_ROT_180;
544 		if (rotation & DRM_MODE_REFLECT_X)
545 			cfg &= ~GSC_IN_ROT_XFLIP;
546 		if (rotation & DRM_MODE_REFLECT_Y)
547 			cfg &= ~GSC_IN_ROT_YFLIP;
548 		break;
549 	case DRM_MODE_ROTATE_270:
550 		cfg |= GSC_IN_ROT_270;
551 		if (rotation & DRM_MODE_REFLECT_X)
552 			cfg &= ~GSC_IN_ROT_XFLIP;
553 		if (rotation & DRM_MODE_REFLECT_Y)
554 			cfg &= ~GSC_IN_ROT_YFLIP;
555 		break;
556 	}
557 
558 	gsc_write(cfg, GSC_IN_CON);
559 
560 	ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
561 }
562 
563 static void gsc_src_set_size(struct gsc_context *ctx,
564 			     struct exynos_drm_ipp_buffer *buf)
565 {
566 	struct gsc_scaler *sc = &ctx->sc;
567 	u32 cfg;
568 
569 	/* pixel offset */
570 	cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) |
571 		GSC_SRCIMG_OFFSET_Y(buf->rect.y));
572 	gsc_write(cfg, GSC_SRCIMG_OFFSET);
573 
574 	/* cropped size */
575 	cfg = (GSC_CROPPED_WIDTH(buf->rect.w) |
576 		GSC_CROPPED_HEIGHT(buf->rect.h));
577 	gsc_write(cfg, GSC_CROPPED_SIZE);
578 
579 	/* original size */
580 	cfg = gsc_read(GSC_SRCIMG_SIZE);
581 	cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
582 		GSC_SRCIMG_WIDTH_MASK);
583 
584 	cfg |= (GSC_SRCIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
585 		GSC_SRCIMG_HEIGHT(buf->buf.height));
586 
587 	gsc_write(cfg, GSC_SRCIMG_SIZE);
588 
589 	cfg = gsc_read(GSC_IN_CON);
590 	cfg &= ~GSC_IN_RGB_TYPE_MASK;
591 
592 	if (buf->rect.w >= GSC_WIDTH_ITU_709)
593 		if (sc->range)
594 			cfg |= GSC_IN_RGB_HD_WIDE;
595 		else
596 			cfg |= GSC_IN_RGB_HD_NARROW;
597 	else
598 		if (sc->range)
599 			cfg |= GSC_IN_RGB_SD_WIDE;
600 		else
601 			cfg |= GSC_IN_RGB_SD_NARROW;
602 
603 	gsc_write(cfg, GSC_IN_CON);
604 }
605 
606 static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
607 			       bool enqueue)
608 {
609 	bool masked = !enqueue;
610 	u32 cfg;
611 	u32 mask = 0x00000001 << buf_id;
612 
613 	/* mask register set */
614 	cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
615 
616 	/* sequence id */
617 	cfg &= ~mask;
618 	cfg |= masked << buf_id;
619 	gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
620 	gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
621 	gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
622 }
623 
624 static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
625 			    struct exynos_drm_ipp_buffer *buf)
626 {
627 	/* address register set */
628 	gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
629 	gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
630 	gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
631 
632 	gsc_src_set_buf_seq(ctx, buf_id, true);
633 }
634 
635 static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt, bool tiled)
636 {
637 	u32 cfg;
638 
639 	DRM_DEV_DEBUG_KMS(ctx->dev, "fmt[0x%x]\n", fmt);
640 
641 	cfg = gsc_read(GSC_OUT_CON);
642 	cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
643 		 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
644 		 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
645 		 GSC_OUT_GLOBAL_ALPHA_MASK);
646 
647 	switch (fmt) {
648 	case DRM_FORMAT_RGB565:
649 		cfg |= GSC_OUT_RGB565;
650 		break;
651 	case DRM_FORMAT_ARGB8888:
652 	case DRM_FORMAT_XRGB8888:
653 		cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
654 		break;
655 	case DRM_FORMAT_BGRX8888:
656 		cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
657 		break;
658 	case DRM_FORMAT_YUYV:
659 		cfg |= (GSC_OUT_YUV422_1P |
660 			GSC_OUT_YUV422_1P_ORDER_LSB_Y |
661 			GSC_OUT_CHROMA_ORDER_CBCR);
662 		break;
663 	case DRM_FORMAT_YVYU:
664 		cfg |= (GSC_OUT_YUV422_1P |
665 			GSC_OUT_YUV422_1P_ORDER_LSB_Y |
666 			GSC_OUT_CHROMA_ORDER_CRCB);
667 		break;
668 	case DRM_FORMAT_UYVY:
669 		cfg |= (GSC_OUT_YUV422_1P |
670 			GSC_OUT_YUV422_1P_OEDER_LSB_C |
671 			GSC_OUT_CHROMA_ORDER_CBCR);
672 		break;
673 	case DRM_FORMAT_VYUY:
674 		cfg |= (GSC_OUT_YUV422_1P |
675 			GSC_OUT_YUV422_1P_OEDER_LSB_C |
676 			GSC_OUT_CHROMA_ORDER_CRCB);
677 		break;
678 	case DRM_FORMAT_NV21:
679 		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
680 		break;
681 	case DRM_FORMAT_NV61:
682 		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
683 		break;
684 	case DRM_FORMAT_YUV422:
685 		cfg |= GSC_OUT_YUV422_3P;
686 		break;
687 	case DRM_FORMAT_YUV420:
688 		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
689 		break;
690 	case DRM_FORMAT_YVU420:
691 		cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
692 		break;
693 	case DRM_FORMAT_NV12:
694 		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
695 		break;
696 	case DRM_FORMAT_NV16:
697 		cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
698 		break;
699 	}
700 
701 	if (tiled)
702 		cfg |= (GSC_IN_TILE_C_16x8 | GSC_OUT_TILE_MODE);
703 
704 	gsc_write(cfg, GSC_OUT_CON);
705 }
706 
707 static int gsc_get_ratio_shift(struct gsc_context *ctx, u32 src, u32 dst,
708 			       u32 *ratio)
709 {
710 	DRM_DEV_DEBUG_KMS(ctx->dev, "src[%d]dst[%d]\n", src, dst);
711 
712 	if (src >= dst * 8) {
713 		DRM_DEV_ERROR(ctx->dev, "failed to make ratio and shift.\n");
714 		return -EINVAL;
715 	} else if (src >= dst * 4)
716 		*ratio = 4;
717 	else if (src >= dst * 2)
718 		*ratio = 2;
719 	else
720 		*ratio = 1;
721 
722 	return 0;
723 }
724 
725 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
726 {
727 	if (hratio == 4 && vratio == 4)
728 		*shfactor = 4;
729 	else if ((hratio == 4 && vratio == 2) ||
730 		 (hratio == 2 && vratio == 4))
731 		*shfactor = 3;
732 	else if ((hratio == 4 && vratio == 1) ||
733 		 (hratio == 1 && vratio == 4) ||
734 		 (hratio == 2 && vratio == 2))
735 		*shfactor = 2;
736 	else if (hratio == 1 && vratio == 1)
737 		*shfactor = 0;
738 	else
739 		*shfactor = 1;
740 }
741 
742 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
743 			     struct drm_exynos_ipp_task_rect *src,
744 			     struct drm_exynos_ipp_task_rect *dst)
745 {
746 	u32 cfg;
747 	u32 src_w, src_h, dst_w, dst_h;
748 	int ret = 0;
749 
750 	src_w = src->w;
751 	src_h = src->h;
752 
753 	if (ctx->rotation) {
754 		dst_w = dst->h;
755 		dst_h = dst->w;
756 	} else {
757 		dst_w = dst->w;
758 		dst_h = dst->h;
759 	}
760 
761 	ret = gsc_get_ratio_shift(ctx, src_w, dst_w, &sc->pre_hratio);
762 	if (ret) {
763 		DRM_DEV_ERROR(ctx->dev, "failed to get ratio horizontal.\n");
764 		return ret;
765 	}
766 
767 	ret = gsc_get_ratio_shift(ctx, src_h, dst_h, &sc->pre_vratio);
768 	if (ret) {
769 		DRM_DEV_ERROR(ctx->dev, "failed to get ratio vertical.\n");
770 		return ret;
771 	}
772 
773 	DRM_DEV_DEBUG_KMS(ctx->dev, "pre_hratio[%d]pre_vratio[%d]\n",
774 			  sc->pre_hratio, sc->pre_vratio);
775 
776 	sc->main_hratio = (src_w << 16) / dst_w;
777 	sc->main_vratio = (src_h << 16) / dst_h;
778 
779 	DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
780 			  sc->main_hratio, sc->main_vratio);
781 
782 	gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
783 		&sc->pre_shfactor);
784 
785 	DRM_DEV_DEBUG_KMS(ctx->dev, "pre_shfactor[%d]\n", sc->pre_shfactor);
786 
787 	cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
788 		GSC_PRESC_H_RATIO(sc->pre_hratio) |
789 		GSC_PRESC_V_RATIO(sc->pre_vratio));
790 	gsc_write(cfg, GSC_PRE_SCALE_RATIO);
791 
792 	return ret;
793 }
794 
795 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
796 {
797 	int i, j, k, sc_ratio;
798 
799 	if (main_hratio <= GSC_SC_UP_MAX_RATIO)
800 		sc_ratio = 0;
801 	else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
802 		sc_ratio = 1;
803 	else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
804 		sc_ratio = 2;
805 	else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
806 		sc_ratio = 3;
807 	else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
808 		sc_ratio = 4;
809 	else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
810 		sc_ratio = 5;
811 	else
812 		sc_ratio = 6;
813 
814 	for (i = 0; i < GSC_COEF_PHASE; i++)
815 		for (j = 0; j < GSC_COEF_H_8T; j++)
816 			for (k = 0; k < GSC_COEF_DEPTH; k++)
817 				gsc_write(h_coef_8t[sc_ratio][i][j],
818 					GSC_HCOEF(i, j, k));
819 }
820 
821 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
822 {
823 	int i, j, k, sc_ratio;
824 
825 	if (main_vratio <= GSC_SC_UP_MAX_RATIO)
826 		sc_ratio = 0;
827 	else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
828 		sc_ratio = 1;
829 	else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
830 		sc_ratio = 2;
831 	else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
832 		sc_ratio = 3;
833 	else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
834 		sc_ratio = 4;
835 	else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
836 		sc_ratio = 5;
837 	else
838 		sc_ratio = 6;
839 
840 	for (i = 0; i < GSC_COEF_PHASE; i++)
841 		for (j = 0; j < GSC_COEF_V_4T; j++)
842 			for (k = 0; k < GSC_COEF_DEPTH; k++)
843 				gsc_write(v_coef_4t[sc_ratio][i][j],
844 					GSC_VCOEF(i, j, k));
845 }
846 
847 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
848 {
849 	u32 cfg;
850 
851 	DRM_DEV_DEBUG_KMS(ctx->dev, "main_hratio[%ld]main_vratio[%ld]\n",
852 			  sc->main_hratio, sc->main_vratio);
853 
854 	gsc_set_h_coef(ctx, sc->main_hratio);
855 	cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
856 	gsc_write(cfg, GSC_MAIN_H_RATIO);
857 
858 	gsc_set_v_coef(ctx, sc->main_vratio);
859 	cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
860 	gsc_write(cfg, GSC_MAIN_V_RATIO);
861 }
862 
863 static void gsc_dst_set_size(struct gsc_context *ctx,
864 			     struct exynos_drm_ipp_buffer *buf)
865 {
866 	struct gsc_scaler *sc = &ctx->sc;
867 	u32 cfg;
868 
869 	/* pixel offset */
870 	cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) |
871 		GSC_DSTIMG_OFFSET_Y(buf->rect.y));
872 	gsc_write(cfg, GSC_DSTIMG_OFFSET);
873 
874 	/* scaled size */
875 	if (ctx->rotation)
876 		cfg = (GSC_SCALED_WIDTH(buf->rect.h) |
877 		       GSC_SCALED_HEIGHT(buf->rect.w));
878 	else
879 		cfg = (GSC_SCALED_WIDTH(buf->rect.w) |
880 		       GSC_SCALED_HEIGHT(buf->rect.h));
881 	gsc_write(cfg, GSC_SCALED_SIZE);
882 
883 	/* original size */
884 	cfg = gsc_read(GSC_DSTIMG_SIZE);
885 	cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK);
886 	cfg |= GSC_DSTIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
887 	       GSC_DSTIMG_HEIGHT(buf->buf.height);
888 	gsc_write(cfg, GSC_DSTIMG_SIZE);
889 
890 	cfg = gsc_read(GSC_OUT_CON);
891 	cfg &= ~GSC_OUT_RGB_TYPE_MASK;
892 
893 	if (buf->rect.w >= GSC_WIDTH_ITU_709)
894 		if (sc->range)
895 			cfg |= GSC_OUT_RGB_HD_WIDE;
896 		else
897 			cfg |= GSC_OUT_RGB_HD_NARROW;
898 	else
899 		if (sc->range)
900 			cfg |= GSC_OUT_RGB_SD_WIDE;
901 		else
902 			cfg |= GSC_OUT_RGB_SD_NARROW;
903 
904 	gsc_write(cfg, GSC_OUT_CON);
905 }
906 
907 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
908 {
909 	u32 cfg, i, buf_num = GSC_REG_SZ;
910 	u32 mask = 0x00000001;
911 
912 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
913 
914 	for (i = 0; i < GSC_REG_SZ; i++)
915 		if (cfg & (mask << i))
916 			buf_num--;
917 
918 	DRM_DEV_DEBUG_KMS(ctx->dev, "buf_num[%d]\n", buf_num);
919 
920 	return buf_num;
921 }
922 
923 static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
924 				bool enqueue)
925 {
926 	bool masked = !enqueue;
927 	u32 cfg;
928 	u32 mask = 0x00000001 << buf_id;
929 
930 	/* mask register set */
931 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
932 
933 	/* sequence id */
934 	cfg &= ~mask;
935 	cfg |= masked << buf_id;
936 	gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
937 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
938 	gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
939 
940 	/* interrupt enable */
941 	if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
942 		gsc_handle_irq(ctx, true, false, true);
943 
944 	/* interrupt disable */
945 	if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
946 		gsc_handle_irq(ctx, false, false, true);
947 }
948 
949 static void gsc_dst_set_addr(struct gsc_context *ctx,
950 			     u32 buf_id, struct exynos_drm_ipp_buffer *buf)
951 {
952 	/* address register set */
953 	gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
954 	gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
955 	gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
956 
957 	gsc_dst_set_buf_seq(ctx, buf_id, true);
958 }
959 
960 static int gsc_get_src_buf_index(struct gsc_context *ctx)
961 {
962 	u32 cfg, curr_index, i;
963 	u32 buf_id = GSC_MAX_SRC;
964 
965 	DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
966 
967 	cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
968 	curr_index = GSC_IN_CURR_GET_INDEX(cfg);
969 
970 	for (i = curr_index; i < GSC_MAX_SRC; i++) {
971 		if (!((cfg >> i) & 0x1)) {
972 			buf_id = i;
973 			break;
974 		}
975 	}
976 
977 	DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
978 			  curr_index, buf_id);
979 
980 	if (buf_id == GSC_MAX_SRC) {
981 		DRM_DEV_ERROR(ctx->dev, "failed to get in buffer index.\n");
982 		return -EINVAL;
983 	}
984 
985 	gsc_src_set_buf_seq(ctx, buf_id, false);
986 
987 	return buf_id;
988 }
989 
990 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
991 {
992 	u32 cfg, curr_index, i;
993 	u32 buf_id = GSC_MAX_DST;
994 
995 	DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
996 
997 	cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
998 	curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
999 
1000 	for (i = curr_index; i < GSC_MAX_DST; i++) {
1001 		if (!((cfg >> i) & 0x1)) {
1002 			buf_id = i;
1003 			break;
1004 		}
1005 	}
1006 
1007 	if (buf_id == GSC_MAX_DST) {
1008 		DRM_DEV_ERROR(ctx->dev, "failed to get out buffer index.\n");
1009 		return -EINVAL;
1010 	}
1011 
1012 	gsc_dst_set_buf_seq(ctx, buf_id, false);
1013 
1014 	DRM_DEV_DEBUG_KMS(ctx->dev, "cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1015 			  curr_index, buf_id);
1016 
1017 	return buf_id;
1018 }
1019 
1020 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1021 {
1022 	struct gsc_context *ctx = dev_id;
1023 	u32 status;
1024 	int err = 0;
1025 
1026 	DRM_DEV_DEBUG_KMS(ctx->dev, "gsc id[%d]\n", ctx->id);
1027 
1028 	status = gsc_read(GSC_IRQ);
1029 	if (status & GSC_IRQ_STATUS_OR_IRQ) {
1030 		dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n",
1031 			ctx->id, status);
1032 		err = -EINVAL;
1033 	}
1034 
1035 	if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1036 		int src_buf_id, dst_buf_id;
1037 
1038 		dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n",
1039 			ctx->id, status);
1040 
1041 		src_buf_id = gsc_get_src_buf_index(ctx);
1042 		dst_buf_id = gsc_get_dst_buf_index(ctx);
1043 
1044 		DRM_DEV_DEBUG_KMS(ctx->dev, "buf_id_src[%d]buf_id_dst[%d]\n",
1045 				  src_buf_id, dst_buf_id);
1046 
1047 		if (src_buf_id < 0 || dst_buf_id < 0)
1048 			err = -EINVAL;
1049 	}
1050 
1051 	if (ctx->task) {
1052 		struct exynos_drm_ipp_task *task = ctx->task;
1053 
1054 		ctx->task = NULL;
1055 		pm_runtime_mark_last_busy(ctx->dev);
1056 		pm_runtime_put_autosuspend(ctx->dev);
1057 		exynos_drm_ipp_task_done(task, err);
1058 	}
1059 
1060 	return IRQ_HANDLED;
1061 }
1062 
1063 static int gsc_reset(struct gsc_context *ctx)
1064 {
1065 	struct gsc_scaler *sc = &ctx->sc;
1066 	int ret;
1067 
1068 	/* reset h/w block */
1069 	ret = gsc_sw_reset(ctx);
1070 	if (ret < 0) {
1071 		dev_err(ctx->dev, "failed to reset hardware.\n");
1072 		return ret;
1073 	}
1074 
1075 	/* scaler setting */
1076 	memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1077 	sc->range = true;
1078 
1079 	return 0;
1080 }
1081 
1082 static void gsc_start(struct gsc_context *ctx)
1083 {
1084 	u32 cfg;
1085 
1086 	gsc_handle_irq(ctx, true, false, true);
1087 
1088 	/* enable one shot */
1089 	cfg = gsc_read(GSC_ENABLE);
1090 	cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1091 		GSC_ENABLE_CLK_GATE_MODE_MASK);
1092 	cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1093 	gsc_write(cfg, GSC_ENABLE);
1094 
1095 	/* src dma memory */
1096 	cfg = gsc_read(GSC_IN_CON);
1097 	cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1098 	cfg |= GSC_IN_PATH_MEMORY;
1099 	gsc_write(cfg, GSC_IN_CON);
1100 
1101 	/* dst dma memory */
1102 	cfg = gsc_read(GSC_OUT_CON);
1103 	cfg |= GSC_OUT_PATH_MEMORY;
1104 	gsc_write(cfg, GSC_OUT_CON);
1105 
1106 	gsc_set_scaler(ctx, &ctx->sc);
1107 
1108 	cfg = gsc_read(GSC_ENABLE);
1109 	cfg |= GSC_ENABLE_ON;
1110 	gsc_write(cfg, GSC_ENABLE);
1111 }
1112 
1113 static int gsc_commit(struct exynos_drm_ipp *ipp,
1114 			  struct exynos_drm_ipp_task *task)
1115 {
1116 	struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp);
1117 	int ret;
1118 
1119 	pm_runtime_get_sync(ctx->dev);
1120 	ctx->task = task;
1121 
1122 	ret = gsc_reset(ctx);
1123 	if (ret) {
1124 		pm_runtime_put_autosuspend(ctx->dev);
1125 		ctx->task = NULL;
1126 		return ret;
1127 	}
1128 
1129 	gsc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier);
1130 	gsc_src_set_transf(ctx, task->transform.rotation);
1131 	gsc_src_set_size(ctx, &task->src);
1132 	gsc_src_set_addr(ctx, 0, &task->src);
1133 	gsc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier);
1134 	gsc_dst_set_size(ctx, &task->dst);
1135 	gsc_dst_set_addr(ctx, 0, &task->dst);
1136 	gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
1137 	gsc_start(ctx);
1138 
1139 	return 0;
1140 }
1141 
1142 static void gsc_abort(struct exynos_drm_ipp *ipp,
1143 			  struct exynos_drm_ipp_task *task)
1144 {
1145 	struct gsc_context *ctx =
1146 			container_of(ipp, struct gsc_context, ipp);
1147 
1148 	gsc_reset(ctx);
1149 	if (ctx->task) {
1150 		struct exynos_drm_ipp_task *task = ctx->task;
1151 
1152 		ctx->task = NULL;
1153 		pm_runtime_mark_last_busy(ctx->dev);
1154 		pm_runtime_put_autosuspend(ctx->dev);
1155 		exynos_drm_ipp_task_done(task, -EIO);
1156 	}
1157 }
1158 
1159 static struct exynos_drm_ipp_funcs ipp_funcs = {
1160 	.commit = gsc_commit,
1161 	.abort = gsc_abort,
1162 };
1163 
1164 static int gsc_bind(struct device *dev, struct device *master, void *data)
1165 {
1166 	struct gsc_context *ctx = dev_get_drvdata(dev);
1167 	struct drm_device *drm_dev = data;
1168 	struct exynos_drm_ipp *ipp = &ctx->ipp;
1169 
1170 	ctx->drm_dev = drm_dev;
1171 	ctx->drm_dev = drm_dev;
1172 	exynos_drm_register_dma(drm_dev, dev);
1173 
1174 	exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
1175 			DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
1176 			DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
1177 			ctx->formats, ctx->num_formats, "gsc");
1178 
1179 	dev_info(dev, "The exynos gscaler has been probed successfully\n");
1180 
1181 	return 0;
1182 }
1183 
1184 static void gsc_unbind(struct device *dev, struct device *master,
1185 			void *data)
1186 {
1187 	struct gsc_context *ctx = dev_get_drvdata(dev);
1188 	struct drm_device *drm_dev = data;
1189 	struct exynos_drm_ipp *ipp = &ctx->ipp;
1190 
1191 	exynos_drm_ipp_unregister(dev, ipp);
1192 	exynos_drm_unregister_dma(drm_dev, dev);
1193 }
1194 
1195 static const struct component_ops gsc_component_ops = {
1196 	.bind	= gsc_bind,
1197 	.unbind = gsc_unbind,
1198 };
1199 
1200 static const unsigned int gsc_formats[] = {
1201 	DRM_FORMAT_ARGB8888,
1202 	DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888,
1203 	DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
1204 	DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
1205 	DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
1206 };
1207 
1208 static const unsigned int gsc_tiled_formats[] = {
1209 	DRM_FORMAT_NV12, DRM_FORMAT_NV21,
1210 };
1211 
1212 static int gsc_probe(struct platform_device *pdev)
1213 {
1214 	struct device *dev = &pdev->dev;
1215 	struct gsc_driverdata *driver_data;
1216 	struct exynos_drm_ipp_formats *formats;
1217 	struct gsc_context *ctx;
1218 	struct resource *res;
1219 	int num_formats, ret, i, j;
1220 
1221 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1222 	if (!ctx)
1223 		return -ENOMEM;
1224 
1225 	driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev);
1226 	ctx->dev = dev;
1227 	ctx->num_clocks = driver_data->num_clocks;
1228 	ctx->clk_names = driver_data->clk_names;
1229 
1230 	/* construct formats/limits array */
1231 	num_formats = ARRAY_SIZE(gsc_formats) + ARRAY_SIZE(gsc_tiled_formats);
1232 	formats = devm_kcalloc(dev, num_formats, sizeof(*formats), GFP_KERNEL);
1233 	if (!formats)
1234 		return -ENOMEM;
1235 
1236 	/* linear formats */
1237 	for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) {
1238 		formats[i].fourcc = gsc_formats[i];
1239 		formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1240 				  DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1241 		formats[i].limits = driver_data->limits;
1242 		formats[i].num_limits = driver_data->num_limits;
1243 	}
1244 
1245 	/* tiled formats */
1246 	for (j = i, i = 0; i < ARRAY_SIZE(gsc_tiled_formats); j++, i++) {
1247 		formats[j].fourcc = gsc_tiled_formats[i];
1248 		formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_16_16_TILE;
1249 		formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1250 				  DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1251 		formats[j].limits = driver_data->limits;
1252 		formats[j].num_limits = driver_data->num_limits;
1253 	}
1254 
1255 	ctx->formats = formats;
1256 	ctx->num_formats = num_formats;
1257 
1258 	/* clock control */
1259 	for (i = 0; i < ctx->num_clocks; i++) {
1260 		ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
1261 		if (IS_ERR(ctx->clocks[i])) {
1262 			dev_err(dev, "failed to get clock: %s\n",
1263 				ctx->clk_names[i]);
1264 			return PTR_ERR(ctx->clocks[i]);
1265 		}
1266 	}
1267 
1268 	/* resource memory */
1269 	ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1270 	ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1271 	if (IS_ERR(ctx->regs))
1272 		return PTR_ERR(ctx->regs);
1273 
1274 	/* resource irq */
1275 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1276 	if (!res) {
1277 		dev_err(dev, "failed to request irq resource.\n");
1278 		return -ENOENT;
1279 	}
1280 
1281 	ctx->irq = res->start;
1282 	ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0,
1283 			       dev_name(dev), ctx);
1284 	if (ret < 0) {
1285 		dev_err(dev, "failed to request irq.\n");
1286 		return ret;
1287 	}
1288 
1289 	/* context initailization */
1290 	ctx->id = pdev->id;
1291 
1292 	platform_set_drvdata(pdev, ctx);
1293 
1294 	pm_runtime_use_autosuspend(dev);
1295 	pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY);
1296 	pm_runtime_enable(dev);
1297 
1298 	ret = component_add(dev, &gsc_component_ops);
1299 	if (ret)
1300 		goto err_pm_dis;
1301 
1302 	dev_info(dev, "drm gsc registered successfully.\n");
1303 
1304 	return 0;
1305 
1306 err_pm_dis:
1307 	pm_runtime_dont_use_autosuspend(dev);
1308 	pm_runtime_disable(dev);
1309 	return ret;
1310 }
1311 
1312 static int gsc_remove(struct platform_device *pdev)
1313 {
1314 	struct device *dev = &pdev->dev;
1315 
1316 	pm_runtime_dont_use_autosuspend(dev);
1317 	pm_runtime_disable(dev);
1318 
1319 	return 0;
1320 }
1321 
1322 static int __maybe_unused gsc_runtime_suspend(struct device *dev)
1323 {
1324 	struct gsc_context *ctx = get_gsc_context(dev);
1325 	int i;
1326 
1327 	DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1328 
1329 	for (i = ctx->num_clocks - 1; i >= 0; i--)
1330 		clk_disable_unprepare(ctx->clocks[i]);
1331 
1332 	return 0;
1333 }
1334 
1335 static int __maybe_unused gsc_runtime_resume(struct device *dev)
1336 {
1337 	struct gsc_context *ctx = get_gsc_context(dev);
1338 	int i, ret;
1339 
1340 	DRM_DEV_DEBUG_KMS(dev, "id[%d]\n", ctx->id);
1341 
1342 	for (i = 0; i < ctx->num_clocks; i++) {
1343 		ret = clk_prepare_enable(ctx->clocks[i]);
1344 		if (ret) {
1345 			while (--i > 0)
1346 				clk_disable_unprepare(ctx->clocks[i]);
1347 			return ret;
1348 		}
1349 	}
1350 	return 0;
1351 }
1352 
1353 static const struct dev_pm_ops gsc_pm_ops = {
1354 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1355 				pm_runtime_force_resume)
1356 	SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1357 };
1358 
1359 static const struct drm_exynos_ipp_limit gsc_5250_limits[] = {
1360 	{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1361 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1362 	{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
1363 	{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1364 			  .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1365 };
1366 
1367 static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
1368 	{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1369 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1370 	{ IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
1371 	{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1372 			  .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1373 };
1374 
1375 static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
1376 	{ IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
1377 	{ IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
1378 	{ IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
1379 	{ IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1380 			  .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1381 };
1382 
1383 static struct gsc_driverdata gsc_exynos5250_drvdata = {
1384 	.clk_names = {"gscl"},
1385 	.num_clocks = 1,
1386 	.limits = gsc_5250_limits,
1387 	.num_limits = ARRAY_SIZE(gsc_5250_limits),
1388 };
1389 
1390 static struct gsc_driverdata gsc_exynos5420_drvdata = {
1391 	.clk_names = {"gscl"},
1392 	.num_clocks = 1,
1393 	.limits = gsc_5420_limits,
1394 	.num_limits = ARRAY_SIZE(gsc_5420_limits),
1395 };
1396 
1397 static struct gsc_driverdata gsc_exynos5433_drvdata = {
1398 	.clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
1399 	.num_clocks = 4,
1400 	.limits = gsc_5433_limits,
1401 	.num_limits = ARRAY_SIZE(gsc_5433_limits),
1402 };
1403 
1404 static const struct of_device_id exynos_drm_gsc_of_match[] = {
1405 	{
1406 		.compatible = "samsung,exynos5-gsc",
1407 		.data = &gsc_exynos5250_drvdata,
1408 	}, {
1409 		.compatible = "samsung,exynos5250-gsc",
1410 		.data = &gsc_exynos5250_drvdata,
1411 	}, {
1412 		.compatible = "samsung,exynos5420-gsc",
1413 		.data = &gsc_exynos5420_drvdata,
1414 	}, {
1415 		.compatible = "samsung,exynos5433-gsc",
1416 		.data = &gsc_exynos5433_drvdata,
1417 	}, {
1418 	},
1419 };
1420 MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
1421 
1422 struct platform_driver gsc_driver = {
1423 	.probe		= gsc_probe,
1424 	.remove		= gsc_remove,
1425 	.driver		= {
1426 		.name	= "exynos-drm-gsc",
1427 		.owner	= THIS_MODULE,
1428 		.pm	= &gsc_pm_ops,
1429 		.of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
1430 	},
1431 };
1432