1 /* 2 * Copyright (C) 2012 Samsung Electronics Co.Ltd 3 * Authors: 4 * Eunchul Kim <chulspro.kim@samsung.com> 5 * Jinyoung Jeon <jy0.jeon@samsung.com> 6 * Sangmin Lee <lsmin.lee@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/platform_device.h> 16 #include <linux/clk.h> 17 #include <linux/pm_runtime.h> 18 #include <plat/map-base.h> 19 20 #include <drm/drmP.h> 21 #include <drm/exynos_drm.h> 22 #include "regs-gsc.h" 23 #include "exynos_drm_drv.h" 24 #include "exynos_drm_ipp.h" 25 #include "exynos_drm_gsc.h" 26 27 /* 28 * GSC stands for General SCaler and 29 * supports image scaler/rotator and input/output DMA operations. 30 * input DMA reads image data from the memory. 31 * output DMA writes image data to memory. 32 * GSC supports image rotation and image effect functions. 33 * 34 * M2M operation : supports crop/scale/rotation/csc so on. 35 * Memory ----> GSC H/W ----> Memory. 36 * Writeback operation : supports cloned screen with FIMD. 37 * FIMD ----> GSC H/W ----> Memory. 38 * Output operation : supports direct display using local path. 39 * Memory ----> GSC H/W ----> FIMD, Mixer. 40 */ 41 42 /* 43 * TODO 44 * 1. check suspend/resume api if needed. 45 * 2. need to check use case platform_device_id. 46 * 3. check src/dst size with, height. 47 * 4. added check_prepare api for right register. 48 * 5. need to add supported list in prop_list. 49 * 6. check prescaler/scaler optimization. 50 */ 51 52 #define GSC_MAX_DEVS 4 53 #define GSC_MAX_SRC 4 54 #define GSC_MAX_DST 16 55 #define GSC_RESET_TIMEOUT 50 56 #define GSC_BUF_STOP 1 57 #define GSC_BUF_START 2 58 #define GSC_REG_SZ 16 59 #define GSC_WIDTH_ITU_709 1280 60 #define GSC_SC_UP_MAX_RATIO 65536 61 #define GSC_SC_DOWN_RATIO_7_8 74898 62 #define GSC_SC_DOWN_RATIO_6_8 87381 63 #define GSC_SC_DOWN_RATIO_5_8 104857 64 #define GSC_SC_DOWN_RATIO_4_8 131072 65 #define GSC_SC_DOWN_RATIO_3_8 174762 66 #define GSC_SC_DOWN_RATIO_2_8 262144 67 #define GSC_REFRESH_MIN 12 68 #define GSC_REFRESH_MAX 60 69 #define GSC_CROP_MAX 8192 70 #define GSC_CROP_MIN 32 71 #define GSC_SCALE_MAX 4224 72 #define GSC_SCALE_MIN 32 73 #define GSC_COEF_RATIO 7 74 #define GSC_COEF_PHASE 9 75 #define GSC_COEF_ATTR 16 76 #define GSC_COEF_H_8T 8 77 #define GSC_COEF_V_4T 4 78 #define GSC_COEF_DEPTH 3 79 80 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev)) 81 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ 82 struct gsc_context, ippdrv); 83 #define gsc_read(offset) readl(ctx->regs + (offset)) 84 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) 85 86 /* 87 * A structure of scaler. 88 * 89 * @range: narrow, wide. 90 * @pre_shfactor: pre sclaer shift factor. 91 * @pre_hratio: horizontal ratio of the prescaler. 92 * @pre_vratio: vertical ratio of the prescaler. 93 * @main_hratio: the main scaler's horizontal ratio. 94 * @main_vratio: the main scaler's vertical ratio. 95 */ 96 struct gsc_scaler { 97 bool range; 98 u32 pre_shfactor; 99 u32 pre_hratio; 100 u32 pre_vratio; 101 unsigned long main_hratio; 102 unsigned long main_vratio; 103 }; 104 105 /* 106 * A structure of scaler capability. 107 * 108 * find user manual 49.2 features. 109 * @tile_w: tile mode or rotation width. 110 * @tile_h: tile mode or rotation height. 111 * @w: other cases width. 112 * @h: other cases height. 113 */ 114 struct gsc_capability { 115 /* tile or rotation */ 116 u32 tile_w; 117 u32 tile_h; 118 /* other cases */ 119 u32 w; 120 u32 h; 121 }; 122 123 /* 124 * A structure of gsc context. 125 * 126 * @ippdrv: prepare initialization using ippdrv. 127 * @regs_res: register resources. 128 * @regs: memory mapped io registers. 129 * @lock: locking of operations. 130 * @gsc_clk: gsc gate clock. 131 * @sc: scaler infomations. 132 * @id: gsc id. 133 * @irq: irq number. 134 * @rotation: supports rotation of src. 135 * @suspended: qos operations. 136 */ 137 struct gsc_context { 138 struct exynos_drm_ippdrv ippdrv; 139 struct resource *regs_res; 140 void __iomem *regs; 141 struct mutex lock; 142 struct clk *gsc_clk; 143 struct gsc_scaler sc; 144 int id; 145 int irq; 146 bool rotation; 147 bool suspended; 148 }; 149 150 /* 8-tap Filter Coefficient */ 151 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = { 152 { /* Ratio <= 65536 (~8:8) */ 153 { 0, 0, 0, 128, 0, 0, 0, 0 }, 154 { -1, 2, -6, 127, 7, -2, 1, 0 }, 155 { -1, 4, -12, 125, 16, -5, 1, 0 }, 156 { -1, 5, -15, 120, 25, -8, 2, 0 }, 157 { -1, 6, -18, 114, 35, -10, 3, -1 }, 158 { -1, 6, -20, 107, 46, -13, 4, -1 }, 159 { -2, 7, -21, 99, 57, -16, 5, -1 }, 160 { -1, 6, -20, 89, 68, -18, 5, -1 }, 161 { -1, 6, -20, 79, 79, -20, 6, -1 }, 162 { -1, 5, -18, 68, 89, -20, 6, -1 }, 163 { -1, 5, -16, 57, 99, -21, 7, -2 }, 164 { -1, 4, -13, 46, 107, -20, 6, -1 }, 165 { -1, 3, -10, 35, 114, -18, 6, -1 }, 166 { 0, 2, -8, 25, 120, -15, 5, -1 }, 167 { 0, 1, -5, 16, 125, -12, 4, -1 }, 168 { 0, 1, -2, 7, 127, -6, 2, -1 } 169 }, { /* 65536 < Ratio <= 74898 (~8:7) */ 170 { 3, -8, 14, 111, 13, -8, 3, 0 }, 171 { 2, -6, 7, 112, 21, -10, 3, -1 }, 172 { 2, -4, 1, 110, 28, -12, 4, -1 }, 173 { 1, -2, -3, 106, 36, -13, 4, -1 }, 174 { 1, -1, -7, 103, 44, -15, 4, -1 }, 175 { 1, 1, -11, 97, 53, -16, 4, -1 }, 176 { 0, 2, -13, 91, 61, -16, 4, -1 }, 177 { 0, 3, -15, 85, 69, -17, 4, -1 }, 178 { 0, 3, -16, 77, 77, -16, 3, 0 }, 179 { -1, 4, -17, 69, 85, -15, 3, 0 }, 180 { -1, 4, -16, 61, 91, -13, 2, 0 }, 181 { -1, 4, -16, 53, 97, -11, 1, 1 }, 182 { -1, 4, -15, 44, 103, -7, -1, 1 }, 183 { -1, 4, -13, 36, 106, -3, -2, 1 }, 184 { -1, 4, -12, 28, 110, 1, -4, 2 }, 185 { -1, 3, -10, 21, 112, 7, -6, 2 } 186 }, { /* 74898 < Ratio <= 87381 (~8:6) */ 187 { 2, -11, 25, 96, 25, -11, 2, 0 }, 188 { 2, -10, 19, 96, 31, -12, 2, 0 }, 189 { 2, -9, 14, 94, 37, -12, 2, 0 }, 190 { 2, -8, 10, 92, 43, -12, 1, 0 }, 191 { 2, -7, 5, 90, 49, -12, 1, 0 }, 192 { 2, -5, 1, 86, 55, -12, 0, 1 }, 193 { 2, -4, -2, 82, 61, -11, -1, 1 }, 194 { 1, -3, -5, 77, 67, -9, -1, 1 }, 195 { 1, -2, -7, 72, 72, -7, -2, 1 }, 196 { 1, -1, -9, 67, 77, -5, -3, 1 }, 197 { 1, -1, -11, 61, 82, -2, -4, 2 }, 198 { 1, 0, -12, 55, 86, 1, -5, 2 }, 199 { 0, 1, -12, 49, 90, 5, -7, 2 }, 200 { 0, 1, -12, 43, 92, 10, -8, 2 }, 201 { 0, 2, -12, 37, 94, 14, -9, 2 }, 202 { 0, 2, -12, 31, 96, 19, -10, 2 } 203 }, { /* 87381 < Ratio <= 104857 (~8:5) */ 204 { -1, -8, 33, 80, 33, -8, -1, 0 }, 205 { -1, -8, 28, 80, 37, -7, -2, 1 }, 206 { 0, -8, 24, 79, 41, -7, -2, 1 }, 207 { 0, -8, 20, 78, 46, -6, -3, 1 }, 208 { 0, -8, 16, 76, 50, -4, -3, 1 }, 209 { 0, -7, 13, 74, 54, -3, -4, 1 }, 210 { 1, -7, 10, 71, 58, -1, -5, 1 }, 211 { 1, -6, 6, 68, 62, 1, -5, 1 }, 212 { 1, -6, 4, 65, 65, 4, -6, 1 }, 213 { 1, -5, 1, 62, 68, 6, -6, 1 }, 214 { 1, -5, -1, 58, 71, 10, -7, 1 }, 215 { 1, -4, -3, 54, 74, 13, -7, 0 }, 216 { 1, -3, -4, 50, 76, 16, -8, 0 }, 217 { 1, -3, -6, 46, 78, 20, -8, 0 }, 218 { 1, -2, -7, 41, 79, 24, -8, 0 }, 219 { 1, -2, -7, 37, 80, 28, -8, -1 } 220 }, { /* 104857 < Ratio <= 131072 (~8:4) */ 221 { -3, 0, 35, 64, 35, 0, -3, 0 }, 222 { -3, -1, 32, 64, 38, 1, -3, 0 }, 223 { -2, -2, 29, 63, 41, 2, -3, 0 }, 224 { -2, -3, 27, 63, 43, 4, -4, 0 }, 225 { -2, -3, 24, 61, 46, 6, -4, 0 }, 226 { -2, -3, 21, 60, 49, 7, -4, 0 }, 227 { -1, -4, 19, 59, 51, 9, -4, -1 }, 228 { -1, -4, 16, 57, 53, 12, -4, -1 }, 229 { -1, -4, 14, 55, 55, 14, -4, -1 }, 230 { -1, -4, 12, 53, 57, 16, -4, -1 }, 231 { -1, -4, 9, 51, 59, 19, -4, -1 }, 232 { 0, -4, 7, 49, 60, 21, -3, -2 }, 233 { 0, -4, 6, 46, 61, 24, -3, -2 }, 234 { 0, -4, 4, 43, 63, 27, -3, -2 }, 235 { 0, -3, 2, 41, 63, 29, -2, -2 }, 236 { 0, -3, 1, 38, 64, 32, -1, -3 } 237 }, { /* 131072 < Ratio <= 174762 (~8:3) */ 238 { -1, 8, 33, 48, 33, 8, -1, 0 }, 239 { -1, 7, 31, 49, 35, 9, -1, -1 }, 240 { -1, 6, 30, 49, 36, 10, -1, -1 }, 241 { -1, 5, 28, 48, 38, 12, -1, -1 }, 242 { -1, 4, 26, 48, 39, 13, 0, -1 }, 243 { -1, 3, 24, 47, 41, 15, 0, -1 }, 244 { -1, 2, 23, 47, 42, 16, 0, -1 }, 245 { -1, 2, 21, 45, 43, 18, 1, -1 }, 246 { -1, 1, 19, 45, 45, 19, 1, -1 }, 247 { -1, 1, 18, 43, 45, 21, 2, -1 }, 248 { -1, 0, 16, 42, 47, 23, 2, -1 }, 249 { -1, 0, 15, 41, 47, 24, 3, -1 }, 250 { -1, 0, 13, 39, 48, 26, 4, -1 }, 251 { -1, -1, 12, 38, 48, 28, 5, -1 }, 252 { -1, -1, 10, 36, 49, 30, 6, -1 }, 253 { -1, -1, 9, 35, 49, 31, 7, -1 } 254 }, { /* 174762 < Ratio <= 262144 (~8:2) */ 255 { 2, 13, 30, 38, 30, 13, 2, 0 }, 256 { 2, 12, 29, 38, 30, 14, 3, 0 }, 257 { 2, 11, 28, 38, 31, 15, 3, 0 }, 258 { 2, 10, 26, 38, 32, 16, 4, 0 }, 259 { 1, 10, 26, 37, 33, 17, 4, 0 }, 260 { 1, 9, 24, 37, 34, 18, 5, 0 }, 261 { 1, 8, 24, 37, 34, 19, 5, 0 }, 262 { 1, 7, 22, 36, 35, 20, 6, 1 }, 263 { 1, 6, 21, 36, 36, 21, 6, 1 }, 264 { 1, 6, 20, 35, 36, 22, 7, 1 }, 265 { 0, 5, 19, 34, 37, 24, 8, 1 }, 266 { 0, 5, 18, 34, 37, 24, 9, 1 }, 267 { 0, 4, 17, 33, 37, 26, 10, 1 }, 268 { 0, 4, 16, 32, 38, 26, 10, 2 }, 269 { 0, 3, 15, 31, 38, 28, 11, 2 }, 270 { 0, 3, 14, 30, 38, 29, 12, 2 } 271 } 272 }; 273 274 /* 4-tap Filter Coefficient */ 275 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = { 276 { /* Ratio <= 65536 (~8:8) */ 277 { 0, 128, 0, 0 }, 278 { -4, 127, 5, 0 }, 279 { -6, 124, 11, -1 }, 280 { -8, 118, 19, -1 }, 281 { -8, 111, 27, -2 }, 282 { -8, 102, 37, -3 }, 283 { -8, 92, 48, -4 }, 284 { -7, 81, 59, -5 }, 285 { -6, 70, 70, -6 }, 286 { -5, 59, 81, -7 }, 287 { -4, 48, 92, -8 }, 288 { -3, 37, 102, -8 }, 289 { -2, 27, 111, -8 }, 290 { -1, 19, 118, -8 }, 291 { -1, 11, 124, -6 }, 292 { 0, 5, 127, -4 } 293 }, { /* 65536 < Ratio <= 74898 (~8:7) */ 294 { 8, 112, 8, 0 }, 295 { 4, 111, 14, -1 }, 296 { 1, 109, 20, -2 }, 297 { -2, 105, 27, -2 }, 298 { -3, 100, 34, -3 }, 299 { -5, 93, 43, -3 }, 300 { -5, 86, 51, -4 }, 301 { -5, 77, 60, -4 }, 302 { -5, 69, 69, -5 }, 303 { -4, 60, 77, -5 }, 304 { -4, 51, 86, -5 }, 305 { -3, 43, 93, -5 }, 306 { -3, 34, 100, -3 }, 307 { -2, 27, 105, -2 }, 308 { -2, 20, 109, 1 }, 309 { -1, 14, 111, 4 } 310 }, { /* 74898 < Ratio <= 87381 (~8:6) */ 311 { 16, 96, 16, 0 }, 312 { 12, 97, 21, -2 }, 313 { 8, 96, 26, -2 }, 314 { 5, 93, 32, -2 }, 315 { 2, 89, 39, -2 }, 316 { 0, 84, 46, -2 }, 317 { -1, 79, 53, -3 }, 318 { -2, 73, 59, -2 }, 319 { -2, 66, 66, -2 }, 320 { -2, 59, 73, -2 }, 321 { -3, 53, 79, -1 }, 322 { -2, 46, 84, 0 }, 323 { -2, 39, 89, 2 }, 324 { -2, 32, 93, 5 }, 325 { -2, 26, 96, 8 }, 326 { -2, 21, 97, 12 } 327 }, { /* 87381 < Ratio <= 104857 (~8:5) */ 328 { 22, 84, 22, 0 }, 329 { 18, 85, 26, -1 }, 330 { 14, 84, 31, -1 }, 331 { 11, 82, 36, -1 }, 332 { 8, 79, 42, -1 }, 333 { 6, 76, 47, -1 }, 334 { 4, 72, 52, 0 }, 335 { 2, 68, 58, 0 }, 336 { 1, 63, 63, 1 }, 337 { 0, 58, 68, 2 }, 338 { 0, 52, 72, 4 }, 339 { -1, 47, 76, 6 }, 340 { -1, 42, 79, 8 }, 341 { -1, 36, 82, 11 }, 342 { -1, 31, 84, 14 }, 343 { -1, 26, 85, 18 } 344 }, { /* 104857 < Ratio <= 131072 (~8:4) */ 345 { 26, 76, 26, 0 }, 346 { 22, 76, 30, 0 }, 347 { 19, 75, 34, 0 }, 348 { 16, 73, 38, 1 }, 349 { 13, 71, 43, 1 }, 350 { 10, 69, 47, 2 }, 351 { 8, 66, 51, 3 }, 352 { 6, 63, 55, 4 }, 353 { 5, 59, 59, 5 }, 354 { 4, 55, 63, 6 }, 355 { 3, 51, 66, 8 }, 356 { 2, 47, 69, 10 }, 357 { 1, 43, 71, 13 }, 358 { 1, 38, 73, 16 }, 359 { 0, 34, 75, 19 }, 360 { 0, 30, 76, 22 } 361 }, { /* 131072 < Ratio <= 174762 (~8:3) */ 362 { 29, 70, 29, 0 }, 363 { 26, 68, 32, 2 }, 364 { 23, 67, 36, 2 }, 365 { 20, 66, 39, 3 }, 366 { 17, 65, 43, 3 }, 367 { 15, 63, 46, 4 }, 368 { 12, 61, 50, 5 }, 369 { 10, 58, 53, 7 }, 370 { 8, 56, 56, 8 }, 371 { 7, 53, 58, 10 }, 372 { 5, 50, 61, 12 }, 373 { 4, 46, 63, 15 }, 374 { 3, 43, 65, 17 }, 375 { 3, 39, 66, 20 }, 376 { 2, 36, 67, 23 }, 377 { 2, 32, 68, 26 } 378 }, { /* 174762 < Ratio <= 262144 (~8:2) */ 379 { 32, 64, 32, 0 }, 380 { 28, 63, 34, 3 }, 381 { 25, 62, 37, 4 }, 382 { 22, 62, 40, 4 }, 383 { 19, 61, 43, 5 }, 384 { 17, 59, 46, 6 }, 385 { 15, 58, 48, 7 }, 386 { 13, 55, 51, 9 }, 387 { 11, 53, 53, 11 }, 388 { 9, 51, 55, 13 }, 389 { 7, 48, 58, 15 }, 390 { 6, 46, 59, 17 }, 391 { 5, 43, 61, 19 }, 392 { 4, 40, 62, 22 }, 393 { 4, 37, 62, 25 }, 394 { 3, 34, 63, 28 } 395 } 396 }; 397 398 static int gsc_sw_reset(struct gsc_context *ctx) 399 { 400 u32 cfg; 401 int count = GSC_RESET_TIMEOUT; 402 403 /* s/w reset */ 404 cfg = (GSC_SW_RESET_SRESET); 405 gsc_write(cfg, GSC_SW_RESET); 406 407 /* wait s/w reset complete */ 408 while (count--) { 409 cfg = gsc_read(GSC_SW_RESET); 410 if (!cfg) 411 break; 412 usleep_range(1000, 2000); 413 } 414 415 if (cfg) { 416 DRM_ERROR("failed to reset gsc h/w.\n"); 417 return -EBUSY; 418 } 419 420 /* reset sequence */ 421 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); 422 cfg |= (GSC_IN_BASE_ADDR_MASK | 423 GSC_IN_BASE_ADDR_PINGPONG(0)); 424 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); 425 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); 426 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); 427 428 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 429 cfg |= (GSC_OUT_BASE_ADDR_MASK | 430 GSC_OUT_BASE_ADDR_PINGPONG(0)); 431 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); 432 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); 433 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); 434 435 return 0; 436 } 437 438 static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable) 439 { 440 u32 gscblk_cfg; 441 442 gscblk_cfg = readl(SYSREG_GSCBLK_CFG1); 443 444 if (enable) 445 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) | 446 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) | 447 GSC_BLK_SW_RESET_WB_DEST(ctx->id); 448 else 449 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id); 450 451 writel(gscblk_cfg, SYSREG_GSCBLK_CFG1); 452 } 453 454 static void gsc_handle_irq(struct gsc_context *ctx, bool enable, 455 bool overflow, bool done) 456 { 457 u32 cfg; 458 459 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", 460 enable, overflow, done); 461 462 cfg = gsc_read(GSC_IRQ); 463 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK); 464 465 if (enable) 466 cfg |= GSC_IRQ_ENABLE; 467 else 468 cfg &= ~GSC_IRQ_ENABLE; 469 470 if (overflow) 471 cfg &= ~GSC_IRQ_OR_MASK; 472 else 473 cfg |= GSC_IRQ_OR_MASK; 474 475 if (done) 476 cfg &= ~GSC_IRQ_FRMDONE_MASK; 477 else 478 cfg |= GSC_IRQ_FRMDONE_MASK; 479 480 gsc_write(cfg, GSC_IRQ); 481 } 482 483 484 static int gsc_src_set_fmt(struct device *dev, u32 fmt) 485 { 486 struct gsc_context *ctx = get_gsc_context(dev); 487 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 488 u32 cfg; 489 490 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 491 492 cfg = gsc_read(GSC_IN_CON); 493 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK | 494 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK | 495 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE | 496 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK); 497 498 switch (fmt) { 499 case DRM_FORMAT_RGB565: 500 cfg |= GSC_IN_RGB565; 501 break; 502 case DRM_FORMAT_XRGB8888: 503 cfg |= GSC_IN_XRGB8888; 504 break; 505 case DRM_FORMAT_BGRX8888: 506 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP); 507 break; 508 case DRM_FORMAT_YUYV: 509 cfg |= (GSC_IN_YUV422_1P | 510 GSC_IN_YUV422_1P_ORDER_LSB_Y | 511 GSC_IN_CHROMA_ORDER_CBCR); 512 break; 513 case DRM_FORMAT_YVYU: 514 cfg |= (GSC_IN_YUV422_1P | 515 GSC_IN_YUV422_1P_ORDER_LSB_Y | 516 GSC_IN_CHROMA_ORDER_CRCB); 517 break; 518 case DRM_FORMAT_UYVY: 519 cfg |= (GSC_IN_YUV422_1P | 520 GSC_IN_YUV422_1P_OEDER_LSB_C | 521 GSC_IN_CHROMA_ORDER_CBCR); 522 break; 523 case DRM_FORMAT_VYUY: 524 cfg |= (GSC_IN_YUV422_1P | 525 GSC_IN_YUV422_1P_OEDER_LSB_C | 526 GSC_IN_CHROMA_ORDER_CRCB); 527 break; 528 case DRM_FORMAT_NV21: 529 case DRM_FORMAT_NV61: 530 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | 531 GSC_IN_YUV420_2P); 532 break; 533 case DRM_FORMAT_YUV422: 534 cfg |= GSC_IN_YUV422_3P; 535 break; 536 case DRM_FORMAT_YUV420: 537 case DRM_FORMAT_YVU420: 538 cfg |= GSC_IN_YUV420_3P; 539 break; 540 case DRM_FORMAT_NV12: 541 case DRM_FORMAT_NV16: 542 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | 543 GSC_IN_YUV420_2P); 544 break; 545 default: 546 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); 547 return -EINVAL; 548 } 549 550 gsc_write(cfg, GSC_IN_CON); 551 552 return 0; 553 } 554 555 static int gsc_src_set_transf(struct device *dev, 556 enum drm_exynos_degree degree, 557 enum drm_exynos_flip flip, bool *swap) 558 { 559 struct gsc_context *ctx = get_gsc_context(dev); 560 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 561 u32 cfg; 562 563 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 564 565 cfg = gsc_read(GSC_IN_CON); 566 cfg &= ~GSC_IN_ROT_MASK; 567 568 switch (degree) { 569 case EXYNOS_DRM_DEGREE_0: 570 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 571 cfg |= GSC_IN_ROT_XFLIP; 572 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 573 cfg |= GSC_IN_ROT_YFLIP; 574 break; 575 case EXYNOS_DRM_DEGREE_90: 576 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 577 cfg |= GSC_IN_ROT_90_XFLIP; 578 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 579 cfg |= GSC_IN_ROT_90_YFLIP; 580 else 581 cfg |= GSC_IN_ROT_90; 582 break; 583 case EXYNOS_DRM_DEGREE_180: 584 cfg |= GSC_IN_ROT_180; 585 break; 586 case EXYNOS_DRM_DEGREE_270: 587 cfg |= GSC_IN_ROT_270; 588 break; 589 default: 590 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 591 return -EINVAL; 592 } 593 594 gsc_write(cfg, GSC_IN_CON); 595 596 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; 597 *swap = ctx->rotation; 598 599 return 0; 600 } 601 602 static int gsc_src_set_size(struct device *dev, int swap, 603 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 604 { 605 struct gsc_context *ctx = get_gsc_context(dev); 606 struct drm_exynos_pos img_pos = *pos; 607 struct gsc_scaler *sc = &ctx->sc; 608 u32 cfg; 609 610 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n", 611 swap, pos->x, pos->y, pos->w, pos->h); 612 613 if (swap) { 614 img_pos.w = pos->h; 615 img_pos.h = pos->w; 616 } 617 618 /* pixel offset */ 619 cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) | 620 GSC_SRCIMG_OFFSET_Y(img_pos.y)); 621 gsc_write(cfg, GSC_SRCIMG_OFFSET); 622 623 /* cropped size */ 624 cfg = (GSC_CROPPED_WIDTH(img_pos.w) | 625 GSC_CROPPED_HEIGHT(img_pos.h)); 626 gsc_write(cfg, GSC_CROPPED_SIZE); 627 628 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize); 629 630 /* original size */ 631 cfg = gsc_read(GSC_SRCIMG_SIZE); 632 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK | 633 GSC_SRCIMG_WIDTH_MASK); 634 635 cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) | 636 GSC_SRCIMG_HEIGHT(sz->vsize)); 637 638 gsc_write(cfg, GSC_SRCIMG_SIZE); 639 640 cfg = gsc_read(GSC_IN_CON); 641 cfg &= ~GSC_IN_RGB_TYPE_MASK; 642 643 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range); 644 645 if (pos->w >= GSC_WIDTH_ITU_709) 646 if (sc->range) 647 cfg |= GSC_IN_RGB_HD_WIDE; 648 else 649 cfg |= GSC_IN_RGB_HD_NARROW; 650 else 651 if (sc->range) 652 cfg |= GSC_IN_RGB_SD_WIDE; 653 else 654 cfg |= GSC_IN_RGB_SD_NARROW; 655 656 gsc_write(cfg, GSC_IN_CON); 657 658 return 0; 659 } 660 661 static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id, 662 enum drm_exynos_ipp_buf_type buf_type) 663 { 664 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 665 bool masked; 666 u32 cfg; 667 u32 mask = 0x00000001 << buf_id; 668 669 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); 670 671 /* mask register set */ 672 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); 673 674 switch (buf_type) { 675 case IPP_BUF_ENQUEUE: 676 masked = false; 677 break; 678 case IPP_BUF_DEQUEUE: 679 masked = true; 680 break; 681 default: 682 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); 683 return -EINVAL; 684 } 685 686 /* sequence id */ 687 cfg &= ~mask; 688 cfg |= masked << buf_id; 689 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); 690 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); 691 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); 692 693 return 0; 694 } 695 696 static int gsc_src_set_addr(struct device *dev, 697 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 698 enum drm_exynos_ipp_buf_type buf_type) 699 { 700 struct gsc_context *ctx = get_gsc_context(dev); 701 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 702 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 703 struct drm_exynos_ipp_property *property; 704 705 if (!c_node) { 706 DRM_ERROR("failed to get c_node.\n"); 707 return -EFAULT; 708 } 709 710 property = &c_node->property; 711 712 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 713 property->prop_id, buf_id, buf_type); 714 715 if (buf_id > GSC_MAX_SRC) { 716 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 717 return -EINVAL; 718 } 719 720 /* address register set */ 721 switch (buf_type) { 722 case IPP_BUF_ENQUEUE: 723 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 724 GSC_IN_BASE_ADDR_Y(buf_id)); 725 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 726 GSC_IN_BASE_ADDR_CB(buf_id)); 727 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 728 GSC_IN_BASE_ADDR_CR(buf_id)); 729 break; 730 case IPP_BUF_DEQUEUE: 731 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id)); 732 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id)); 733 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id)); 734 break; 735 default: 736 /* bypass */ 737 break; 738 } 739 740 return gsc_src_set_buf_seq(ctx, buf_id, buf_type); 741 } 742 743 static struct exynos_drm_ipp_ops gsc_src_ops = { 744 .set_fmt = gsc_src_set_fmt, 745 .set_transf = gsc_src_set_transf, 746 .set_size = gsc_src_set_size, 747 .set_addr = gsc_src_set_addr, 748 }; 749 750 static int gsc_dst_set_fmt(struct device *dev, u32 fmt) 751 { 752 struct gsc_context *ctx = get_gsc_context(dev); 753 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 754 u32 cfg; 755 756 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 757 758 cfg = gsc_read(GSC_OUT_CON); 759 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK | 760 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK | 761 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK | 762 GSC_OUT_GLOBAL_ALPHA_MASK); 763 764 switch (fmt) { 765 case DRM_FORMAT_RGB565: 766 cfg |= GSC_OUT_RGB565; 767 break; 768 case DRM_FORMAT_XRGB8888: 769 cfg |= GSC_OUT_XRGB8888; 770 break; 771 case DRM_FORMAT_BGRX8888: 772 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP); 773 break; 774 case DRM_FORMAT_YUYV: 775 cfg |= (GSC_OUT_YUV422_1P | 776 GSC_OUT_YUV422_1P_ORDER_LSB_Y | 777 GSC_OUT_CHROMA_ORDER_CBCR); 778 break; 779 case DRM_FORMAT_YVYU: 780 cfg |= (GSC_OUT_YUV422_1P | 781 GSC_OUT_YUV422_1P_ORDER_LSB_Y | 782 GSC_OUT_CHROMA_ORDER_CRCB); 783 break; 784 case DRM_FORMAT_UYVY: 785 cfg |= (GSC_OUT_YUV422_1P | 786 GSC_OUT_YUV422_1P_OEDER_LSB_C | 787 GSC_OUT_CHROMA_ORDER_CBCR); 788 break; 789 case DRM_FORMAT_VYUY: 790 cfg |= (GSC_OUT_YUV422_1P | 791 GSC_OUT_YUV422_1P_OEDER_LSB_C | 792 GSC_OUT_CHROMA_ORDER_CRCB); 793 break; 794 case DRM_FORMAT_NV21: 795 case DRM_FORMAT_NV61: 796 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P); 797 break; 798 case DRM_FORMAT_YUV422: 799 case DRM_FORMAT_YUV420: 800 case DRM_FORMAT_YVU420: 801 cfg |= GSC_OUT_YUV420_3P; 802 break; 803 case DRM_FORMAT_NV12: 804 case DRM_FORMAT_NV16: 805 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | 806 GSC_OUT_YUV420_2P); 807 break; 808 default: 809 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); 810 return -EINVAL; 811 } 812 813 gsc_write(cfg, GSC_OUT_CON); 814 815 return 0; 816 } 817 818 static int gsc_dst_set_transf(struct device *dev, 819 enum drm_exynos_degree degree, 820 enum drm_exynos_flip flip, bool *swap) 821 { 822 struct gsc_context *ctx = get_gsc_context(dev); 823 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 824 u32 cfg; 825 826 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 827 828 cfg = gsc_read(GSC_IN_CON); 829 cfg &= ~GSC_IN_ROT_MASK; 830 831 switch (degree) { 832 case EXYNOS_DRM_DEGREE_0: 833 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 834 cfg |= GSC_IN_ROT_XFLIP; 835 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 836 cfg |= GSC_IN_ROT_YFLIP; 837 break; 838 case EXYNOS_DRM_DEGREE_90: 839 if (flip & EXYNOS_DRM_FLIP_VERTICAL) 840 cfg |= GSC_IN_ROT_90_XFLIP; 841 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 842 cfg |= GSC_IN_ROT_90_YFLIP; 843 else 844 cfg |= GSC_IN_ROT_90; 845 break; 846 case EXYNOS_DRM_DEGREE_180: 847 cfg |= GSC_IN_ROT_180; 848 break; 849 case EXYNOS_DRM_DEGREE_270: 850 cfg |= GSC_IN_ROT_270; 851 break; 852 default: 853 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 854 return -EINVAL; 855 } 856 857 gsc_write(cfg, GSC_IN_CON); 858 859 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; 860 *swap = ctx->rotation; 861 862 return 0; 863 } 864 865 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio) 866 { 867 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst); 868 869 if (src >= dst * 8) { 870 DRM_ERROR("failed to make ratio and shift.\n"); 871 return -EINVAL; 872 } else if (src >= dst * 4) 873 *ratio = 4; 874 else if (src >= dst * 2) 875 *ratio = 2; 876 else 877 *ratio = 1; 878 879 return 0; 880 } 881 882 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor) 883 { 884 if (hratio == 4 && vratio == 4) 885 *shfactor = 4; 886 else if ((hratio == 4 && vratio == 2) || 887 (hratio == 2 && vratio == 4)) 888 *shfactor = 3; 889 else if ((hratio == 4 && vratio == 1) || 890 (hratio == 1 && vratio == 4) || 891 (hratio == 2 && vratio == 2)) 892 *shfactor = 2; 893 else if (hratio == 1 && vratio == 1) 894 *shfactor = 0; 895 else 896 *shfactor = 1; 897 } 898 899 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc, 900 struct drm_exynos_pos *src, struct drm_exynos_pos *dst) 901 { 902 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 903 u32 cfg; 904 u32 src_w, src_h, dst_w, dst_h; 905 int ret = 0; 906 907 src_w = src->w; 908 src_h = src->h; 909 910 if (ctx->rotation) { 911 dst_w = dst->h; 912 dst_h = dst->w; 913 } else { 914 dst_w = dst->w; 915 dst_h = dst->h; 916 } 917 918 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio); 919 if (ret) { 920 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); 921 return ret; 922 } 923 924 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio); 925 if (ret) { 926 dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); 927 return ret; 928 } 929 930 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n", 931 sc->pre_hratio, sc->pre_vratio); 932 933 sc->main_hratio = (src_w << 16) / dst_w; 934 sc->main_vratio = (src_h << 16) / dst_h; 935 936 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", 937 sc->main_hratio, sc->main_vratio); 938 939 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio, 940 &sc->pre_shfactor); 941 942 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor); 943 944 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) | 945 GSC_PRESC_H_RATIO(sc->pre_hratio) | 946 GSC_PRESC_V_RATIO(sc->pre_vratio)); 947 gsc_write(cfg, GSC_PRE_SCALE_RATIO); 948 949 return ret; 950 } 951 952 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio) 953 { 954 int i, j, k, sc_ratio; 955 956 if (main_hratio <= GSC_SC_UP_MAX_RATIO) 957 sc_ratio = 0; 958 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8) 959 sc_ratio = 1; 960 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8) 961 sc_ratio = 2; 962 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8) 963 sc_ratio = 3; 964 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8) 965 sc_ratio = 4; 966 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8) 967 sc_ratio = 5; 968 else 969 sc_ratio = 6; 970 971 for (i = 0; i < GSC_COEF_PHASE; i++) 972 for (j = 0; j < GSC_COEF_H_8T; j++) 973 for (k = 0; k < GSC_COEF_DEPTH; k++) 974 gsc_write(h_coef_8t[sc_ratio][i][j], 975 GSC_HCOEF(i, j, k)); 976 } 977 978 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio) 979 { 980 int i, j, k, sc_ratio; 981 982 if (main_vratio <= GSC_SC_UP_MAX_RATIO) 983 sc_ratio = 0; 984 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8) 985 sc_ratio = 1; 986 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8) 987 sc_ratio = 2; 988 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8) 989 sc_ratio = 3; 990 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8) 991 sc_ratio = 4; 992 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8) 993 sc_ratio = 5; 994 else 995 sc_ratio = 6; 996 997 for (i = 0; i < GSC_COEF_PHASE; i++) 998 for (j = 0; j < GSC_COEF_V_4T; j++) 999 for (k = 0; k < GSC_COEF_DEPTH; k++) 1000 gsc_write(v_coef_4t[sc_ratio][i][j], 1001 GSC_VCOEF(i, j, k)); 1002 } 1003 1004 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc) 1005 { 1006 u32 cfg; 1007 1008 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", 1009 sc->main_hratio, sc->main_vratio); 1010 1011 gsc_set_h_coef(ctx, sc->main_hratio); 1012 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio); 1013 gsc_write(cfg, GSC_MAIN_H_RATIO); 1014 1015 gsc_set_v_coef(ctx, sc->main_vratio); 1016 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio); 1017 gsc_write(cfg, GSC_MAIN_V_RATIO); 1018 } 1019 1020 static int gsc_dst_set_size(struct device *dev, int swap, 1021 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 1022 { 1023 struct gsc_context *ctx = get_gsc_context(dev); 1024 struct drm_exynos_pos img_pos = *pos; 1025 struct gsc_scaler *sc = &ctx->sc; 1026 u32 cfg; 1027 1028 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n", 1029 swap, pos->x, pos->y, pos->w, pos->h); 1030 1031 if (swap) { 1032 img_pos.w = pos->h; 1033 img_pos.h = pos->w; 1034 } 1035 1036 /* pixel offset */ 1037 cfg = (GSC_DSTIMG_OFFSET_X(pos->x) | 1038 GSC_DSTIMG_OFFSET_Y(pos->y)); 1039 gsc_write(cfg, GSC_DSTIMG_OFFSET); 1040 1041 /* scaled size */ 1042 cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h)); 1043 gsc_write(cfg, GSC_SCALED_SIZE); 1044 1045 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize); 1046 1047 /* original size */ 1048 cfg = gsc_read(GSC_DSTIMG_SIZE); 1049 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | 1050 GSC_DSTIMG_WIDTH_MASK); 1051 cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) | 1052 GSC_DSTIMG_HEIGHT(sz->vsize)); 1053 gsc_write(cfg, GSC_DSTIMG_SIZE); 1054 1055 cfg = gsc_read(GSC_OUT_CON); 1056 cfg &= ~GSC_OUT_RGB_TYPE_MASK; 1057 1058 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range); 1059 1060 if (pos->w >= GSC_WIDTH_ITU_709) 1061 if (sc->range) 1062 cfg |= GSC_OUT_RGB_HD_WIDE; 1063 else 1064 cfg |= GSC_OUT_RGB_HD_NARROW; 1065 else 1066 if (sc->range) 1067 cfg |= GSC_OUT_RGB_SD_WIDE; 1068 else 1069 cfg |= GSC_OUT_RGB_SD_NARROW; 1070 1071 gsc_write(cfg, GSC_OUT_CON); 1072 1073 return 0; 1074 } 1075 1076 static int gsc_dst_get_buf_seq(struct gsc_context *ctx) 1077 { 1078 u32 cfg, i, buf_num = GSC_REG_SZ; 1079 u32 mask = 0x00000001; 1080 1081 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 1082 1083 for (i = 0; i < GSC_REG_SZ; i++) 1084 if (cfg & (mask << i)) 1085 buf_num--; 1086 1087 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); 1088 1089 return buf_num; 1090 } 1091 1092 static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id, 1093 enum drm_exynos_ipp_buf_type buf_type) 1094 { 1095 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1096 bool masked; 1097 u32 cfg; 1098 u32 mask = 0x00000001 << buf_id; 1099 int ret = 0; 1100 1101 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); 1102 1103 mutex_lock(&ctx->lock); 1104 1105 /* mask register set */ 1106 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 1107 1108 switch (buf_type) { 1109 case IPP_BUF_ENQUEUE: 1110 masked = false; 1111 break; 1112 case IPP_BUF_DEQUEUE: 1113 masked = true; 1114 break; 1115 default: 1116 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); 1117 ret = -EINVAL; 1118 goto err_unlock; 1119 } 1120 1121 /* sequence id */ 1122 cfg &= ~mask; 1123 cfg |= masked << buf_id; 1124 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); 1125 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); 1126 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); 1127 1128 /* interrupt enable */ 1129 if (buf_type == IPP_BUF_ENQUEUE && 1130 gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START) 1131 gsc_handle_irq(ctx, true, false, true); 1132 1133 /* interrupt disable */ 1134 if (buf_type == IPP_BUF_DEQUEUE && 1135 gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP) 1136 gsc_handle_irq(ctx, false, false, true); 1137 1138 err_unlock: 1139 mutex_unlock(&ctx->lock); 1140 return ret; 1141 } 1142 1143 static int gsc_dst_set_addr(struct device *dev, 1144 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 1145 enum drm_exynos_ipp_buf_type buf_type) 1146 { 1147 struct gsc_context *ctx = get_gsc_context(dev); 1148 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1149 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 1150 struct drm_exynos_ipp_property *property; 1151 1152 if (!c_node) { 1153 DRM_ERROR("failed to get c_node.\n"); 1154 return -EFAULT; 1155 } 1156 1157 property = &c_node->property; 1158 1159 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 1160 property->prop_id, buf_id, buf_type); 1161 1162 if (buf_id > GSC_MAX_DST) { 1163 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 1164 return -EINVAL; 1165 } 1166 1167 /* address register set */ 1168 switch (buf_type) { 1169 case IPP_BUF_ENQUEUE: 1170 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 1171 GSC_OUT_BASE_ADDR_Y(buf_id)); 1172 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 1173 GSC_OUT_BASE_ADDR_CB(buf_id)); 1174 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 1175 GSC_OUT_BASE_ADDR_CR(buf_id)); 1176 break; 1177 case IPP_BUF_DEQUEUE: 1178 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id)); 1179 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id)); 1180 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id)); 1181 break; 1182 default: 1183 /* bypass */ 1184 break; 1185 } 1186 1187 return gsc_dst_set_buf_seq(ctx, buf_id, buf_type); 1188 } 1189 1190 static struct exynos_drm_ipp_ops gsc_dst_ops = { 1191 .set_fmt = gsc_dst_set_fmt, 1192 .set_transf = gsc_dst_set_transf, 1193 .set_size = gsc_dst_set_size, 1194 .set_addr = gsc_dst_set_addr, 1195 }; 1196 1197 static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable) 1198 { 1199 DRM_DEBUG_KMS("enable[%d]\n", enable); 1200 1201 if (enable) { 1202 clk_enable(ctx->gsc_clk); 1203 ctx->suspended = false; 1204 } else { 1205 clk_disable(ctx->gsc_clk); 1206 ctx->suspended = true; 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int gsc_get_src_buf_index(struct gsc_context *ctx) 1213 { 1214 u32 cfg, curr_index, i; 1215 u32 buf_id = GSC_MAX_SRC; 1216 int ret; 1217 1218 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); 1219 1220 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); 1221 curr_index = GSC_IN_CURR_GET_INDEX(cfg); 1222 1223 for (i = curr_index; i < GSC_MAX_SRC; i++) { 1224 if (!((cfg >> i) & 0x1)) { 1225 buf_id = i; 1226 break; 1227 } 1228 } 1229 1230 if (buf_id == GSC_MAX_SRC) { 1231 DRM_ERROR("failed to get in buffer index.\n"); 1232 return -EINVAL; 1233 } 1234 1235 ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE); 1236 if (ret < 0) { 1237 DRM_ERROR("failed to dequeue.\n"); 1238 return ret; 1239 } 1240 1241 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, 1242 curr_index, buf_id); 1243 1244 return buf_id; 1245 } 1246 1247 static int gsc_get_dst_buf_index(struct gsc_context *ctx) 1248 { 1249 u32 cfg, curr_index, i; 1250 u32 buf_id = GSC_MAX_DST; 1251 int ret; 1252 1253 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); 1254 1255 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); 1256 curr_index = GSC_OUT_CURR_GET_INDEX(cfg); 1257 1258 for (i = curr_index; i < GSC_MAX_DST; i++) { 1259 if (!((cfg >> i) & 0x1)) { 1260 buf_id = i; 1261 break; 1262 } 1263 } 1264 1265 if (buf_id == GSC_MAX_DST) { 1266 DRM_ERROR("failed to get out buffer index.\n"); 1267 return -EINVAL; 1268 } 1269 1270 ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE); 1271 if (ret < 0) { 1272 DRM_ERROR("failed to dequeue.\n"); 1273 return ret; 1274 } 1275 1276 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, 1277 curr_index, buf_id); 1278 1279 return buf_id; 1280 } 1281 1282 static irqreturn_t gsc_irq_handler(int irq, void *dev_id) 1283 { 1284 struct gsc_context *ctx = dev_id; 1285 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1286 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 1287 struct drm_exynos_ipp_event_work *event_work = 1288 c_node->event_work; 1289 u32 status; 1290 int buf_id[EXYNOS_DRM_OPS_MAX]; 1291 1292 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); 1293 1294 status = gsc_read(GSC_IRQ); 1295 if (status & GSC_IRQ_STATUS_OR_IRQ) { 1296 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n", 1297 ctx->id, status); 1298 return IRQ_NONE; 1299 } 1300 1301 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) { 1302 dev_dbg(ippdrv->dev, "occurred frame done at %d, status 0x%x.\n", 1303 ctx->id, status); 1304 1305 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx); 1306 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0) 1307 return IRQ_HANDLED; 1308 1309 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx); 1310 if (buf_id[EXYNOS_DRM_OPS_DST] < 0) 1311 return IRQ_HANDLED; 1312 1313 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n", 1314 buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]); 1315 1316 event_work->ippdrv = ippdrv; 1317 event_work->buf_id[EXYNOS_DRM_OPS_SRC] = 1318 buf_id[EXYNOS_DRM_OPS_SRC]; 1319 event_work->buf_id[EXYNOS_DRM_OPS_DST] = 1320 buf_id[EXYNOS_DRM_OPS_DST]; 1321 queue_work(ippdrv->event_workq, &event_work->work); 1322 } 1323 1324 return IRQ_HANDLED; 1325 } 1326 1327 static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) 1328 { 1329 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list; 1330 1331 prop_list->version = 1; 1332 prop_list->writeback = 1; 1333 prop_list->refresh_min = GSC_REFRESH_MIN; 1334 prop_list->refresh_max = GSC_REFRESH_MAX; 1335 prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) | 1336 (1 << EXYNOS_DRM_FLIP_HORIZONTAL); 1337 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | 1338 (1 << EXYNOS_DRM_DEGREE_90) | 1339 (1 << EXYNOS_DRM_DEGREE_180) | 1340 (1 << EXYNOS_DRM_DEGREE_270); 1341 prop_list->csc = 1; 1342 prop_list->crop = 1; 1343 prop_list->crop_max.hsize = GSC_CROP_MAX; 1344 prop_list->crop_max.vsize = GSC_CROP_MAX; 1345 prop_list->crop_min.hsize = GSC_CROP_MIN; 1346 prop_list->crop_min.vsize = GSC_CROP_MIN; 1347 prop_list->scale = 1; 1348 prop_list->scale_max.hsize = GSC_SCALE_MAX; 1349 prop_list->scale_max.vsize = GSC_SCALE_MAX; 1350 prop_list->scale_min.hsize = GSC_SCALE_MIN; 1351 prop_list->scale_min.vsize = GSC_SCALE_MIN; 1352 1353 return 0; 1354 } 1355 1356 static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip) 1357 { 1358 switch (flip) { 1359 case EXYNOS_DRM_FLIP_NONE: 1360 case EXYNOS_DRM_FLIP_VERTICAL: 1361 case EXYNOS_DRM_FLIP_HORIZONTAL: 1362 case EXYNOS_DRM_FLIP_BOTH: 1363 return true; 1364 default: 1365 DRM_DEBUG_KMS("invalid flip\n"); 1366 return false; 1367 } 1368 } 1369 1370 static int gsc_ippdrv_check_property(struct device *dev, 1371 struct drm_exynos_ipp_property *property) 1372 { 1373 struct gsc_context *ctx = get_gsc_context(dev); 1374 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1375 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list; 1376 struct drm_exynos_ipp_config *config; 1377 struct drm_exynos_pos *pos; 1378 struct drm_exynos_sz *sz; 1379 bool swap; 1380 int i; 1381 1382 for_each_ipp_ops(i) { 1383 if ((i == EXYNOS_DRM_OPS_SRC) && 1384 (property->cmd == IPP_CMD_WB)) 1385 continue; 1386 1387 config = &property->config[i]; 1388 pos = &config->pos; 1389 sz = &config->sz; 1390 1391 /* check for flip */ 1392 if (!gsc_check_drm_flip(config->flip)) { 1393 DRM_ERROR("invalid flip.\n"); 1394 goto err_property; 1395 } 1396 1397 /* check for degree */ 1398 switch (config->degree) { 1399 case EXYNOS_DRM_DEGREE_90: 1400 case EXYNOS_DRM_DEGREE_270: 1401 swap = true; 1402 break; 1403 case EXYNOS_DRM_DEGREE_0: 1404 case EXYNOS_DRM_DEGREE_180: 1405 swap = false; 1406 break; 1407 default: 1408 DRM_ERROR("invalid degree.\n"); 1409 goto err_property; 1410 } 1411 1412 /* check for buffer bound */ 1413 if ((pos->x + pos->w > sz->hsize) || 1414 (pos->y + pos->h > sz->vsize)) { 1415 DRM_ERROR("out of buf bound.\n"); 1416 goto err_property; 1417 } 1418 1419 /* check for crop */ 1420 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { 1421 if (swap) { 1422 if ((pos->h < pp->crop_min.hsize) || 1423 (sz->vsize > pp->crop_max.hsize) || 1424 (pos->w < pp->crop_min.vsize) || 1425 (sz->hsize > pp->crop_max.vsize)) { 1426 DRM_ERROR("out of crop size.\n"); 1427 goto err_property; 1428 } 1429 } else { 1430 if ((pos->w < pp->crop_min.hsize) || 1431 (sz->hsize > pp->crop_max.hsize) || 1432 (pos->h < pp->crop_min.vsize) || 1433 (sz->vsize > pp->crop_max.vsize)) { 1434 DRM_ERROR("out of crop size.\n"); 1435 goto err_property; 1436 } 1437 } 1438 } 1439 1440 /* check for scale */ 1441 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { 1442 if (swap) { 1443 if ((pos->h < pp->scale_min.hsize) || 1444 (sz->vsize > pp->scale_max.hsize) || 1445 (pos->w < pp->scale_min.vsize) || 1446 (sz->hsize > pp->scale_max.vsize)) { 1447 DRM_ERROR("out of scale size.\n"); 1448 goto err_property; 1449 } 1450 } else { 1451 if ((pos->w < pp->scale_min.hsize) || 1452 (sz->hsize > pp->scale_max.hsize) || 1453 (pos->h < pp->scale_min.vsize) || 1454 (sz->vsize > pp->scale_max.vsize)) { 1455 DRM_ERROR("out of scale size.\n"); 1456 goto err_property; 1457 } 1458 } 1459 } 1460 } 1461 1462 return 0; 1463 1464 err_property: 1465 for_each_ipp_ops(i) { 1466 if ((i == EXYNOS_DRM_OPS_SRC) && 1467 (property->cmd == IPP_CMD_WB)) 1468 continue; 1469 1470 config = &property->config[i]; 1471 pos = &config->pos; 1472 sz = &config->sz; 1473 1474 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", 1475 i ? "dst" : "src", config->flip, config->degree, 1476 pos->x, pos->y, pos->w, pos->h, 1477 sz->hsize, sz->vsize); 1478 } 1479 1480 return -EINVAL; 1481 } 1482 1483 1484 static int gsc_ippdrv_reset(struct device *dev) 1485 { 1486 struct gsc_context *ctx = get_gsc_context(dev); 1487 struct gsc_scaler *sc = &ctx->sc; 1488 int ret; 1489 1490 /* reset h/w block */ 1491 ret = gsc_sw_reset(ctx); 1492 if (ret < 0) { 1493 dev_err(dev, "failed to reset hardware.\n"); 1494 return ret; 1495 } 1496 1497 /* scaler setting */ 1498 memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 1499 sc->range = true; 1500 1501 return 0; 1502 } 1503 1504 static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) 1505 { 1506 struct gsc_context *ctx = get_gsc_context(dev); 1507 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1508 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 1509 struct drm_exynos_ipp_property *property; 1510 struct drm_exynos_ipp_config *config; 1511 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; 1512 struct drm_exynos_ipp_set_wb set_wb; 1513 u32 cfg; 1514 int ret, i; 1515 1516 DRM_DEBUG_KMS("cmd[%d]\n", cmd); 1517 1518 if (!c_node) { 1519 DRM_ERROR("failed to get c_node.\n"); 1520 return -EINVAL; 1521 } 1522 1523 property = &c_node->property; 1524 1525 gsc_handle_irq(ctx, true, false, true); 1526 1527 for_each_ipp_ops(i) { 1528 config = &property->config[i]; 1529 img_pos[i] = config->pos; 1530 } 1531 1532 switch (cmd) { 1533 case IPP_CMD_M2M: 1534 /* enable one shot */ 1535 cfg = gsc_read(GSC_ENABLE); 1536 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK | 1537 GSC_ENABLE_CLK_GATE_MODE_MASK); 1538 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT; 1539 gsc_write(cfg, GSC_ENABLE); 1540 1541 /* src dma memory */ 1542 cfg = gsc_read(GSC_IN_CON); 1543 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); 1544 cfg |= GSC_IN_PATH_MEMORY; 1545 gsc_write(cfg, GSC_IN_CON); 1546 1547 /* dst dma memory */ 1548 cfg = gsc_read(GSC_OUT_CON); 1549 cfg |= GSC_OUT_PATH_MEMORY; 1550 gsc_write(cfg, GSC_OUT_CON); 1551 break; 1552 case IPP_CMD_WB: 1553 set_wb.enable = 1; 1554 set_wb.refresh = property->refresh_rate; 1555 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable); 1556 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 1557 1558 /* src local path */ 1559 cfg = gsc_read(GSC_IN_CON); 1560 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); 1561 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB); 1562 gsc_write(cfg, GSC_IN_CON); 1563 1564 /* dst dma memory */ 1565 cfg = gsc_read(GSC_OUT_CON); 1566 cfg |= GSC_OUT_PATH_MEMORY; 1567 gsc_write(cfg, GSC_OUT_CON); 1568 break; 1569 case IPP_CMD_OUTPUT: 1570 /* src dma memory */ 1571 cfg = gsc_read(GSC_IN_CON); 1572 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); 1573 cfg |= GSC_IN_PATH_MEMORY; 1574 gsc_write(cfg, GSC_IN_CON); 1575 1576 /* dst local path */ 1577 cfg = gsc_read(GSC_OUT_CON); 1578 cfg |= GSC_OUT_PATH_MEMORY; 1579 gsc_write(cfg, GSC_OUT_CON); 1580 break; 1581 default: 1582 ret = -EINVAL; 1583 dev_err(dev, "invalid operations.\n"); 1584 return ret; 1585 } 1586 1587 ret = gsc_set_prescaler(ctx, &ctx->sc, 1588 &img_pos[EXYNOS_DRM_OPS_SRC], 1589 &img_pos[EXYNOS_DRM_OPS_DST]); 1590 if (ret) { 1591 dev_err(dev, "failed to set precalser.\n"); 1592 return ret; 1593 } 1594 1595 gsc_set_scaler(ctx, &ctx->sc); 1596 1597 cfg = gsc_read(GSC_ENABLE); 1598 cfg |= GSC_ENABLE_ON; 1599 gsc_write(cfg, GSC_ENABLE); 1600 1601 return 0; 1602 } 1603 1604 static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) 1605 { 1606 struct gsc_context *ctx = get_gsc_context(dev); 1607 struct drm_exynos_ipp_set_wb set_wb = {0, 0}; 1608 u32 cfg; 1609 1610 DRM_DEBUG_KMS("cmd[%d]\n", cmd); 1611 1612 switch (cmd) { 1613 case IPP_CMD_M2M: 1614 /* bypass */ 1615 break; 1616 case IPP_CMD_WB: 1617 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable); 1618 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 1619 break; 1620 case IPP_CMD_OUTPUT: 1621 default: 1622 dev_err(dev, "invalid operations.\n"); 1623 break; 1624 } 1625 1626 gsc_handle_irq(ctx, false, false, true); 1627 1628 /* reset sequence */ 1629 gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK); 1630 gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK); 1631 gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK); 1632 1633 cfg = gsc_read(GSC_ENABLE); 1634 cfg &= ~GSC_ENABLE_ON; 1635 gsc_write(cfg, GSC_ENABLE); 1636 } 1637 1638 static int gsc_probe(struct platform_device *pdev) 1639 { 1640 struct device *dev = &pdev->dev; 1641 struct gsc_context *ctx; 1642 struct resource *res; 1643 struct exynos_drm_ippdrv *ippdrv; 1644 int ret; 1645 1646 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1647 if (!ctx) 1648 return -ENOMEM; 1649 1650 /* clock control */ 1651 ctx->gsc_clk = devm_clk_get(dev, "gscl"); 1652 if (IS_ERR(ctx->gsc_clk)) { 1653 dev_err(dev, "failed to get gsc clock.\n"); 1654 return PTR_ERR(ctx->gsc_clk); 1655 } 1656 1657 /* resource memory */ 1658 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1659 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1660 if (IS_ERR(ctx->regs)) 1661 return PTR_ERR(ctx->regs); 1662 1663 /* resource irq */ 1664 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1665 if (!res) { 1666 dev_err(dev, "failed to request irq resource.\n"); 1667 return -ENOENT; 1668 } 1669 1670 ctx->irq = res->start; 1671 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler, 1672 IRQF_ONESHOT, "drm_gsc", ctx); 1673 if (ret < 0) { 1674 dev_err(dev, "failed to request irq.\n"); 1675 return ret; 1676 } 1677 1678 /* context initailization */ 1679 ctx->id = pdev->id; 1680 1681 ippdrv = &ctx->ippdrv; 1682 ippdrv->dev = dev; 1683 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops; 1684 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops; 1685 ippdrv->check_property = gsc_ippdrv_check_property; 1686 ippdrv->reset = gsc_ippdrv_reset; 1687 ippdrv->start = gsc_ippdrv_start; 1688 ippdrv->stop = gsc_ippdrv_stop; 1689 ret = gsc_init_prop_list(ippdrv); 1690 if (ret < 0) { 1691 dev_err(dev, "failed to init property list.\n"); 1692 return ret; 1693 } 1694 1695 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv); 1696 1697 mutex_init(&ctx->lock); 1698 platform_set_drvdata(pdev, ctx); 1699 1700 pm_runtime_set_active(dev); 1701 pm_runtime_enable(dev); 1702 1703 ret = exynos_drm_ippdrv_register(ippdrv); 1704 if (ret < 0) { 1705 dev_err(dev, "failed to register drm gsc device.\n"); 1706 goto err_ippdrv_register; 1707 } 1708 1709 dev_info(dev, "drm gsc registered successfully.\n"); 1710 1711 return 0; 1712 1713 err_ippdrv_register: 1714 pm_runtime_disable(dev); 1715 return ret; 1716 } 1717 1718 static int gsc_remove(struct platform_device *pdev) 1719 { 1720 struct device *dev = &pdev->dev; 1721 struct gsc_context *ctx = get_gsc_context(dev); 1722 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 1723 1724 exynos_drm_ippdrv_unregister(ippdrv); 1725 mutex_destroy(&ctx->lock); 1726 1727 pm_runtime_set_suspended(dev); 1728 pm_runtime_disable(dev); 1729 1730 return 0; 1731 } 1732 1733 #ifdef CONFIG_PM_SLEEP 1734 static int gsc_suspend(struct device *dev) 1735 { 1736 struct gsc_context *ctx = get_gsc_context(dev); 1737 1738 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1739 1740 if (pm_runtime_suspended(dev)) 1741 return 0; 1742 1743 return gsc_clk_ctrl(ctx, false); 1744 } 1745 1746 static int gsc_resume(struct device *dev) 1747 { 1748 struct gsc_context *ctx = get_gsc_context(dev); 1749 1750 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1751 1752 if (!pm_runtime_suspended(dev)) 1753 return gsc_clk_ctrl(ctx, true); 1754 1755 return 0; 1756 } 1757 #endif 1758 1759 #ifdef CONFIG_PM 1760 static int gsc_runtime_suspend(struct device *dev) 1761 { 1762 struct gsc_context *ctx = get_gsc_context(dev); 1763 1764 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1765 1766 return gsc_clk_ctrl(ctx, false); 1767 } 1768 1769 static int gsc_runtime_resume(struct device *dev) 1770 { 1771 struct gsc_context *ctx = get_gsc_context(dev); 1772 1773 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1774 1775 return gsc_clk_ctrl(ctx, true); 1776 } 1777 #endif 1778 1779 static const struct dev_pm_ops gsc_pm_ops = { 1780 SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume) 1781 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL) 1782 }; 1783 1784 struct platform_driver gsc_driver = { 1785 .probe = gsc_probe, 1786 .remove = gsc_remove, 1787 .driver = { 1788 .name = "exynos-drm-gsc", 1789 .owner = THIS_MODULE, 1790 .pm = &gsc_pm_ops, 1791 }, 1792 }; 1793 1794