1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/component.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/samsung_fimd.h> 29 #include <drm/exynos_drm.h> 30 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fbdev.h" 33 #include "exynos_drm_crtc.h" 34 #include "exynos_drm_plane.h" 35 #include "exynos_drm_iommu.h" 36 37 /* 38 * FIMD stands for Fully Interactive Mobile Display and 39 * as a display controller, it transfers contents drawn on memory 40 * to a LCD Panel through Display Interfaces such as RGB or 41 * CPU Interface. 42 */ 43 44 #define FIMD_DEFAULT_FRAMERATE 60 45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 46 47 /* position control register for hardware window 0, 2 ~ 4.*/ 48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 50 /* 51 * size control register for hardware windows 0 and alpha control register 52 * for hardware windows 1 ~ 4 53 */ 54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 55 /* size control register for hardware windows 1 ~ 2. */ 56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 57 58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 60 61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 62 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) 63 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 64 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 65 66 /* color key control register for hardware window 1 ~ 4. */ 67 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 68 /* color key value register for hardware window 1 ~ 4. */ 69 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 70 71 /* I80 / RGB trigger control register */ 72 #define TRIGCON 0x1A4 73 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 74 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 75 76 /* display mode change control register except exynos4 */ 77 #define VIDOUT_CON 0x000 78 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 79 80 /* I80 interface control for main LDI register */ 81 #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 82 #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 83 #define LCD_CS_SETUP(x) ((x) << 16) 84 #define LCD_WR_SETUP(x) ((x) << 12) 85 #define LCD_WR_ACTIVE(x) ((x) << 8) 86 #define LCD_WR_HOLD(x) ((x) << 4) 87 #define I80IFEN_ENABLE (1 << 0) 88 89 /* FIMD has totally five hardware windows. */ 90 #define WINDOWS_NR 5 91 92 struct fimd_driver_data { 93 unsigned int timing_base; 94 unsigned int lcdblk_offset; 95 unsigned int lcdblk_vt_shift; 96 unsigned int lcdblk_bypass_shift; 97 98 unsigned int has_shadowcon:1; 99 unsigned int has_clksel:1; 100 unsigned int has_limited_fmt:1; 101 unsigned int has_vidoutcon:1; 102 unsigned int has_vtsel:1; 103 }; 104 105 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 106 .timing_base = 0x0, 107 .has_clksel = 1, 108 .has_limited_fmt = 1, 109 }; 110 111 static struct fimd_driver_data exynos3_fimd_driver_data = { 112 .timing_base = 0x20000, 113 .lcdblk_offset = 0x210, 114 .lcdblk_bypass_shift = 1, 115 .has_shadowcon = 1, 116 .has_vidoutcon = 1, 117 }; 118 119 static struct fimd_driver_data exynos4_fimd_driver_data = { 120 .timing_base = 0x0, 121 .lcdblk_offset = 0x210, 122 .lcdblk_vt_shift = 10, 123 .lcdblk_bypass_shift = 1, 124 .has_shadowcon = 1, 125 .has_vtsel = 1, 126 }; 127 128 static struct fimd_driver_data exynos4415_fimd_driver_data = { 129 .timing_base = 0x20000, 130 .lcdblk_offset = 0x210, 131 .lcdblk_vt_shift = 10, 132 .lcdblk_bypass_shift = 1, 133 .has_shadowcon = 1, 134 .has_vidoutcon = 1, 135 .has_vtsel = 1, 136 }; 137 138 static struct fimd_driver_data exynos5_fimd_driver_data = { 139 .timing_base = 0x20000, 140 .lcdblk_offset = 0x214, 141 .lcdblk_vt_shift = 24, 142 .lcdblk_bypass_shift = 15, 143 .has_shadowcon = 1, 144 .has_vidoutcon = 1, 145 .has_vtsel = 1, 146 }; 147 148 struct fimd_context { 149 struct device *dev; 150 struct drm_device *drm_dev; 151 struct exynos_drm_crtc *crtc; 152 struct exynos_drm_plane planes[WINDOWS_NR]; 153 struct clk *bus_clk; 154 struct clk *lcd_clk; 155 void __iomem *regs; 156 struct regmap *sysreg; 157 unsigned int default_win; 158 unsigned long irq_flags; 159 u32 vidcon0; 160 u32 vidcon1; 161 u32 vidout_con; 162 u32 i80ifcon; 163 bool i80_if; 164 bool suspended; 165 int pipe; 166 wait_queue_head_t wait_vsync_queue; 167 atomic_t wait_vsync_event; 168 atomic_t win_updated; 169 atomic_t triggering; 170 171 struct exynos_drm_panel_info panel; 172 struct fimd_driver_data *driver_data; 173 struct drm_encoder *encoder; 174 }; 175 176 static const struct of_device_id fimd_driver_dt_match[] = { 177 { .compatible = "samsung,s3c6400-fimd", 178 .data = &s3c64xx_fimd_driver_data }, 179 { .compatible = "samsung,exynos3250-fimd", 180 .data = &exynos3_fimd_driver_data }, 181 { .compatible = "samsung,exynos4210-fimd", 182 .data = &exynos4_fimd_driver_data }, 183 { .compatible = "samsung,exynos4415-fimd", 184 .data = &exynos4415_fimd_driver_data }, 185 { .compatible = "samsung,exynos5250-fimd", 186 .data = &exynos5_fimd_driver_data }, 187 {}, 188 }; 189 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 190 191 static const uint32_t fimd_formats[] = { 192 DRM_FORMAT_C8, 193 DRM_FORMAT_XRGB1555, 194 DRM_FORMAT_RGB565, 195 DRM_FORMAT_XRGB8888, 196 DRM_FORMAT_ARGB8888, 197 }; 198 199 static inline struct fimd_driver_data *drm_fimd_get_driver_data( 200 struct platform_device *pdev) 201 { 202 const struct of_device_id *of_id = 203 of_match_device(fimd_driver_dt_match, &pdev->dev); 204 205 return (struct fimd_driver_data *)of_id->data; 206 } 207 208 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 209 { 210 struct fimd_context *ctx = crtc->ctx; 211 u32 val; 212 213 if (ctx->suspended) 214 return -EPERM; 215 216 if (!test_and_set_bit(0, &ctx->irq_flags)) { 217 val = readl(ctx->regs + VIDINTCON0); 218 219 val |= VIDINTCON0_INT_ENABLE; 220 221 if (ctx->i80_if) { 222 val |= VIDINTCON0_INT_I80IFDONE; 223 val |= VIDINTCON0_INT_SYSMAINCON; 224 val &= ~VIDINTCON0_INT_SYSSUBCON; 225 } else { 226 val |= VIDINTCON0_INT_FRAME; 227 228 val &= ~VIDINTCON0_FRAMESEL0_MASK; 229 val |= VIDINTCON0_FRAMESEL0_VSYNC; 230 val &= ~VIDINTCON0_FRAMESEL1_MASK; 231 val |= VIDINTCON0_FRAMESEL1_NONE; 232 } 233 234 writel(val, ctx->regs + VIDINTCON0); 235 } 236 237 return 0; 238 } 239 240 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 241 { 242 struct fimd_context *ctx = crtc->ctx; 243 u32 val; 244 245 if (ctx->suspended) 246 return; 247 248 if (test_and_clear_bit(0, &ctx->irq_flags)) { 249 val = readl(ctx->regs + VIDINTCON0); 250 251 val &= ~VIDINTCON0_INT_ENABLE; 252 253 if (ctx->i80_if) { 254 val &= ~VIDINTCON0_INT_I80IFDONE; 255 val &= ~VIDINTCON0_INT_SYSMAINCON; 256 val &= ~VIDINTCON0_INT_SYSSUBCON; 257 } else 258 val &= ~VIDINTCON0_INT_FRAME; 259 260 writel(val, ctx->regs + VIDINTCON0); 261 } 262 } 263 264 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 265 { 266 struct fimd_context *ctx = crtc->ctx; 267 268 if (ctx->suspended) 269 return; 270 271 atomic_set(&ctx->wait_vsync_event, 1); 272 273 /* 274 * wait for FIMD to signal VSYNC interrupt or return after 275 * timeout which is set to 50ms (refresh rate of 20). 276 */ 277 if (!wait_event_timeout(ctx->wait_vsync_queue, 278 !atomic_read(&ctx->wait_vsync_event), 279 HZ/20)) 280 DRM_DEBUG_KMS("vblank wait timed out.\n"); 281 } 282 283 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 284 bool enable) 285 { 286 u32 val = readl(ctx->regs + WINCON(win)); 287 288 if (enable) 289 val |= WINCONx_ENWIN; 290 else 291 val &= ~WINCONx_ENWIN; 292 293 writel(val, ctx->regs + WINCON(win)); 294 } 295 296 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 297 unsigned int win, 298 bool enable) 299 { 300 u32 val = readl(ctx->regs + SHADOWCON); 301 302 if (enable) 303 val |= SHADOWCON_CHx_ENABLE(win); 304 else 305 val &= ~SHADOWCON_CHx_ENABLE(win); 306 307 writel(val, ctx->regs + SHADOWCON); 308 } 309 310 static void fimd_clear_channels(struct exynos_drm_crtc *crtc) 311 { 312 struct fimd_context *ctx = crtc->ctx; 313 unsigned int win, ch_enabled = 0; 314 315 DRM_DEBUG_KMS("%s\n", __FILE__); 316 317 /* Hardware is in unknown state, so ensure it gets enabled properly */ 318 pm_runtime_get_sync(ctx->dev); 319 320 clk_prepare_enable(ctx->bus_clk); 321 clk_prepare_enable(ctx->lcd_clk); 322 323 /* Check if any channel is enabled. */ 324 for (win = 0; win < WINDOWS_NR; win++) { 325 u32 val = readl(ctx->regs + WINCON(win)); 326 327 if (val & WINCONx_ENWIN) { 328 fimd_enable_video_output(ctx, win, false); 329 330 if (ctx->driver_data->has_shadowcon) 331 fimd_enable_shadow_channel_path(ctx, win, 332 false); 333 334 ch_enabled = 1; 335 } 336 } 337 338 /* Wait for vsync, as disable channel takes effect at next vsync */ 339 if (ch_enabled) { 340 int pipe = ctx->pipe; 341 342 /* ensure that vblank interrupt won't be reported to core */ 343 ctx->suspended = false; 344 ctx->pipe = -1; 345 346 fimd_enable_vblank(ctx->crtc); 347 fimd_wait_for_vblank(ctx->crtc); 348 fimd_disable_vblank(ctx->crtc); 349 350 ctx->suspended = true; 351 ctx->pipe = pipe; 352 } 353 354 clk_disable_unprepare(ctx->lcd_clk); 355 clk_disable_unprepare(ctx->bus_clk); 356 357 pm_runtime_put(ctx->dev); 358 } 359 360 static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 361 const struct drm_display_mode *mode) 362 { 363 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 364 u32 clkdiv; 365 366 if (ctx->i80_if) { 367 /* 368 * The frame done interrupt should be occurred prior to the 369 * next TE signal. 370 */ 371 ideal_clk *= 2; 372 } 373 374 /* Find the clock divider value that gets us closest to ideal_clk */ 375 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 376 377 return (clkdiv < 0x100) ? clkdiv : 0xff; 378 } 379 380 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, 381 const struct drm_display_mode *mode, 382 struct drm_display_mode *adjusted_mode) 383 { 384 if (adjusted_mode->vrefresh == 0) 385 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 386 387 return true; 388 } 389 390 static void fimd_commit(struct exynos_drm_crtc *crtc) 391 { 392 struct fimd_context *ctx = crtc->ctx; 393 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 394 struct fimd_driver_data *driver_data = ctx->driver_data; 395 void *timing_base = ctx->regs + driver_data->timing_base; 396 u32 val, clkdiv; 397 398 if (ctx->suspended) 399 return; 400 401 /* nothing to do if we haven't set the mode yet */ 402 if (mode->htotal == 0 || mode->vtotal == 0) 403 return; 404 405 if (ctx->i80_if) { 406 val = ctx->i80ifcon | I80IFEN_ENABLE; 407 writel(val, timing_base + I80IFCONFAx(0)); 408 409 /* disable auto frame rate */ 410 writel(0, timing_base + I80IFCONFBx(0)); 411 412 /* set video type selection to I80 interface */ 413 if (driver_data->has_vtsel && ctx->sysreg && 414 regmap_update_bits(ctx->sysreg, 415 driver_data->lcdblk_offset, 416 0x3 << driver_data->lcdblk_vt_shift, 417 0x1 << driver_data->lcdblk_vt_shift)) { 418 DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 419 return; 420 } 421 } else { 422 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 423 u32 vidcon1; 424 425 /* setup polarity values */ 426 vidcon1 = ctx->vidcon1; 427 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 428 vidcon1 |= VIDCON1_INV_VSYNC; 429 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 430 vidcon1 |= VIDCON1_INV_HSYNC; 431 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 432 433 /* setup vertical timing values. */ 434 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 435 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 436 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 437 438 val = VIDTCON0_VBPD(vbpd - 1) | 439 VIDTCON0_VFPD(vfpd - 1) | 440 VIDTCON0_VSPW(vsync_len - 1); 441 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 442 443 /* setup horizontal timing values. */ 444 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 445 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 446 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 447 448 val = VIDTCON1_HBPD(hbpd - 1) | 449 VIDTCON1_HFPD(hfpd - 1) | 450 VIDTCON1_HSPW(hsync_len - 1); 451 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 452 } 453 454 if (driver_data->has_vidoutcon) 455 writel(ctx->vidout_con, timing_base + VIDOUT_CON); 456 457 /* set bypass selection */ 458 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 459 driver_data->lcdblk_offset, 460 0x1 << driver_data->lcdblk_bypass_shift, 461 0x1 << driver_data->lcdblk_bypass_shift)) { 462 DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 463 return; 464 } 465 466 /* setup horizontal and vertical display size. */ 467 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 468 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 469 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 470 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 471 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 472 473 /* 474 * fields of register with prefix '_F' would be updated 475 * at vsync(same as dma start) 476 */ 477 val = ctx->vidcon0; 478 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 479 480 if (ctx->driver_data->has_clksel) 481 val |= VIDCON0_CLKSEL_LCD; 482 483 clkdiv = fimd_calc_clkdiv(ctx, mode); 484 if (clkdiv > 1) 485 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 486 487 writel(val, ctx->regs + VIDCON0); 488 } 489 490 491 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, 492 struct drm_framebuffer *fb) 493 { 494 unsigned long val; 495 496 val = WINCONx_ENWIN; 497 498 /* 499 * In case of s3c64xx, window 0 doesn't support alpha channel. 500 * So the request format is ARGB8888 then change it to XRGB8888. 501 */ 502 if (ctx->driver_data->has_limited_fmt && !win) { 503 if (fb->pixel_format == DRM_FORMAT_ARGB8888) 504 fb->pixel_format = DRM_FORMAT_XRGB8888; 505 } 506 507 switch (fb->pixel_format) { 508 case DRM_FORMAT_C8: 509 val |= WINCON0_BPPMODE_8BPP_PALETTE; 510 val |= WINCONx_BURSTLEN_8WORD; 511 val |= WINCONx_BYTSWP; 512 break; 513 case DRM_FORMAT_XRGB1555: 514 val |= WINCON0_BPPMODE_16BPP_1555; 515 val |= WINCONx_HAWSWP; 516 val |= WINCONx_BURSTLEN_16WORD; 517 break; 518 case DRM_FORMAT_RGB565: 519 val |= WINCON0_BPPMODE_16BPP_565; 520 val |= WINCONx_HAWSWP; 521 val |= WINCONx_BURSTLEN_16WORD; 522 break; 523 case DRM_FORMAT_XRGB8888: 524 val |= WINCON0_BPPMODE_24BPP_888; 525 val |= WINCONx_WSWP; 526 val |= WINCONx_BURSTLEN_16WORD; 527 break; 528 case DRM_FORMAT_ARGB8888: 529 val |= WINCON1_BPPMODE_25BPP_A1888 530 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 531 val |= WINCONx_WSWP; 532 val |= WINCONx_BURSTLEN_16WORD; 533 break; 534 default: 535 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 536 537 val |= WINCON0_BPPMODE_24BPP_888; 538 val |= WINCONx_WSWP; 539 val |= WINCONx_BURSTLEN_16WORD; 540 break; 541 } 542 543 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); 544 545 /* 546 * In case of exynos, setting dma-burst to 16Word causes permanent 547 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 548 * switching which is based on plane size is not recommended as 549 * plane size varies alot towards the end of the screen and rapid 550 * movement causes unstable DMA which results into iommu crash/tear. 551 */ 552 553 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 554 val &= ~WINCONx_BURSTLEN_MASK; 555 val |= WINCONx_BURSTLEN_4WORD; 556 } 557 558 writel(val, ctx->regs + WINCON(win)); 559 560 /* hardware window 0 doesn't support alpha channel. */ 561 if (win != 0) { 562 /* OSD alpha */ 563 val = VIDISD14C_ALPHA0_R(0xf) | 564 VIDISD14C_ALPHA0_G(0xf) | 565 VIDISD14C_ALPHA0_B(0xf) | 566 VIDISD14C_ALPHA1_R(0xf) | 567 VIDISD14C_ALPHA1_G(0xf) | 568 VIDISD14C_ALPHA1_B(0xf); 569 570 writel(val, ctx->regs + VIDOSD_C(win)); 571 572 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | 573 VIDW_ALPHA_G(0xf); 574 writel(val, ctx->regs + VIDWnALPHA0(win)); 575 writel(val, ctx->regs + VIDWnALPHA1(win)); 576 } 577 } 578 579 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 580 { 581 unsigned int keycon0 = 0, keycon1 = 0; 582 583 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 584 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 585 586 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 587 588 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 589 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 590 } 591 592 /** 593 * shadow_protect_win() - disable updating values from shadow registers at vsync 594 * 595 * @win: window to protect registers for 596 * @protect: 1 to protect (disable updates) 597 */ 598 static void fimd_shadow_protect_win(struct fimd_context *ctx, 599 unsigned int win, bool protect) 600 { 601 u32 reg, bits, val; 602 603 /* 604 * SHADOWCON/PRTCON register is used for enabling timing. 605 * 606 * for example, once only width value of a register is set, 607 * if the dma is started then fimd hardware could malfunction so 608 * with protect window setting, the register fields with prefix '_F' 609 * wouldn't be updated at vsync also but updated once unprotect window 610 * is set. 611 */ 612 613 if (ctx->driver_data->has_shadowcon) { 614 reg = SHADOWCON; 615 bits = SHADOWCON_WINx_PROTECT(win); 616 } else { 617 reg = PRTCON; 618 bits = PRTCON_PROTECT; 619 } 620 621 val = readl(ctx->regs + reg); 622 if (protect) 623 val |= bits; 624 else 625 val &= ~bits; 626 writel(val, ctx->regs + reg); 627 } 628 629 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc, 630 struct exynos_drm_plane *plane) 631 { 632 struct fimd_context *ctx = crtc->ctx; 633 634 if (ctx->suspended) 635 return; 636 637 fimd_shadow_protect_win(ctx, plane->zpos, true); 638 } 639 640 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc, 641 struct exynos_drm_plane *plane) 642 { 643 struct fimd_context *ctx = crtc->ctx; 644 645 if (ctx->suspended) 646 return; 647 648 fimd_shadow_protect_win(ctx, plane->zpos, false); 649 } 650 651 static void fimd_update_plane(struct exynos_drm_crtc *crtc, 652 struct exynos_drm_plane *plane) 653 { 654 struct fimd_context *ctx = crtc->ctx; 655 struct drm_plane_state *state = plane->base.state; 656 dma_addr_t dma_addr; 657 unsigned long val, size, offset; 658 unsigned int last_x, last_y, buf_offsize, line_size; 659 unsigned int win = plane->zpos; 660 unsigned int bpp = state->fb->bits_per_pixel >> 3; 661 unsigned int pitch = state->fb->pitches[0]; 662 663 if (ctx->suspended) 664 return; 665 666 offset = plane->src_x * bpp; 667 offset += plane->src_y * pitch; 668 669 /* buffer start address */ 670 dma_addr = plane->dma_addr[0] + offset; 671 val = (unsigned long)dma_addr; 672 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 673 674 /* buffer end address */ 675 size = pitch * plane->crtc_h; 676 val = (unsigned long)(dma_addr + size); 677 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 678 679 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 680 (unsigned long)dma_addr, val, size); 681 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 682 plane->crtc_w, plane->crtc_h); 683 684 /* buffer size */ 685 buf_offsize = pitch - (plane->crtc_w * bpp); 686 line_size = plane->crtc_w * bpp; 687 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 688 VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 689 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 690 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 691 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 692 693 /* OSD position */ 694 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 695 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | 696 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | 697 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); 698 writel(val, ctx->regs + VIDOSD_A(win)); 699 700 last_x = plane->crtc_x + plane->crtc_w; 701 if (last_x) 702 last_x--; 703 last_y = plane->crtc_y + plane->crtc_h; 704 if (last_y) 705 last_y--; 706 707 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 708 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 709 710 writel(val, ctx->regs + VIDOSD_B(win)); 711 712 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 713 plane->crtc_x, plane->crtc_y, last_x, last_y); 714 715 /* OSD size */ 716 if (win != 3 && win != 4) { 717 u32 offset = VIDOSD_D(win); 718 if (win == 0) 719 offset = VIDOSD_C(win); 720 val = plane->crtc_w * plane->crtc_h; 721 writel(val, ctx->regs + offset); 722 723 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 724 } 725 726 fimd_win_set_pixfmt(ctx, win, state->fb); 727 728 /* hardware window 0 doesn't support color key. */ 729 if (win != 0) 730 fimd_win_set_colkey(ctx, win); 731 732 fimd_enable_video_output(ctx, win, true); 733 734 if (ctx->driver_data->has_shadowcon) 735 fimd_enable_shadow_channel_path(ctx, win, true); 736 737 if (ctx->i80_if) 738 atomic_set(&ctx->win_updated, 1); 739 } 740 741 static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 742 struct exynos_drm_plane *plane) 743 { 744 struct fimd_context *ctx = crtc->ctx; 745 unsigned int win = plane->zpos; 746 747 if (ctx->suspended) 748 return; 749 750 fimd_enable_video_output(ctx, win, false); 751 752 if (ctx->driver_data->has_shadowcon) 753 fimd_enable_shadow_channel_path(ctx, win, false); 754 } 755 756 static void fimd_enable(struct exynos_drm_crtc *crtc) 757 { 758 struct fimd_context *ctx = crtc->ctx; 759 int ret; 760 761 if (!ctx->suspended) 762 return; 763 764 ctx->suspended = false; 765 766 pm_runtime_get_sync(ctx->dev); 767 768 ret = clk_prepare_enable(ctx->bus_clk); 769 if (ret < 0) { 770 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 771 return; 772 } 773 774 ret = clk_prepare_enable(ctx->lcd_clk); 775 if (ret < 0) { 776 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 777 return; 778 } 779 780 /* if vblank was enabled status, enable it again. */ 781 if (test_and_clear_bit(0, &ctx->irq_flags)) 782 fimd_enable_vblank(ctx->crtc); 783 784 fimd_commit(ctx->crtc); 785 } 786 787 static void fimd_disable(struct exynos_drm_crtc *crtc) 788 { 789 struct fimd_context *ctx = crtc->ctx; 790 int i; 791 792 if (ctx->suspended) 793 return; 794 795 /* 796 * We need to make sure that all windows are disabled before we 797 * suspend that connector. Otherwise we might try to scan from 798 * a destroyed buffer later. 799 */ 800 for (i = 0; i < WINDOWS_NR; i++) 801 fimd_disable_plane(crtc, &ctx->planes[i]); 802 803 fimd_enable_vblank(crtc); 804 fimd_wait_for_vblank(crtc); 805 fimd_disable_vblank(crtc); 806 807 writel(0, ctx->regs + VIDCON0); 808 809 clk_disable_unprepare(ctx->lcd_clk); 810 clk_disable_unprepare(ctx->bus_clk); 811 812 pm_runtime_put_sync(ctx->dev); 813 814 ctx->suspended = true; 815 } 816 817 static void fimd_trigger(struct device *dev) 818 { 819 struct fimd_context *ctx = dev_get_drvdata(dev); 820 struct fimd_driver_data *driver_data = ctx->driver_data; 821 void *timing_base = ctx->regs + driver_data->timing_base; 822 u32 reg; 823 824 /* 825 * Skips triggering if in triggering state, because multiple triggering 826 * requests can cause panel reset. 827 */ 828 if (atomic_read(&ctx->triggering)) 829 return; 830 831 /* Enters triggering mode */ 832 atomic_set(&ctx->triggering, 1); 833 834 reg = readl(timing_base + TRIGCON); 835 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 836 writel(reg, timing_base + TRIGCON); 837 838 /* 839 * Exits triggering mode if vblank is not enabled yet, because when the 840 * VIDINTCON0 register is not set, it can not exit from triggering mode. 841 */ 842 if (!test_bit(0, &ctx->irq_flags)) 843 atomic_set(&ctx->triggering, 0); 844 } 845 846 static void fimd_te_handler(struct exynos_drm_crtc *crtc) 847 { 848 struct fimd_context *ctx = crtc->ctx; 849 850 /* Checks the crtc is detached already from encoder */ 851 if (ctx->pipe < 0 || !ctx->drm_dev) 852 return; 853 854 /* 855 * If there is a page flip request, triggers and handles the page flip 856 * event so that current fb can be updated into panel GRAM. 857 */ 858 if (atomic_add_unless(&ctx->win_updated, -1, 0)) 859 fimd_trigger(ctx->dev); 860 861 /* Wakes up vsync event queue */ 862 if (atomic_read(&ctx->wait_vsync_event)) { 863 atomic_set(&ctx->wait_vsync_event, 0); 864 wake_up(&ctx->wait_vsync_queue); 865 } 866 867 if (test_bit(0, &ctx->irq_flags)) 868 drm_crtc_handle_vblank(&ctx->crtc->base); 869 } 870 871 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) 872 { 873 struct fimd_context *ctx = crtc->ctx; 874 u32 val; 875 876 /* 877 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE 878 * clock. On these SoCs the bootloader may enable it but any 879 * power domain off/on will reset it to disable state. 880 */ 881 if (ctx->driver_data != &exynos5_fimd_driver_data) 882 return; 883 884 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 885 writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); 886 } 887 888 static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 889 .enable = fimd_enable, 890 .disable = fimd_disable, 891 .mode_fixup = fimd_mode_fixup, 892 .commit = fimd_commit, 893 .enable_vblank = fimd_enable_vblank, 894 .disable_vblank = fimd_disable_vblank, 895 .wait_for_vblank = fimd_wait_for_vblank, 896 .atomic_begin = fimd_atomic_begin, 897 .update_plane = fimd_update_plane, 898 .disable_plane = fimd_disable_plane, 899 .atomic_flush = fimd_atomic_flush, 900 .te_handler = fimd_te_handler, 901 .clock_enable = fimd_dp_clock_enable, 902 }; 903 904 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 905 { 906 struct fimd_context *ctx = (struct fimd_context *)dev_id; 907 u32 val, clear_bit, start, start_s; 908 int win; 909 910 val = readl(ctx->regs + VIDINTCON1); 911 912 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 913 if (val & clear_bit) 914 writel(clear_bit, ctx->regs + VIDINTCON1); 915 916 /* check the crtc is detached already from encoder */ 917 if (ctx->pipe < 0 || !ctx->drm_dev) 918 goto out; 919 920 if (!ctx->i80_if) 921 drm_crtc_handle_vblank(&ctx->crtc->base); 922 923 for (win = 0 ; win < WINDOWS_NR ; win++) { 924 struct exynos_drm_plane *plane = &ctx->planes[win]; 925 926 if (!plane->pending_fb) 927 continue; 928 929 start = readl(ctx->regs + VIDWx_BUF_START(win, 0)); 930 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0)); 931 if (start == start_s) 932 exynos_drm_crtc_finish_update(ctx->crtc, plane); 933 } 934 935 if (ctx->i80_if) { 936 /* Exits triggering mode */ 937 atomic_set(&ctx->triggering, 0); 938 } else { 939 /* set wait vsync event to zero and wake up queue. */ 940 if (atomic_read(&ctx->wait_vsync_event)) { 941 atomic_set(&ctx->wait_vsync_event, 0); 942 wake_up(&ctx->wait_vsync_queue); 943 } 944 } 945 946 out: 947 return IRQ_HANDLED; 948 } 949 950 static int fimd_bind(struct device *dev, struct device *master, void *data) 951 { 952 struct fimd_context *ctx = dev_get_drvdata(dev); 953 struct drm_device *drm_dev = data; 954 struct exynos_drm_private *priv = drm_dev->dev_private; 955 struct exynos_drm_plane *exynos_plane; 956 enum drm_plane_type type; 957 unsigned int zpos; 958 int ret; 959 960 ctx->drm_dev = drm_dev; 961 ctx->pipe = priv->pipe++; 962 963 for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 964 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 965 DRM_PLANE_TYPE_OVERLAY; 966 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 967 1 << ctx->pipe, type, fimd_formats, 968 ARRAY_SIZE(fimd_formats), zpos); 969 if (ret) 970 return ret; 971 } 972 973 exynos_plane = &ctx->planes[ctx->default_win]; 974 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 975 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 976 &fimd_crtc_ops, ctx); 977 if (IS_ERR(ctx->crtc)) 978 return PTR_ERR(ctx->crtc); 979 980 if (ctx->encoder) 981 exynos_dpi_bind(drm_dev, ctx->encoder); 982 983 if (is_drm_iommu_supported(drm_dev)) 984 fimd_clear_channels(ctx->crtc); 985 986 ret = drm_iommu_attach_device(drm_dev, dev); 987 if (ret) 988 priv->pipe--; 989 990 return ret; 991 } 992 993 static void fimd_unbind(struct device *dev, struct device *master, 994 void *data) 995 { 996 struct fimd_context *ctx = dev_get_drvdata(dev); 997 998 fimd_disable(ctx->crtc); 999 1000 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 1001 1002 if (ctx->encoder) 1003 exynos_dpi_remove(ctx->encoder); 1004 } 1005 1006 static const struct component_ops fimd_component_ops = { 1007 .bind = fimd_bind, 1008 .unbind = fimd_unbind, 1009 }; 1010 1011 static int fimd_probe(struct platform_device *pdev) 1012 { 1013 struct device *dev = &pdev->dev; 1014 struct fimd_context *ctx; 1015 struct device_node *i80_if_timings; 1016 struct resource *res; 1017 int ret; 1018 1019 if (!dev->of_node) 1020 return -ENODEV; 1021 1022 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1023 if (!ctx) 1024 return -ENOMEM; 1025 1026 ctx->dev = dev; 1027 ctx->suspended = true; 1028 ctx->driver_data = drm_fimd_get_driver_data(pdev); 1029 1030 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 1031 ctx->vidcon1 |= VIDCON1_INV_VDEN; 1032 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 1033 ctx->vidcon1 |= VIDCON1_INV_VCLK; 1034 1035 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 1036 if (i80_if_timings) { 1037 u32 val; 1038 1039 ctx->i80_if = true; 1040 1041 if (ctx->driver_data->has_vidoutcon) 1042 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 1043 else 1044 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 1045 /* 1046 * The user manual describes that this "DSI_EN" bit is required 1047 * to enable I80 24-bit data interface. 1048 */ 1049 ctx->vidcon0 |= VIDCON0_DSI_EN; 1050 1051 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 1052 val = 0; 1053 ctx->i80ifcon = LCD_CS_SETUP(val); 1054 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 1055 val = 0; 1056 ctx->i80ifcon |= LCD_WR_SETUP(val); 1057 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 1058 val = 1; 1059 ctx->i80ifcon |= LCD_WR_ACTIVE(val); 1060 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 1061 val = 0; 1062 ctx->i80ifcon |= LCD_WR_HOLD(val); 1063 } 1064 of_node_put(i80_if_timings); 1065 1066 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1067 "samsung,sysreg"); 1068 if (IS_ERR(ctx->sysreg)) { 1069 dev_warn(dev, "failed to get system register.\n"); 1070 ctx->sysreg = NULL; 1071 } 1072 1073 ctx->bus_clk = devm_clk_get(dev, "fimd"); 1074 if (IS_ERR(ctx->bus_clk)) { 1075 dev_err(dev, "failed to get bus clock\n"); 1076 return PTR_ERR(ctx->bus_clk); 1077 } 1078 1079 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1080 if (IS_ERR(ctx->lcd_clk)) { 1081 dev_err(dev, "failed to get lcd clock\n"); 1082 return PTR_ERR(ctx->lcd_clk); 1083 } 1084 1085 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1086 1087 ctx->regs = devm_ioremap_resource(dev, res); 1088 if (IS_ERR(ctx->regs)) 1089 return PTR_ERR(ctx->regs); 1090 1091 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1092 ctx->i80_if ? "lcd_sys" : "vsync"); 1093 if (!res) { 1094 dev_err(dev, "irq request failed.\n"); 1095 return -ENXIO; 1096 } 1097 1098 ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1099 0, "drm_fimd", ctx); 1100 if (ret) { 1101 dev_err(dev, "irq request failed.\n"); 1102 return ret; 1103 } 1104 1105 init_waitqueue_head(&ctx->wait_vsync_queue); 1106 atomic_set(&ctx->wait_vsync_event, 0); 1107 1108 platform_set_drvdata(pdev, ctx); 1109 1110 ctx->encoder = exynos_dpi_probe(dev); 1111 if (IS_ERR(ctx->encoder)) 1112 return PTR_ERR(ctx->encoder); 1113 1114 pm_runtime_enable(dev); 1115 1116 ret = component_add(dev, &fimd_component_ops); 1117 if (ret) 1118 goto err_disable_pm_runtime; 1119 1120 return ret; 1121 1122 err_disable_pm_runtime: 1123 pm_runtime_disable(dev); 1124 1125 return ret; 1126 } 1127 1128 static int fimd_remove(struct platform_device *pdev) 1129 { 1130 pm_runtime_disable(&pdev->dev); 1131 1132 component_del(&pdev->dev, &fimd_component_ops); 1133 1134 return 0; 1135 } 1136 1137 struct platform_driver fimd_driver = { 1138 .probe = fimd_probe, 1139 .remove = fimd_remove, 1140 .driver = { 1141 .name = "exynos4-fb", 1142 .owner = THIS_MODULE, 1143 .of_match_table = fimd_driver_dt_match, 1144 }, 1145 }; 1146