1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/component.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/samsung_fimd.h> 29 #include <drm/exynos_drm.h> 30 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fbdev.h" 33 #include "exynos_drm_crtc.h" 34 #include "exynos_drm_plane.h" 35 #include "exynos_drm_iommu.h" 36 37 /* 38 * FIMD stands for Fully Interactive Mobile Display and 39 * as a display controller, it transfers contents drawn on memory 40 * to a LCD Panel through Display Interfaces such as RGB or 41 * CPU Interface. 42 */ 43 44 #define FIMD_DEFAULT_FRAMERATE 60 45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 46 47 /* position control register for hardware window 0, 2 ~ 4.*/ 48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 50 /* 51 * size control register for hardware windows 0 and alpha control register 52 * for hardware windows 1 ~ 4 53 */ 54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 55 /* size control register for hardware windows 1 ~ 2. */ 56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 57 58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 60 61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 62 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 63 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 64 65 /* color key control register for hardware window 1 ~ 4. */ 66 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 67 /* color key value register for hardware window 1 ~ 4. */ 68 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 69 70 /* I80 / RGB trigger control register */ 71 #define TRIGCON 0x1A4 72 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 73 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 74 75 /* display mode change control register except exynos4 */ 76 #define VIDOUT_CON 0x000 77 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 78 79 /* I80 interface control for main LDI register */ 80 #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 81 #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 82 #define LCD_CS_SETUP(x) ((x) << 16) 83 #define LCD_WR_SETUP(x) ((x) << 12) 84 #define LCD_WR_ACTIVE(x) ((x) << 8) 85 #define LCD_WR_HOLD(x) ((x) << 4) 86 #define I80IFEN_ENABLE (1 << 0) 87 88 /* FIMD has totally five hardware windows. */ 89 #define WINDOWS_NR 5 90 91 struct fimd_driver_data { 92 unsigned int timing_base; 93 unsigned int lcdblk_offset; 94 unsigned int lcdblk_vt_shift; 95 unsigned int lcdblk_bypass_shift; 96 97 unsigned int has_shadowcon:1; 98 unsigned int has_clksel:1; 99 unsigned int has_limited_fmt:1; 100 unsigned int has_vidoutcon:1; 101 unsigned int has_vtsel:1; 102 }; 103 104 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 105 .timing_base = 0x0, 106 .has_clksel = 1, 107 .has_limited_fmt = 1, 108 }; 109 110 static struct fimd_driver_data exynos3_fimd_driver_data = { 111 .timing_base = 0x20000, 112 .lcdblk_offset = 0x210, 113 .lcdblk_bypass_shift = 1, 114 .has_shadowcon = 1, 115 .has_vidoutcon = 1, 116 }; 117 118 static struct fimd_driver_data exynos4_fimd_driver_data = { 119 .timing_base = 0x0, 120 .lcdblk_offset = 0x210, 121 .lcdblk_vt_shift = 10, 122 .lcdblk_bypass_shift = 1, 123 .has_shadowcon = 1, 124 .has_vtsel = 1, 125 }; 126 127 static struct fimd_driver_data exynos4415_fimd_driver_data = { 128 .timing_base = 0x20000, 129 .lcdblk_offset = 0x210, 130 .lcdblk_vt_shift = 10, 131 .lcdblk_bypass_shift = 1, 132 .has_shadowcon = 1, 133 .has_vidoutcon = 1, 134 .has_vtsel = 1, 135 }; 136 137 static struct fimd_driver_data exynos5_fimd_driver_data = { 138 .timing_base = 0x20000, 139 .lcdblk_offset = 0x214, 140 .lcdblk_vt_shift = 24, 141 .lcdblk_bypass_shift = 15, 142 .has_shadowcon = 1, 143 .has_vidoutcon = 1, 144 .has_vtsel = 1, 145 }; 146 147 struct fimd_context { 148 struct device *dev; 149 struct drm_device *drm_dev; 150 struct exynos_drm_crtc *crtc; 151 struct exynos_drm_plane planes[WINDOWS_NR]; 152 struct clk *bus_clk; 153 struct clk *lcd_clk; 154 void __iomem *regs; 155 struct regmap *sysreg; 156 unsigned int default_win; 157 unsigned long irq_flags; 158 u32 vidcon0; 159 u32 vidcon1; 160 u32 vidout_con; 161 u32 i80ifcon; 162 bool i80_if; 163 bool suspended; 164 int pipe; 165 wait_queue_head_t wait_vsync_queue; 166 atomic_t wait_vsync_event; 167 atomic_t win_updated; 168 atomic_t triggering; 169 170 struct exynos_drm_panel_info panel; 171 struct fimd_driver_data *driver_data; 172 struct drm_encoder *encoder; 173 }; 174 175 static const struct of_device_id fimd_driver_dt_match[] = { 176 { .compatible = "samsung,s3c6400-fimd", 177 .data = &s3c64xx_fimd_driver_data }, 178 { .compatible = "samsung,exynos3250-fimd", 179 .data = &exynos3_fimd_driver_data }, 180 { .compatible = "samsung,exynos4210-fimd", 181 .data = &exynos4_fimd_driver_data }, 182 { .compatible = "samsung,exynos4415-fimd", 183 .data = &exynos4415_fimd_driver_data }, 184 { .compatible = "samsung,exynos5250-fimd", 185 .data = &exynos5_fimd_driver_data }, 186 {}, 187 }; 188 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 189 190 static inline struct fimd_driver_data *drm_fimd_get_driver_data( 191 struct platform_device *pdev) 192 { 193 const struct of_device_id *of_id = 194 of_match_device(fimd_driver_dt_match, &pdev->dev); 195 196 return (struct fimd_driver_data *)of_id->data; 197 } 198 199 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 200 { 201 struct fimd_context *ctx = crtc->ctx; 202 u32 val; 203 204 if (ctx->suspended) 205 return -EPERM; 206 207 if (!test_and_set_bit(0, &ctx->irq_flags)) { 208 val = readl(ctx->regs + VIDINTCON0); 209 210 val |= VIDINTCON0_INT_ENABLE; 211 212 if (ctx->i80_if) { 213 val |= VIDINTCON0_INT_I80IFDONE; 214 val |= VIDINTCON0_INT_SYSMAINCON; 215 val &= ~VIDINTCON0_INT_SYSSUBCON; 216 } else { 217 val |= VIDINTCON0_INT_FRAME; 218 219 val &= ~VIDINTCON0_FRAMESEL0_MASK; 220 val |= VIDINTCON0_FRAMESEL0_VSYNC; 221 val &= ~VIDINTCON0_FRAMESEL1_MASK; 222 val |= VIDINTCON0_FRAMESEL1_NONE; 223 } 224 225 writel(val, ctx->regs + VIDINTCON0); 226 } 227 228 return 0; 229 } 230 231 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 232 { 233 struct fimd_context *ctx = crtc->ctx; 234 u32 val; 235 236 if (ctx->suspended) 237 return; 238 239 if (test_and_clear_bit(0, &ctx->irq_flags)) { 240 val = readl(ctx->regs + VIDINTCON0); 241 242 val &= ~VIDINTCON0_INT_ENABLE; 243 244 if (ctx->i80_if) { 245 val &= ~VIDINTCON0_INT_I80IFDONE; 246 val &= ~VIDINTCON0_INT_SYSMAINCON; 247 val &= ~VIDINTCON0_INT_SYSSUBCON; 248 } else 249 val &= ~VIDINTCON0_INT_FRAME; 250 251 writel(val, ctx->regs + VIDINTCON0); 252 } 253 } 254 255 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 256 { 257 struct fimd_context *ctx = crtc->ctx; 258 259 if (ctx->suspended) 260 return; 261 262 atomic_set(&ctx->wait_vsync_event, 1); 263 264 /* 265 * wait for FIMD to signal VSYNC interrupt or return after 266 * timeout which is set to 50ms (refresh rate of 20). 267 */ 268 if (!wait_event_timeout(ctx->wait_vsync_queue, 269 !atomic_read(&ctx->wait_vsync_event), 270 HZ/20)) 271 DRM_DEBUG_KMS("vblank wait timed out.\n"); 272 } 273 274 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 275 bool enable) 276 { 277 u32 val = readl(ctx->regs + WINCON(win)); 278 279 if (enable) 280 val |= WINCONx_ENWIN; 281 else 282 val &= ~WINCONx_ENWIN; 283 284 writel(val, ctx->regs + WINCON(win)); 285 } 286 287 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 288 unsigned int win, 289 bool enable) 290 { 291 u32 val = readl(ctx->regs + SHADOWCON); 292 293 if (enable) 294 val |= SHADOWCON_CHx_ENABLE(win); 295 else 296 val &= ~SHADOWCON_CHx_ENABLE(win); 297 298 writel(val, ctx->regs + SHADOWCON); 299 } 300 301 static void fimd_clear_channels(struct exynos_drm_crtc *crtc) 302 { 303 struct fimd_context *ctx = crtc->ctx; 304 unsigned int win, ch_enabled = 0; 305 306 DRM_DEBUG_KMS("%s\n", __FILE__); 307 308 /* Hardware is in unknown state, so ensure it gets enabled properly */ 309 pm_runtime_get_sync(ctx->dev); 310 311 clk_prepare_enable(ctx->bus_clk); 312 clk_prepare_enable(ctx->lcd_clk); 313 314 /* Check if any channel is enabled. */ 315 for (win = 0; win < WINDOWS_NR; win++) { 316 u32 val = readl(ctx->regs + WINCON(win)); 317 318 if (val & WINCONx_ENWIN) { 319 fimd_enable_video_output(ctx, win, false); 320 321 if (ctx->driver_data->has_shadowcon) 322 fimd_enable_shadow_channel_path(ctx, win, 323 false); 324 325 ch_enabled = 1; 326 } 327 } 328 329 /* Wait for vsync, as disable channel takes effect at next vsync */ 330 if (ch_enabled) { 331 int pipe = ctx->pipe; 332 333 /* ensure that vblank interrupt won't be reported to core */ 334 ctx->suspended = false; 335 ctx->pipe = -1; 336 337 fimd_enable_vblank(ctx->crtc); 338 fimd_wait_for_vblank(ctx->crtc); 339 fimd_disable_vblank(ctx->crtc); 340 341 ctx->suspended = true; 342 ctx->pipe = pipe; 343 } 344 345 clk_disable_unprepare(ctx->lcd_clk); 346 clk_disable_unprepare(ctx->bus_clk); 347 348 pm_runtime_put(ctx->dev); 349 } 350 351 static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 352 const struct drm_display_mode *mode) 353 { 354 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 355 u32 clkdiv; 356 357 if (ctx->i80_if) { 358 /* 359 * The frame done interrupt should be occurred prior to the 360 * next TE signal. 361 */ 362 ideal_clk *= 2; 363 } 364 365 /* Find the clock divider value that gets us closest to ideal_clk */ 366 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 367 368 return (clkdiv < 0x100) ? clkdiv : 0xff; 369 } 370 371 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, 372 const struct drm_display_mode *mode, 373 struct drm_display_mode *adjusted_mode) 374 { 375 if (adjusted_mode->vrefresh == 0) 376 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 377 378 return true; 379 } 380 381 static void fimd_commit(struct exynos_drm_crtc *crtc) 382 { 383 struct fimd_context *ctx = crtc->ctx; 384 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 385 struct fimd_driver_data *driver_data = ctx->driver_data; 386 void *timing_base = ctx->regs + driver_data->timing_base; 387 u32 val, clkdiv; 388 389 if (ctx->suspended) 390 return; 391 392 /* nothing to do if we haven't set the mode yet */ 393 if (mode->htotal == 0 || mode->vtotal == 0) 394 return; 395 396 if (ctx->i80_if) { 397 val = ctx->i80ifcon | I80IFEN_ENABLE; 398 writel(val, timing_base + I80IFCONFAx(0)); 399 400 /* disable auto frame rate */ 401 writel(0, timing_base + I80IFCONFBx(0)); 402 403 /* set video type selection to I80 interface */ 404 if (driver_data->has_vtsel && ctx->sysreg && 405 regmap_update_bits(ctx->sysreg, 406 driver_data->lcdblk_offset, 407 0x3 << driver_data->lcdblk_vt_shift, 408 0x1 << driver_data->lcdblk_vt_shift)) { 409 DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 410 return; 411 } 412 } else { 413 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 414 u32 vidcon1; 415 416 /* setup polarity values */ 417 vidcon1 = ctx->vidcon1; 418 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 419 vidcon1 |= VIDCON1_INV_VSYNC; 420 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 421 vidcon1 |= VIDCON1_INV_HSYNC; 422 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 423 424 /* setup vertical timing values. */ 425 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 426 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 427 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 428 429 val = VIDTCON0_VBPD(vbpd - 1) | 430 VIDTCON0_VFPD(vfpd - 1) | 431 VIDTCON0_VSPW(vsync_len - 1); 432 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 433 434 /* setup horizontal timing values. */ 435 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 436 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 437 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 438 439 val = VIDTCON1_HBPD(hbpd - 1) | 440 VIDTCON1_HFPD(hfpd - 1) | 441 VIDTCON1_HSPW(hsync_len - 1); 442 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 443 } 444 445 if (driver_data->has_vidoutcon) 446 writel(ctx->vidout_con, timing_base + VIDOUT_CON); 447 448 /* set bypass selection */ 449 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 450 driver_data->lcdblk_offset, 451 0x1 << driver_data->lcdblk_bypass_shift, 452 0x1 << driver_data->lcdblk_bypass_shift)) { 453 DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 454 return; 455 } 456 457 /* setup horizontal and vertical display size. */ 458 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 459 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 460 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 461 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 462 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 463 464 /* 465 * fields of register with prefix '_F' would be updated 466 * at vsync(same as dma start) 467 */ 468 val = ctx->vidcon0; 469 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 470 471 if (ctx->driver_data->has_clksel) 472 val |= VIDCON0_CLKSEL_LCD; 473 474 clkdiv = fimd_calc_clkdiv(ctx, mode); 475 if (clkdiv > 1) 476 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 477 478 writel(val, ctx->regs + VIDCON0); 479 } 480 481 482 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, 483 struct drm_framebuffer *fb) 484 { 485 unsigned long val; 486 487 val = WINCONx_ENWIN; 488 489 /* 490 * In case of s3c64xx, window 0 doesn't support alpha channel. 491 * So the request format is ARGB8888 then change it to XRGB8888. 492 */ 493 if (ctx->driver_data->has_limited_fmt && !win) { 494 if (fb->pixel_format == DRM_FORMAT_ARGB8888) 495 fb->pixel_format = DRM_FORMAT_XRGB8888; 496 } 497 498 switch (fb->pixel_format) { 499 case DRM_FORMAT_C8: 500 val |= WINCON0_BPPMODE_8BPP_PALETTE; 501 val |= WINCONx_BURSTLEN_8WORD; 502 val |= WINCONx_BYTSWP; 503 break; 504 case DRM_FORMAT_XRGB1555: 505 val |= WINCON0_BPPMODE_16BPP_1555; 506 val |= WINCONx_HAWSWP; 507 val |= WINCONx_BURSTLEN_16WORD; 508 break; 509 case DRM_FORMAT_RGB565: 510 val |= WINCON0_BPPMODE_16BPP_565; 511 val |= WINCONx_HAWSWP; 512 val |= WINCONx_BURSTLEN_16WORD; 513 break; 514 case DRM_FORMAT_XRGB8888: 515 val |= WINCON0_BPPMODE_24BPP_888; 516 val |= WINCONx_WSWP; 517 val |= WINCONx_BURSTLEN_16WORD; 518 break; 519 case DRM_FORMAT_ARGB8888: 520 val |= WINCON1_BPPMODE_25BPP_A1888 521 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 522 val |= WINCONx_WSWP; 523 val |= WINCONx_BURSTLEN_16WORD; 524 break; 525 default: 526 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 527 528 val |= WINCON0_BPPMODE_24BPP_888; 529 val |= WINCONx_WSWP; 530 val |= WINCONx_BURSTLEN_16WORD; 531 break; 532 } 533 534 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); 535 536 /* 537 * In case of exynos, setting dma-burst to 16Word causes permanent 538 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 539 * switching which is based on plane size is not recommended as 540 * plane size varies alot towards the end of the screen and rapid 541 * movement causes unstable DMA which results into iommu crash/tear. 542 */ 543 544 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 545 val &= ~WINCONx_BURSTLEN_MASK; 546 val |= WINCONx_BURSTLEN_4WORD; 547 } 548 549 writel(val, ctx->regs + WINCON(win)); 550 551 /* hardware window 0 doesn't support alpha channel. */ 552 if (win != 0) { 553 /* OSD alpha */ 554 val = VIDISD14C_ALPHA0_R(0xf) | 555 VIDISD14C_ALPHA0_G(0xf) | 556 VIDISD14C_ALPHA0_B(0xf) | 557 VIDISD14C_ALPHA1_R(0xf) | 558 VIDISD14C_ALPHA1_G(0xf) | 559 VIDISD14C_ALPHA1_B(0xf); 560 561 writel(val, ctx->regs + VIDOSD_C(win)); 562 563 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | 564 VIDW_ALPHA_G(0xf); 565 writel(val, ctx->regs + VIDWnALPHA0(win)); 566 writel(val, ctx->regs + VIDWnALPHA1(win)); 567 } 568 } 569 570 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 571 { 572 unsigned int keycon0 = 0, keycon1 = 0; 573 574 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 575 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 576 577 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 578 579 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 580 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 581 } 582 583 /** 584 * shadow_protect_win() - disable updating values from shadow registers at vsync 585 * 586 * @win: window to protect registers for 587 * @protect: 1 to protect (disable updates) 588 */ 589 static void fimd_shadow_protect_win(struct fimd_context *ctx, 590 unsigned int win, bool protect) 591 { 592 u32 reg, bits, val; 593 594 if (ctx->driver_data->has_shadowcon) { 595 reg = SHADOWCON; 596 bits = SHADOWCON_WINx_PROTECT(win); 597 } else { 598 reg = PRTCON; 599 bits = PRTCON_PROTECT; 600 } 601 602 val = readl(ctx->regs + reg); 603 if (protect) 604 val |= bits; 605 else 606 val &= ~bits; 607 writel(val, ctx->regs + reg); 608 } 609 610 static void fimd_update_plane(struct exynos_drm_crtc *crtc, 611 struct exynos_drm_plane *plane) 612 { 613 struct fimd_context *ctx = crtc->ctx; 614 struct drm_plane_state *state = plane->base.state; 615 dma_addr_t dma_addr; 616 unsigned long val, size, offset; 617 unsigned int last_x, last_y, buf_offsize, line_size; 618 unsigned int win = plane->zpos; 619 unsigned int bpp = state->fb->bits_per_pixel >> 3; 620 unsigned int pitch = state->fb->pitches[0]; 621 622 if (ctx->suspended) 623 return; 624 625 /* 626 * SHADOWCON/PRTCON register is used for enabling timing. 627 * 628 * for example, once only width value of a register is set, 629 * if the dma is started then fimd hardware could malfunction so 630 * with protect window setting, the register fields with prefix '_F' 631 * wouldn't be updated at vsync also but updated once unprotect window 632 * is set. 633 */ 634 635 /* protect windows */ 636 fimd_shadow_protect_win(ctx, win, true); 637 638 639 offset = plane->src_x * bpp; 640 offset += plane->src_y * pitch; 641 642 /* buffer start address */ 643 dma_addr = plane->dma_addr[0] + offset; 644 val = (unsigned long)dma_addr; 645 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 646 647 /* buffer end address */ 648 size = pitch * plane->crtc_h; 649 val = (unsigned long)(dma_addr + size); 650 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 651 652 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 653 (unsigned long)dma_addr, val, size); 654 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 655 plane->crtc_w, plane->crtc_h); 656 657 /* buffer size */ 658 buf_offsize = pitch - (plane->crtc_w * bpp); 659 line_size = plane->crtc_w * bpp; 660 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 661 VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 662 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 663 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 664 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 665 666 /* OSD position */ 667 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 668 VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | 669 VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | 670 VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); 671 writel(val, ctx->regs + VIDOSD_A(win)); 672 673 last_x = plane->crtc_x + plane->crtc_w; 674 if (last_x) 675 last_x--; 676 last_y = plane->crtc_y + plane->crtc_h; 677 if (last_y) 678 last_y--; 679 680 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 681 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 682 683 writel(val, ctx->regs + VIDOSD_B(win)); 684 685 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 686 plane->crtc_x, plane->crtc_y, last_x, last_y); 687 688 /* OSD size */ 689 if (win != 3 && win != 4) { 690 u32 offset = VIDOSD_D(win); 691 if (win == 0) 692 offset = VIDOSD_C(win); 693 val = plane->crtc_w * plane->crtc_h; 694 writel(val, ctx->regs + offset); 695 696 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 697 } 698 699 fimd_win_set_pixfmt(ctx, win, state->fb); 700 701 /* hardware window 0 doesn't support color key. */ 702 if (win != 0) 703 fimd_win_set_colkey(ctx, win); 704 705 fimd_enable_video_output(ctx, win, true); 706 707 if (ctx->driver_data->has_shadowcon) 708 fimd_enable_shadow_channel_path(ctx, win, true); 709 710 /* Enable DMA channel and unprotect windows */ 711 fimd_shadow_protect_win(ctx, win, false); 712 713 if (ctx->i80_if) 714 atomic_set(&ctx->win_updated, 1); 715 } 716 717 static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 718 struct exynos_drm_plane *plane) 719 { 720 struct fimd_context *ctx = crtc->ctx; 721 unsigned int win = plane->zpos; 722 723 if (ctx->suspended) 724 return; 725 726 /* protect windows */ 727 fimd_shadow_protect_win(ctx, win, true); 728 729 fimd_enable_video_output(ctx, win, false); 730 731 if (ctx->driver_data->has_shadowcon) 732 fimd_enable_shadow_channel_path(ctx, win, false); 733 734 /* unprotect windows */ 735 fimd_shadow_protect_win(ctx, win, false); 736 } 737 738 static void fimd_enable(struct exynos_drm_crtc *crtc) 739 { 740 struct fimd_context *ctx = crtc->ctx; 741 int ret; 742 743 if (!ctx->suspended) 744 return; 745 746 ctx->suspended = false; 747 748 pm_runtime_get_sync(ctx->dev); 749 750 ret = clk_prepare_enable(ctx->bus_clk); 751 if (ret < 0) { 752 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 753 return; 754 } 755 756 ret = clk_prepare_enable(ctx->lcd_clk); 757 if (ret < 0) { 758 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 759 return; 760 } 761 762 /* if vblank was enabled status, enable it again. */ 763 if (test_and_clear_bit(0, &ctx->irq_flags)) 764 fimd_enable_vblank(ctx->crtc); 765 766 fimd_commit(ctx->crtc); 767 } 768 769 static void fimd_disable(struct exynos_drm_crtc *crtc) 770 { 771 struct fimd_context *ctx = crtc->ctx; 772 int i; 773 774 if (ctx->suspended) 775 return; 776 777 /* 778 * We need to make sure that all windows are disabled before we 779 * suspend that connector. Otherwise we might try to scan from 780 * a destroyed buffer later. 781 */ 782 for (i = 0; i < WINDOWS_NR; i++) 783 fimd_disable_plane(crtc, &ctx->planes[i]); 784 785 fimd_enable_vblank(crtc); 786 fimd_wait_for_vblank(crtc); 787 fimd_disable_vblank(crtc); 788 789 writel(0, ctx->regs + VIDCON0); 790 791 clk_disable_unprepare(ctx->lcd_clk); 792 clk_disable_unprepare(ctx->bus_clk); 793 794 pm_runtime_put_sync(ctx->dev); 795 796 ctx->suspended = true; 797 } 798 799 static void fimd_trigger(struct device *dev) 800 { 801 struct fimd_context *ctx = dev_get_drvdata(dev); 802 struct fimd_driver_data *driver_data = ctx->driver_data; 803 void *timing_base = ctx->regs + driver_data->timing_base; 804 u32 reg; 805 806 /* 807 * Skips triggering if in triggering state, because multiple triggering 808 * requests can cause panel reset. 809 */ 810 if (atomic_read(&ctx->triggering)) 811 return; 812 813 /* Enters triggering mode */ 814 atomic_set(&ctx->triggering, 1); 815 816 reg = readl(timing_base + TRIGCON); 817 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 818 writel(reg, timing_base + TRIGCON); 819 820 /* 821 * Exits triggering mode if vblank is not enabled yet, because when the 822 * VIDINTCON0 register is not set, it can not exit from triggering mode. 823 */ 824 if (!test_bit(0, &ctx->irq_flags)) 825 atomic_set(&ctx->triggering, 0); 826 } 827 828 static void fimd_te_handler(struct exynos_drm_crtc *crtc) 829 { 830 struct fimd_context *ctx = crtc->ctx; 831 832 /* Checks the crtc is detached already from encoder */ 833 if (ctx->pipe < 0 || !ctx->drm_dev) 834 return; 835 836 /* 837 * If there is a page flip request, triggers and handles the page flip 838 * event so that current fb can be updated into panel GRAM. 839 */ 840 if (atomic_add_unless(&ctx->win_updated, -1, 0)) 841 fimd_trigger(ctx->dev); 842 843 /* Wakes up vsync event queue */ 844 if (atomic_read(&ctx->wait_vsync_event)) { 845 atomic_set(&ctx->wait_vsync_event, 0); 846 wake_up(&ctx->wait_vsync_queue); 847 } 848 849 if (test_bit(0, &ctx->irq_flags)) 850 drm_crtc_handle_vblank(&ctx->crtc->base); 851 } 852 853 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) 854 { 855 struct fimd_context *ctx = crtc->ctx; 856 u32 val; 857 858 /* 859 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE 860 * clock. On these SoCs the bootloader may enable it but any 861 * power domain off/on will reset it to disable state. 862 */ 863 if (ctx->driver_data != &exynos5_fimd_driver_data) 864 return; 865 866 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 867 writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); 868 } 869 870 static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 871 .enable = fimd_enable, 872 .disable = fimd_disable, 873 .mode_fixup = fimd_mode_fixup, 874 .commit = fimd_commit, 875 .enable_vblank = fimd_enable_vblank, 876 .disable_vblank = fimd_disable_vblank, 877 .wait_for_vblank = fimd_wait_for_vblank, 878 .update_plane = fimd_update_plane, 879 .disable_plane = fimd_disable_plane, 880 .te_handler = fimd_te_handler, 881 .clock_enable = fimd_dp_clock_enable, 882 }; 883 884 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 885 { 886 struct fimd_context *ctx = (struct fimd_context *)dev_id; 887 u32 val, clear_bit; 888 889 val = readl(ctx->regs + VIDINTCON1); 890 891 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 892 if (val & clear_bit) 893 writel(clear_bit, ctx->regs + VIDINTCON1); 894 895 /* check the crtc is detached already from encoder */ 896 if (ctx->pipe < 0 || !ctx->drm_dev) 897 goto out; 898 899 if (ctx->i80_if) { 900 exynos_drm_crtc_finish_pageflip(ctx->crtc); 901 902 /* Exits triggering mode */ 903 atomic_set(&ctx->triggering, 0); 904 } else { 905 drm_crtc_handle_vblank(&ctx->crtc->base); 906 exynos_drm_crtc_finish_pageflip(ctx->crtc); 907 908 /* set wait vsync event to zero and wake up queue. */ 909 if (atomic_read(&ctx->wait_vsync_event)) { 910 atomic_set(&ctx->wait_vsync_event, 0); 911 wake_up(&ctx->wait_vsync_queue); 912 } 913 } 914 915 out: 916 return IRQ_HANDLED; 917 } 918 919 static int fimd_bind(struct device *dev, struct device *master, void *data) 920 { 921 struct fimd_context *ctx = dev_get_drvdata(dev); 922 struct drm_device *drm_dev = data; 923 struct exynos_drm_private *priv = drm_dev->dev_private; 924 struct exynos_drm_plane *exynos_plane; 925 enum drm_plane_type type; 926 unsigned int zpos; 927 int ret; 928 929 ctx->drm_dev = drm_dev; 930 ctx->pipe = priv->pipe++; 931 932 for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 933 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 934 DRM_PLANE_TYPE_OVERLAY; 935 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 936 1 << ctx->pipe, type, zpos); 937 if (ret) 938 return ret; 939 } 940 941 exynos_plane = &ctx->planes[ctx->default_win]; 942 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 943 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 944 &fimd_crtc_ops, ctx); 945 if (IS_ERR(ctx->crtc)) 946 return PTR_ERR(ctx->crtc); 947 948 if (ctx->encoder) 949 exynos_dpi_bind(drm_dev, ctx->encoder); 950 951 if (is_drm_iommu_supported(drm_dev)) 952 fimd_clear_channels(ctx->crtc); 953 954 ret = drm_iommu_attach_device(drm_dev, dev); 955 if (ret) 956 priv->pipe--; 957 958 return ret; 959 } 960 961 static void fimd_unbind(struct device *dev, struct device *master, 962 void *data) 963 { 964 struct fimd_context *ctx = dev_get_drvdata(dev); 965 966 fimd_disable(ctx->crtc); 967 968 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 969 970 if (ctx->encoder) 971 exynos_dpi_remove(ctx->encoder); 972 } 973 974 static const struct component_ops fimd_component_ops = { 975 .bind = fimd_bind, 976 .unbind = fimd_unbind, 977 }; 978 979 static int fimd_probe(struct platform_device *pdev) 980 { 981 struct device *dev = &pdev->dev; 982 struct fimd_context *ctx; 983 struct device_node *i80_if_timings; 984 struct resource *res; 985 int ret; 986 987 if (!dev->of_node) 988 return -ENODEV; 989 990 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 991 if (!ctx) 992 return -ENOMEM; 993 994 ctx->dev = dev; 995 ctx->suspended = true; 996 ctx->driver_data = drm_fimd_get_driver_data(pdev); 997 998 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 999 ctx->vidcon1 |= VIDCON1_INV_VDEN; 1000 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 1001 ctx->vidcon1 |= VIDCON1_INV_VCLK; 1002 1003 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 1004 if (i80_if_timings) { 1005 u32 val; 1006 1007 ctx->i80_if = true; 1008 1009 if (ctx->driver_data->has_vidoutcon) 1010 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 1011 else 1012 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 1013 /* 1014 * The user manual describes that this "DSI_EN" bit is required 1015 * to enable I80 24-bit data interface. 1016 */ 1017 ctx->vidcon0 |= VIDCON0_DSI_EN; 1018 1019 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 1020 val = 0; 1021 ctx->i80ifcon = LCD_CS_SETUP(val); 1022 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 1023 val = 0; 1024 ctx->i80ifcon |= LCD_WR_SETUP(val); 1025 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 1026 val = 1; 1027 ctx->i80ifcon |= LCD_WR_ACTIVE(val); 1028 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 1029 val = 0; 1030 ctx->i80ifcon |= LCD_WR_HOLD(val); 1031 } 1032 of_node_put(i80_if_timings); 1033 1034 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1035 "samsung,sysreg"); 1036 if (IS_ERR(ctx->sysreg)) { 1037 dev_warn(dev, "failed to get system register.\n"); 1038 ctx->sysreg = NULL; 1039 } 1040 1041 ctx->bus_clk = devm_clk_get(dev, "fimd"); 1042 if (IS_ERR(ctx->bus_clk)) { 1043 dev_err(dev, "failed to get bus clock\n"); 1044 return PTR_ERR(ctx->bus_clk); 1045 } 1046 1047 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1048 if (IS_ERR(ctx->lcd_clk)) { 1049 dev_err(dev, "failed to get lcd clock\n"); 1050 return PTR_ERR(ctx->lcd_clk); 1051 } 1052 1053 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1054 1055 ctx->regs = devm_ioremap_resource(dev, res); 1056 if (IS_ERR(ctx->regs)) 1057 return PTR_ERR(ctx->regs); 1058 1059 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1060 ctx->i80_if ? "lcd_sys" : "vsync"); 1061 if (!res) { 1062 dev_err(dev, "irq request failed.\n"); 1063 return -ENXIO; 1064 } 1065 1066 ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1067 0, "drm_fimd", ctx); 1068 if (ret) { 1069 dev_err(dev, "irq request failed.\n"); 1070 return ret; 1071 } 1072 1073 init_waitqueue_head(&ctx->wait_vsync_queue); 1074 atomic_set(&ctx->wait_vsync_event, 0); 1075 1076 platform_set_drvdata(pdev, ctx); 1077 1078 ctx->encoder = exynos_dpi_probe(dev); 1079 if (IS_ERR(ctx->encoder)) 1080 return PTR_ERR(ctx->encoder); 1081 1082 pm_runtime_enable(dev); 1083 1084 ret = component_add(dev, &fimd_component_ops); 1085 if (ret) 1086 goto err_disable_pm_runtime; 1087 1088 return ret; 1089 1090 err_disable_pm_runtime: 1091 pm_runtime_disable(dev); 1092 1093 return ret; 1094 } 1095 1096 static int fimd_remove(struct platform_device *pdev) 1097 { 1098 pm_runtime_disable(&pdev->dev); 1099 1100 component_del(&pdev->dev, &fimd_component_ops); 1101 1102 return 0; 1103 } 1104 1105 struct platform_driver fimd_driver = { 1106 .probe = fimd_probe, 1107 .remove = fimd_remove, 1108 .driver = { 1109 .name = "exynos4-fb", 1110 .owner = THIS_MODULE, 1111 .of_match_table = fimd_driver_dt_match, 1112 }, 1113 }; 1114