1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* exynos_drm_fimd.c
3  *
4  * Copyright (C) 2011 Samsung Electronics Co.Ltd
5  * Authors:
6  *	Joonyoung Shim <jy0922.shim@samsung.com>
7  *	Inki Dae <inki.dae@samsung.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 
20 #include <video/of_display_timing.h>
21 #include <video/of_videomode.h>
22 #include <video/samsung_fimd.h>
23 
24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_vblank.h>
26 #include <drm/exynos_drm.h>
27 
28 #include "exynos_drm_crtc.h"
29 #include "exynos_drm_drv.h"
30 #include "exynos_drm_fb.h"
31 #include "exynos_drm_plane.h"
32 
33 /*
34  * FIMD stands for Fully Interactive Mobile Display and
35  * as a display controller, it transfers contents drawn on memory
36  * to a LCD Panel through Display Interfaces such as RGB or
37  * CPU Interface.
38  */
39 
40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
41 
42 /* position control register for hardware window 0, 2 ~ 4.*/
43 #define VIDOSD_A(win)		(VIDOSD_BASE + 0x00 + (win) * 16)
44 #define VIDOSD_B(win)		(VIDOSD_BASE + 0x04 + (win) * 16)
45 /*
46  * size control register for hardware windows 0 and alpha control register
47  * for hardware windows 1 ~ 4
48  */
49 #define VIDOSD_C(win)		(VIDOSD_BASE + 0x08 + (win) * 16)
50 /* size control register for hardware windows 1 ~ 2. */
51 #define VIDOSD_D(win)		(VIDOSD_BASE + 0x0C + (win) * 16)
52 
53 #define VIDWnALPHA0(win)	(VIDW_ALPHA + 0x00 + (win) * 8)
54 #define VIDWnALPHA1(win)	(VIDW_ALPHA + 0x04 + (win) * 8)
55 
56 #define VIDWx_BUF_START(win, buf)	(VIDW_BUF_START(buf) + (win) * 8)
57 #define VIDWx_BUF_START_S(win, buf)	(VIDW_BUF_START_S(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf)		(VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf)	(VIDW_BUF_SIZE(buf) + (win) * 4)
60 
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x)		((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x)		((WKEYCON1 + 0x140) + ((x - 1) * 8))
65 
66 /* I80 trigger control register */
67 #define TRIGCON				0x1A4
68 #define TRGMODE_ENABLE			(1 << 0)
69 #define SWTRGCMD_ENABLE			(1 << 1)
70 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
71 #define HWTRGEN_ENABLE			(1 << 3)
72 #define HWTRGMASK_ENABLE		(1 << 4)
73 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
74 #define HWTRIGEN_PER_ENABLE		(1 << 31)
75 
76 /* display mode change control register except exynos4 */
77 #define VIDOUT_CON			0x000
78 #define VIDOUT_CON_F_I80_LDI0		(0x2 << 8)
79 
80 /* I80 interface control for main LDI register */
81 #define I80IFCONFAx(x)			(0x1B0 + (x) * 4)
82 #define I80IFCONFBx(x)			(0x1B8 + (x) * 4)
83 #define LCD_CS_SETUP(x)			((x) << 16)
84 #define LCD_WR_SETUP(x)			((x) << 12)
85 #define LCD_WR_ACTIVE(x)		((x) << 8)
86 #define LCD_WR_HOLD(x)			((x) << 4)
87 #define I80IFEN_ENABLE			(1 << 0)
88 
89 /* FIMD has totally five hardware windows. */
90 #define WINDOWS_NR	5
91 
92 /* HW trigger flag on i80 panel. */
93 #define I80_HW_TRG     (1 << 1)
94 
95 struct fimd_driver_data {
96 	unsigned int timing_base;
97 	unsigned int lcdblk_offset;
98 	unsigned int lcdblk_vt_shift;
99 	unsigned int lcdblk_bypass_shift;
100 	unsigned int lcdblk_mic_bypass_shift;
101 	unsigned int trg_type;
102 
103 	unsigned int has_shadowcon:1;
104 	unsigned int has_clksel:1;
105 	unsigned int has_limited_fmt:1;
106 	unsigned int has_vidoutcon:1;
107 	unsigned int has_vtsel:1;
108 	unsigned int has_mic_bypass:1;
109 	unsigned int has_dp_clk:1;
110 	unsigned int has_hw_trigger:1;
111 	unsigned int has_trigger_per_te:1;
112 };
113 
114 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
115 	.timing_base = 0x0,
116 	.has_clksel = 1,
117 	.has_limited_fmt = 1,
118 };
119 
120 static struct fimd_driver_data s5pv210_fimd_driver_data = {
121 	.timing_base = 0x0,
122 	.has_shadowcon = 1,
123 	.has_clksel = 1,
124 };
125 
126 static struct fimd_driver_data exynos3_fimd_driver_data = {
127 	.timing_base = 0x20000,
128 	.lcdblk_offset = 0x210,
129 	.lcdblk_bypass_shift = 1,
130 	.has_shadowcon = 1,
131 	.has_vidoutcon = 1,
132 };
133 
134 static struct fimd_driver_data exynos4_fimd_driver_data = {
135 	.timing_base = 0x0,
136 	.lcdblk_offset = 0x210,
137 	.lcdblk_vt_shift = 10,
138 	.lcdblk_bypass_shift = 1,
139 	.has_shadowcon = 1,
140 	.has_vtsel = 1,
141 };
142 
143 static struct fimd_driver_data exynos5_fimd_driver_data = {
144 	.timing_base = 0x20000,
145 	.lcdblk_offset = 0x214,
146 	.lcdblk_vt_shift = 24,
147 	.lcdblk_bypass_shift = 15,
148 	.has_shadowcon = 1,
149 	.has_vidoutcon = 1,
150 	.has_vtsel = 1,
151 	.has_dp_clk = 1,
152 };
153 
154 static struct fimd_driver_data exynos5420_fimd_driver_data = {
155 	.timing_base = 0x20000,
156 	.lcdblk_offset = 0x214,
157 	.lcdblk_vt_shift = 24,
158 	.lcdblk_bypass_shift = 15,
159 	.lcdblk_mic_bypass_shift = 11,
160 	.has_shadowcon = 1,
161 	.has_vidoutcon = 1,
162 	.has_vtsel = 1,
163 	.has_mic_bypass = 1,
164 	.has_dp_clk = 1,
165 };
166 
167 struct fimd_context {
168 	struct device			*dev;
169 	struct drm_device		*drm_dev;
170 	void				*dma_priv;
171 	struct exynos_drm_crtc		*crtc;
172 	struct exynos_drm_plane		planes[WINDOWS_NR];
173 	struct exynos_drm_plane_config	configs[WINDOWS_NR];
174 	struct clk			*bus_clk;
175 	struct clk			*lcd_clk;
176 	void __iomem			*regs;
177 	struct regmap			*sysreg;
178 	unsigned long			irq_flags;
179 	u32				vidcon0;
180 	u32				vidcon1;
181 	u32				vidout_con;
182 	u32				i80ifcon;
183 	bool				i80_if;
184 	bool				suspended;
185 	wait_queue_head_t		wait_vsync_queue;
186 	atomic_t			wait_vsync_event;
187 	atomic_t			win_updated;
188 	atomic_t			triggering;
189 	u32				clkdiv;
190 
191 	const struct fimd_driver_data *driver_data;
192 	struct drm_encoder *encoder;
193 	struct exynos_drm_clk		dp_clk;
194 };
195 
196 static const struct of_device_id fimd_driver_dt_match[] = {
197 	{ .compatible = "samsung,s3c6400-fimd",
198 	  .data = &s3c64xx_fimd_driver_data },
199 	{ .compatible = "samsung,s5pv210-fimd",
200 	  .data = &s5pv210_fimd_driver_data },
201 	{ .compatible = "samsung,exynos3250-fimd",
202 	  .data = &exynos3_fimd_driver_data },
203 	{ .compatible = "samsung,exynos4210-fimd",
204 	  .data = &exynos4_fimd_driver_data },
205 	{ .compatible = "samsung,exynos5250-fimd",
206 	  .data = &exynos5_fimd_driver_data },
207 	{ .compatible = "samsung,exynos5420-fimd",
208 	  .data = &exynos5420_fimd_driver_data },
209 	{},
210 };
211 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
212 
213 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
214 	DRM_PLANE_TYPE_PRIMARY,
215 	DRM_PLANE_TYPE_OVERLAY,
216 	DRM_PLANE_TYPE_OVERLAY,
217 	DRM_PLANE_TYPE_OVERLAY,
218 	DRM_PLANE_TYPE_CURSOR,
219 };
220 
221 static const uint32_t fimd_formats[] = {
222 	DRM_FORMAT_C8,
223 	DRM_FORMAT_XRGB1555,
224 	DRM_FORMAT_RGB565,
225 	DRM_FORMAT_XRGB8888,
226 	DRM_FORMAT_ARGB8888,
227 };
228 
229 static const unsigned int capabilities[WINDOWS_NR] = {
230 	0,
231 	EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
232 	EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
233 	EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
234 	EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
235 };
236 
237 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
238 				 u32 val)
239 {
240 	val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
241 	writel(val, ctx->regs + reg);
242 }
243 
244 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
245 {
246 	struct fimd_context *ctx = crtc->ctx;
247 	u32 val;
248 
249 	if (ctx->suspended)
250 		return -EPERM;
251 
252 	if (!test_and_set_bit(0, &ctx->irq_flags)) {
253 		val = readl(ctx->regs + VIDINTCON0);
254 
255 		val |= VIDINTCON0_INT_ENABLE;
256 
257 		if (ctx->i80_if) {
258 			val |= VIDINTCON0_INT_I80IFDONE;
259 			val |= VIDINTCON0_INT_SYSMAINCON;
260 			val &= ~VIDINTCON0_INT_SYSSUBCON;
261 		} else {
262 			val |= VIDINTCON0_INT_FRAME;
263 
264 			val &= ~VIDINTCON0_FRAMESEL0_MASK;
265 			val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
266 			val &= ~VIDINTCON0_FRAMESEL1_MASK;
267 			val |= VIDINTCON0_FRAMESEL1_NONE;
268 		}
269 
270 		writel(val, ctx->regs + VIDINTCON0);
271 	}
272 
273 	return 0;
274 }
275 
276 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
277 {
278 	struct fimd_context *ctx = crtc->ctx;
279 	u32 val;
280 
281 	if (ctx->suspended)
282 		return;
283 
284 	if (test_and_clear_bit(0, &ctx->irq_flags)) {
285 		val = readl(ctx->regs + VIDINTCON0);
286 
287 		val &= ~VIDINTCON0_INT_ENABLE;
288 
289 		if (ctx->i80_if) {
290 			val &= ~VIDINTCON0_INT_I80IFDONE;
291 			val &= ~VIDINTCON0_INT_SYSMAINCON;
292 			val &= ~VIDINTCON0_INT_SYSSUBCON;
293 		} else
294 			val &= ~VIDINTCON0_INT_FRAME;
295 
296 		writel(val, ctx->regs + VIDINTCON0);
297 	}
298 }
299 
300 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
301 {
302 	struct fimd_context *ctx = crtc->ctx;
303 
304 	if (ctx->suspended)
305 		return;
306 
307 	atomic_set(&ctx->wait_vsync_event, 1);
308 
309 	/*
310 	 * wait for FIMD to signal VSYNC interrupt or return after
311 	 * timeout which is set to 50ms (refresh rate of 20).
312 	 */
313 	if (!wait_event_timeout(ctx->wait_vsync_queue,
314 				!atomic_read(&ctx->wait_vsync_event),
315 				HZ/20))
316 		DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
317 }
318 
319 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
320 					bool enable)
321 {
322 	u32 val = readl(ctx->regs + WINCON(win));
323 
324 	if (enable)
325 		val |= WINCONx_ENWIN;
326 	else
327 		val &= ~WINCONx_ENWIN;
328 
329 	writel(val, ctx->regs + WINCON(win));
330 }
331 
332 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
333 						unsigned int win,
334 						bool enable)
335 {
336 	u32 val = readl(ctx->regs + SHADOWCON);
337 
338 	if (enable)
339 		val |= SHADOWCON_CHx_ENABLE(win);
340 	else
341 		val &= ~SHADOWCON_CHx_ENABLE(win);
342 
343 	writel(val, ctx->regs + SHADOWCON);
344 }
345 
346 static int fimd_clear_channels(struct exynos_drm_crtc *crtc)
347 {
348 	struct fimd_context *ctx = crtc->ctx;
349 	unsigned int win, ch_enabled = 0;
350 	int ret;
351 
352 	/* Hardware is in unknown state, so ensure it gets enabled properly */
353 	ret = pm_runtime_resume_and_get(ctx->dev);
354 	if (ret < 0) {
355 		dev_err(ctx->dev, "failed to enable FIMD device.\n");
356 		return ret;
357 	}
358 
359 	clk_prepare_enable(ctx->bus_clk);
360 	clk_prepare_enable(ctx->lcd_clk);
361 
362 	/* Check if any channel is enabled. */
363 	for (win = 0; win < WINDOWS_NR; win++) {
364 		u32 val = readl(ctx->regs + WINCON(win));
365 
366 		if (val & WINCONx_ENWIN) {
367 			fimd_enable_video_output(ctx, win, false);
368 
369 			if (ctx->driver_data->has_shadowcon)
370 				fimd_enable_shadow_channel_path(ctx, win,
371 								false);
372 
373 			ch_enabled = 1;
374 		}
375 	}
376 
377 	/* Wait for vsync, as disable channel takes effect at next vsync */
378 	if (ch_enabled) {
379 		ctx->suspended = false;
380 
381 		fimd_enable_vblank(ctx->crtc);
382 		fimd_wait_for_vblank(ctx->crtc);
383 		fimd_disable_vblank(ctx->crtc);
384 
385 		ctx->suspended = true;
386 	}
387 
388 	clk_disable_unprepare(ctx->lcd_clk);
389 	clk_disable_unprepare(ctx->bus_clk);
390 
391 	pm_runtime_put(ctx->dev);
392 
393 	return 0;
394 }
395 
396 
397 static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
398 		struct drm_crtc_state *state)
399 {
400 	struct drm_display_mode *mode = &state->adjusted_mode;
401 	struct fimd_context *ctx = crtc->ctx;
402 	unsigned long ideal_clk, lcd_rate;
403 	u32 clkdiv;
404 
405 	if (mode->clock == 0) {
406 		DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
407 		return -EINVAL;
408 	}
409 
410 	ideal_clk = mode->clock * 1000;
411 
412 	if (ctx->i80_if) {
413 		/*
414 		 * The frame done interrupt should be occurred prior to the
415 		 * next TE signal.
416 		 */
417 		ideal_clk *= 2;
418 	}
419 
420 	lcd_rate = clk_get_rate(ctx->lcd_clk);
421 	if (2 * lcd_rate < ideal_clk) {
422 		DRM_DEV_ERROR(ctx->dev,
423 			      "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
424 			      lcd_rate, ideal_clk);
425 		return -EINVAL;
426 	}
427 
428 	/* Find the clock divider value that gets us closest to ideal_clk */
429 	clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
430 	if (clkdiv >= 0x200) {
431 		DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
432 			      ideal_clk);
433 		return -EINVAL;
434 	}
435 
436 	ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
437 
438 	return 0;
439 }
440 
441 static void fimd_setup_trigger(struct fimd_context *ctx)
442 {
443 	void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
444 	u32 trg_type = ctx->driver_data->trg_type;
445 	u32 val = readl(timing_base + TRIGCON);
446 
447 	val &= ~(TRGMODE_ENABLE);
448 
449 	if (trg_type == I80_HW_TRG) {
450 		if (ctx->driver_data->has_hw_trigger)
451 			val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
452 		if (ctx->driver_data->has_trigger_per_te)
453 			val |= HWTRIGEN_PER_ENABLE;
454 	} else {
455 		val |= TRGMODE_ENABLE;
456 	}
457 
458 	writel(val, timing_base + TRIGCON);
459 }
460 
461 static void fimd_commit(struct exynos_drm_crtc *crtc)
462 {
463 	struct fimd_context *ctx = crtc->ctx;
464 	struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
465 	const struct fimd_driver_data *driver_data = ctx->driver_data;
466 	void *timing_base = ctx->regs + driver_data->timing_base;
467 	u32 val;
468 
469 	if (ctx->suspended)
470 		return;
471 
472 	/* nothing to do if we haven't set the mode yet */
473 	if (mode->htotal == 0 || mode->vtotal == 0)
474 		return;
475 
476 	if (ctx->i80_if) {
477 		val = ctx->i80ifcon | I80IFEN_ENABLE;
478 		writel(val, timing_base + I80IFCONFAx(0));
479 
480 		/* disable auto frame rate */
481 		writel(0, timing_base + I80IFCONFBx(0));
482 
483 		/* set video type selection to I80 interface */
484 		if (driver_data->has_vtsel && ctx->sysreg &&
485 				regmap_update_bits(ctx->sysreg,
486 					driver_data->lcdblk_offset,
487 					0x3 << driver_data->lcdblk_vt_shift,
488 					0x1 << driver_data->lcdblk_vt_shift)) {
489 			DRM_DEV_ERROR(ctx->dev,
490 				      "Failed to update sysreg for I80 i/f.\n");
491 			return;
492 		}
493 	} else {
494 		int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
495 		u32 vidcon1;
496 
497 		/* setup polarity values */
498 		vidcon1 = ctx->vidcon1;
499 		if (mode->flags & DRM_MODE_FLAG_NVSYNC)
500 			vidcon1 |= VIDCON1_INV_VSYNC;
501 		if (mode->flags & DRM_MODE_FLAG_NHSYNC)
502 			vidcon1 |= VIDCON1_INV_HSYNC;
503 		writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
504 
505 		/* setup vertical timing values. */
506 		vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
507 		vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
508 		vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
509 
510 		val = VIDTCON0_VBPD(vbpd - 1) |
511 			VIDTCON0_VFPD(vfpd - 1) |
512 			VIDTCON0_VSPW(vsync_len - 1);
513 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
514 
515 		/* setup horizontal timing values.  */
516 		hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
517 		hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
518 		hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
519 
520 		val = VIDTCON1_HBPD(hbpd - 1) |
521 			VIDTCON1_HFPD(hfpd - 1) |
522 			VIDTCON1_HSPW(hsync_len - 1);
523 		writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
524 	}
525 
526 	if (driver_data->has_vidoutcon)
527 		writel(ctx->vidout_con, timing_base + VIDOUT_CON);
528 
529 	/* set bypass selection */
530 	if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
531 				driver_data->lcdblk_offset,
532 				0x1 << driver_data->lcdblk_bypass_shift,
533 				0x1 << driver_data->lcdblk_bypass_shift)) {
534 		DRM_DEV_ERROR(ctx->dev,
535 			      "Failed to update sysreg for bypass setting.\n");
536 		return;
537 	}
538 
539 	/* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
540 	 * bit should be cleared.
541 	 */
542 	if (driver_data->has_mic_bypass && ctx->sysreg &&
543 	    regmap_update_bits(ctx->sysreg,
544 				driver_data->lcdblk_offset,
545 				0x1 << driver_data->lcdblk_mic_bypass_shift,
546 				0x1 << driver_data->lcdblk_mic_bypass_shift)) {
547 		DRM_DEV_ERROR(ctx->dev,
548 			      "Failed to update sysreg for bypass mic.\n");
549 		return;
550 	}
551 
552 	/* setup horizontal and vertical display size. */
553 	val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
554 	       VIDTCON2_HOZVAL(mode->hdisplay - 1) |
555 	       VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
556 	       VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
557 	writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
558 
559 	fimd_setup_trigger(ctx);
560 
561 	/*
562 	 * fields of register with prefix '_F' would be updated
563 	 * at vsync(same as dma start)
564 	 */
565 	val = ctx->vidcon0;
566 	val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
567 
568 	if (ctx->driver_data->has_clksel)
569 		val |= VIDCON0_CLKSEL_LCD;
570 
571 	if (ctx->clkdiv > 1)
572 		val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
573 
574 	writel(val, ctx->regs + VIDCON0);
575 }
576 
577 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
578 			       unsigned int alpha, unsigned int pixel_alpha)
579 {
580 	u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
581 	u32 val = 0;
582 
583 	switch (pixel_alpha) {
584 	case DRM_MODE_BLEND_PIXEL_NONE:
585 	case DRM_MODE_BLEND_COVERAGE:
586 		val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
587 		val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
588 		break;
589 	case DRM_MODE_BLEND_PREMULTI:
590 	default:
591 		if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
592 			val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
593 			val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
594 		} else {
595 			val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
596 			val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
597 		}
598 		break;
599 	}
600 	fimd_set_bits(ctx, BLENDEQx(win), mask, val);
601 }
602 
603 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
604 				unsigned int alpha, unsigned int pixel_alpha)
605 {
606 	u32 win_alpha_l = (alpha >> 8) & 0xf;
607 	u32 win_alpha_h = alpha >> 12;
608 	u32 val = 0;
609 
610 	switch (pixel_alpha) {
611 	case DRM_MODE_BLEND_PIXEL_NONE:
612 		break;
613 	case DRM_MODE_BLEND_COVERAGE:
614 	case DRM_MODE_BLEND_PREMULTI:
615 	default:
616 		val |= WINCON1_ALPHA_SEL;
617 		val |= WINCON1_BLD_PIX;
618 		val |= WINCON1_ALPHA_MUL;
619 		break;
620 	}
621 	fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
622 
623 	/* OSD alpha */
624 	val = VIDISD14C_ALPHA0_R(win_alpha_h) |
625 		VIDISD14C_ALPHA0_G(win_alpha_h) |
626 		VIDISD14C_ALPHA0_B(win_alpha_h) |
627 		VIDISD14C_ALPHA1_R(0x0) |
628 		VIDISD14C_ALPHA1_G(0x0) |
629 		VIDISD14C_ALPHA1_B(0x0);
630 	writel(val, ctx->regs + VIDOSD_C(win));
631 
632 	val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
633 		VIDW_ALPHA_B(win_alpha_l);
634 	writel(val, ctx->regs + VIDWnALPHA0(win));
635 
636 	val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
637 		VIDW_ALPHA_B(0x0);
638 	writel(val, ctx->regs + VIDWnALPHA1(win));
639 
640 	fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
641 			BLENDCON_NEW_8BIT_ALPHA_VALUE);
642 }
643 
644 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
645 				struct drm_framebuffer *fb, int width)
646 {
647 	struct exynos_drm_plane plane = ctx->planes[win];
648 	struct exynos_drm_plane_state *state =
649 		to_exynos_plane_state(plane.base.state);
650 	uint32_t pixel_format = fb->format->format;
651 	unsigned int alpha = state->base.alpha;
652 	u32 val = WINCONx_ENWIN;
653 	unsigned int pixel_alpha;
654 
655 	if (fb->format->has_alpha)
656 		pixel_alpha = state->base.pixel_blend_mode;
657 	else
658 		pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
659 
660 	/*
661 	 * In case of s3c64xx, window 0 doesn't support alpha channel.
662 	 * So the request format is ARGB8888 then change it to XRGB8888.
663 	 */
664 	if (ctx->driver_data->has_limited_fmt && !win) {
665 		if (pixel_format == DRM_FORMAT_ARGB8888)
666 			pixel_format = DRM_FORMAT_XRGB8888;
667 	}
668 
669 	switch (pixel_format) {
670 	case DRM_FORMAT_C8:
671 		val |= WINCON0_BPPMODE_8BPP_PALETTE;
672 		val |= WINCONx_BURSTLEN_8WORD;
673 		val |= WINCONx_BYTSWP;
674 		break;
675 	case DRM_FORMAT_XRGB1555:
676 		val |= WINCON0_BPPMODE_16BPP_1555;
677 		val |= WINCONx_HAWSWP;
678 		val |= WINCONx_BURSTLEN_16WORD;
679 		break;
680 	case DRM_FORMAT_RGB565:
681 		val |= WINCON0_BPPMODE_16BPP_565;
682 		val |= WINCONx_HAWSWP;
683 		val |= WINCONx_BURSTLEN_16WORD;
684 		break;
685 	case DRM_FORMAT_XRGB8888:
686 		val |= WINCON0_BPPMODE_24BPP_888;
687 		val |= WINCONx_WSWP;
688 		val |= WINCONx_BURSTLEN_16WORD;
689 		break;
690 	case DRM_FORMAT_ARGB8888:
691 	default:
692 		val |= WINCON1_BPPMODE_25BPP_A1888;
693 		val |= WINCONx_WSWP;
694 		val |= WINCONx_BURSTLEN_16WORD;
695 		break;
696 	}
697 
698 	/*
699 	 * Setting dma-burst to 16Word causes permanent tearing for very small
700 	 * buffers, e.g. cursor buffer. Burst Mode switching which based on
701 	 * plane size is not recommended as plane size varies alot towards the
702 	 * end of the screen and rapid movement causes unstable DMA, but it is
703 	 * still better to change dma-burst than displaying garbage.
704 	 */
705 
706 	if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
707 		val &= ~WINCONx_BURSTLEN_MASK;
708 		val |= WINCONx_BURSTLEN_4WORD;
709 	}
710 	fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
711 
712 	/* hardware window 0 doesn't support alpha channel. */
713 	if (win != 0) {
714 		fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
715 		fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
716 	}
717 }
718 
719 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
720 {
721 	unsigned int keycon0 = 0, keycon1 = 0;
722 
723 	keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
724 			WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
725 
726 	keycon1 = WxKEYCON1_COLVAL(0xffffffff);
727 
728 	writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
729 	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
730 }
731 
732 /**
733  * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync
734  *
735  * @ctx: local driver data
736  * @win: window to protect registers for
737  * @protect: 1 to protect (disable updates)
738  */
739 static void fimd_shadow_protect_win(struct fimd_context *ctx,
740 				    unsigned int win, bool protect)
741 {
742 	u32 reg, bits, val;
743 
744 	/*
745 	 * SHADOWCON/PRTCON register is used for enabling timing.
746 	 *
747 	 * for example, once only width value of a register is set,
748 	 * if the dma is started then fimd hardware could malfunction so
749 	 * with protect window setting, the register fields with prefix '_F'
750 	 * wouldn't be updated at vsync also but updated once unprotect window
751 	 * is set.
752 	 */
753 
754 	if (ctx->driver_data->has_shadowcon) {
755 		reg = SHADOWCON;
756 		bits = SHADOWCON_WINx_PROTECT(win);
757 	} else {
758 		reg = PRTCON;
759 		bits = PRTCON_PROTECT;
760 	}
761 
762 	val = readl(ctx->regs + reg);
763 	if (protect)
764 		val |= bits;
765 	else
766 		val &= ~bits;
767 	writel(val, ctx->regs + reg);
768 }
769 
770 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
771 {
772 	struct fimd_context *ctx = crtc->ctx;
773 	int i;
774 
775 	if (ctx->suspended)
776 		return;
777 
778 	for (i = 0; i < WINDOWS_NR; i++)
779 		fimd_shadow_protect_win(ctx, i, true);
780 }
781 
782 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
783 {
784 	struct fimd_context *ctx = crtc->ctx;
785 	int i;
786 
787 	if (ctx->suspended)
788 		return;
789 
790 	for (i = 0; i < WINDOWS_NR; i++)
791 		fimd_shadow_protect_win(ctx, i, false);
792 
793 	exynos_crtc_handle_event(crtc);
794 }
795 
796 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
797 			      struct exynos_drm_plane *plane)
798 {
799 	struct exynos_drm_plane_state *state =
800 				to_exynos_plane_state(plane->base.state);
801 	struct fimd_context *ctx = crtc->ctx;
802 	struct drm_framebuffer *fb = state->base.fb;
803 	dma_addr_t dma_addr;
804 	unsigned long val, size, offset;
805 	unsigned int last_x, last_y, buf_offsize, line_size;
806 	unsigned int win = plane->index;
807 	unsigned int cpp = fb->format->cpp[0];
808 	unsigned int pitch = fb->pitches[0];
809 
810 	if (ctx->suspended)
811 		return;
812 
813 	offset = state->src.x * cpp;
814 	offset += state->src.y * pitch;
815 
816 	/* buffer start address */
817 	dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
818 	val = (unsigned long)dma_addr;
819 	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
820 
821 	/* buffer end address */
822 	size = pitch * state->crtc.h;
823 	val = (unsigned long)(dma_addr + size);
824 	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
825 
826 	DRM_DEV_DEBUG_KMS(ctx->dev,
827 			  "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
828 			  (unsigned long)dma_addr, val, size);
829 	DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
830 			  state->crtc.w, state->crtc.h);
831 
832 	/* buffer size */
833 	buf_offsize = pitch - (state->crtc.w * cpp);
834 	line_size = state->crtc.w * cpp;
835 	val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
836 		VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
837 		VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
838 		VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
839 	writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
840 
841 	/* OSD position */
842 	val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
843 		VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
844 		VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
845 		VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
846 	writel(val, ctx->regs + VIDOSD_A(win));
847 
848 	last_x = state->crtc.x + state->crtc.w;
849 	if (last_x)
850 		last_x--;
851 	last_y = state->crtc.y + state->crtc.h;
852 	if (last_y)
853 		last_y--;
854 
855 	val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
856 		VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
857 
858 	writel(val, ctx->regs + VIDOSD_B(win));
859 
860 	DRM_DEV_DEBUG_KMS(ctx->dev,
861 			  "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
862 			  state->crtc.x, state->crtc.y, last_x, last_y);
863 
864 	/* OSD size */
865 	if (win != 3 && win != 4) {
866 		u32 offset = VIDOSD_D(win);
867 		if (win == 0)
868 			offset = VIDOSD_C(win);
869 		val = state->crtc.w * state->crtc.h;
870 		writel(val, ctx->regs + offset);
871 
872 		DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
873 				  (unsigned int)val);
874 	}
875 
876 	fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
877 
878 	/* hardware window 0 doesn't support color key. */
879 	if (win != 0)
880 		fimd_win_set_colkey(ctx, win);
881 
882 	fimd_enable_video_output(ctx, win, true);
883 
884 	if (ctx->driver_data->has_shadowcon)
885 		fimd_enable_shadow_channel_path(ctx, win, true);
886 
887 	if (ctx->i80_if)
888 		atomic_set(&ctx->win_updated, 1);
889 }
890 
891 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
892 			       struct exynos_drm_plane *plane)
893 {
894 	struct fimd_context *ctx = crtc->ctx;
895 	unsigned int win = plane->index;
896 
897 	if (ctx->suspended)
898 		return;
899 
900 	fimd_enable_video_output(ctx, win, false);
901 
902 	if (ctx->driver_data->has_shadowcon)
903 		fimd_enable_shadow_channel_path(ctx, win, false);
904 }
905 
906 static void fimd_atomic_enable(struct exynos_drm_crtc *crtc)
907 {
908 	struct fimd_context *ctx = crtc->ctx;
909 
910 	if (!ctx->suspended)
911 		return;
912 
913 	ctx->suspended = false;
914 
915 	if (pm_runtime_resume_and_get(ctx->dev) < 0) {
916 		dev_warn(ctx->dev, "failed to enable FIMD device.\n");
917 		return;
918 	}
919 
920 	/* if vblank was enabled status, enable it again. */
921 	if (test_and_clear_bit(0, &ctx->irq_flags))
922 		fimd_enable_vblank(ctx->crtc);
923 
924 	fimd_commit(ctx->crtc);
925 }
926 
927 static void fimd_atomic_disable(struct exynos_drm_crtc *crtc)
928 {
929 	struct fimd_context *ctx = crtc->ctx;
930 	int i;
931 
932 	if (ctx->suspended)
933 		return;
934 
935 	/*
936 	 * We need to make sure that all windows are disabled before we
937 	 * suspend that connector. Otherwise we might try to scan from
938 	 * a destroyed buffer later.
939 	 */
940 	for (i = 0; i < WINDOWS_NR; i++)
941 		fimd_disable_plane(crtc, &ctx->planes[i]);
942 
943 	fimd_enable_vblank(crtc);
944 	fimd_wait_for_vblank(crtc);
945 	fimd_disable_vblank(crtc);
946 
947 	writel(0, ctx->regs + VIDCON0);
948 
949 	pm_runtime_put_sync(ctx->dev);
950 	ctx->suspended = true;
951 }
952 
953 static void fimd_trigger(struct device *dev)
954 {
955 	struct fimd_context *ctx = dev_get_drvdata(dev);
956 	const struct fimd_driver_data *driver_data = ctx->driver_data;
957 	void *timing_base = ctx->regs + driver_data->timing_base;
958 	u32 reg;
959 
960 	 /*
961 	  * Skips triggering if in triggering state, because multiple triggering
962 	  * requests can cause panel reset.
963 	  */
964 	if (atomic_read(&ctx->triggering))
965 		return;
966 
967 	/* Enters triggering mode */
968 	atomic_set(&ctx->triggering, 1);
969 
970 	reg = readl(timing_base + TRIGCON);
971 	reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
972 	writel(reg, timing_base + TRIGCON);
973 
974 	/*
975 	 * Exits triggering mode if vblank is not enabled yet, because when the
976 	 * VIDINTCON0 register is not set, it can not exit from triggering mode.
977 	 */
978 	if (!test_bit(0, &ctx->irq_flags))
979 		atomic_set(&ctx->triggering, 0);
980 }
981 
982 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
983 {
984 	struct fimd_context *ctx = crtc->ctx;
985 	u32 trg_type = ctx->driver_data->trg_type;
986 
987 	/* Checks the crtc is detached already from encoder */
988 	if (!ctx->drm_dev)
989 		return;
990 
991 	if (trg_type == I80_HW_TRG)
992 		goto out;
993 
994 	/*
995 	 * If there is a page flip request, triggers and handles the page flip
996 	 * event so that current fb can be updated into panel GRAM.
997 	 */
998 	if (atomic_add_unless(&ctx->win_updated, -1, 0))
999 		fimd_trigger(ctx->dev);
1000 
1001 out:
1002 	/* Wakes up vsync event queue */
1003 	if (atomic_read(&ctx->wait_vsync_event)) {
1004 		atomic_set(&ctx->wait_vsync_event, 0);
1005 		wake_up(&ctx->wait_vsync_queue);
1006 	}
1007 
1008 	if (test_bit(0, &ctx->irq_flags))
1009 		drm_crtc_handle_vblank(&ctx->crtc->base);
1010 }
1011 
1012 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
1013 {
1014 	struct fimd_context *ctx = container_of(clk, struct fimd_context,
1015 						dp_clk);
1016 	u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1017 	writel(val, ctx->regs + DP_MIE_CLKCON);
1018 }
1019 
1020 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
1021 	.atomic_enable = fimd_atomic_enable,
1022 	.atomic_disable = fimd_atomic_disable,
1023 	.enable_vblank = fimd_enable_vblank,
1024 	.disable_vblank = fimd_disable_vblank,
1025 	.atomic_begin = fimd_atomic_begin,
1026 	.update_plane = fimd_update_plane,
1027 	.disable_plane = fimd_disable_plane,
1028 	.atomic_flush = fimd_atomic_flush,
1029 	.atomic_check = fimd_atomic_check,
1030 	.te_handler = fimd_te_handler,
1031 };
1032 
1033 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1034 {
1035 	struct fimd_context *ctx = (struct fimd_context *)dev_id;
1036 	u32 val, clear_bit;
1037 
1038 	val = readl(ctx->regs + VIDINTCON1);
1039 
1040 	clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1041 	if (val & clear_bit)
1042 		writel(clear_bit, ctx->regs + VIDINTCON1);
1043 
1044 	/* check the crtc is detached already from encoder */
1045 	if (!ctx->drm_dev)
1046 		goto out;
1047 
1048 	if (!ctx->i80_if)
1049 		drm_crtc_handle_vblank(&ctx->crtc->base);
1050 
1051 	if (ctx->i80_if) {
1052 		/* Exits triggering mode */
1053 		atomic_set(&ctx->triggering, 0);
1054 	} else {
1055 		/* set wait vsync event to zero and wake up queue. */
1056 		if (atomic_read(&ctx->wait_vsync_event)) {
1057 			atomic_set(&ctx->wait_vsync_event, 0);
1058 			wake_up(&ctx->wait_vsync_queue);
1059 		}
1060 	}
1061 
1062 out:
1063 	return IRQ_HANDLED;
1064 }
1065 
1066 static int fimd_bind(struct device *dev, struct device *master, void *data)
1067 {
1068 	struct fimd_context *ctx = dev_get_drvdata(dev);
1069 	struct drm_device *drm_dev = data;
1070 	struct exynos_drm_plane *exynos_plane;
1071 	unsigned int i;
1072 	int ret;
1073 
1074 	ctx->drm_dev = drm_dev;
1075 
1076 	for (i = 0; i < WINDOWS_NR; i++) {
1077 		ctx->configs[i].pixel_formats = fimd_formats;
1078 		ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1079 		ctx->configs[i].zpos = i;
1080 		ctx->configs[i].type = fimd_win_types[i];
1081 		ctx->configs[i].capabilities = capabilities[i];
1082 		ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1083 					&ctx->configs[i]);
1084 		if (ret)
1085 			return ret;
1086 	}
1087 
1088 	exynos_plane = &ctx->planes[DEFAULT_WIN];
1089 	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1090 			EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1091 	if (IS_ERR(ctx->crtc))
1092 		return PTR_ERR(ctx->crtc);
1093 
1094 	if (ctx->driver_data->has_dp_clk) {
1095 		ctx->dp_clk.enable = fimd_dp_clock_enable;
1096 		ctx->crtc->pipe_clk = &ctx->dp_clk;
1097 	}
1098 
1099 	if (ctx->encoder)
1100 		exynos_dpi_bind(drm_dev, ctx->encoder);
1101 
1102 	if (is_drm_iommu_supported(drm_dev)) {
1103 		int ret;
1104 
1105 		ret = fimd_clear_channels(ctx->crtc);
1106 		if (ret < 0)
1107 			return ret;
1108 	}
1109 
1110 	return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1111 }
1112 
1113 static void fimd_unbind(struct device *dev, struct device *master,
1114 			void *data)
1115 {
1116 	struct fimd_context *ctx = dev_get_drvdata(dev);
1117 
1118 	fimd_atomic_disable(ctx->crtc);
1119 
1120 	exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
1121 
1122 	if (ctx->encoder)
1123 		exynos_dpi_remove(ctx->encoder);
1124 }
1125 
1126 static const struct component_ops fimd_component_ops = {
1127 	.bind	= fimd_bind,
1128 	.unbind = fimd_unbind,
1129 };
1130 
1131 static int fimd_probe(struct platform_device *pdev)
1132 {
1133 	struct device *dev = &pdev->dev;
1134 	struct fimd_context *ctx;
1135 	struct device_node *i80_if_timings;
1136 	struct resource *res;
1137 	int ret;
1138 
1139 	if (!dev->of_node)
1140 		return -ENODEV;
1141 
1142 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1143 	if (!ctx)
1144 		return -ENOMEM;
1145 
1146 	ctx->dev = dev;
1147 	ctx->suspended = true;
1148 	ctx->driver_data = of_device_get_match_data(dev);
1149 
1150 	if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1151 		ctx->vidcon1 |= VIDCON1_INV_VDEN;
1152 	if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1153 		ctx->vidcon1 |= VIDCON1_INV_VCLK;
1154 
1155 	i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1156 	if (i80_if_timings) {
1157 		u32 val;
1158 
1159 		ctx->i80_if = true;
1160 
1161 		if (ctx->driver_data->has_vidoutcon)
1162 			ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1163 		else
1164 			ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1165 		/*
1166 		 * The user manual describes that this "DSI_EN" bit is required
1167 		 * to enable I80 24-bit data interface.
1168 		 */
1169 		ctx->vidcon0 |= VIDCON0_DSI_EN;
1170 
1171 		if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1172 			val = 0;
1173 		ctx->i80ifcon = LCD_CS_SETUP(val);
1174 		if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1175 			val = 0;
1176 		ctx->i80ifcon |= LCD_WR_SETUP(val);
1177 		if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1178 			val = 1;
1179 		ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1180 		if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1181 			val = 0;
1182 		ctx->i80ifcon |= LCD_WR_HOLD(val);
1183 	}
1184 	of_node_put(i80_if_timings);
1185 
1186 	ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1187 							"samsung,sysreg");
1188 	if (IS_ERR(ctx->sysreg)) {
1189 		dev_warn(dev, "failed to get system register.\n");
1190 		ctx->sysreg = NULL;
1191 	}
1192 
1193 	ctx->bus_clk = devm_clk_get(dev, "fimd");
1194 	if (IS_ERR(ctx->bus_clk)) {
1195 		dev_err(dev, "failed to get bus clock\n");
1196 		return PTR_ERR(ctx->bus_clk);
1197 	}
1198 
1199 	ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1200 	if (IS_ERR(ctx->lcd_clk)) {
1201 		dev_err(dev, "failed to get lcd clock\n");
1202 		return PTR_ERR(ctx->lcd_clk);
1203 	}
1204 
1205 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1206 
1207 	ctx->regs = devm_ioremap_resource(dev, res);
1208 	if (IS_ERR(ctx->regs))
1209 		return PTR_ERR(ctx->regs);
1210 
1211 	res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1212 					   ctx->i80_if ? "lcd_sys" : "vsync");
1213 	if (!res) {
1214 		dev_err(dev, "irq request failed.\n");
1215 		return -ENXIO;
1216 	}
1217 
1218 	ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1219 							0, "drm_fimd", ctx);
1220 	if (ret) {
1221 		dev_err(dev, "irq request failed.\n");
1222 		return ret;
1223 	}
1224 
1225 	init_waitqueue_head(&ctx->wait_vsync_queue);
1226 	atomic_set(&ctx->wait_vsync_event, 0);
1227 
1228 	platform_set_drvdata(pdev, ctx);
1229 
1230 	ctx->encoder = exynos_dpi_probe(dev);
1231 	if (IS_ERR(ctx->encoder))
1232 		return PTR_ERR(ctx->encoder);
1233 
1234 	pm_runtime_enable(dev);
1235 
1236 	ret = component_add(dev, &fimd_component_ops);
1237 	if (ret)
1238 		goto err_disable_pm_runtime;
1239 
1240 	return ret;
1241 
1242 err_disable_pm_runtime:
1243 	pm_runtime_disable(dev);
1244 
1245 	return ret;
1246 }
1247 
1248 static int fimd_remove(struct platform_device *pdev)
1249 {
1250 	pm_runtime_disable(&pdev->dev);
1251 
1252 	component_del(&pdev->dev, &fimd_component_ops);
1253 
1254 	return 0;
1255 }
1256 
1257 #ifdef CONFIG_PM
1258 static int exynos_fimd_suspend(struct device *dev)
1259 {
1260 	struct fimd_context *ctx = dev_get_drvdata(dev);
1261 
1262 	clk_disable_unprepare(ctx->lcd_clk);
1263 	clk_disable_unprepare(ctx->bus_clk);
1264 
1265 	return 0;
1266 }
1267 
1268 static int exynos_fimd_resume(struct device *dev)
1269 {
1270 	struct fimd_context *ctx = dev_get_drvdata(dev);
1271 	int ret;
1272 
1273 	ret = clk_prepare_enable(ctx->bus_clk);
1274 	if (ret < 0) {
1275 		DRM_DEV_ERROR(dev,
1276 			      "Failed to prepare_enable the bus clk [%d]\n",
1277 			      ret);
1278 		return ret;
1279 	}
1280 
1281 	ret = clk_prepare_enable(ctx->lcd_clk);
1282 	if  (ret < 0) {
1283 		DRM_DEV_ERROR(dev,
1284 			      "Failed to prepare_enable the lcd clk [%d]\n",
1285 			      ret);
1286 		return ret;
1287 	}
1288 
1289 	return 0;
1290 }
1291 #endif
1292 
1293 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1294 	SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1295 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1296 				pm_runtime_force_resume)
1297 };
1298 
1299 struct platform_driver fimd_driver = {
1300 	.probe		= fimd_probe,
1301 	.remove		= fimd_remove,
1302 	.driver		= {
1303 		.name	= "exynos4-fb",
1304 		.owner	= THIS_MODULE,
1305 		.pm	= &exynos_fimd_pm_ops,
1306 		.of_match_table = fimd_driver_dt_match,
1307 	},
1308 };
1309