1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/component.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/samsung_fimd.h> 29 #include <drm/exynos_drm.h> 30 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fb.h" 33 #include "exynos_drm_fbdev.h" 34 #include "exynos_drm_crtc.h" 35 #include "exynos_drm_plane.h" 36 #include "exynos_drm_iommu.h" 37 38 /* 39 * FIMD stands for Fully Interactive Mobile Display and 40 * as a display controller, it transfers contents drawn on memory 41 * to a LCD Panel through Display Interfaces such as RGB or 42 * CPU Interface. 43 */ 44 45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 46 47 /* position control register for hardware window 0, 2 ~ 4.*/ 48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 50 /* 51 * size control register for hardware windows 0 and alpha control register 52 * for hardware windows 1 ~ 4 53 */ 54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 55 /* size control register for hardware windows 1 ~ 2. */ 56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 57 58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 60 61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 62 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) 63 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 64 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 65 66 /* color key control register for hardware window 1 ~ 4. */ 67 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 68 /* color key value register for hardware window 1 ~ 4. */ 69 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 70 71 /* I80 / RGB trigger control register */ 72 #define TRIGCON 0x1A4 73 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 74 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 75 76 /* display mode change control register except exynos4 */ 77 #define VIDOUT_CON 0x000 78 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 79 80 /* I80 interface control for main LDI register */ 81 #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 82 #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 83 #define LCD_CS_SETUP(x) ((x) << 16) 84 #define LCD_WR_SETUP(x) ((x) << 12) 85 #define LCD_WR_ACTIVE(x) ((x) << 8) 86 #define LCD_WR_HOLD(x) ((x) << 4) 87 #define I80IFEN_ENABLE (1 << 0) 88 89 /* FIMD has totally five hardware windows. */ 90 #define WINDOWS_NR 5 91 92 struct fimd_driver_data { 93 unsigned int timing_base; 94 unsigned int lcdblk_offset; 95 unsigned int lcdblk_vt_shift; 96 unsigned int lcdblk_bypass_shift; 97 unsigned int lcdblk_mic_bypass_shift; 98 99 unsigned int has_shadowcon:1; 100 unsigned int has_clksel:1; 101 unsigned int has_limited_fmt:1; 102 unsigned int has_vidoutcon:1; 103 unsigned int has_vtsel:1; 104 unsigned int has_mic_bypass:1; 105 }; 106 107 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 108 .timing_base = 0x0, 109 .has_clksel = 1, 110 .has_limited_fmt = 1, 111 }; 112 113 static struct fimd_driver_data exynos3_fimd_driver_data = { 114 .timing_base = 0x20000, 115 .lcdblk_offset = 0x210, 116 .lcdblk_bypass_shift = 1, 117 .has_shadowcon = 1, 118 .has_vidoutcon = 1, 119 }; 120 121 static struct fimd_driver_data exynos4_fimd_driver_data = { 122 .timing_base = 0x0, 123 .lcdblk_offset = 0x210, 124 .lcdblk_vt_shift = 10, 125 .lcdblk_bypass_shift = 1, 126 .has_shadowcon = 1, 127 .has_vtsel = 1, 128 }; 129 130 static struct fimd_driver_data exynos4415_fimd_driver_data = { 131 .timing_base = 0x20000, 132 .lcdblk_offset = 0x210, 133 .lcdblk_vt_shift = 10, 134 .lcdblk_bypass_shift = 1, 135 .has_shadowcon = 1, 136 .has_vidoutcon = 1, 137 .has_vtsel = 1, 138 }; 139 140 static struct fimd_driver_data exynos5_fimd_driver_data = { 141 .timing_base = 0x20000, 142 .lcdblk_offset = 0x214, 143 .lcdblk_vt_shift = 24, 144 .lcdblk_bypass_shift = 15, 145 .has_shadowcon = 1, 146 .has_vidoutcon = 1, 147 .has_vtsel = 1, 148 }; 149 150 static struct fimd_driver_data exynos5420_fimd_driver_data = { 151 .timing_base = 0x20000, 152 .lcdblk_offset = 0x214, 153 .lcdblk_vt_shift = 24, 154 .lcdblk_bypass_shift = 15, 155 .lcdblk_mic_bypass_shift = 11, 156 .has_shadowcon = 1, 157 .has_vidoutcon = 1, 158 .has_vtsel = 1, 159 .has_mic_bypass = 1, 160 }; 161 162 struct fimd_context { 163 struct device *dev; 164 struct drm_device *drm_dev; 165 struct exynos_drm_crtc *crtc; 166 struct exynos_drm_plane planes[WINDOWS_NR]; 167 struct exynos_drm_plane_config configs[WINDOWS_NR]; 168 struct clk *bus_clk; 169 struct clk *lcd_clk; 170 void __iomem *regs; 171 struct regmap *sysreg; 172 unsigned long irq_flags; 173 u32 vidcon0; 174 u32 vidcon1; 175 u32 vidout_con; 176 u32 i80ifcon; 177 bool i80_if; 178 bool suspended; 179 int pipe; 180 wait_queue_head_t wait_vsync_queue; 181 atomic_t wait_vsync_event; 182 atomic_t win_updated; 183 atomic_t triggering; 184 185 struct fimd_driver_data *driver_data; 186 struct drm_encoder *encoder; 187 }; 188 189 static const struct of_device_id fimd_driver_dt_match[] = { 190 { .compatible = "samsung,s3c6400-fimd", 191 .data = &s3c64xx_fimd_driver_data }, 192 { .compatible = "samsung,exynos3250-fimd", 193 .data = &exynos3_fimd_driver_data }, 194 { .compatible = "samsung,exynos4210-fimd", 195 .data = &exynos4_fimd_driver_data }, 196 { .compatible = "samsung,exynos4415-fimd", 197 .data = &exynos4415_fimd_driver_data }, 198 { .compatible = "samsung,exynos5250-fimd", 199 .data = &exynos5_fimd_driver_data }, 200 { .compatible = "samsung,exynos5420-fimd", 201 .data = &exynos5420_fimd_driver_data }, 202 {}, 203 }; 204 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 205 206 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { 207 DRM_PLANE_TYPE_PRIMARY, 208 DRM_PLANE_TYPE_OVERLAY, 209 DRM_PLANE_TYPE_OVERLAY, 210 DRM_PLANE_TYPE_OVERLAY, 211 DRM_PLANE_TYPE_CURSOR, 212 }; 213 214 static const uint32_t fimd_formats[] = { 215 DRM_FORMAT_C8, 216 DRM_FORMAT_XRGB1555, 217 DRM_FORMAT_RGB565, 218 DRM_FORMAT_XRGB8888, 219 DRM_FORMAT_ARGB8888, 220 }; 221 222 static inline struct fimd_driver_data *drm_fimd_get_driver_data( 223 struct platform_device *pdev) 224 { 225 const struct of_device_id *of_id = 226 of_match_device(fimd_driver_dt_match, &pdev->dev); 227 228 return (struct fimd_driver_data *)of_id->data; 229 } 230 231 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 232 { 233 struct fimd_context *ctx = crtc->ctx; 234 u32 val; 235 236 if (ctx->suspended) 237 return -EPERM; 238 239 if (!test_and_set_bit(0, &ctx->irq_flags)) { 240 val = readl(ctx->regs + VIDINTCON0); 241 242 val |= VIDINTCON0_INT_ENABLE; 243 244 if (ctx->i80_if) { 245 val |= VIDINTCON0_INT_I80IFDONE; 246 val |= VIDINTCON0_INT_SYSMAINCON; 247 val &= ~VIDINTCON0_INT_SYSSUBCON; 248 } else { 249 val |= VIDINTCON0_INT_FRAME; 250 251 val &= ~VIDINTCON0_FRAMESEL0_MASK; 252 val |= VIDINTCON0_FRAMESEL0_VSYNC; 253 val &= ~VIDINTCON0_FRAMESEL1_MASK; 254 val |= VIDINTCON0_FRAMESEL1_NONE; 255 } 256 257 writel(val, ctx->regs + VIDINTCON0); 258 } 259 260 return 0; 261 } 262 263 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 264 { 265 struct fimd_context *ctx = crtc->ctx; 266 u32 val; 267 268 if (ctx->suspended) 269 return; 270 271 if (test_and_clear_bit(0, &ctx->irq_flags)) { 272 val = readl(ctx->regs + VIDINTCON0); 273 274 val &= ~VIDINTCON0_INT_ENABLE; 275 276 if (ctx->i80_if) { 277 val &= ~VIDINTCON0_INT_I80IFDONE; 278 val &= ~VIDINTCON0_INT_SYSMAINCON; 279 val &= ~VIDINTCON0_INT_SYSSUBCON; 280 } else 281 val &= ~VIDINTCON0_INT_FRAME; 282 283 writel(val, ctx->regs + VIDINTCON0); 284 } 285 } 286 287 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 288 { 289 struct fimd_context *ctx = crtc->ctx; 290 291 if (ctx->suspended) 292 return; 293 294 atomic_set(&ctx->wait_vsync_event, 1); 295 296 /* 297 * wait for FIMD to signal VSYNC interrupt or return after 298 * timeout which is set to 50ms (refresh rate of 20). 299 */ 300 if (!wait_event_timeout(ctx->wait_vsync_queue, 301 !atomic_read(&ctx->wait_vsync_event), 302 HZ/20)) 303 DRM_DEBUG_KMS("vblank wait timed out.\n"); 304 } 305 306 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 307 bool enable) 308 { 309 u32 val = readl(ctx->regs + WINCON(win)); 310 311 if (enable) 312 val |= WINCONx_ENWIN; 313 else 314 val &= ~WINCONx_ENWIN; 315 316 writel(val, ctx->regs + WINCON(win)); 317 } 318 319 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 320 unsigned int win, 321 bool enable) 322 { 323 u32 val = readl(ctx->regs + SHADOWCON); 324 325 if (enable) 326 val |= SHADOWCON_CHx_ENABLE(win); 327 else 328 val &= ~SHADOWCON_CHx_ENABLE(win); 329 330 writel(val, ctx->regs + SHADOWCON); 331 } 332 333 static void fimd_clear_channels(struct exynos_drm_crtc *crtc) 334 { 335 struct fimd_context *ctx = crtc->ctx; 336 unsigned int win, ch_enabled = 0; 337 338 DRM_DEBUG_KMS("%s\n", __FILE__); 339 340 /* Hardware is in unknown state, so ensure it gets enabled properly */ 341 pm_runtime_get_sync(ctx->dev); 342 343 clk_prepare_enable(ctx->bus_clk); 344 clk_prepare_enable(ctx->lcd_clk); 345 346 /* Check if any channel is enabled. */ 347 for (win = 0; win < WINDOWS_NR; win++) { 348 u32 val = readl(ctx->regs + WINCON(win)); 349 350 if (val & WINCONx_ENWIN) { 351 fimd_enable_video_output(ctx, win, false); 352 353 if (ctx->driver_data->has_shadowcon) 354 fimd_enable_shadow_channel_path(ctx, win, 355 false); 356 357 ch_enabled = 1; 358 } 359 } 360 361 /* Wait for vsync, as disable channel takes effect at next vsync */ 362 if (ch_enabled) { 363 int pipe = ctx->pipe; 364 365 /* ensure that vblank interrupt won't be reported to core */ 366 ctx->suspended = false; 367 ctx->pipe = -1; 368 369 fimd_enable_vblank(ctx->crtc); 370 fimd_wait_for_vblank(ctx->crtc); 371 fimd_disable_vblank(ctx->crtc); 372 373 ctx->suspended = true; 374 ctx->pipe = pipe; 375 } 376 377 clk_disable_unprepare(ctx->lcd_clk); 378 clk_disable_unprepare(ctx->bus_clk); 379 380 pm_runtime_put(ctx->dev); 381 } 382 383 static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 384 const struct drm_display_mode *mode) 385 { 386 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 387 u32 clkdiv; 388 389 if (ctx->i80_if) { 390 /* 391 * The frame done interrupt should be occurred prior to the 392 * next TE signal. 393 */ 394 ideal_clk *= 2; 395 } 396 397 /* Find the clock divider value that gets us closest to ideal_clk */ 398 clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk); 399 400 return (clkdiv < 0x100) ? clkdiv : 0xff; 401 } 402 403 static void fimd_commit(struct exynos_drm_crtc *crtc) 404 { 405 struct fimd_context *ctx = crtc->ctx; 406 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 407 struct fimd_driver_data *driver_data = ctx->driver_data; 408 void *timing_base = ctx->regs + driver_data->timing_base; 409 u32 val, clkdiv; 410 411 if (ctx->suspended) 412 return; 413 414 /* nothing to do if we haven't set the mode yet */ 415 if (mode->htotal == 0 || mode->vtotal == 0) 416 return; 417 418 if (ctx->i80_if) { 419 val = ctx->i80ifcon | I80IFEN_ENABLE; 420 writel(val, timing_base + I80IFCONFAx(0)); 421 422 /* disable auto frame rate */ 423 writel(0, timing_base + I80IFCONFBx(0)); 424 425 /* set video type selection to I80 interface */ 426 if (driver_data->has_vtsel && ctx->sysreg && 427 regmap_update_bits(ctx->sysreg, 428 driver_data->lcdblk_offset, 429 0x3 << driver_data->lcdblk_vt_shift, 430 0x1 << driver_data->lcdblk_vt_shift)) { 431 DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 432 return; 433 } 434 } else { 435 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 436 u32 vidcon1; 437 438 /* setup polarity values */ 439 vidcon1 = ctx->vidcon1; 440 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 441 vidcon1 |= VIDCON1_INV_VSYNC; 442 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 443 vidcon1 |= VIDCON1_INV_HSYNC; 444 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 445 446 /* setup vertical timing values. */ 447 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 448 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 449 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 450 451 val = VIDTCON0_VBPD(vbpd - 1) | 452 VIDTCON0_VFPD(vfpd - 1) | 453 VIDTCON0_VSPW(vsync_len - 1); 454 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 455 456 /* setup horizontal timing values. */ 457 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 458 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 459 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 460 461 val = VIDTCON1_HBPD(hbpd - 1) | 462 VIDTCON1_HFPD(hfpd - 1) | 463 VIDTCON1_HSPW(hsync_len - 1); 464 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 465 } 466 467 if (driver_data->has_vidoutcon) 468 writel(ctx->vidout_con, timing_base + VIDOUT_CON); 469 470 /* set bypass selection */ 471 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 472 driver_data->lcdblk_offset, 473 0x1 << driver_data->lcdblk_bypass_shift, 474 0x1 << driver_data->lcdblk_bypass_shift)) { 475 DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 476 return; 477 } 478 479 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass 480 * bit should be cleared. 481 */ 482 if (driver_data->has_mic_bypass && ctx->sysreg && 483 regmap_update_bits(ctx->sysreg, 484 driver_data->lcdblk_offset, 485 0x1 << driver_data->lcdblk_mic_bypass_shift, 486 0x1 << driver_data->lcdblk_mic_bypass_shift)) { 487 DRM_ERROR("Failed to update sysreg for bypass mic.\n"); 488 return; 489 } 490 491 /* setup horizontal and vertical display size. */ 492 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 493 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 494 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 495 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 496 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 497 498 /* 499 * fields of register with prefix '_F' would be updated 500 * at vsync(same as dma start) 501 */ 502 val = ctx->vidcon0; 503 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 504 505 if (ctx->driver_data->has_clksel) 506 val |= VIDCON0_CLKSEL_LCD; 507 508 clkdiv = fimd_calc_clkdiv(ctx, mode); 509 if (clkdiv > 1) 510 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 511 512 writel(val, ctx->regs + VIDCON0); 513 } 514 515 516 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, 517 uint32_t pixel_format, int width) 518 { 519 unsigned long val; 520 521 val = WINCONx_ENWIN; 522 523 /* 524 * In case of s3c64xx, window 0 doesn't support alpha channel. 525 * So the request format is ARGB8888 then change it to XRGB8888. 526 */ 527 if (ctx->driver_data->has_limited_fmt && !win) { 528 if (pixel_format == DRM_FORMAT_ARGB8888) 529 pixel_format = DRM_FORMAT_XRGB8888; 530 } 531 532 switch (pixel_format) { 533 case DRM_FORMAT_C8: 534 val |= WINCON0_BPPMODE_8BPP_PALETTE; 535 val |= WINCONx_BURSTLEN_8WORD; 536 val |= WINCONx_BYTSWP; 537 break; 538 case DRM_FORMAT_XRGB1555: 539 val |= WINCON0_BPPMODE_16BPP_1555; 540 val |= WINCONx_HAWSWP; 541 val |= WINCONx_BURSTLEN_16WORD; 542 break; 543 case DRM_FORMAT_RGB565: 544 val |= WINCON0_BPPMODE_16BPP_565; 545 val |= WINCONx_HAWSWP; 546 val |= WINCONx_BURSTLEN_16WORD; 547 break; 548 case DRM_FORMAT_XRGB8888: 549 val |= WINCON0_BPPMODE_24BPP_888; 550 val |= WINCONx_WSWP; 551 val |= WINCONx_BURSTLEN_16WORD; 552 break; 553 case DRM_FORMAT_ARGB8888: 554 val |= WINCON1_BPPMODE_25BPP_A1888 555 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 556 val |= WINCONx_WSWP; 557 val |= WINCONx_BURSTLEN_16WORD; 558 break; 559 default: 560 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 561 562 val |= WINCON0_BPPMODE_24BPP_888; 563 val |= WINCONx_WSWP; 564 val |= WINCONx_BURSTLEN_16WORD; 565 break; 566 } 567 568 /* 569 * Setting dma-burst to 16Word causes permanent tearing for very small 570 * buffers, e.g. cursor buffer. Burst Mode switching which based on 571 * plane size is not recommended as plane size varies alot towards the 572 * end of the screen and rapid movement causes unstable DMA, but it is 573 * still better to change dma-burst than displaying garbage. 574 */ 575 576 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 577 val &= ~WINCONx_BURSTLEN_MASK; 578 val |= WINCONx_BURSTLEN_4WORD; 579 } 580 581 writel(val, ctx->regs + WINCON(win)); 582 583 /* hardware window 0 doesn't support alpha channel. */ 584 if (win != 0) { 585 /* OSD alpha */ 586 val = VIDISD14C_ALPHA0_R(0xf) | 587 VIDISD14C_ALPHA0_G(0xf) | 588 VIDISD14C_ALPHA0_B(0xf) | 589 VIDISD14C_ALPHA1_R(0xf) | 590 VIDISD14C_ALPHA1_G(0xf) | 591 VIDISD14C_ALPHA1_B(0xf); 592 593 writel(val, ctx->regs + VIDOSD_C(win)); 594 595 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | 596 VIDW_ALPHA_G(0xf); 597 writel(val, ctx->regs + VIDWnALPHA0(win)); 598 writel(val, ctx->regs + VIDWnALPHA1(win)); 599 } 600 } 601 602 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 603 { 604 unsigned int keycon0 = 0, keycon1 = 0; 605 606 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 607 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 608 609 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 610 611 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 612 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 613 } 614 615 /** 616 * shadow_protect_win() - disable updating values from shadow registers at vsync 617 * 618 * @win: window to protect registers for 619 * @protect: 1 to protect (disable updates) 620 */ 621 static void fimd_shadow_protect_win(struct fimd_context *ctx, 622 unsigned int win, bool protect) 623 { 624 u32 reg, bits, val; 625 626 /* 627 * SHADOWCON/PRTCON register is used for enabling timing. 628 * 629 * for example, once only width value of a register is set, 630 * if the dma is started then fimd hardware could malfunction so 631 * with protect window setting, the register fields with prefix '_F' 632 * wouldn't be updated at vsync also but updated once unprotect window 633 * is set. 634 */ 635 636 if (ctx->driver_data->has_shadowcon) { 637 reg = SHADOWCON; 638 bits = SHADOWCON_WINx_PROTECT(win); 639 } else { 640 reg = PRTCON; 641 bits = PRTCON_PROTECT; 642 } 643 644 val = readl(ctx->regs + reg); 645 if (protect) 646 val |= bits; 647 else 648 val &= ~bits; 649 writel(val, ctx->regs + reg); 650 } 651 652 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) 653 { 654 struct fimd_context *ctx = crtc->ctx; 655 int i; 656 657 if (ctx->suspended) 658 return; 659 660 for (i = 0; i < WINDOWS_NR; i++) 661 fimd_shadow_protect_win(ctx, i, true); 662 } 663 664 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) 665 { 666 struct fimd_context *ctx = crtc->ctx; 667 int i; 668 669 if (ctx->suspended) 670 return; 671 672 for (i = 0; i < WINDOWS_NR; i++) 673 fimd_shadow_protect_win(ctx, i, false); 674 } 675 676 static void fimd_update_plane(struct exynos_drm_crtc *crtc, 677 struct exynos_drm_plane *plane) 678 { 679 struct exynos_drm_plane_state *state = 680 to_exynos_plane_state(plane->base.state); 681 struct fimd_context *ctx = crtc->ctx; 682 struct drm_framebuffer *fb = state->base.fb; 683 dma_addr_t dma_addr; 684 unsigned long val, size, offset; 685 unsigned int last_x, last_y, buf_offsize, line_size; 686 unsigned int win = plane->index; 687 unsigned int bpp = fb->bits_per_pixel >> 3; 688 unsigned int pitch = fb->pitches[0]; 689 690 if (ctx->suspended) 691 return; 692 693 offset = state->src.x * bpp; 694 offset += state->src.y * pitch; 695 696 /* buffer start address */ 697 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; 698 val = (unsigned long)dma_addr; 699 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 700 701 /* buffer end address */ 702 size = pitch * state->crtc.h; 703 val = (unsigned long)(dma_addr + size); 704 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 705 706 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 707 (unsigned long)dma_addr, val, size); 708 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 709 state->crtc.w, state->crtc.h); 710 711 /* buffer size */ 712 buf_offsize = pitch - (state->crtc.w * bpp); 713 line_size = state->crtc.w * bpp; 714 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 715 VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 716 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 717 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 718 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 719 720 /* OSD position */ 721 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 722 VIDOSDxA_TOPLEFT_Y(state->crtc.y) | 723 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | 724 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); 725 writel(val, ctx->regs + VIDOSD_A(win)); 726 727 last_x = state->crtc.x + state->crtc.w; 728 if (last_x) 729 last_x--; 730 last_y = state->crtc.y + state->crtc.h; 731 if (last_y) 732 last_y--; 733 734 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 735 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 736 737 writel(val, ctx->regs + VIDOSD_B(win)); 738 739 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 740 state->crtc.x, state->crtc.y, last_x, last_y); 741 742 /* OSD size */ 743 if (win != 3 && win != 4) { 744 u32 offset = VIDOSD_D(win); 745 if (win == 0) 746 offset = VIDOSD_C(win); 747 val = state->crtc.w * state->crtc.h; 748 writel(val, ctx->regs + offset); 749 750 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 751 } 752 753 fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w); 754 755 /* hardware window 0 doesn't support color key. */ 756 if (win != 0) 757 fimd_win_set_colkey(ctx, win); 758 759 fimd_enable_video_output(ctx, win, true); 760 761 if (ctx->driver_data->has_shadowcon) 762 fimd_enable_shadow_channel_path(ctx, win, true); 763 764 if (ctx->i80_if) 765 atomic_set(&ctx->win_updated, 1); 766 } 767 768 static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 769 struct exynos_drm_plane *plane) 770 { 771 struct fimd_context *ctx = crtc->ctx; 772 unsigned int win = plane->index; 773 774 if (ctx->suspended) 775 return; 776 777 fimd_enable_video_output(ctx, win, false); 778 779 if (ctx->driver_data->has_shadowcon) 780 fimd_enable_shadow_channel_path(ctx, win, false); 781 } 782 783 static void fimd_enable(struct exynos_drm_crtc *crtc) 784 { 785 struct fimd_context *ctx = crtc->ctx; 786 787 if (!ctx->suspended) 788 return; 789 790 ctx->suspended = false; 791 792 pm_runtime_get_sync(ctx->dev); 793 794 /* if vblank was enabled status, enable it again. */ 795 if (test_and_clear_bit(0, &ctx->irq_flags)) 796 fimd_enable_vblank(ctx->crtc); 797 798 fimd_commit(ctx->crtc); 799 } 800 801 static void fimd_disable(struct exynos_drm_crtc *crtc) 802 { 803 struct fimd_context *ctx = crtc->ctx; 804 int i; 805 806 if (ctx->suspended) 807 return; 808 809 /* 810 * We need to make sure that all windows are disabled before we 811 * suspend that connector. Otherwise we might try to scan from 812 * a destroyed buffer later. 813 */ 814 for (i = 0; i < WINDOWS_NR; i++) 815 fimd_disable_plane(crtc, &ctx->planes[i]); 816 817 fimd_enable_vblank(crtc); 818 fimd_wait_for_vblank(crtc); 819 fimd_disable_vblank(crtc); 820 821 writel(0, ctx->regs + VIDCON0); 822 823 pm_runtime_put_sync(ctx->dev); 824 ctx->suspended = true; 825 } 826 827 static void fimd_trigger(struct device *dev) 828 { 829 struct fimd_context *ctx = dev_get_drvdata(dev); 830 struct fimd_driver_data *driver_data = ctx->driver_data; 831 void *timing_base = ctx->regs + driver_data->timing_base; 832 u32 reg; 833 834 /* 835 * Skips triggering if in triggering state, because multiple triggering 836 * requests can cause panel reset. 837 */ 838 if (atomic_read(&ctx->triggering)) 839 return; 840 841 /* Enters triggering mode */ 842 atomic_set(&ctx->triggering, 1); 843 844 reg = readl(timing_base + TRIGCON); 845 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 846 writel(reg, timing_base + TRIGCON); 847 848 /* 849 * Exits triggering mode if vblank is not enabled yet, because when the 850 * VIDINTCON0 register is not set, it can not exit from triggering mode. 851 */ 852 if (!test_bit(0, &ctx->irq_flags)) 853 atomic_set(&ctx->triggering, 0); 854 } 855 856 static void fimd_te_handler(struct exynos_drm_crtc *crtc) 857 { 858 struct fimd_context *ctx = crtc->ctx; 859 860 /* Checks the crtc is detached already from encoder */ 861 if (ctx->pipe < 0 || !ctx->drm_dev) 862 return; 863 864 /* 865 * If there is a page flip request, triggers and handles the page flip 866 * event so that current fb can be updated into panel GRAM. 867 */ 868 if (atomic_add_unless(&ctx->win_updated, -1, 0)) 869 fimd_trigger(ctx->dev); 870 871 /* Wakes up vsync event queue */ 872 if (atomic_read(&ctx->wait_vsync_event)) { 873 atomic_set(&ctx->wait_vsync_event, 0); 874 wake_up(&ctx->wait_vsync_queue); 875 } 876 877 if (test_bit(0, &ctx->irq_flags)) 878 drm_crtc_handle_vblank(&ctx->crtc->base); 879 } 880 881 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) 882 { 883 struct fimd_context *ctx = crtc->ctx; 884 u32 val; 885 886 /* 887 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE 888 * clock. On these SoCs the bootloader may enable it but any 889 * power domain off/on will reset it to disable state. 890 */ 891 if (ctx->driver_data != &exynos5_fimd_driver_data || 892 ctx->driver_data != &exynos5420_fimd_driver_data) 893 return; 894 895 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 896 writel(val, ctx->regs + DP_MIE_CLKCON); 897 } 898 899 static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 900 .enable = fimd_enable, 901 .disable = fimd_disable, 902 .commit = fimd_commit, 903 .enable_vblank = fimd_enable_vblank, 904 .disable_vblank = fimd_disable_vblank, 905 .wait_for_vblank = fimd_wait_for_vblank, 906 .atomic_begin = fimd_atomic_begin, 907 .update_plane = fimd_update_plane, 908 .disable_plane = fimd_disable_plane, 909 .atomic_flush = fimd_atomic_flush, 910 .te_handler = fimd_te_handler, 911 .clock_enable = fimd_dp_clock_enable, 912 }; 913 914 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 915 { 916 struct fimd_context *ctx = (struct fimd_context *)dev_id; 917 u32 val, clear_bit, start, start_s; 918 int win; 919 920 val = readl(ctx->regs + VIDINTCON1); 921 922 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 923 if (val & clear_bit) 924 writel(clear_bit, ctx->regs + VIDINTCON1); 925 926 /* check the crtc is detached already from encoder */ 927 if (ctx->pipe < 0 || !ctx->drm_dev) 928 goto out; 929 930 if (!ctx->i80_if) 931 drm_crtc_handle_vblank(&ctx->crtc->base); 932 933 for (win = 0 ; win < WINDOWS_NR ; win++) { 934 struct exynos_drm_plane *plane = &ctx->planes[win]; 935 936 if (!plane->pending_fb) 937 continue; 938 939 start = readl(ctx->regs + VIDWx_BUF_START(win, 0)); 940 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0)); 941 if (start == start_s) 942 exynos_drm_crtc_finish_update(ctx->crtc, plane); 943 } 944 945 if (ctx->i80_if) { 946 /* Exits triggering mode */ 947 atomic_set(&ctx->triggering, 0); 948 } else { 949 /* set wait vsync event to zero and wake up queue. */ 950 if (atomic_read(&ctx->wait_vsync_event)) { 951 atomic_set(&ctx->wait_vsync_event, 0); 952 wake_up(&ctx->wait_vsync_queue); 953 } 954 } 955 956 out: 957 return IRQ_HANDLED; 958 } 959 960 static int fimd_bind(struct device *dev, struct device *master, void *data) 961 { 962 struct fimd_context *ctx = dev_get_drvdata(dev); 963 struct drm_device *drm_dev = data; 964 struct exynos_drm_private *priv = drm_dev->dev_private; 965 struct exynos_drm_plane *exynos_plane; 966 unsigned int i; 967 int ret; 968 969 ctx->drm_dev = drm_dev; 970 ctx->pipe = priv->pipe++; 971 972 for (i = 0; i < WINDOWS_NR; i++) { 973 ctx->configs[i].pixel_formats = fimd_formats; 974 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); 975 ctx->configs[i].zpos = i; 976 ctx->configs[i].type = fimd_win_types[i]; 977 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 978 1 << ctx->pipe, &ctx->configs[i]); 979 if (ret) 980 return ret; 981 } 982 983 exynos_plane = &ctx->planes[DEFAULT_WIN]; 984 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 985 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 986 &fimd_crtc_ops, ctx); 987 if (IS_ERR(ctx->crtc)) 988 return PTR_ERR(ctx->crtc); 989 990 if (ctx->encoder) 991 exynos_dpi_bind(drm_dev, ctx->encoder); 992 993 if (is_drm_iommu_supported(drm_dev)) 994 fimd_clear_channels(ctx->crtc); 995 996 ret = drm_iommu_attach_device(drm_dev, dev); 997 if (ret) 998 priv->pipe--; 999 1000 return ret; 1001 } 1002 1003 static void fimd_unbind(struct device *dev, struct device *master, 1004 void *data) 1005 { 1006 struct fimd_context *ctx = dev_get_drvdata(dev); 1007 1008 fimd_disable(ctx->crtc); 1009 1010 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 1011 1012 if (ctx->encoder) 1013 exynos_dpi_remove(ctx->encoder); 1014 } 1015 1016 static const struct component_ops fimd_component_ops = { 1017 .bind = fimd_bind, 1018 .unbind = fimd_unbind, 1019 }; 1020 1021 static int fimd_probe(struct platform_device *pdev) 1022 { 1023 struct device *dev = &pdev->dev; 1024 struct fimd_context *ctx; 1025 struct device_node *i80_if_timings; 1026 struct resource *res; 1027 int ret; 1028 1029 if (!dev->of_node) 1030 return -ENODEV; 1031 1032 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1033 if (!ctx) 1034 return -ENOMEM; 1035 1036 ctx->dev = dev; 1037 ctx->suspended = true; 1038 ctx->driver_data = drm_fimd_get_driver_data(pdev); 1039 1040 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 1041 ctx->vidcon1 |= VIDCON1_INV_VDEN; 1042 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 1043 ctx->vidcon1 |= VIDCON1_INV_VCLK; 1044 1045 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 1046 if (i80_if_timings) { 1047 u32 val; 1048 1049 ctx->i80_if = true; 1050 1051 if (ctx->driver_data->has_vidoutcon) 1052 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 1053 else 1054 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 1055 /* 1056 * The user manual describes that this "DSI_EN" bit is required 1057 * to enable I80 24-bit data interface. 1058 */ 1059 ctx->vidcon0 |= VIDCON0_DSI_EN; 1060 1061 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 1062 val = 0; 1063 ctx->i80ifcon = LCD_CS_SETUP(val); 1064 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 1065 val = 0; 1066 ctx->i80ifcon |= LCD_WR_SETUP(val); 1067 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 1068 val = 1; 1069 ctx->i80ifcon |= LCD_WR_ACTIVE(val); 1070 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 1071 val = 0; 1072 ctx->i80ifcon |= LCD_WR_HOLD(val); 1073 } 1074 of_node_put(i80_if_timings); 1075 1076 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1077 "samsung,sysreg"); 1078 if (IS_ERR(ctx->sysreg)) { 1079 dev_warn(dev, "failed to get system register.\n"); 1080 ctx->sysreg = NULL; 1081 } 1082 1083 ctx->bus_clk = devm_clk_get(dev, "fimd"); 1084 if (IS_ERR(ctx->bus_clk)) { 1085 dev_err(dev, "failed to get bus clock\n"); 1086 return PTR_ERR(ctx->bus_clk); 1087 } 1088 1089 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1090 if (IS_ERR(ctx->lcd_clk)) { 1091 dev_err(dev, "failed to get lcd clock\n"); 1092 return PTR_ERR(ctx->lcd_clk); 1093 } 1094 1095 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1096 1097 ctx->regs = devm_ioremap_resource(dev, res); 1098 if (IS_ERR(ctx->regs)) 1099 return PTR_ERR(ctx->regs); 1100 1101 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1102 ctx->i80_if ? "lcd_sys" : "vsync"); 1103 if (!res) { 1104 dev_err(dev, "irq request failed.\n"); 1105 return -ENXIO; 1106 } 1107 1108 ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1109 0, "drm_fimd", ctx); 1110 if (ret) { 1111 dev_err(dev, "irq request failed.\n"); 1112 return ret; 1113 } 1114 1115 init_waitqueue_head(&ctx->wait_vsync_queue); 1116 atomic_set(&ctx->wait_vsync_event, 0); 1117 1118 platform_set_drvdata(pdev, ctx); 1119 1120 ctx->encoder = exynos_dpi_probe(dev); 1121 if (IS_ERR(ctx->encoder)) 1122 return PTR_ERR(ctx->encoder); 1123 1124 pm_runtime_enable(dev); 1125 1126 ret = component_add(dev, &fimd_component_ops); 1127 if (ret) 1128 goto err_disable_pm_runtime; 1129 1130 return ret; 1131 1132 err_disable_pm_runtime: 1133 pm_runtime_disable(dev); 1134 1135 return ret; 1136 } 1137 1138 static int fimd_remove(struct platform_device *pdev) 1139 { 1140 pm_runtime_disable(&pdev->dev); 1141 1142 component_del(&pdev->dev, &fimd_component_ops); 1143 1144 return 0; 1145 } 1146 1147 #ifdef CONFIG_PM 1148 static int exynos_fimd_suspend(struct device *dev) 1149 { 1150 struct fimd_context *ctx = dev_get_drvdata(dev); 1151 1152 clk_disable_unprepare(ctx->lcd_clk); 1153 clk_disable_unprepare(ctx->bus_clk); 1154 1155 return 0; 1156 } 1157 1158 static int exynos_fimd_resume(struct device *dev) 1159 { 1160 struct fimd_context *ctx = dev_get_drvdata(dev); 1161 int ret; 1162 1163 ret = clk_prepare_enable(ctx->bus_clk); 1164 if (ret < 0) { 1165 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 1166 return ret; 1167 } 1168 1169 ret = clk_prepare_enable(ctx->lcd_clk); 1170 if (ret < 0) { 1171 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 1172 return ret; 1173 } 1174 1175 return 0; 1176 } 1177 #endif 1178 1179 static const struct dev_pm_ops exynos_fimd_pm_ops = { 1180 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL) 1181 }; 1182 1183 struct platform_driver fimd_driver = { 1184 .probe = fimd_probe, 1185 .remove = fimd_remove, 1186 .driver = { 1187 .name = "exynos4-fb", 1188 .owner = THIS_MODULE, 1189 .pm = &exynos_fimd_pm_ops, 1190 .of_match_table = fimd_driver_dt_match, 1191 }, 1192 }; 1193