1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/component.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/samsung_fimd.h> 29 #include <drm/exynos_drm.h> 30 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fbdev.h" 33 #include "exynos_drm_crtc.h" 34 #include "exynos_drm_iommu.h" 35 36 /* 37 * FIMD stands for Fully Interactive Mobile Display and 38 * as a display controller, it transfers contents drawn on memory 39 * to a LCD Panel through Display Interfaces such as RGB or 40 * CPU Interface. 41 */ 42 43 #define FIMD_DEFAULT_FRAMERATE 60 44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 45 46 /* position control register for hardware window 0, 2 ~ 4.*/ 47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 49 /* 50 * size control register for hardware windows 0 and alpha control register 51 * for hardware windows 1 ~ 4 52 */ 53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 54 /* size control register for hardware windows 1 ~ 2. */ 55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 56 57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 60 61 /* color key control register for hardware window 1 ~ 4. */ 62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 63 /* color key value register for hardware window 1 ~ 4. */ 64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 65 66 /* I80 / RGB trigger control register */ 67 #define TRIGCON 0x1A4 68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 70 71 /* display mode change control register except exynos4 */ 72 #define VIDOUT_CON 0x000 73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 74 75 /* I80 interface control for main LDI register */ 76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 78 #define LCD_CS_SETUP(x) ((x) << 16) 79 #define LCD_WR_SETUP(x) ((x) << 12) 80 #define LCD_WR_ACTIVE(x) ((x) << 8) 81 #define LCD_WR_HOLD(x) ((x) << 4) 82 #define I80IFEN_ENABLE (1 << 0) 83 84 /* FIMD has totally five hardware windows. */ 85 #define WINDOWS_NR 5 86 87 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev)) 88 89 struct fimd_driver_data { 90 unsigned int timing_base; 91 unsigned int lcdblk_offset; 92 unsigned int lcdblk_vt_shift; 93 unsigned int lcdblk_bypass_shift; 94 95 unsigned int has_shadowcon:1; 96 unsigned int has_clksel:1; 97 unsigned int has_limited_fmt:1; 98 unsigned int has_vidoutcon:1; 99 unsigned int has_vtsel:1; 100 }; 101 102 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 103 .timing_base = 0x0, 104 .has_clksel = 1, 105 .has_limited_fmt = 1, 106 }; 107 108 static struct fimd_driver_data exynos3_fimd_driver_data = { 109 .timing_base = 0x20000, 110 .lcdblk_offset = 0x210, 111 .lcdblk_bypass_shift = 1, 112 .has_shadowcon = 1, 113 .has_vidoutcon = 1, 114 }; 115 116 static struct fimd_driver_data exynos4_fimd_driver_data = { 117 .timing_base = 0x0, 118 .lcdblk_offset = 0x210, 119 .lcdblk_vt_shift = 10, 120 .lcdblk_bypass_shift = 1, 121 .has_shadowcon = 1, 122 .has_vtsel = 1, 123 }; 124 125 static struct fimd_driver_data exynos4415_fimd_driver_data = { 126 .timing_base = 0x20000, 127 .lcdblk_offset = 0x210, 128 .lcdblk_vt_shift = 10, 129 .lcdblk_bypass_shift = 1, 130 .has_shadowcon = 1, 131 .has_vidoutcon = 1, 132 .has_vtsel = 1, 133 }; 134 135 static struct fimd_driver_data exynos5_fimd_driver_data = { 136 .timing_base = 0x20000, 137 .lcdblk_offset = 0x214, 138 .lcdblk_vt_shift = 24, 139 .lcdblk_bypass_shift = 15, 140 .has_shadowcon = 1, 141 .has_vidoutcon = 1, 142 .has_vtsel = 1, 143 }; 144 145 struct fimd_win_data { 146 unsigned int offset_x; 147 unsigned int offset_y; 148 unsigned int ovl_width; 149 unsigned int ovl_height; 150 unsigned int fb_width; 151 unsigned int fb_height; 152 unsigned int bpp; 153 unsigned int pixel_format; 154 dma_addr_t dma_addr; 155 unsigned int buf_offsize; 156 unsigned int line_size; /* bytes */ 157 bool enabled; 158 bool resume; 159 }; 160 161 struct fimd_context { 162 struct device *dev; 163 struct drm_device *drm_dev; 164 struct clk *bus_clk; 165 struct clk *lcd_clk; 166 void __iomem *regs; 167 struct regmap *sysreg; 168 struct drm_display_mode mode; 169 struct fimd_win_data win_data[WINDOWS_NR]; 170 unsigned int default_win; 171 unsigned long irq_flags; 172 u32 vidcon0; 173 u32 vidcon1; 174 u32 vidout_con; 175 u32 i80ifcon; 176 bool i80_if; 177 bool suspended; 178 int pipe; 179 wait_queue_head_t wait_vsync_queue; 180 atomic_t wait_vsync_event; 181 atomic_t win_updated; 182 atomic_t triggering; 183 184 struct exynos_drm_panel_info panel; 185 struct fimd_driver_data *driver_data; 186 struct exynos_drm_display *display; 187 }; 188 189 static const struct of_device_id fimd_driver_dt_match[] = { 190 { .compatible = "samsung,s3c6400-fimd", 191 .data = &s3c64xx_fimd_driver_data }, 192 { .compatible = "samsung,exynos3250-fimd", 193 .data = &exynos3_fimd_driver_data }, 194 { .compatible = "samsung,exynos4210-fimd", 195 .data = &exynos4_fimd_driver_data }, 196 { .compatible = "samsung,exynos4415-fimd", 197 .data = &exynos4415_fimd_driver_data }, 198 { .compatible = "samsung,exynos5250-fimd", 199 .data = &exynos5_fimd_driver_data }, 200 {}, 201 }; 202 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 203 204 static inline struct fimd_driver_data *drm_fimd_get_driver_data( 205 struct platform_device *pdev) 206 { 207 const struct of_device_id *of_id = 208 of_match_device(fimd_driver_dt_match, &pdev->dev); 209 210 return (struct fimd_driver_data *)of_id->data; 211 } 212 213 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr) 214 { 215 struct fimd_context *ctx = mgr->ctx; 216 217 if (ctx->suspended) 218 return; 219 220 atomic_set(&ctx->wait_vsync_event, 1); 221 222 /* 223 * wait for FIMD to signal VSYNC interrupt or return after 224 * timeout which is set to 50ms (refresh rate of 20). 225 */ 226 if (!wait_event_timeout(ctx->wait_vsync_queue, 227 !atomic_read(&ctx->wait_vsync_event), 228 HZ/20)) 229 DRM_DEBUG_KMS("vblank wait timed out.\n"); 230 } 231 232 static void fimd_clear_channel(struct exynos_drm_manager *mgr) 233 { 234 struct fimd_context *ctx = mgr->ctx; 235 int win, ch_enabled = 0; 236 237 DRM_DEBUG_KMS("%s\n", __FILE__); 238 239 /* Check if any channel is enabled. */ 240 for (win = 0; win < WINDOWS_NR; win++) { 241 u32 val = readl(ctx->regs + WINCON(win)); 242 243 if (val & WINCONx_ENWIN) { 244 /* wincon */ 245 val &= ~WINCONx_ENWIN; 246 writel(val, ctx->regs + WINCON(win)); 247 248 /* unprotect windows */ 249 if (ctx->driver_data->has_shadowcon) { 250 val = readl(ctx->regs + SHADOWCON); 251 val &= ~SHADOWCON_CHx_ENABLE(win); 252 writel(val, ctx->regs + SHADOWCON); 253 } 254 ch_enabled = 1; 255 } 256 } 257 258 /* Wait for vsync, as disable channel takes effect at next vsync */ 259 if (ch_enabled) { 260 unsigned int state = ctx->suspended; 261 262 ctx->suspended = 0; 263 fimd_wait_for_vblank(mgr); 264 ctx->suspended = state; 265 } 266 } 267 268 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr, 269 struct drm_device *drm_dev) 270 { 271 struct fimd_context *ctx = mgr->ctx; 272 struct exynos_drm_private *priv; 273 priv = drm_dev->dev_private; 274 275 mgr->drm_dev = ctx->drm_dev = drm_dev; 276 mgr->pipe = ctx->pipe = priv->pipe++; 277 278 /* attach this sub driver to iommu mapping if supported. */ 279 if (is_drm_iommu_supported(ctx->drm_dev)) { 280 /* 281 * If any channel is already active, iommu will throw 282 * a PAGE FAULT when enabled. So clear any channel if enabled. 283 */ 284 fimd_clear_channel(mgr); 285 drm_iommu_attach_device(ctx->drm_dev, ctx->dev); 286 } 287 288 return 0; 289 } 290 291 static void fimd_mgr_remove(struct exynos_drm_manager *mgr) 292 { 293 struct fimd_context *ctx = mgr->ctx; 294 295 /* detach this sub driver from iommu mapping if supported. */ 296 if (is_drm_iommu_supported(ctx->drm_dev)) 297 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 298 } 299 300 static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 301 const struct drm_display_mode *mode) 302 { 303 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 304 u32 clkdiv; 305 306 if (ctx->i80_if) { 307 /* 308 * The frame done interrupt should be occurred prior to the 309 * next TE signal. 310 */ 311 ideal_clk *= 2; 312 } 313 314 /* Find the clock divider value that gets us closest to ideal_clk */ 315 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 316 317 return (clkdiv < 0x100) ? clkdiv : 0xff; 318 } 319 320 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr, 321 const struct drm_display_mode *mode, 322 struct drm_display_mode *adjusted_mode) 323 { 324 if (adjusted_mode->vrefresh == 0) 325 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 326 327 return true; 328 } 329 330 static void fimd_mode_set(struct exynos_drm_manager *mgr, 331 const struct drm_display_mode *in_mode) 332 { 333 struct fimd_context *ctx = mgr->ctx; 334 335 drm_mode_copy(&ctx->mode, in_mode); 336 } 337 338 static void fimd_commit(struct exynos_drm_manager *mgr) 339 { 340 struct fimd_context *ctx = mgr->ctx; 341 struct drm_display_mode *mode = &ctx->mode; 342 struct fimd_driver_data *driver_data = ctx->driver_data; 343 void *timing_base = ctx->regs + driver_data->timing_base; 344 u32 val, clkdiv; 345 346 if (ctx->suspended) 347 return; 348 349 /* nothing to do if we haven't set the mode yet */ 350 if (mode->htotal == 0 || mode->vtotal == 0) 351 return; 352 353 if (ctx->i80_if) { 354 val = ctx->i80ifcon | I80IFEN_ENABLE; 355 writel(val, timing_base + I80IFCONFAx(0)); 356 357 /* disable auto frame rate */ 358 writel(0, timing_base + I80IFCONFBx(0)); 359 360 /* set video type selection to I80 interface */ 361 if (driver_data->has_vtsel && ctx->sysreg && 362 regmap_update_bits(ctx->sysreg, 363 driver_data->lcdblk_offset, 364 0x3 << driver_data->lcdblk_vt_shift, 365 0x1 << driver_data->lcdblk_vt_shift)) { 366 DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 367 return; 368 } 369 } else { 370 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 371 u32 vidcon1; 372 373 /* setup polarity values */ 374 vidcon1 = ctx->vidcon1; 375 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 376 vidcon1 |= VIDCON1_INV_VSYNC; 377 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 378 vidcon1 |= VIDCON1_INV_HSYNC; 379 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 380 381 /* setup vertical timing values. */ 382 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 383 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 384 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 385 386 val = VIDTCON0_VBPD(vbpd - 1) | 387 VIDTCON0_VFPD(vfpd - 1) | 388 VIDTCON0_VSPW(vsync_len - 1); 389 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 390 391 /* setup horizontal timing values. */ 392 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 393 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 394 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 395 396 val = VIDTCON1_HBPD(hbpd - 1) | 397 VIDTCON1_HFPD(hfpd - 1) | 398 VIDTCON1_HSPW(hsync_len - 1); 399 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 400 } 401 402 if (driver_data->has_vidoutcon) 403 writel(ctx->vidout_con, timing_base + VIDOUT_CON); 404 405 /* set bypass selection */ 406 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 407 driver_data->lcdblk_offset, 408 0x1 << driver_data->lcdblk_bypass_shift, 409 0x1 << driver_data->lcdblk_bypass_shift)) { 410 DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 411 return; 412 } 413 414 /* setup horizontal and vertical display size. */ 415 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 416 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 417 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 418 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 419 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 420 421 /* 422 * fields of register with prefix '_F' would be updated 423 * at vsync(same as dma start) 424 */ 425 val = ctx->vidcon0; 426 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 427 428 if (ctx->driver_data->has_clksel) 429 val |= VIDCON0_CLKSEL_LCD; 430 431 clkdiv = fimd_calc_clkdiv(ctx, mode); 432 if (clkdiv > 1) 433 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 434 435 writel(val, ctx->regs + VIDCON0); 436 } 437 438 static int fimd_enable_vblank(struct exynos_drm_manager *mgr) 439 { 440 struct fimd_context *ctx = mgr->ctx; 441 u32 val; 442 443 if (ctx->suspended) 444 return -EPERM; 445 446 if (!test_and_set_bit(0, &ctx->irq_flags)) { 447 val = readl(ctx->regs + VIDINTCON0); 448 449 val |= VIDINTCON0_INT_ENABLE; 450 val |= VIDINTCON0_INT_FRAME; 451 452 val &= ~VIDINTCON0_FRAMESEL0_MASK; 453 val |= VIDINTCON0_FRAMESEL0_VSYNC; 454 val &= ~VIDINTCON0_FRAMESEL1_MASK; 455 val |= VIDINTCON0_FRAMESEL1_NONE; 456 457 writel(val, ctx->regs + VIDINTCON0); 458 } 459 460 return 0; 461 } 462 463 static void fimd_disable_vblank(struct exynos_drm_manager *mgr) 464 { 465 struct fimd_context *ctx = mgr->ctx; 466 u32 val; 467 468 if (ctx->suspended) 469 return; 470 471 if (test_and_clear_bit(0, &ctx->irq_flags)) { 472 val = readl(ctx->regs + VIDINTCON0); 473 474 val &= ~VIDINTCON0_INT_FRAME; 475 val &= ~VIDINTCON0_INT_ENABLE; 476 477 writel(val, ctx->regs + VIDINTCON0); 478 } 479 } 480 481 static void fimd_win_mode_set(struct exynos_drm_manager *mgr, 482 struct exynos_drm_overlay *overlay) 483 { 484 struct fimd_context *ctx = mgr->ctx; 485 struct fimd_win_data *win_data; 486 int win; 487 unsigned long offset; 488 489 if (!overlay) { 490 DRM_ERROR("overlay is NULL\n"); 491 return; 492 } 493 494 win = overlay->zpos; 495 if (win == DEFAULT_ZPOS) 496 win = ctx->default_win; 497 498 if (win < 0 || win >= WINDOWS_NR) 499 return; 500 501 offset = overlay->fb_x * (overlay->bpp >> 3); 502 offset += overlay->fb_y * overlay->pitch; 503 504 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); 505 506 win_data = &ctx->win_data[win]; 507 508 win_data->offset_x = overlay->crtc_x; 509 win_data->offset_y = overlay->crtc_y; 510 win_data->ovl_width = overlay->crtc_width; 511 win_data->ovl_height = overlay->crtc_height; 512 win_data->fb_width = overlay->fb_width; 513 win_data->fb_height = overlay->fb_height; 514 win_data->dma_addr = overlay->dma_addr[0] + offset; 515 win_data->bpp = overlay->bpp; 516 win_data->pixel_format = overlay->pixel_format; 517 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * 518 (overlay->bpp >> 3); 519 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); 520 521 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", 522 win_data->offset_x, win_data->offset_y); 523 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 524 win_data->ovl_width, win_data->ovl_height); 525 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); 526 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", 527 overlay->fb_width, overlay->crtc_width); 528 } 529 530 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) 531 { 532 struct fimd_win_data *win_data = &ctx->win_data[win]; 533 unsigned long val; 534 535 val = WINCONx_ENWIN; 536 537 /* 538 * In case of s3c64xx, window 0 doesn't support alpha channel. 539 * So the request format is ARGB8888 then change it to XRGB8888. 540 */ 541 if (ctx->driver_data->has_limited_fmt && !win) { 542 if (win_data->pixel_format == DRM_FORMAT_ARGB8888) 543 win_data->pixel_format = DRM_FORMAT_XRGB8888; 544 } 545 546 switch (win_data->pixel_format) { 547 case DRM_FORMAT_C8: 548 val |= WINCON0_BPPMODE_8BPP_PALETTE; 549 val |= WINCONx_BURSTLEN_8WORD; 550 val |= WINCONx_BYTSWP; 551 break; 552 case DRM_FORMAT_XRGB1555: 553 val |= WINCON0_BPPMODE_16BPP_1555; 554 val |= WINCONx_HAWSWP; 555 val |= WINCONx_BURSTLEN_16WORD; 556 break; 557 case DRM_FORMAT_RGB565: 558 val |= WINCON0_BPPMODE_16BPP_565; 559 val |= WINCONx_HAWSWP; 560 val |= WINCONx_BURSTLEN_16WORD; 561 break; 562 case DRM_FORMAT_XRGB8888: 563 val |= WINCON0_BPPMODE_24BPP_888; 564 val |= WINCONx_WSWP; 565 val |= WINCONx_BURSTLEN_16WORD; 566 break; 567 case DRM_FORMAT_ARGB8888: 568 val |= WINCON1_BPPMODE_25BPP_A1888 569 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 570 val |= WINCONx_WSWP; 571 val |= WINCONx_BURSTLEN_16WORD; 572 break; 573 default: 574 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 575 576 val |= WINCON0_BPPMODE_24BPP_888; 577 val |= WINCONx_WSWP; 578 val |= WINCONx_BURSTLEN_16WORD; 579 break; 580 } 581 582 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); 583 584 /* 585 * In case of exynos, setting dma-burst to 16Word causes permanent 586 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 587 * switching which is based on overlay size is not recommended as 588 * overlay size varies alot towards the end of the screen and rapid 589 * movement causes unstable DMA which results into iommu crash/tear. 590 */ 591 592 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 593 val &= ~WINCONx_BURSTLEN_MASK; 594 val |= WINCONx_BURSTLEN_4WORD; 595 } 596 597 writel(val, ctx->regs + WINCON(win)); 598 } 599 600 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 601 { 602 unsigned int keycon0 = 0, keycon1 = 0; 603 604 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 605 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 606 607 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 608 609 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 610 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 611 } 612 613 /** 614 * shadow_protect_win() - disable updating values from shadow registers at vsync 615 * 616 * @win: window to protect registers for 617 * @protect: 1 to protect (disable updates) 618 */ 619 static void fimd_shadow_protect_win(struct fimd_context *ctx, 620 int win, bool protect) 621 { 622 u32 reg, bits, val; 623 624 if (ctx->driver_data->has_shadowcon) { 625 reg = SHADOWCON; 626 bits = SHADOWCON_WINx_PROTECT(win); 627 } else { 628 reg = PRTCON; 629 bits = PRTCON_PROTECT; 630 } 631 632 val = readl(ctx->regs + reg); 633 if (protect) 634 val |= bits; 635 else 636 val &= ~bits; 637 writel(val, ctx->regs + reg); 638 } 639 640 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos) 641 { 642 struct fimd_context *ctx = mgr->ctx; 643 struct fimd_win_data *win_data; 644 int win = zpos; 645 unsigned long val, alpha, size; 646 unsigned int last_x; 647 unsigned int last_y; 648 649 if (ctx->suspended) 650 return; 651 652 if (win == DEFAULT_ZPOS) 653 win = ctx->default_win; 654 655 if (win < 0 || win >= WINDOWS_NR) 656 return; 657 658 win_data = &ctx->win_data[win]; 659 660 /* If suspended, enable this on resume */ 661 if (ctx->suspended) { 662 win_data->resume = true; 663 return; 664 } 665 666 /* 667 * SHADOWCON/PRTCON register is used for enabling timing. 668 * 669 * for example, once only width value of a register is set, 670 * if the dma is started then fimd hardware could malfunction so 671 * with protect window setting, the register fields with prefix '_F' 672 * wouldn't be updated at vsync also but updated once unprotect window 673 * is set. 674 */ 675 676 /* protect windows */ 677 fimd_shadow_protect_win(ctx, win, true); 678 679 /* buffer start address */ 680 val = (unsigned long)win_data->dma_addr; 681 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 682 683 /* buffer end address */ 684 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); 685 val = (unsigned long)(win_data->dma_addr + size); 686 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 687 688 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 689 (unsigned long)win_data->dma_addr, val, size); 690 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 691 win_data->ovl_width, win_data->ovl_height); 692 693 /* buffer size */ 694 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | 695 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | 696 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | 697 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); 698 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 699 700 /* OSD position */ 701 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | 702 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | 703 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | 704 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); 705 writel(val, ctx->regs + VIDOSD_A(win)); 706 707 last_x = win_data->offset_x + win_data->ovl_width; 708 if (last_x) 709 last_x--; 710 last_y = win_data->offset_y + win_data->ovl_height; 711 if (last_y) 712 last_y--; 713 714 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 715 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 716 717 writel(val, ctx->regs + VIDOSD_B(win)); 718 719 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 720 win_data->offset_x, win_data->offset_y, last_x, last_y); 721 722 /* hardware window 0 doesn't support alpha channel. */ 723 if (win != 0) { 724 /* OSD alpha */ 725 alpha = VIDISD14C_ALPHA1_R(0xf) | 726 VIDISD14C_ALPHA1_G(0xf) | 727 VIDISD14C_ALPHA1_B(0xf); 728 729 writel(alpha, ctx->regs + VIDOSD_C(win)); 730 } 731 732 /* OSD size */ 733 if (win != 3 && win != 4) { 734 u32 offset = VIDOSD_D(win); 735 if (win == 0) 736 offset = VIDOSD_C(win); 737 val = win_data->ovl_width * win_data->ovl_height; 738 writel(val, ctx->regs + offset); 739 740 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 741 } 742 743 fimd_win_set_pixfmt(ctx, win); 744 745 /* hardware window 0 doesn't support color key. */ 746 if (win != 0) 747 fimd_win_set_colkey(ctx, win); 748 749 /* wincon */ 750 val = readl(ctx->regs + WINCON(win)); 751 val |= WINCONx_ENWIN; 752 writel(val, ctx->regs + WINCON(win)); 753 754 /* Enable DMA channel and unprotect windows */ 755 fimd_shadow_protect_win(ctx, win, false); 756 757 if (ctx->driver_data->has_shadowcon) { 758 val = readl(ctx->regs + SHADOWCON); 759 val |= SHADOWCON_CHx_ENABLE(win); 760 writel(val, ctx->regs + SHADOWCON); 761 } 762 763 win_data->enabled = true; 764 765 if (ctx->i80_if) 766 atomic_set(&ctx->win_updated, 1); 767 } 768 769 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos) 770 { 771 struct fimd_context *ctx = mgr->ctx; 772 struct fimd_win_data *win_data; 773 int win = zpos; 774 u32 val; 775 776 if (win == DEFAULT_ZPOS) 777 win = ctx->default_win; 778 779 if (win < 0 || win >= WINDOWS_NR) 780 return; 781 782 win_data = &ctx->win_data[win]; 783 784 if (ctx->suspended) { 785 /* do not resume this window*/ 786 win_data->resume = false; 787 return; 788 } 789 790 /* protect windows */ 791 fimd_shadow_protect_win(ctx, win, true); 792 793 /* wincon */ 794 val = readl(ctx->regs + WINCON(win)); 795 val &= ~WINCONx_ENWIN; 796 writel(val, ctx->regs + WINCON(win)); 797 798 /* unprotect windows */ 799 if (ctx->driver_data->has_shadowcon) { 800 val = readl(ctx->regs + SHADOWCON); 801 val &= ~SHADOWCON_CHx_ENABLE(win); 802 writel(val, ctx->regs + SHADOWCON); 803 } 804 805 fimd_shadow_protect_win(ctx, win, false); 806 807 win_data->enabled = false; 808 } 809 810 static void fimd_window_suspend(struct exynos_drm_manager *mgr) 811 { 812 struct fimd_context *ctx = mgr->ctx; 813 struct fimd_win_data *win_data; 814 int i; 815 816 for (i = 0; i < WINDOWS_NR; i++) { 817 win_data = &ctx->win_data[i]; 818 win_data->resume = win_data->enabled; 819 if (win_data->enabled) 820 fimd_win_disable(mgr, i); 821 } 822 } 823 824 static void fimd_window_resume(struct exynos_drm_manager *mgr) 825 { 826 struct fimd_context *ctx = mgr->ctx; 827 struct fimd_win_data *win_data; 828 int i; 829 830 for (i = 0; i < WINDOWS_NR; i++) { 831 win_data = &ctx->win_data[i]; 832 win_data->enabled = win_data->resume; 833 win_data->resume = false; 834 } 835 } 836 837 static void fimd_apply(struct exynos_drm_manager *mgr) 838 { 839 struct fimd_context *ctx = mgr->ctx; 840 struct fimd_win_data *win_data; 841 int i; 842 843 for (i = 0; i < WINDOWS_NR; i++) { 844 win_data = &ctx->win_data[i]; 845 if (win_data->enabled) 846 fimd_win_commit(mgr, i); 847 else 848 fimd_win_disable(mgr, i); 849 } 850 851 fimd_commit(mgr); 852 } 853 854 static int fimd_poweron(struct exynos_drm_manager *mgr) 855 { 856 struct fimd_context *ctx = mgr->ctx; 857 int ret; 858 859 if (!ctx->suspended) 860 return 0; 861 862 ctx->suspended = false; 863 864 pm_runtime_get_sync(ctx->dev); 865 866 ret = clk_prepare_enable(ctx->bus_clk); 867 if (ret < 0) { 868 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 869 goto bus_clk_err; 870 } 871 872 ret = clk_prepare_enable(ctx->lcd_clk); 873 if (ret < 0) { 874 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 875 goto lcd_clk_err; 876 } 877 878 /* if vblank was enabled status, enable it again. */ 879 if (test_and_clear_bit(0, &ctx->irq_flags)) { 880 ret = fimd_enable_vblank(mgr); 881 if (ret) { 882 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); 883 goto enable_vblank_err; 884 } 885 } 886 887 fimd_window_resume(mgr); 888 889 fimd_apply(mgr); 890 891 return 0; 892 893 enable_vblank_err: 894 clk_disable_unprepare(ctx->lcd_clk); 895 lcd_clk_err: 896 clk_disable_unprepare(ctx->bus_clk); 897 bus_clk_err: 898 ctx->suspended = true; 899 return ret; 900 } 901 902 static int fimd_poweroff(struct exynos_drm_manager *mgr) 903 { 904 struct fimd_context *ctx = mgr->ctx; 905 906 if (ctx->suspended) 907 return 0; 908 909 /* 910 * We need to make sure that all windows are disabled before we 911 * suspend that connector. Otherwise we might try to scan from 912 * a destroyed buffer later. 913 */ 914 fimd_window_suspend(mgr); 915 916 clk_disable_unprepare(ctx->lcd_clk); 917 clk_disable_unprepare(ctx->bus_clk); 918 919 pm_runtime_put_sync(ctx->dev); 920 921 ctx->suspended = true; 922 return 0; 923 } 924 925 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode) 926 { 927 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); 928 929 switch (mode) { 930 case DRM_MODE_DPMS_ON: 931 fimd_poweron(mgr); 932 break; 933 case DRM_MODE_DPMS_STANDBY: 934 case DRM_MODE_DPMS_SUSPEND: 935 case DRM_MODE_DPMS_OFF: 936 fimd_poweroff(mgr); 937 break; 938 default: 939 DRM_DEBUG_KMS("unspecified mode %d\n", mode); 940 break; 941 } 942 } 943 944 static void fimd_trigger(struct device *dev) 945 { 946 struct exynos_drm_manager *mgr = get_fimd_manager(dev); 947 struct fimd_context *ctx = mgr->ctx; 948 struct fimd_driver_data *driver_data = ctx->driver_data; 949 void *timing_base = ctx->regs + driver_data->timing_base; 950 u32 reg; 951 952 atomic_set(&ctx->triggering, 1); 953 954 reg = readl(ctx->regs + VIDINTCON0); 955 reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE | 956 VIDINTCON0_INT_SYSMAINCON); 957 writel(reg, ctx->regs + VIDINTCON0); 958 959 reg = readl(timing_base + TRIGCON); 960 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 961 writel(reg, timing_base + TRIGCON); 962 } 963 964 static void fimd_te_handler(struct exynos_drm_manager *mgr) 965 { 966 struct fimd_context *ctx = mgr->ctx; 967 968 /* Checks the crtc is detached already from encoder */ 969 if (ctx->pipe < 0 || !ctx->drm_dev) 970 return; 971 972 /* 973 * Skips to trigger if in triggering state, because multiple triggering 974 * requests can cause panel reset. 975 */ 976 if (atomic_read(&ctx->triggering)) 977 return; 978 979 /* 980 * If there is a page flip request, triggers and handles the page flip 981 * event so that current fb can be updated into panel GRAM. 982 */ 983 if (atomic_add_unless(&ctx->win_updated, -1, 0)) 984 fimd_trigger(ctx->dev); 985 986 /* Wakes up vsync event queue */ 987 if (atomic_read(&ctx->wait_vsync_event)) { 988 atomic_set(&ctx->wait_vsync_event, 0); 989 wake_up(&ctx->wait_vsync_queue); 990 } 991 992 if (!atomic_read(&ctx->triggering)) 993 drm_handle_vblank(ctx->drm_dev, ctx->pipe); 994 } 995 996 static struct exynos_drm_manager_ops fimd_manager_ops = { 997 .dpms = fimd_dpms, 998 .mode_fixup = fimd_mode_fixup, 999 .mode_set = fimd_mode_set, 1000 .commit = fimd_commit, 1001 .enable_vblank = fimd_enable_vblank, 1002 .disable_vblank = fimd_disable_vblank, 1003 .wait_for_vblank = fimd_wait_for_vblank, 1004 .win_mode_set = fimd_win_mode_set, 1005 .win_commit = fimd_win_commit, 1006 .win_disable = fimd_win_disable, 1007 .te_handler = fimd_te_handler, 1008 }; 1009 1010 static struct exynos_drm_manager fimd_manager = { 1011 .type = EXYNOS_DISPLAY_TYPE_LCD, 1012 .ops = &fimd_manager_ops, 1013 }; 1014 1015 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 1016 { 1017 struct fimd_context *ctx = (struct fimd_context *)dev_id; 1018 u32 val, clear_bit; 1019 1020 val = readl(ctx->regs + VIDINTCON1); 1021 1022 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 1023 if (val & clear_bit) 1024 writel(clear_bit, ctx->regs + VIDINTCON1); 1025 1026 /* check the crtc is detached already from encoder */ 1027 if (ctx->pipe < 0 || !ctx->drm_dev) 1028 goto out; 1029 1030 if (ctx->i80_if) { 1031 /* unset I80 frame done interrupt */ 1032 val = readl(ctx->regs + VIDINTCON0); 1033 val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON); 1034 writel(val, ctx->regs + VIDINTCON0); 1035 1036 /* exit triggering mode */ 1037 atomic_set(&ctx->triggering, 0); 1038 1039 drm_handle_vblank(ctx->drm_dev, ctx->pipe); 1040 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); 1041 } else { 1042 drm_handle_vblank(ctx->drm_dev, ctx->pipe); 1043 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); 1044 1045 /* set wait vsync event to zero and wake up queue. */ 1046 if (atomic_read(&ctx->wait_vsync_event)) { 1047 atomic_set(&ctx->wait_vsync_event, 0); 1048 wake_up(&ctx->wait_vsync_queue); 1049 } 1050 } 1051 1052 out: 1053 return IRQ_HANDLED; 1054 } 1055 1056 static int fimd_bind(struct device *dev, struct device *master, void *data) 1057 { 1058 struct fimd_context *ctx = fimd_manager.ctx; 1059 struct drm_device *drm_dev = data; 1060 1061 fimd_mgr_initialize(&fimd_manager, drm_dev); 1062 exynos_drm_crtc_create(&fimd_manager); 1063 if (ctx->display) 1064 exynos_drm_create_enc_conn(drm_dev, ctx->display); 1065 1066 return 0; 1067 1068 } 1069 1070 static void fimd_unbind(struct device *dev, struct device *master, 1071 void *data) 1072 { 1073 struct exynos_drm_manager *mgr = dev_get_drvdata(dev); 1074 struct fimd_context *ctx = fimd_manager.ctx; 1075 1076 fimd_dpms(mgr, DRM_MODE_DPMS_OFF); 1077 1078 if (ctx->display) 1079 exynos_dpi_remove(dev); 1080 1081 fimd_mgr_remove(mgr); 1082 } 1083 1084 static const struct component_ops fimd_component_ops = { 1085 .bind = fimd_bind, 1086 .unbind = fimd_unbind, 1087 }; 1088 1089 static int fimd_probe(struct platform_device *pdev) 1090 { 1091 struct device *dev = &pdev->dev; 1092 struct fimd_context *ctx; 1093 struct device_node *i80_if_timings; 1094 struct resource *res; 1095 int ret = -EINVAL; 1096 1097 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC, 1098 fimd_manager.type); 1099 if (ret) 1100 return ret; 1101 1102 if (!dev->of_node) { 1103 ret = -ENODEV; 1104 goto err_del_component; 1105 } 1106 1107 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1108 if (!ctx) { 1109 ret = -ENOMEM; 1110 goto err_del_component; 1111 } 1112 1113 ctx->dev = dev; 1114 ctx->suspended = true; 1115 ctx->driver_data = drm_fimd_get_driver_data(pdev); 1116 1117 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 1118 ctx->vidcon1 |= VIDCON1_INV_VDEN; 1119 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 1120 ctx->vidcon1 |= VIDCON1_INV_VCLK; 1121 1122 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 1123 if (i80_if_timings) { 1124 u32 val; 1125 1126 ctx->i80_if = true; 1127 1128 if (ctx->driver_data->has_vidoutcon) 1129 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 1130 else 1131 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 1132 /* 1133 * The user manual describes that this "DSI_EN" bit is required 1134 * to enable I80 24-bit data interface. 1135 */ 1136 ctx->vidcon0 |= VIDCON0_DSI_EN; 1137 1138 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 1139 val = 0; 1140 ctx->i80ifcon = LCD_CS_SETUP(val); 1141 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 1142 val = 0; 1143 ctx->i80ifcon |= LCD_WR_SETUP(val); 1144 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 1145 val = 1; 1146 ctx->i80ifcon |= LCD_WR_ACTIVE(val); 1147 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 1148 val = 0; 1149 ctx->i80ifcon |= LCD_WR_HOLD(val); 1150 } 1151 of_node_put(i80_if_timings); 1152 1153 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1154 "samsung,sysreg"); 1155 if (IS_ERR(ctx->sysreg)) { 1156 dev_warn(dev, "failed to get system register.\n"); 1157 ctx->sysreg = NULL; 1158 } 1159 1160 ctx->bus_clk = devm_clk_get(dev, "fimd"); 1161 if (IS_ERR(ctx->bus_clk)) { 1162 dev_err(dev, "failed to get bus clock\n"); 1163 ret = PTR_ERR(ctx->bus_clk); 1164 goto err_del_component; 1165 } 1166 1167 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1168 if (IS_ERR(ctx->lcd_clk)) { 1169 dev_err(dev, "failed to get lcd clock\n"); 1170 ret = PTR_ERR(ctx->lcd_clk); 1171 goto err_del_component; 1172 } 1173 1174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1175 1176 ctx->regs = devm_ioremap_resource(dev, res); 1177 if (IS_ERR(ctx->regs)) { 1178 ret = PTR_ERR(ctx->regs); 1179 goto err_del_component; 1180 } 1181 1182 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1183 ctx->i80_if ? "lcd_sys" : "vsync"); 1184 if (!res) { 1185 dev_err(dev, "irq request failed.\n"); 1186 ret = -ENXIO; 1187 goto err_del_component; 1188 } 1189 1190 ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1191 0, "drm_fimd", ctx); 1192 if (ret) { 1193 dev_err(dev, "irq request failed.\n"); 1194 goto err_del_component; 1195 } 1196 1197 init_waitqueue_head(&ctx->wait_vsync_queue); 1198 atomic_set(&ctx->wait_vsync_event, 0); 1199 1200 platform_set_drvdata(pdev, &fimd_manager); 1201 1202 fimd_manager.ctx = ctx; 1203 1204 ctx->display = exynos_dpi_probe(dev); 1205 if (IS_ERR(ctx->display)) 1206 return PTR_ERR(ctx->display); 1207 1208 pm_runtime_enable(&pdev->dev); 1209 1210 ret = component_add(&pdev->dev, &fimd_component_ops); 1211 if (ret) 1212 goto err_disable_pm_runtime; 1213 1214 return ret; 1215 1216 err_disable_pm_runtime: 1217 pm_runtime_disable(&pdev->dev); 1218 1219 err_del_component: 1220 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC); 1221 return ret; 1222 } 1223 1224 static int fimd_remove(struct platform_device *pdev) 1225 { 1226 pm_runtime_disable(&pdev->dev); 1227 1228 component_del(&pdev->dev, &fimd_component_ops); 1229 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC); 1230 1231 return 0; 1232 } 1233 1234 struct platform_driver fimd_driver = { 1235 .probe = fimd_probe, 1236 .remove = fimd_remove, 1237 .driver = { 1238 .name = "exynos4-fb", 1239 .owner = THIS_MODULE, 1240 .of_match_table = fimd_driver_dt_match, 1241 }, 1242 }; 1243