1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/component.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/regmap.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/samsung_fimd.h> 29 #include <drm/exynos_drm.h> 30 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fb.h" 33 #include "exynos_drm_crtc.h" 34 #include "exynos_drm_plane.h" 35 36 /* 37 * FIMD stands for Fully Interactive Mobile Display and 38 * as a display controller, it transfers contents drawn on memory 39 * to a LCD Panel through Display Interfaces such as RGB or 40 * CPU Interface. 41 */ 42 43 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 44 45 /* position control register for hardware window 0, 2 ~ 4.*/ 46 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 47 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 48 /* 49 * size control register for hardware windows 0 and alpha control register 50 * for hardware windows 1 ~ 4 51 */ 52 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 53 /* size control register for hardware windows 1 ~ 2. */ 54 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 55 56 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 57 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 58 59 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 60 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) 61 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 62 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 63 64 /* color key control register for hardware window 1 ~ 4. */ 65 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 66 /* color key value register for hardware window 1 ~ 4. */ 67 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 68 69 /* I80 trigger control register */ 70 #define TRIGCON 0x1A4 71 #define TRGMODE_ENABLE (1 << 0) 72 #define SWTRGCMD_ENABLE (1 << 1) 73 /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */ 74 #define HWTRGEN_ENABLE (1 << 3) 75 #define HWTRGMASK_ENABLE (1 << 4) 76 /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */ 77 #define HWTRIGEN_PER_ENABLE (1 << 31) 78 79 /* display mode change control register except exynos4 */ 80 #define VIDOUT_CON 0x000 81 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 82 83 /* I80 interface control for main LDI register */ 84 #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 85 #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 86 #define LCD_CS_SETUP(x) ((x) << 16) 87 #define LCD_WR_SETUP(x) ((x) << 12) 88 #define LCD_WR_ACTIVE(x) ((x) << 8) 89 #define LCD_WR_HOLD(x) ((x) << 4) 90 #define I80IFEN_ENABLE (1 << 0) 91 92 /* FIMD has totally five hardware windows. */ 93 #define WINDOWS_NR 5 94 95 /* HW trigger flag on i80 panel. */ 96 #define I80_HW_TRG (1 << 1) 97 98 struct fimd_driver_data { 99 unsigned int timing_base; 100 unsigned int lcdblk_offset; 101 unsigned int lcdblk_vt_shift; 102 unsigned int lcdblk_bypass_shift; 103 unsigned int lcdblk_mic_bypass_shift; 104 unsigned int trg_type; 105 106 unsigned int has_shadowcon:1; 107 unsigned int has_clksel:1; 108 unsigned int has_limited_fmt:1; 109 unsigned int has_vidoutcon:1; 110 unsigned int has_vtsel:1; 111 unsigned int has_mic_bypass:1; 112 unsigned int has_dp_clk:1; 113 unsigned int has_hw_trigger:1; 114 unsigned int has_trigger_per_te:1; 115 }; 116 117 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 118 .timing_base = 0x0, 119 .has_clksel = 1, 120 .has_limited_fmt = 1, 121 }; 122 123 static struct fimd_driver_data s5pv210_fimd_driver_data = { 124 .timing_base = 0x0, 125 .has_shadowcon = 1, 126 .has_clksel = 1, 127 }; 128 129 static struct fimd_driver_data exynos3_fimd_driver_data = { 130 .timing_base = 0x20000, 131 .lcdblk_offset = 0x210, 132 .lcdblk_bypass_shift = 1, 133 .has_shadowcon = 1, 134 .has_vidoutcon = 1, 135 }; 136 137 static struct fimd_driver_data exynos4_fimd_driver_data = { 138 .timing_base = 0x0, 139 .lcdblk_offset = 0x210, 140 .lcdblk_vt_shift = 10, 141 .lcdblk_bypass_shift = 1, 142 .has_shadowcon = 1, 143 .has_vtsel = 1, 144 }; 145 146 static struct fimd_driver_data exynos5_fimd_driver_data = { 147 .timing_base = 0x20000, 148 .lcdblk_offset = 0x214, 149 .lcdblk_vt_shift = 24, 150 .lcdblk_bypass_shift = 15, 151 .has_shadowcon = 1, 152 .has_vidoutcon = 1, 153 .has_vtsel = 1, 154 .has_dp_clk = 1, 155 }; 156 157 static struct fimd_driver_data exynos5420_fimd_driver_data = { 158 .timing_base = 0x20000, 159 .lcdblk_offset = 0x214, 160 .lcdblk_vt_shift = 24, 161 .lcdblk_bypass_shift = 15, 162 .lcdblk_mic_bypass_shift = 11, 163 .has_shadowcon = 1, 164 .has_vidoutcon = 1, 165 .has_vtsel = 1, 166 .has_mic_bypass = 1, 167 .has_dp_clk = 1, 168 }; 169 170 struct fimd_context { 171 struct device *dev; 172 struct drm_device *drm_dev; 173 struct exynos_drm_crtc *crtc; 174 struct exynos_drm_plane planes[WINDOWS_NR]; 175 struct exynos_drm_plane_config configs[WINDOWS_NR]; 176 struct clk *bus_clk; 177 struct clk *lcd_clk; 178 void __iomem *regs; 179 struct regmap *sysreg; 180 unsigned long irq_flags; 181 u32 vidcon0; 182 u32 vidcon1; 183 u32 vidout_con; 184 u32 i80ifcon; 185 bool i80_if; 186 bool suspended; 187 wait_queue_head_t wait_vsync_queue; 188 atomic_t wait_vsync_event; 189 atomic_t win_updated; 190 atomic_t triggering; 191 u32 clkdiv; 192 193 const struct fimd_driver_data *driver_data; 194 struct drm_encoder *encoder; 195 struct exynos_drm_clk dp_clk; 196 }; 197 198 static const struct of_device_id fimd_driver_dt_match[] = { 199 { .compatible = "samsung,s3c6400-fimd", 200 .data = &s3c64xx_fimd_driver_data }, 201 { .compatible = "samsung,s5pv210-fimd", 202 .data = &s5pv210_fimd_driver_data }, 203 { .compatible = "samsung,exynos3250-fimd", 204 .data = &exynos3_fimd_driver_data }, 205 { .compatible = "samsung,exynos4210-fimd", 206 .data = &exynos4_fimd_driver_data }, 207 { .compatible = "samsung,exynos5250-fimd", 208 .data = &exynos5_fimd_driver_data }, 209 { .compatible = "samsung,exynos5420-fimd", 210 .data = &exynos5420_fimd_driver_data }, 211 {}, 212 }; 213 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 214 215 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = { 216 DRM_PLANE_TYPE_PRIMARY, 217 DRM_PLANE_TYPE_OVERLAY, 218 DRM_PLANE_TYPE_OVERLAY, 219 DRM_PLANE_TYPE_OVERLAY, 220 DRM_PLANE_TYPE_CURSOR, 221 }; 222 223 static const uint32_t fimd_formats[] = { 224 DRM_FORMAT_C8, 225 DRM_FORMAT_XRGB1555, 226 DRM_FORMAT_RGB565, 227 DRM_FORMAT_XRGB8888, 228 DRM_FORMAT_ARGB8888, 229 }; 230 231 static const unsigned int capabilities[WINDOWS_NR] = { 232 0, 233 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 234 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 235 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 236 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 237 }; 238 239 static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask, 240 u32 val) 241 { 242 val = (val & mask) | (readl(ctx->regs + reg) & ~mask); 243 writel(val, ctx->regs + reg); 244 } 245 246 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 247 { 248 struct fimd_context *ctx = crtc->ctx; 249 u32 val; 250 251 if (ctx->suspended) 252 return -EPERM; 253 254 if (!test_and_set_bit(0, &ctx->irq_flags)) { 255 val = readl(ctx->regs + VIDINTCON0); 256 257 val |= VIDINTCON0_INT_ENABLE; 258 259 if (ctx->i80_if) { 260 val |= VIDINTCON0_INT_I80IFDONE; 261 val |= VIDINTCON0_INT_SYSMAINCON; 262 val &= ~VIDINTCON0_INT_SYSSUBCON; 263 } else { 264 val |= VIDINTCON0_INT_FRAME; 265 266 val &= ~VIDINTCON0_FRAMESEL0_MASK; 267 val |= VIDINTCON0_FRAMESEL0_FRONTPORCH; 268 val &= ~VIDINTCON0_FRAMESEL1_MASK; 269 val |= VIDINTCON0_FRAMESEL1_NONE; 270 } 271 272 writel(val, ctx->regs + VIDINTCON0); 273 } 274 275 return 0; 276 } 277 278 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 279 { 280 struct fimd_context *ctx = crtc->ctx; 281 u32 val; 282 283 if (ctx->suspended) 284 return; 285 286 if (test_and_clear_bit(0, &ctx->irq_flags)) { 287 val = readl(ctx->regs + VIDINTCON0); 288 289 val &= ~VIDINTCON0_INT_ENABLE; 290 291 if (ctx->i80_if) { 292 val &= ~VIDINTCON0_INT_I80IFDONE; 293 val &= ~VIDINTCON0_INT_SYSMAINCON; 294 val &= ~VIDINTCON0_INT_SYSSUBCON; 295 } else 296 val &= ~VIDINTCON0_INT_FRAME; 297 298 writel(val, ctx->regs + VIDINTCON0); 299 } 300 } 301 302 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 303 { 304 struct fimd_context *ctx = crtc->ctx; 305 306 if (ctx->suspended) 307 return; 308 309 atomic_set(&ctx->wait_vsync_event, 1); 310 311 /* 312 * wait for FIMD to signal VSYNC interrupt or return after 313 * timeout which is set to 50ms (refresh rate of 20). 314 */ 315 if (!wait_event_timeout(ctx->wait_vsync_queue, 316 !atomic_read(&ctx->wait_vsync_event), 317 HZ/20)) 318 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); 319 } 320 321 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 322 bool enable) 323 { 324 u32 val = readl(ctx->regs + WINCON(win)); 325 326 if (enable) 327 val |= WINCONx_ENWIN; 328 else 329 val &= ~WINCONx_ENWIN; 330 331 writel(val, ctx->regs + WINCON(win)); 332 } 333 334 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 335 unsigned int win, 336 bool enable) 337 { 338 u32 val = readl(ctx->regs + SHADOWCON); 339 340 if (enable) 341 val |= SHADOWCON_CHx_ENABLE(win); 342 else 343 val &= ~SHADOWCON_CHx_ENABLE(win); 344 345 writel(val, ctx->regs + SHADOWCON); 346 } 347 348 static void fimd_clear_channels(struct exynos_drm_crtc *crtc) 349 { 350 struct fimd_context *ctx = crtc->ctx; 351 unsigned int win, ch_enabled = 0; 352 353 /* Hardware is in unknown state, so ensure it gets enabled properly */ 354 pm_runtime_get_sync(ctx->dev); 355 356 clk_prepare_enable(ctx->bus_clk); 357 clk_prepare_enable(ctx->lcd_clk); 358 359 /* Check if any channel is enabled. */ 360 for (win = 0; win < WINDOWS_NR; win++) { 361 u32 val = readl(ctx->regs + WINCON(win)); 362 363 if (val & WINCONx_ENWIN) { 364 fimd_enable_video_output(ctx, win, false); 365 366 if (ctx->driver_data->has_shadowcon) 367 fimd_enable_shadow_channel_path(ctx, win, 368 false); 369 370 ch_enabled = 1; 371 } 372 } 373 374 /* Wait for vsync, as disable channel takes effect at next vsync */ 375 if (ch_enabled) { 376 ctx->suspended = false; 377 378 fimd_enable_vblank(ctx->crtc); 379 fimd_wait_for_vblank(ctx->crtc); 380 fimd_disable_vblank(ctx->crtc); 381 382 ctx->suspended = true; 383 } 384 385 clk_disable_unprepare(ctx->lcd_clk); 386 clk_disable_unprepare(ctx->bus_clk); 387 388 pm_runtime_put(ctx->dev); 389 } 390 391 392 static int fimd_atomic_check(struct exynos_drm_crtc *crtc, 393 struct drm_crtc_state *state) 394 { 395 struct drm_display_mode *mode = &state->adjusted_mode; 396 struct fimd_context *ctx = crtc->ctx; 397 unsigned long ideal_clk, lcd_rate; 398 u32 clkdiv; 399 400 if (mode->clock == 0) { 401 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n"); 402 return -EINVAL; 403 } 404 405 ideal_clk = mode->clock * 1000; 406 407 if (ctx->i80_if) { 408 /* 409 * The frame done interrupt should be occurred prior to the 410 * next TE signal. 411 */ 412 ideal_clk *= 2; 413 } 414 415 lcd_rate = clk_get_rate(ctx->lcd_clk); 416 if (2 * lcd_rate < ideal_clk) { 417 DRM_DEV_ERROR(ctx->dev, 418 "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n", 419 lcd_rate, ideal_clk); 420 return -EINVAL; 421 } 422 423 /* Find the clock divider value that gets us closest to ideal_clk */ 424 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); 425 if (clkdiv >= 0x200) { 426 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n", 427 ideal_clk); 428 return -EINVAL; 429 } 430 431 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; 432 433 return 0; 434 } 435 436 static void fimd_setup_trigger(struct fimd_context *ctx) 437 { 438 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; 439 u32 trg_type = ctx->driver_data->trg_type; 440 u32 val = readl(timing_base + TRIGCON); 441 442 val &= ~(TRGMODE_ENABLE); 443 444 if (trg_type == I80_HW_TRG) { 445 if (ctx->driver_data->has_hw_trigger) 446 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE; 447 if (ctx->driver_data->has_trigger_per_te) 448 val |= HWTRIGEN_PER_ENABLE; 449 } else { 450 val |= TRGMODE_ENABLE; 451 } 452 453 writel(val, timing_base + TRIGCON); 454 } 455 456 static void fimd_commit(struct exynos_drm_crtc *crtc) 457 { 458 struct fimd_context *ctx = crtc->ctx; 459 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 460 const struct fimd_driver_data *driver_data = ctx->driver_data; 461 void *timing_base = ctx->regs + driver_data->timing_base; 462 u32 val; 463 464 if (ctx->suspended) 465 return; 466 467 /* nothing to do if we haven't set the mode yet */ 468 if (mode->htotal == 0 || mode->vtotal == 0) 469 return; 470 471 if (ctx->i80_if) { 472 val = ctx->i80ifcon | I80IFEN_ENABLE; 473 writel(val, timing_base + I80IFCONFAx(0)); 474 475 /* disable auto frame rate */ 476 writel(0, timing_base + I80IFCONFBx(0)); 477 478 /* set video type selection to I80 interface */ 479 if (driver_data->has_vtsel && ctx->sysreg && 480 regmap_update_bits(ctx->sysreg, 481 driver_data->lcdblk_offset, 482 0x3 << driver_data->lcdblk_vt_shift, 483 0x1 << driver_data->lcdblk_vt_shift)) { 484 DRM_DEV_ERROR(ctx->dev, 485 "Failed to update sysreg for I80 i/f.\n"); 486 return; 487 } 488 } else { 489 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 490 u32 vidcon1; 491 492 /* setup polarity values */ 493 vidcon1 = ctx->vidcon1; 494 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 495 vidcon1 |= VIDCON1_INV_VSYNC; 496 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 497 vidcon1 |= VIDCON1_INV_HSYNC; 498 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 499 500 /* setup vertical timing values. */ 501 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 502 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 503 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 504 505 val = VIDTCON0_VBPD(vbpd - 1) | 506 VIDTCON0_VFPD(vfpd - 1) | 507 VIDTCON0_VSPW(vsync_len - 1); 508 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 509 510 /* setup horizontal timing values. */ 511 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 512 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 513 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 514 515 val = VIDTCON1_HBPD(hbpd - 1) | 516 VIDTCON1_HFPD(hfpd - 1) | 517 VIDTCON1_HSPW(hsync_len - 1); 518 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 519 } 520 521 if (driver_data->has_vidoutcon) 522 writel(ctx->vidout_con, timing_base + VIDOUT_CON); 523 524 /* set bypass selection */ 525 if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 526 driver_data->lcdblk_offset, 527 0x1 << driver_data->lcdblk_bypass_shift, 528 0x1 << driver_data->lcdblk_bypass_shift)) { 529 DRM_DEV_ERROR(ctx->dev, 530 "Failed to update sysreg for bypass setting.\n"); 531 return; 532 } 533 534 /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass 535 * bit should be cleared. 536 */ 537 if (driver_data->has_mic_bypass && ctx->sysreg && 538 regmap_update_bits(ctx->sysreg, 539 driver_data->lcdblk_offset, 540 0x1 << driver_data->lcdblk_mic_bypass_shift, 541 0x1 << driver_data->lcdblk_mic_bypass_shift)) { 542 DRM_DEV_ERROR(ctx->dev, 543 "Failed to update sysreg for bypass mic.\n"); 544 return; 545 } 546 547 /* setup horizontal and vertical display size. */ 548 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 549 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 550 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 551 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 552 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 553 554 fimd_setup_trigger(ctx); 555 556 /* 557 * fields of register with prefix '_F' would be updated 558 * at vsync(same as dma start) 559 */ 560 val = ctx->vidcon0; 561 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 562 563 if (ctx->driver_data->has_clksel) 564 val |= VIDCON0_CLKSEL_LCD; 565 566 if (ctx->clkdiv > 1) 567 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; 568 569 writel(val, ctx->regs + VIDCON0); 570 } 571 572 static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win, 573 unsigned int alpha, unsigned int pixel_alpha) 574 { 575 u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf); 576 u32 val = 0; 577 578 switch (pixel_alpha) { 579 case DRM_MODE_BLEND_PIXEL_NONE: 580 case DRM_MODE_BLEND_COVERAGE: 581 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A); 582 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); 583 break; 584 case DRM_MODE_BLEND_PREMULTI: 585 default: 586 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 587 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0); 588 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); 589 } else { 590 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE); 591 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A); 592 } 593 break; 594 } 595 fimd_set_bits(ctx, BLENDEQx(win), mask, val); 596 } 597 598 static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win, 599 unsigned int alpha, unsigned int pixel_alpha) 600 { 601 u32 win_alpha_l = (alpha >> 8) & 0xf; 602 u32 win_alpha_h = alpha >> 12; 603 u32 val = 0; 604 605 switch (pixel_alpha) { 606 case DRM_MODE_BLEND_PIXEL_NONE: 607 break; 608 case DRM_MODE_BLEND_COVERAGE: 609 case DRM_MODE_BLEND_PREMULTI: 610 default: 611 val |= WINCON1_ALPHA_SEL; 612 val |= WINCON1_BLD_PIX; 613 val |= WINCON1_ALPHA_MUL; 614 break; 615 } 616 fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val); 617 618 /* OSD alpha */ 619 val = VIDISD14C_ALPHA0_R(win_alpha_h) | 620 VIDISD14C_ALPHA0_G(win_alpha_h) | 621 VIDISD14C_ALPHA0_B(win_alpha_h) | 622 VIDISD14C_ALPHA1_R(0x0) | 623 VIDISD14C_ALPHA1_G(0x0) | 624 VIDISD14C_ALPHA1_B(0x0); 625 writel(val, ctx->regs + VIDOSD_C(win)); 626 627 val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) | 628 VIDW_ALPHA_B(win_alpha_l); 629 writel(val, ctx->regs + VIDWnALPHA0(win)); 630 631 val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) | 632 VIDW_ALPHA_B(0x0); 633 writel(val, ctx->regs + VIDWnALPHA1(win)); 634 635 fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK, 636 BLENDCON_NEW_8BIT_ALPHA_VALUE); 637 } 638 639 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, 640 struct drm_framebuffer *fb, int width) 641 { 642 struct exynos_drm_plane plane = ctx->planes[win]; 643 struct exynos_drm_plane_state *state = 644 to_exynos_plane_state(plane.base.state); 645 uint32_t pixel_format = fb->format->format; 646 unsigned int alpha = state->base.alpha; 647 u32 val = WINCONx_ENWIN; 648 unsigned int pixel_alpha; 649 650 if (fb->format->has_alpha) 651 pixel_alpha = state->base.pixel_blend_mode; 652 else 653 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; 654 655 /* 656 * In case of s3c64xx, window 0 doesn't support alpha channel. 657 * So the request format is ARGB8888 then change it to XRGB8888. 658 */ 659 if (ctx->driver_data->has_limited_fmt && !win) { 660 if (pixel_format == DRM_FORMAT_ARGB8888) 661 pixel_format = DRM_FORMAT_XRGB8888; 662 } 663 664 switch (pixel_format) { 665 case DRM_FORMAT_C8: 666 val |= WINCON0_BPPMODE_8BPP_PALETTE; 667 val |= WINCONx_BURSTLEN_8WORD; 668 val |= WINCONx_BYTSWP; 669 break; 670 case DRM_FORMAT_XRGB1555: 671 val |= WINCON0_BPPMODE_16BPP_1555; 672 val |= WINCONx_HAWSWP; 673 val |= WINCONx_BURSTLEN_16WORD; 674 break; 675 case DRM_FORMAT_RGB565: 676 val |= WINCON0_BPPMODE_16BPP_565; 677 val |= WINCONx_HAWSWP; 678 val |= WINCONx_BURSTLEN_16WORD; 679 break; 680 case DRM_FORMAT_XRGB8888: 681 val |= WINCON0_BPPMODE_24BPP_888; 682 val |= WINCONx_WSWP; 683 val |= WINCONx_BURSTLEN_16WORD; 684 break; 685 case DRM_FORMAT_ARGB8888: 686 default: 687 val |= WINCON1_BPPMODE_25BPP_A1888; 688 val |= WINCONx_WSWP; 689 val |= WINCONx_BURSTLEN_16WORD; 690 break; 691 } 692 693 /* 694 * Setting dma-burst to 16Word causes permanent tearing for very small 695 * buffers, e.g. cursor buffer. Burst Mode switching which based on 696 * plane size is not recommended as plane size varies alot towards the 697 * end of the screen and rapid movement causes unstable DMA, but it is 698 * still better to change dma-burst than displaying garbage. 699 */ 700 701 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 702 val &= ~WINCONx_BURSTLEN_MASK; 703 val |= WINCONx_BURSTLEN_4WORD; 704 } 705 fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val); 706 707 /* hardware window 0 doesn't support alpha channel. */ 708 if (win != 0) { 709 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha); 710 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha); 711 } 712 } 713 714 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 715 { 716 unsigned int keycon0 = 0, keycon1 = 0; 717 718 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 719 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 720 721 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 722 723 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 724 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 725 } 726 727 /** 728 * shadow_protect_win() - disable updating values from shadow registers at vsync 729 * 730 * @win: window to protect registers for 731 * @protect: 1 to protect (disable updates) 732 */ 733 static void fimd_shadow_protect_win(struct fimd_context *ctx, 734 unsigned int win, bool protect) 735 { 736 u32 reg, bits, val; 737 738 /* 739 * SHADOWCON/PRTCON register is used for enabling timing. 740 * 741 * for example, once only width value of a register is set, 742 * if the dma is started then fimd hardware could malfunction so 743 * with protect window setting, the register fields with prefix '_F' 744 * wouldn't be updated at vsync also but updated once unprotect window 745 * is set. 746 */ 747 748 if (ctx->driver_data->has_shadowcon) { 749 reg = SHADOWCON; 750 bits = SHADOWCON_WINx_PROTECT(win); 751 } else { 752 reg = PRTCON; 753 bits = PRTCON_PROTECT; 754 } 755 756 val = readl(ctx->regs + reg); 757 if (protect) 758 val |= bits; 759 else 760 val &= ~bits; 761 writel(val, ctx->regs + reg); 762 } 763 764 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc) 765 { 766 struct fimd_context *ctx = crtc->ctx; 767 int i; 768 769 if (ctx->suspended) 770 return; 771 772 for (i = 0; i < WINDOWS_NR; i++) 773 fimd_shadow_protect_win(ctx, i, true); 774 } 775 776 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc) 777 { 778 struct fimd_context *ctx = crtc->ctx; 779 int i; 780 781 if (ctx->suspended) 782 return; 783 784 for (i = 0; i < WINDOWS_NR; i++) 785 fimd_shadow_protect_win(ctx, i, false); 786 787 exynos_crtc_handle_event(crtc); 788 } 789 790 static void fimd_update_plane(struct exynos_drm_crtc *crtc, 791 struct exynos_drm_plane *plane) 792 { 793 struct exynos_drm_plane_state *state = 794 to_exynos_plane_state(plane->base.state); 795 struct fimd_context *ctx = crtc->ctx; 796 struct drm_framebuffer *fb = state->base.fb; 797 dma_addr_t dma_addr; 798 unsigned long val, size, offset; 799 unsigned int last_x, last_y, buf_offsize, line_size; 800 unsigned int win = plane->index; 801 unsigned int cpp = fb->format->cpp[0]; 802 unsigned int pitch = fb->pitches[0]; 803 804 if (ctx->suspended) 805 return; 806 807 offset = state->src.x * cpp; 808 offset += state->src.y * pitch; 809 810 /* buffer start address */ 811 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset; 812 val = (unsigned long)dma_addr; 813 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 814 815 /* buffer end address */ 816 size = pitch * state->crtc.h; 817 val = (unsigned long)(dma_addr + size); 818 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 819 820 DRM_DEV_DEBUG_KMS(ctx->dev, 821 "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 822 (unsigned long)dma_addr, val, size); 823 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", 824 state->crtc.w, state->crtc.h); 825 826 /* buffer size */ 827 buf_offsize = pitch - (state->crtc.w * cpp); 828 line_size = state->crtc.w * cpp; 829 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 830 VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 831 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 832 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 833 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 834 835 /* OSD position */ 836 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 837 VIDOSDxA_TOPLEFT_Y(state->crtc.y) | 838 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) | 839 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y); 840 writel(val, ctx->regs + VIDOSD_A(win)); 841 842 last_x = state->crtc.x + state->crtc.w; 843 if (last_x) 844 last_x--; 845 last_y = state->crtc.y + state->crtc.h; 846 if (last_y) 847 last_y--; 848 849 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 850 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 851 852 writel(val, ctx->regs + VIDOSD_B(win)); 853 854 DRM_DEV_DEBUG_KMS(ctx->dev, 855 "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 856 state->crtc.x, state->crtc.y, last_x, last_y); 857 858 /* OSD size */ 859 if (win != 3 && win != 4) { 860 u32 offset = VIDOSD_D(win); 861 if (win == 0) 862 offset = VIDOSD_C(win); 863 val = state->crtc.w * state->crtc.h; 864 writel(val, ctx->regs + offset); 865 866 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n", 867 (unsigned int)val); 868 } 869 870 fimd_win_set_pixfmt(ctx, win, fb, state->src.w); 871 872 /* hardware window 0 doesn't support color key. */ 873 if (win != 0) 874 fimd_win_set_colkey(ctx, win); 875 876 fimd_enable_video_output(ctx, win, true); 877 878 if (ctx->driver_data->has_shadowcon) 879 fimd_enable_shadow_channel_path(ctx, win, true); 880 881 if (ctx->i80_if) 882 atomic_set(&ctx->win_updated, 1); 883 } 884 885 static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 886 struct exynos_drm_plane *plane) 887 { 888 struct fimd_context *ctx = crtc->ctx; 889 unsigned int win = plane->index; 890 891 if (ctx->suspended) 892 return; 893 894 fimd_enable_video_output(ctx, win, false); 895 896 if (ctx->driver_data->has_shadowcon) 897 fimd_enable_shadow_channel_path(ctx, win, false); 898 } 899 900 static void fimd_enable(struct exynos_drm_crtc *crtc) 901 { 902 struct fimd_context *ctx = crtc->ctx; 903 904 if (!ctx->suspended) 905 return; 906 907 ctx->suspended = false; 908 909 pm_runtime_get_sync(ctx->dev); 910 911 /* if vblank was enabled status, enable it again. */ 912 if (test_and_clear_bit(0, &ctx->irq_flags)) 913 fimd_enable_vblank(ctx->crtc); 914 915 fimd_commit(ctx->crtc); 916 } 917 918 static void fimd_disable(struct exynos_drm_crtc *crtc) 919 { 920 struct fimd_context *ctx = crtc->ctx; 921 int i; 922 923 if (ctx->suspended) 924 return; 925 926 /* 927 * We need to make sure that all windows are disabled before we 928 * suspend that connector. Otherwise we might try to scan from 929 * a destroyed buffer later. 930 */ 931 for (i = 0; i < WINDOWS_NR; i++) 932 fimd_disable_plane(crtc, &ctx->planes[i]); 933 934 fimd_enable_vblank(crtc); 935 fimd_wait_for_vblank(crtc); 936 fimd_disable_vblank(crtc); 937 938 writel(0, ctx->regs + VIDCON0); 939 940 pm_runtime_put_sync(ctx->dev); 941 ctx->suspended = true; 942 } 943 944 static void fimd_trigger(struct device *dev) 945 { 946 struct fimd_context *ctx = dev_get_drvdata(dev); 947 const struct fimd_driver_data *driver_data = ctx->driver_data; 948 void *timing_base = ctx->regs + driver_data->timing_base; 949 u32 reg; 950 951 /* 952 * Skips triggering if in triggering state, because multiple triggering 953 * requests can cause panel reset. 954 */ 955 if (atomic_read(&ctx->triggering)) 956 return; 957 958 /* Enters triggering mode */ 959 atomic_set(&ctx->triggering, 1); 960 961 reg = readl(timing_base + TRIGCON); 962 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE); 963 writel(reg, timing_base + TRIGCON); 964 965 /* 966 * Exits triggering mode if vblank is not enabled yet, because when the 967 * VIDINTCON0 register is not set, it can not exit from triggering mode. 968 */ 969 if (!test_bit(0, &ctx->irq_flags)) 970 atomic_set(&ctx->triggering, 0); 971 } 972 973 static void fimd_te_handler(struct exynos_drm_crtc *crtc) 974 { 975 struct fimd_context *ctx = crtc->ctx; 976 u32 trg_type = ctx->driver_data->trg_type; 977 978 /* Checks the crtc is detached already from encoder */ 979 if (!ctx->drm_dev) 980 return; 981 982 if (trg_type == I80_HW_TRG) 983 goto out; 984 985 /* 986 * If there is a page flip request, triggers and handles the page flip 987 * event so that current fb can be updated into panel GRAM. 988 */ 989 if (atomic_add_unless(&ctx->win_updated, -1, 0)) 990 fimd_trigger(ctx->dev); 991 992 out: 993 /* Wakes up vsync event queue */ 994 if (atomic_read(&ctx->wait_vsync_event)) { 995 atomic_set(&ctx->wait_vsync_event, 0); 996 wake_up(&ctx->wait_vsync_queue); 997 } 998 999 if (test_bit(0, &ctx->irq_flags)) 1000 drm_crtc_handle_vblank(&ctx->crtc->base); 1001 } 1002 1003 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable) 1004 { 1005 struct fimd_context *ctx = container_of(clk, struct fimd_context, 1006 dp_clk); 1007 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 1008 writel(val, ctx->regs + DP_MIE_CLKCON); 1009 } 1010 1011 static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 1012 .enable = fimd_enable, 1013 .disable = fimd_disable, 1014 .enable_vblank = fimd_enable_vblank, 1015 .disable_vblank = fimd_disable_vblank, 1016 .atomic_begin = fimd_atomic_begin, 1017 .update_plane = fimd_update_plane, 1018 .disable_plane = fimd_disable_plane, 1019 .atomic_flush = fimd_atomic_flush, 1020 .atomic_check = fimd_atomic_check, 1021 .te_handler = fimd_te_handler, 1022 }; 1023 1024 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 1025 { 1026 struct fimd_context *ctx = (struct fimd_context *)dev_id; 1027 u32 val, clear_bit; 1028 1029 val = readl(ctx->regs + VIDINTCON1); 1030 1031 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 1032 if (val & clear_bit) 1033 writel(clear_bit, ctx->regs + VIDINTCON1); 1034 1035 /* check the crtc is detached already from encoder */ 1036 if (!ctx->drm_dev) 1037 goto out; 1038 1039 if (!ctx->i80_if) 1040 drm_crtc_handle_vblank(&ctx->crtc->base); 1041 1042 if (ctx->i80_if) { 1043 /* Exits triggering mode */ 1044 atomic_set(&ctx->triggering, 0); 1045 } else { 1046 /* set wait vsync event to zero and wake up queue. */ 1047 if (atomic_read(&ctx->wait_vsync_event)) { 1048 atomic_set(&ctx->wait_vsync_event, 0); 1049 wake_up(&ctx->wait_vsync_queue); 1050 } 1051 } 1052 1053 out: 1054 return IRQ_HANDLED; 1055 } 1056 1057 static int fimd_bind(struct device *dev, struct device *master, void *data) 1058 { 1059 struct fimd_context *ctx = dev_get_drvdata(dev); 1060 struct drm_device *drm_dev = data; 1061 struct exynos_drm_plane *exynos_plane; 1062 unsigned int i; 1063 int ret; 1064 1065 ctx->drm_dev = drm_dev; 1066 1067 for (i = 0; i < WINDOWS_NR; i++) { 1068 ctx->configs[i].pixel_formats = fimd_formats; 1069 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats); 1070 ctx->configs[i].zpos = i; 1071 ctx->configs[i].type = fimd_win_types[i]; 1072 ctx->configs[i].capabilities = capabilities[i]; 1073 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 1074 &ctx->configs[i]); 1075 if (ret) 1076 return ret; 1077 } 1078 1079 exynos_plane = &ctx->planes[DEFAULT_WIN]; 1080 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 1081 EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); 1082 if (IS_ERR(ctx->crtc)) 1083 return PTR_ERR(ctx->crtc); 1084 1085 if (ctx->driver_data->has_dp_clk) { 1086 ctx->dp_clk.enable = fimd_dp_clock_enable; 1087 ctx->crtc->pipe_clk = &ctx->dp_clk; 1088 } 1089 1090 if (ctx->encoder) 1091 exynos_dpi_bind(drm_dev, ctx->encoder); 1092 1093 if (is_drm_iommu_supported(drm_dev)) 1094 fimd_clear_channels(ctx->crtc); 1095 1096 return exynos_drm_register_dma(drm_dev, dev); 1097 } 1098 1099 static void fimd_unbind(struct device *dev, struct device *master, 1100 void *data) 1101 { 1102 struct fimd_context *ctx = dev_get_drvdata(dev); 1103 1104 fimd_disable(ctx->crtc); 1105 1106 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev); 1107 1108 if (ctx->encoder) 1109 exynos_dpi_remove(ctx->encoder); 1110 } 1111 1112 static const struct component_ops fimd_component_ops = { 1113 .bind = fimd_bind, 1114 .unbind = fimd_unbind, 1115 }; 1116 1117 static int fimd_probe(struct platform_device *pdev) 1118 { 1119 struct device *dev = &pdev->dev; 1120 struct fimd_context *ctx; 1121 struct device_node *i80_if_timings; 1122 struct resource *res; 1123 int ret; 1124 1125 if (!dev->of_node) 1126 return -ENODEV; 1127 1128 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1129 if (!ctx) 1130 return -ENOMEM; 1131 1132 ctx->dev = dev; 1133 ctx->suspended = true; 1134 ctx->driver_data = of_device_get_match_data(dev); 1135 1136 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 1137 ctx->vidcon1 |= VIDCON1_INV_VDEN; 1138 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 1139 ctx->vidcon1 |= VIDCON1_INV_VCLK; 1140 1141 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 1142 if (i80_if_timings) { 1143 u32 val; 1144 1145 ctx->i80_if = true; 1146 1147 if (ctx->driver_data->has_vidoutcon) 1148 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 1149 else 1150 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 1151 /* 1152 * The user manual describes that this "DSI_EN" bit is required 1153 * to enable I80 24-bit data interface. 1154 */ 1155 ctx->vidcon0 |= VIDCON0_DSI_EN; 1156 1157 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 1158 val = 0; 1159 ctx->i80ifcon = LCD_CS_SETUP(val); 1160 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 1161 val = 0; 1162 ctx->i80ifcon |= LCD_WR_SETUP(val); 1163 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 1164 val = 1; 1165 ctx->i80ifcon |= LCD_WR_ACTIVE(val); 1166 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 1167 val = 0; 1168 ctx->i80ifcon |= LCD_WR_HOLD(val); 1169 } 1170 of_node_put(i80_if_timings); 1171 1172 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 1173 "samsung,sysreg"); 1174 if (IS_ERR(ctx->sysreg)) { 1175 dev_warn(dev, "failed to get system register.\n"); 1176 ctx->sysreg = NULL; 1177 } 1178 1179 ctx->bus_clk = devm_clk_get(dev, "fimd"); 1180 if (IS_ERR(ctx->bus_clk)) { 1181 dev_err(dev, "failed to get bus clock\n"); 1182 return PTR_ERR(ctx->bus_clk); 1183 } 1184 1185 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1186 if (IS_ERR(ctx->lcd_clk)) { 1187 dev_err(dev, "failed to get lcd clock\n"); 1188 return PTR_ERR(ctx->lcd_clk); 1189 } 1190 1191 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1192 1193 ctx->regs = devm_ioremap_resource(dev, res); 1194 if (IS_ERR(ctx->regs)) 1195 return PTR_ERR(ctx->regs); 1196 1197 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 1198 ctx->i80_if ? "lcd_sys" : "vsync"); 1199 if (!res) { 1200 dev_err(dev, "irq request failed.\n"); 1201 return -ENXIO; 1202 } 1203 1204 ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1205 0, "drm_fimd", ctx); 1206 if (ret) { 1207 dev_err(dev, "irq request failed.\n"); 1208 return ret; 1209 } 1210 1211 init_waitqueue_head(&ctx->wait_vsync_queue); 1212 atomic_set(&ctx->wait_vsync_event, 0); 1213 1214 platform_set_drvdata(pdev, ctx); 1215 1216 ctx->encoder = exynos_dpi_probe(dev); 1217 if (IS_ERR(ctx->encoder)) 1218 return PTR_ERR(ctx->encoder); 1219 1220 pm_runtime_enable(dev); 1221 1222 ret = component_add(dev, &fimd_component_ops); 1223 if (ret) 1224 goto err_disable_pm_runtime; 1225 1226 return ret; 1227 1228 err_disable_pm_runtime: 1229 pm_runtime_disable(dev); 1230 1231 return ret; 1232 } 1233 1234 static int fimd_remove(struct platform_device *pdev) 1235 { 1236 pm_runtime_disable(&pdev->dev); 1237 1238 component_del(&pdev->dev, &fimd_component_ops); 1239 1240 return 0; 1241 } 1242 1243 #ifdef CONFIG_PM 1244 static int exynos_fimd_suspend(struct device *dev) 1245 { 1246 struct fimd_context *ctx = dev_get_drvdata(dev); 1247 1248 clk_disable_unprepare(ctx->lcd_clk); 1249 clk_disable_unprepare(ctx->bus_clk); 1250 1251 return 0; 1252 } 1253 1254 static int exynos_fimd_resume(struct device *dev) 1255 { 1256 struct fimd_context *ctx = dev_get_drvdata(dev); 1257 int ret; 1258 1259 ret = clk_prepare_enable(ctx->bus_clk); 1260 if (ret < 0) { 1261 DRM_DEV_ERROR(dev, 1262 "Failed to prepare_enable the bus clk [%d]\n", 1263 ret); 1264 return ret; 1265 } 1266 1267 ret = clk_prepare_enable(ctx->lcd_clk); 1268 if (ret < 0) { 1269 DRM_DEV_ERROR(dev, 1270 "Failed to prepare_enable the lcd clk [%d]\n", 1271 ret); 1272 return ret; 1273 } 1274 1275 return 0; 1276 } 1277 #endif 1278 1279 static const struct dev_pm_ops exynos_fimd_pm_ops = { 1280 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL) 1281 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1282 pm_runtime_force_resume) 1283 }; 1284 1285 struct platform_driver fimd_driver = { 1286 .probe = fimd_probe, 1287 .remove = fimd_remove, 1288 .driver = { 1289 .name = "exynos4-fb", 1290 .owner = THIS_MODULE, 1291 .pm = &exynos_fimd_pm_ops, 1292 .of_match_table = fimd_driver_dt_match, 1293 }, 1294 }; 1295