1 /* exynos_drm_fimd.c 2 * 3 * Copyright (C) 2011 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Inki Dae <inki.dae@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 16 #include <linux/kernel.h> 17 #include <linux/platform_device.h> 18 #include <linux/clk.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/pm_runtime.h> 22 23 #include <video/of_display_timing.h> 24 #include <video/of_videomode.h> 25 #include <video/samsung_fimd.h> 26 #include <drm/exynos_drm.h> 27 28 #include "exynos_drm_drv.h" 29 #include "exynos_drm_fbdev.h" 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_iommu.h" 32 33 /* 34 * FIMD stands for Fully Interactive Mobile Display and 35 * as a display controller, it transfers contents drawn on memory 36 * to a LCD Panel through Display Interfaces such as RGB or 37 * CPU Interface. 38 */ 39 40 #define FIMD_DEFAULT_FRAMERATE 60 41 42 /* position control register for hardware window 0, 2 ~ 4.*/ 43 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 44 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 45 /* 46 * size control register for hardware windows 0 and alpha control register 47 * for hardware windows 1 ~ 4 48 */ 49 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 50 /* size control register for hardware windows 1 ~ 2. */ 51 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 52 53 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 54 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 55 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 56 57 /* color key control register for hardware window 1 ~ 4. */ 58 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 59 /* color key value register for hardware window 1 ~ 4. */ 60 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 61 62 /* FIMD has totally five hardware windows. */ 63 #define WINDOWS_NR 5 64 65 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev)) 66 67 struct fimd_driver_data { 68 unsigned int timing_base; 69 70 unsigned int has_shadowcon:1; 71 unsigned int has_clksel:1; 72 unsigned int has_limited_fmt:1; 73 }; 74 75 static struct fimd_driver_data s3c64xx_fimd_driver_data = { 76 .timing_base = 0x0, 77 .has_clksel = 1, 78 .has_limited_fmt = 1, 79 }; 80 81 static struct fimd_driver_data exynos4_fimd_driver_data = { 82 .timing_base = 0x0, 83 .has_shadowcon = 1, 84 }; 85 86 static struct fimd_driver_data exynos5_fimd_driver_data = { 87 .timing_base = 0x20000, 88 .has_shadowcon = 1, 89 }; 90 91 struct fimd_win_data { 92 unsigned int offset_x; 93 unsigned int offset_y; 94 unsigned int ovl_width; 95 unsigned int ovl_height; 96 unsigned int fb_width; 97 unsigned int fb_height; 98 unsigned int bpp; 99 unsigned int pixel_format; 100 dma_addr_t dma_addr; 101 unsigned int buf_offsize; 102 unsigned int line_size; /* bytes */ 103 bool enabled; 104 bool resume; 105 }; 106 107 struct fimd_context { 108 struct device *dev; 109 struct drm_device *drm_dev; 110 struct clk *bus_clk; 111 struct clk *lcd_clk; 112 void __iomem *regs; 113 struct drm_display_mode mode; 114 struct fimd_win_data win_data[WINDOWS_NR]; 115 unsigned int default_win; 116 unsigned long irq_flags; 117 u32 vidcon0; 118 u32 vidcon1; 119 bool suspended; 120 int pipe; 121 wait_queue_head_t wait_vsync_queue; 122 atomic_t wait_vsync_event; 123 124 struct exynos_drm_panel_info panel; 125 struct fimd_driver_data *driver_data; 126 }; 127 128 static const struct of_device_id fimd_driver_dt_match[] = { 129 { .compatible = "samsung,s3c6400-fimd", 130 .data = &s3c64xx_fimd_driver_data }, 131 { .compatible = "samsung,exynos4210-fimd", 132 .data = &exynos4_fimd_driver_data }, 133 { .compatible = "samsung,exynos5250-fimd", 134 .data = &exynos5_fimd_driver_data }, 135 {}, 136 }; 137 138 static inline struct fimd_driver_data *drm_fimd_get_driver_data( 139 struct platform_device *pdev) 140 { 141 const struct of_device_id *of_id = 142 of_match_device(fimd_driver_dt_match, &pdev->dev); 143 144 return (struct fimd_driver_data *)of_id->data; 145 } 146 147 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr, 148 struct drm_device *drm_dev, int pipe) 149 { 150 struct fimd_context *ctx = mgr->ctx; 151 152 ctx->drm_dev = drm_dev; 153 ctx->pipe = pipe; 154 155 /* 156 * enable drm irq mode. 157 * - with irq_enabled = true, we can use the vblank feature. 158 * 159 * P.S. note that we wouldn't use drm irq handler but 160 * just specific driver own one instead because 161 * drm framework supports only one irq handler. 162 */ 163 drm_dev->irq_enabled = true; 164 165 /* 166 * with vblank_disable_allowed = true, vblank interrupt will be disabled 167 * by drm timer once a current process gives up ownership of 168 * vblank event.(after drm_vblank_put function is called) 169 */ 170 drm_dev->vblank_disable_allowed = true; 171 172 /* attach this sub driver to iommu mapping if supported. */ 173 if (is_drm_iommu_supported(ctx->drm_dev)) 174 drm_iommu_attach_device(ctx->drm_dev, ctx->dev); 175 176 return 0; 177 } 178 179 static void fimd_mgr_remove(struct exynos_drm_manager *mgr) 180 { 181 struct fimd_context *ctx = mgr->ctx; 182 183 /* detach this sub driver from iommu mapping if supported. */ 184 if (is_drm_iommu_supported(ctx->drm_dev)) 185 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 186 } 187 188 static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 189 const struct drm_display_mode *mode) 190 { 191 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 192 u32 clkdiv; 193 194 /* Find the clock divider value that gets us closest to ideal_clk */ 195 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 196 197 return (clkdiv < 0x100) ? clkdiv : 0xff; 198 } 199 200 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr, 201 const struct drm_display_mode *mode, 202 struct drm_display_mode *adjusted_mode) 203 { 204 if (adjusted_mode->vrefresh == 0) 205 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 206 207 return true; 208 } 209 210 static void fimd_mode_set(struct exynos_drm_manager *mgr, 211 const struct drm_display_mode *in_mode) 212 { 213 struct fimd_context *ctx = mgr->ctx; 214 215 drm_mode_copy(&ctx->mode, in_mode); 216 } 217 218 static void fimd_commit(struct exynos_drm_manager *mgr) 219 { 220 struct fimd_context *ctx = mgr->ctx; 221 struct drm_display_mode *mode = &ctx->mode; 222 struct fimd_driver_data *driver_data; 223 u32 val, clkdiv, vidcon1; 224 int hblank, vblank, vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 225 226 driver_data = ctx->driver_data; 227 if (ctx->suspended) 228 return; 229 230 /* nothing to do if we haven't set the mode yet */ 231 if (mode->htotal == 0 || mode->vtotal == 0) 232 return; 233 234 /* setup polarity values */ 235 vidcon1 = ctx->vidcon1; 236 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 237 vidcon1 |= VIDCON1_INV_VSYNC; 238 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 239 vidcon1 |= VIDCON1_INV_HSYNC; 240 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 241 242 /* setup vertical timing values. */ 243 vblank = mode->crtc_vblank_end - mode->crtc_vblank_start; 244 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 245 vbpd = (vblank - vsync_len) / 2; 246 vfpd = vblank - vsync_len - vbpd; 247 248 val = VIDTCON0_VBPD(vbpd - 1) | 249 VIDTCON0_VFPD(vfpd - 1) | 250 VIDTCON0_VSPW(vsync_len - 1); 251 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 252 253 /* setup horizontal timing values. */ 254 hblank = mode->crtc_hblank_end - mode->crtc_hblank_start; 255 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 256 hbpd = (hblank - hsync_len) / 2; 257 hfpd = hblank - hsync_len - hbpd; 258 259 val = VIDTCON1_HBPD(hbpd - 1) | 260 VIDTCON1_HFPD(hfpd - 1) | 261 VIDTCON1_HSPW(hsync_len - 1); 262 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 263 264 /* setup horizontal and vertical display size. */ 265 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 266 VIDTCON2_HOZVAL(mode->hdisplay - 1) | 267 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 268 VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 269 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 270 271 /* setup clock source, clock divider, enable dma. */ 272 val = ctx->vidcon0; 273 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); 274 275 if (ctx->driver_data->has_clksel) { 276 val &= ~VIDCON0_CLKSEL_MASK; 277 val |= VIDCON0_CLKSEL_LCD; 278 } 279 280 clkdiv = fimd_calc_clkdiv(ctx, mode); 281 if (clkdiv > 1) 282 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 283 else 284 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ 285 286 /* 287 * fields of register with prefix '_F' would be updated 288 * at vsync(same as dma start) 289 */ 290 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 291 writel(val, ctx->regs + VIDCON0); 292 } 293 294 static int fimd_enable_vblank(struct exynos_drm_manager *mgr) 295 { 296 struct fimd_context *ctx = mgr->ctx; 297 u32 val; 298 299 if (ctx->suspended) 300 return -EPERM; 301 302 if (!test_and_set_bit(0, &ctx->irq_flags)) { 303 val = readl(ctx->regs + VIDINTCON0); 304 305 val |= VIDINTCON0_INT_ENABLE; 306 val |= VIDINTCON0_INT_FRAME; 307 308 val &= ~VIDINTCON0_FRAMESEL0_MASK; 309 val |= VIDINTCON0_FRAMESEL0_VSYNC; 310 val &= ~VIDINTCON0_FRAMESEL1_MASK; 311 val |= VIDINTCON0_FRAMESEL1_NONE; 312 313 writel(val, ctx->regs + VIDINTCON0); 314 } 315 316 return 0; 317 } 318 319 static void fimd_disable_vblank(struct exynos_drm_manager *mgr) 320 { 321 struct fimd_context *ctx = mgr->ctx; 322 u32 val; 323 324 if (ctx->suspended) 325 return; 326 327 if (test_and_clear_bit(0, &ctx->irq_flags)) { 328 val = readl(ctx->regs + VIDINTCON0); 329 330 val &= ~VIDINTCON0_INT_FRAME; 331 val &= ~VIDINTCON0_INT_ENABLE; 332 333 writel(val, ctx->regs + VIDINTCON0); 334 } 335 } 336 337 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr) 338 { 339 struct fimd_context *ctx = mgr->ctx; 340 341 if (ctx->suspended) 342 return; 343 344 atomic_set(&ctx->wait_vsync_event, 1); 345 346 /* 347 * wait for FIMD to signal VSYNC interrupt or return after 348 * timeout which is set to 50ms (refresh rate of 20). 349 */ 350 if (!wait_event_timeout(ctx->wait_vsync_queue, 351 !atomic_read(&ctx->wait_vsync_event), 352 HZ/20)) 353 DRM_DEBUG_KMS("vblank wait timed out.\n"); 354 } 355 356 static void fimd_win_mode_set(struct exynos_drm_manager *mgr, 357 struct exynos_drm_overlay *overlay) 358 { 359 struct fimd_context *ctx = mgr->ctx; 360 struct fimd_win_data *win_data; 361 int win; 362 unsigned long offset; 363 364 if (!overlay) { 365 DRM_ERROR("overlay is NULL\n"); 366 return; 367 } 368 369 win = overlay->zpos; 370 if (win == DEFAULT_ZPOS) 371 win = ctx->default_win; 372 373 if (win < 0 || win >= WINDOWS_NR) 374 return; 375 376 offset = overlay->fb_x * (overlay->bpp >> 3); 377 offset += overlay->fb_y * overlay->pitch; 378 379 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); 380 381 win_data = &ctx->win_data[win]; 382 383 win_data->offset_x = overlay->crtc_x; 384 win_data->offset_y = overlay->crtc_y; 385 win_data->ovl_width = overlay->crtc_width; 386 win_data->ovl_height = overlay->crtc_height; 387 win_data->fb_width = overlay->fb_width; 388 win_data->fb_height = overlay->fb_height; 389 win_data->dma_addr = overlay->dma_addr[0] + offset; 390 win_data->bpp = overlay->bpp; 391 win_data->pixel_format = overlay->pixel_format; 392 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * 393 (overlay->bpp >> 3); 394 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); 395 396 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", 397 win_data->offset_x, win_data->offset_y); 398 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 399 win_data->ovl_width, win_data->ovl_height); 400 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); 401 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", 402 overlay->fb_width, overlay->crtc_width); 403 } 404 405 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) 406 { 407 struct fimd_win_data *win_data = &ctx->win_data[win]; 408 unsigned long val; 409 410 val = WINCONx_ENWIN; 411 412 /* 413 * In case of s3c64xx, window 0 doesn't support alpha channel. 414 * So the request format is ARGB8888 then change it to XRGB8888. 415 */ 416 if (ctx->driver_data->has_limited_fmt && !win) { 417 if (win_data->pixel_format == DRM_FORMAT_ARGB8888) 418 win_data->pixel_format = DRM_FORMAT_XRGB8888; 419 } 420 421 switch (win_data->pixel_format) { 422 case DRM_FORMAT_C8: 423 val |= WINCON0_BPPMODE_8BPP_PALETTE; 424 val |= WINCONx_BURSTLEN_8WORD; 425 val |= WINCONx_BYTSWP; 426 break; 427 case DRM_FORMAT_XRGB1555: 428 val |= WINCON0_BPPMODE_16BPP_1555; 429 val |= WINCONx_HAWSWP; 430 val |= WINCONx_BURSTLEN_16WORD; 431 break; 432 case DRM_FORMAT_RGB565: 433 val |= WINCON0_BPPMODE_16BPP_565; 434 val |= WINCONx_HAWSWP; 435 val |= WINCONx_BURSTLEN_16WORD; 436 break; 437 case DRM_FORMAT_XRGB8888: 438 val |= WINCON0_BPPMODE_24BPP_888; 439 val |= WINCONx_WSWP; 440 val |= WINCONx_BURSTLEN_16WORD; 441 break; 442 case DRM_FORMAT_ARGB8888: 443 val |= WINCON1_BPPMODE_25BPP_A1888 444 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 445 val |= WINCONx_WSWP; 446 val |= WINCONx_BURSTLEN_16WORD; 447 break; 448 default: 449 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 450 451 val |= WINCON0_BPPMODE_24BPP_888; 452 val |= WINCONx_WSWP; 453 val |= WINCONx_BURSTLEN_16WORD; 454 break; 455 } 456 457 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); 458 459 writel(val, ctx->regs + WINCON(win)); 460 } 461 462 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 463 { 464 unsigned int keycon0 = 0, keycon1 = 0; 465 466 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 467 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 468 469 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 470 471 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 472 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 473 } 474 475 /** 476 * shadow_protect_win() - disable updating values from shadow registers at vsync 477 * 478 * @win: window to protect registers for 479 * @protect: 1 to protect (disable updates) 480 */ 481 static void fimd_shadow_protect_win(struct fimd_context *ctx, 482 int win, bool protect) 483 { 484 u32 reg, bits, val; 485 486 if (ctx->driver_data->has_shadowcon) { 487 reg = SHADOWCON; 488 bits = SHADOWCON_WINx_PROTECT(win); 489 } else { 490 reg = PRTCON; 491 bits = PRTCON_PROTECT; 492 } 493 494 val = readl(ctx->regs + reg); 495 if (protect) 496 val |= bits; 497 else 498 val &= ~bits; 499 writel(val, ctx->regs + reg); 500 } 501 502 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos) 503 { 504 struct fimd_context *ctx = mgr->ctx; 505 struct fimd_win_data *win_data; 506 int win = zpos; 507 unsigned long val, alpha, size; 508 unsigned int last_x; 509 unsigned int last_y; 510 511 if (ctx->suspended) 512 return; 513 514 if (win == DEFAULT_ZPOS) 515 win = ctx->default_win; 516 517 if (win < 0 || win >= WINDOWS_NR) 518 return; 519 520 win_data = &ctx->win_data[win]; 521 522 /* 523 * SHADOWCON/PRTCON register is used for enabling timing. 524 * 525 * for example, once only width value of a register is set, 526 * if the dma is started then fimd hardware could malfunction so 527 * with protect window setting, the register fields with prefix '_F' 528 * wouldn't be updated at vsync also but updated once unprotect window 529 * is set. 530 */ 531 532 /* protect windows */ 533 fimd_shadow_protect_win(ctx, win, true); 534 535 /* buffer start address */ 536 val = (unsigned long)win_data->dma_addr; 537 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 538 539 /* buffer end address */ 540 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); 541 val = (unsigned long)(win_data->dma_addr + size); 542 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 543 544 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 545 (unsigned long)win_data->dma_addr, val, size); 546 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 547 win_data->ovl_width, win_data->ovl_height); 548 549 /* buffer size */ 550 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | 551 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | 552 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | 553 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); 554 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 555 556 /* OSD position */ 557 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | 558 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | 559 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | 560 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); 561 writel(val, ctx->regs + VIDOSD_A(win)); 562 563 last_x = win_data->offset_x + win_data->ovl_width; 564 if (last_x) 565 last_x--; 566 last_y = win_data->offset_y + win_data->ovl_height; 567 if (last_y) 568 last_y--; 569 570 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 571 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 572 573 writel(val, ctx->regs + VIDOSD_B(win)); 574 575 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 576 win_data->offset_x, win_data->offset_y, last_x, last_y); 577 578 /* hardware window 0 doesn't support alpha channel. */ 579 if (win != 0) { 580 /* OSD alpha */ 581 alpha = VIDISD14C_ALPHA1_R(0xf) | 582 VIDISD14C_ALPHA1_G(0xf) | 583 VIDISD14C_ALPHA1_B(0xf); 584 585 writel(alpha, ctx->regs + VIDOSD_C(win)); 586 } 587 588 /* OSD size */ 589 if (win != 3 && win != 4) { 590 u32 offset = VIDOSD_D(win); 591 if (win == 0) 592 offset = VIDOSD_C(win); 593 val = win_data->ovl_width * win_data->ovl_height; 594 writel(val, ctx->regs + offset); 595 596 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 597 } 598 599 fimd_win_set_pixfmt(ctx, win); 600 601 /* hardware window 0 doesn't support color key. */ 602 if (win != 0) 603 fimd_win_set_colkey(ctx, win); 604 605 /* wincon */ 606 val = readl(ctx->regs + WINCON(win)); 607 val |= WINCONx_ENWIN; 608 writel(val, ctx->regs + WINCON(win)); 609 610 /* Enable DMA channel and unprotect windows */ 611 fimd_shadow_protect_win(ctx, win, false); 612 613 if (ctx->driver_data->has_shadowcon) { 614 val = readl(ctx->regs + SHADOWCON); 615 val |= SHADOWCON_CHx_ENABLE(win); 616 writel(val, ctx->regs + SHADOWCON); 617 } 618 619 win_data->enabled = true; 620 } 621 622 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos) 623 { 624 struct fimd_context *ctx = mgr->ctx; 625 struct fimd_win_data *win_data; 626 int win = zpos; 627 u32 val; 628 629 if (win == DEFAULT_ZPOS) 630 win = ctx->default_win; 631 632 if (win < 0 || win >= WINDOWS_NR) 633 return; 634 635 win_data = &ctx->win_data[win]; 636 637 if (ctx->suspended) { 638 /* do not resume this window*/ 639 win_data->resume = false; 640 return; 641 } 642 643 /* protect windows */ 644 fimd_shadow_protect_win(ctx, win, true); 645 646 /* wincon */ 647 val = readl(ctx->regs + WINCON(win)); 648 val &= ~WINCONx_ENWIN; 649 writel(val, ctx->regs + WINCON(win)); 650 651 /* unprotect windows */ 652 if (ctx->driver_data->has_shadowcon) { 653 val = readl(ctx->regs + SHADOWCON); 654 val &= ~SHADOWCON_CHx_ENABLE(win); 655 writel(val, ctx->regs + SHADOWCON); 656 } 657 658 fimd_shadow_protect_win(ctx, win, false); 659 660 win_data->enabled = false; 661 } 662 663 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode) 664 { 665 struct fimd_context *ctx = mgr->ctx; 666 667 DRM_DEBUG_KMS("%d\n", mode); 668 669 switch (mode) { 670 case DRM_MODE_DPMS_ON: 671 /* 672 * enable fimd hardware only if suspended status. 673 * 674 * P.S. fimd_dpms function would be called at booting time so 675 * clk_enable could be called double time. 676 */ 677 if (ctx->suspended) 678 pm_runtime_get_sync(ctx->dev); 679 break; 680 case DRM_MODE_DPMS_STANDBY: 681 case DRM_MODE_DPMS_SUSPEND: 682 case DRM_MODE_DPMS_OFF: 683 if (!ctx->suspended) 684 pm_runtime_put_sync(ctx->dev); 685 break; 686 default: 687 DRM_DEBUG_KMS("unspecified mode %d\n", mode); 688 break; 689 } 690 } 691 692 static struct exynos_drm_manager_ops fimd_manager_ops = { 693 .initialize = fimd_mgr_initialize, 694 .remove = fimd_mgr_remove, 695 .dpms = fimd_dpms, 696 .mode_fixup = fimd_mode_fixup, 697 .mode_set = fimd_mode_set, 698 .commit = fimd_commit, 699 .enable_vblank = fimd_enable_vblank, 700 .disable_vblank = fimd_disable_vblank, 701 .wait_for_vblank = fimd_wait_for_vblank, 702 .win_mode_set = fimd_win_mode_set, 703 .win_commit = fimd_win_commit, 704 .win_disable = fimd_win_disable, 705 }; 706 707 static struct exynos_drm_manager fimd_manager = { 708 .type = EXYNOS_DISPLAY_TYPE_LCD, 709 .ops = &fimd_manager_ops, 710 }; 711 712 static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 713 { 714 struct fimd_context *ctx = (struct fimd_context *)dev_id; 715 u32 val; 716 717 val = readl(ctx->regs + VIDINTCON1); 718 719 if (val & VIDINTCON1_INT_FRAME) 720 /* VSYNC interrupt */ 721 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); 722 723 /* check the crtc is detached already from encoder */ 724 if (ctx->pipe < 0 || !ctx->drm_dev) 725 goto out; 726 727 drm_handle_vblank(ctx->drm_dev, ctx->pipe); 728 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); 729 730 /* set wait vsync event to zero and wake up queue. */ 731 if (atomic_read(&ctx->wait_vsync_event)) { 732 atomic_set(&ctx->wait_vsync_event, 0); 733 wake_up(&ctx->wait_vsync_queue); 734 } 735 out: 736 return IRQ_HANDLED; 737 } 738 739 static void fimd_clear_win(struct fimd_context *ctx, int win) 740 { 741 writel(0, ctx->regs + WINCON(win)); 742 writel(0, ctx->regs + VIDOSD_A(win)); 743 writel(0, ctx->regs + VIDOSD_B(win)); 744 writel(0, ctx->regs + VIDOSD_C(win)); 745 746 if (win == 1 || win == 2) 747 writel(0, ctx->regs + VIDOSD_D(win)); 748 749 fimd_shadow_protect_win(ctx, win, false); 750 } 751 752 static int fimd_clock(struct fimd_context *ctx, bool enable) 753 { 754 if (enable) { 755 int ret; 756 757 ret = clk_prepare_enable(ctx->bus_clk); 758 if (ret < 0) 759 return ret; 760 761 ret = clk_prepare_enable(ctx->lcd_clk); 762 if (ret < 0) { 763 clk_disable_unprepare(ctx->bus_clk); 764 return ret; 765 } 766 } else { 767 clk_disable_unprepare(ctx->lcd_clk); 768 clk_disable_unprepare(ctx->bus_clk); 769 } 770 771 return 0; 772 } 773 774 static void fimd_window_suspend(struct exynos_drm_manager *mgr) 775 { 776 struct fimd_context *ctx = mgr->ctx; 777 struct fimd_win_data *win_data; 778 int i; 779 780 for (i = 0; i < WINDOWS_NR; i++) { 781 win_data = &ctx->win_data[i]; 782 win_data->resume = win_data->enabled; 783 fimd_win_disable(mgr, i); 784 } 785 fimd_wait_for_vblank(mgr); 786 } 787 788 static void fimd_window_resume(struct exynos_drm_manager *mgr) 789 { 790 struct fimd_context *ctx = mgr->ctx; 791 struct fimd_win_data *win_data; 792 int i; 793 794 for (i = 0; i < WINDOWS_NR; i++) { 795 win_data = &ctx->win_data[i]; 796 win_data->enabled = win_data->resume; 797 win_data->resume = false; 798 } 799 } 800 801 static void fimd_apply(struct exynos_drm_manager *mgr) 802 { 803 struct fimd_context *ctx = mgr->ctx; 804 struct fimd_win_data *win_data; 805 int i; 806 807 for (i = 0; i < WINDOWS_NR; i++) { 808 win_data = &ctx->win_data[i]; 809 if (win_data->enabled) 810 fimd_win_commit(mgr, i); 811 } 812 813 fimd_commit(mgr); 814 } 815 816 static int fimd_activate(struct exynos_drm_manager *mgr, bool enable) 817 { 818 struct fimd_context *ctx = mgr->ctx; 819 820 if (enable) { 821 int ret; 822 823 ret = fimd_clock(ctx, true); 824 if (ret < 0) 825 return ret; 826 827 ctx->suspended = false; 828 829 /* if vblank was enabled status, enable it again. */ 830 if (test_and_clear_bit(0, &ctx->irq_flags)) 831 fimd_enable_vblank(mgr); 832 833 fimd_window_resume(mgr); 834 835 fimd_apply(mgr); 836 } else { 837 fimd_window_suspend(mgr); 838 839 fimd_clock(ctx, false); 840 ctx->suspended = true; 841 } 842 843 return 0; 844 } 845 846 static int fimd_probe(struct platform_device *pdev) 847 { 848 struct device *dev = &pdev->dev; 849 struct fimd_context *ctx; 850 struct resource *res; 851 int win; 852 int ret = -EINVAL; 853 854 if (!dev->of_node) 855 return -ENODEV; 856 857 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 858 if (!ctx) 859 return -ENOMEM; 860 861 ctx->dev = dev; 862 863 if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 864 ctx->vidcon1 |= VIDCON1_INV_VDEN; 865 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 866 ctx->vidcon1 |= VIDCON1_INV_VCLK; 867 868 ctx->bus_clk = devm_clk_get(dev, "fimd"); 869 if (IS_ERR(ctx->bus_clk)) { 870 dev_err(dev, "failed to get bus clock\n"); 871 return PTR_ERR(ctx->bus_clk); 872 } 873 874 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 875 if (IS_ERR(ctx->lcd_clk)) { 876 dev_err(dev, "failed to get lcd clock\n"); 877 return PTR_ERR(ctx->lcd_clk); 878 } 879 880 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 881 882 ctx->regs = devm_ioremap_resource(dev, res); 883 if (IS_ERR(ctx->regs)) 884 return PTR_ERR(ctx->regs); 885 886 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync"); 887 if (!res) { 888 dev_err(dev, "irq request failed.\n"); 889 return -ENXIO; 890 } 891 892 ret = devm_request_irq(dev, res->start, fimd_irq_handler, 893 0, "drm_fimd", ctx); 894 if (ret) { 895 dev_err(dev, "irq request failed.\n"); 896 return ret; 897 } 898 899 ctx->driver_data = drm_fimd_get_driver_data(pdev); 900 init_waitqueue_head(&ctx->wait_vsync_queue); 901 atomic_set(&ctx->wait_vsync_event, 0); 902 903 platform_set_drvdata(pdev, &fimd_manager); 904 905 fimd_manager.ctx = ctx; 906 exynos_drm_manager_register(&fimd_manager); 907 908 pm_runtime_enable(dev); 909 pm_runtime_get_sync(dev); 910 911 for (win = 0; win < WINDOWS_NR; win++) 912 fimd_clear_win(ctx, win); 913 914 return 0; 915 } 916 917 static int fimd_remove(struct platform_device *pdev) 918 { 919 struct device *dev = &pdev->dev; 920 struct exynos_drm_manager *mgr = platform_get_drvdata(pdev); 921 struct fimd_context *ctx = mgr->ctx; 922 923 exynos_drm_manager_unregister(&fimd_manager); 924 925 if (ctx->suspended) 926 goto out; 927 928 pm_runtime_set_suspended(dev); 929 pm_runtime_put_sync(dev); 930 931 out: 932 pm_runtime_disable(dev); 933 934 return 0; 935 } 936 937 #ifdef CONFIG_PM_SLEEP 938 static int fimd_suspend(struct device *dev) 939 { 940 struct exynos_drm_manager *mgr = get_fimd_manager(dev); 941 942 /* 943 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is 944 * called here, an error would be returned by that interface 945 * because the usage_count of pm runtime is more than 1. 946 */ 947 if (!pm_runtime_suspended(dev)) 948 return fimd_activate(mgr, false); 949 950 return 0; 951 } 952 953 static int fimd_resume(struct device *dev) 954 { 955 struct exynos_drm_manager *mgr = get_fimd_manager(dev); 956 957 /* 958 * if entered to sleep when lcd panel was on, the usage_count 959 * of pm runtime would still be 1 so in this case, fimd driver 960 * should be on directly not drawing on pm runtime interface. 961 */ 962 if (pm_runtime_suspended(dev)) 963 return 0; 964 965 return fimd_activate(mgr, true); 966 } 967 #endif 968 969 #ifdef CONFIG_PM_RUNTIME 970 static int fimd_runtime_suspend(struct device *dev) 971 { 972 struct exynos_drm_manager *mgr = get_fimd_manager(dev); 973 974 return fimd_activate(mgr, false); 975 } 976 977 static int fimd_runtime_resume(struct device *dev) 978 { 979 struct exynos_drm_manager *mgr = get_fimd_manager(dev); 980 981 return fimd_activate(mgr, true); 982 } 983 #endif 984 985 static const struct dev_pm_ops fimd_pm_ops = { 986 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) 987 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) 988 }; 989 990 struct platform_driver fimd_driver = { 991 .probe = fimd_probe, 992 .remove = fimd_remove, 993 .driver = { 994 .name = "exynos4-fb", 995 .owner = THIS_MODULE, 996 .pm = &fimd_pm_ops, 997 .of_match_table = fimd_driver_dt_match, 998 }, 999 }; 1000