11c248b7dSInki Dae /* exynos_drm_fimd.c 21c248b7dSInki Dae * 31c248b7dSInki Dae * Copyright (C) 2011 Samsung Electronics Co.Ltd 41c248b7dSInki Dae * Authors: 51c248b7dSInki Dae * Joonyoung Shim <jy0922.shim@samsung.com> 61c248b7dSInki Dae * Inki Dae <inki.dae@samsung.com> 71c248b7dSInki Dae * 81c248b7dSInki Dae * This program is free software; you can redistribute it and/or modify it 91c248b7dSInki Dae * under the terms of the GNU General Public License as published by the 101c248b7dSInki Dae * Free Software Foundation; either version 2 of the License, or (at your 111c248b7dSInki Dae * option) any later version. 121c248b7dSInki Dae * 131c248b7dSInki Dae */ 14760285e7SDavid Howells #include <drm/drmP.h> 151c248b7dSInki Dae 161c248b7dSInki Dae #include <linux/kernel.h> 171c248b7dSInki Dae #include <linux/platform_device.h> 181c248b7dSInki Dae #include <linux/clk.h> 193f1c781dSSachin Kamat #include <linux/of.h> 20d636ead8SJoonyoung Shim #include <linux/of_device.h> 21cb91f6a0SJoonyoung Shim #include <linux/pm_runtime.h> 22f37cd5e8SInki Dae #include <linux/component.h> 233854fab2SYoungJun Cho #include <linux/mfd/syscon.h> 243854fab2SYoungJun Cho #include <linux/regmap.h> 251c248b7dSInki Dae 267f4596f4SVikas Sajjan #include <video/of_display_timing.h> 27111e6055SAndrzej Hajda #include <video/of_videomode.h> 285a213a55SLeela Krishna Amudala #include <video/samsung_fimd.h> 291c248b7dSInki Dae #include <drm/exynos_drm.h> 301c248b7dSInki Dae 311c248b7dSInki Dae #include "exynos_drm_drv.h" 321c248b7dSInki Dae #include "exynos_drm_fbdev.h" 331c248b7dSInki Dae #include "exynos_drm_crtc.h" 347ee14cdcSGustavo Padovan #include "exynos_drm_plane.h" 35bcc5cd1cSInki Dae #include "exynos_drm_iommu.h" 361c248b7dSInki Dae 371c248b7dSInki Dae /* 38b8654b37SSachin Kamat * FIMD stands for Fully Interactive Mobile Display and 391c248b7dSInki Dae * as a display controller, it transfers contents drawn on memory 401c248b7dSInki Dae * to a LCD Panel through Display Interfaces such as RGB or 411c248b7dSInki Dae * CPU Interface. 421c248b7dSInki Dae */ 431c248b7dSInki Dae 44111e6055SAndrzej Hajda #define FIMD_DEFAULT_FRAMERATE 60 4566367461SRahul Sharma #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 46111e6055SAndrzej Hajda 471c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/ 481c248b7dSInki Dae #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 491c248b7dSInki Dae #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 500f10cf14SLeela Krishna Amudala /* 510f10cf14SLeela Krishna Amudala * size control register for hardware windows 0 and alpha control register 520f10cf14SLeela Krishna Amudala * for hardware windows 1 ~ 4 530f10cf14SLeela Krishna Amudala */ 540f10cf14SLeela Krishna Amudala #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 550f10cf14SLeela Krishna Amudala /* size control register for hardware windows 1 ~ 2. */ 561c248b7dSInki Dae #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 571c248b7dSInki Dae 58453b44a3SGustavo Padovan #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 59453b44a3SGustavo Padovan #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 60453b44a3SGustavo Padovan 611c248b7dSInki Dae #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 621c248b7dSInki Dae #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 631c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 641c248b7dSInki Dae 651c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */ 660f10cf14SLeela Krishna Amudala #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 671c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */ 680f10cf14SLeela Krishna Amudala #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 691c248b7dSInki Dae 703854fab2SYoungJun Cho /* I80 / RGB trigger control register */ 713854fab2SYoungJun Cho #define TRIGCON 0x1A4 723854fab2SYoungJun Cho #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 733854fab2SYoungJun Cho #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 743854fab2SYoungJun Cho 753854fab2SYoungJun Cho /* display mode change control register except exynos4 */ 763854fab2SYoungJun Cho #define VIDOUT_CON 0x000 773854fab2SYoungJun Cho #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 783854fab2SYoungJun Cho 793854fab2SYoungJun Cho /* I80 interface control for main LDI register */ 803854fab2SYoungJun Cho #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 813854fab2SYoungJun Cho #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 823854fab2SYoungJun Cho #define LCD_CS_SETUP(x) ((x) << 16) 833854fab2SYoungJun Cho #define LCD_WR_SETUP(x) ((x) << 12) 843854fab2SYoungJun Cho #define LCD_WR_ACTIVE(x) ((x) << 8) 853854fab2SYoungJun Cho #define LCD_WR_HOLD(x) ((x) << 4) 863854fab2SYoungJun Cho #define I80IFEN_ENABLE (1 << 0) 873854fab2SYoungJun Cho 881c248b7dSInki Dae /* FIMD has totally five hardware windows. */ 891c248b7dSInki Dae #define WINDOWS_NR 5 901c248b7dSInki Dae 91e2e13389SLeela Krishna Amudala struct fimd_driver_data { 92e2e13389SLeela Krishna Amudala unsigned int timing_base; 933854fab2SYoungJun Cho unsigned int lcdblk_offset; 943854fab2SYoungJun Cho unsigned int lcdblk_vt_shift; 953854fab2SYoungJun Cho unsigned int lcdblk_bypass_shift; 96de7af100STomasz Figa 97de7af100STomasz Figa unsigned int has_shadowcon:1; 98411d9ed4STomasz Figa unsigned int has_clksel:1; 995cc4621aSInki Dae unsigned int has_limited_fmt:1; 1003854fab2SYoungJun Cho unsigned int has_vidoutcon:1; 1013c3c9c1dSJoonyoung Shim unsigned int has_vtsel:1; 102e2e13389SLeela Krishna Amudala }; 103e2e13389SLeela Krishna Amudala 104725ddeadSTomasz Figa static struct fimd_driver_data s3c64xx_fimd_driver_data = { 105725ddeadSTomasz Figa .timing_base = 0x0, 106725ddeadSTomasz Figa .has_clksel = 1, 1075cc4621aSInki Dae .has_limited_fmt = 1, 108725ddeadSTomasz Figa }; 109725ddeadSTomasz Figa 110d6ce7b58SInki Dae static struct fimd_driver_data exynos3_fimd_driver_data = { 111d6ce7b58SInki Dae .timing_base = 0x20000, 112d6ce7b58SInki Dae .lcdblk_offset = 0x210, 113d6ce7b58SInki Dae .lcdblk_bypass_shift = 1, 114d6ce7b58SInki Dae .has_shadowcon = 1, 115d6ce7b58SInki Dae .has_vidoutcon = 1, 116d6ce7b58SInki Dae }; 117d6ce7b58SInki Dae 1186ecf18f9SSachin Kamat static struct fimd_driver_data exynos4_fimd_driver_data = { 119e2e13389SLeela Krishna Amudala .timing_base = 0x0, 1203854fab2SYoungJun Cho .lcdblk_offset = 0x210, 1213854fab2SYoungJun Cho .lcdblk_vt_shift = 10, 1223854fab2SYoungJun Cho .lcdblk_bypass_shift = 1, 123de7af100STomasz Figa .has_shadowcon = 1, 1243c3c9c1dSJoonyoung Shim .has_vtsel = 1, 125e2e13389SLeela Krishna Amudala }; 126e2e13389SLeela Krishna Amudala 127dcb622aaSYoungJun Cho static struct fimd_driver_data exynos4415_fimd_driver_data = { 128dcb622aaSYoungJun Cho .timing_base = 0x20000, 129dcb622aaSYoungJun Cho .lcdblk_offset = 0x210, 130dcb622aaSYoungJun Cho .lcdblk_vt_shift = 10, 131dcb622aaSYoungJun Cho .lcdblk_bypass_shift = 1, 132dcb622aaSYoungJun Cho .has_shadowcon = 1, 133dcb622aaSYoungJun Cho .has_vidoutcon = 1, 1343c3c9c1dSJoonyoung Shim .has_vtsel = 1, 135dcb622aaSYoungJun Cho }; 136dcb622aaSYoungJun Cho 1376ecf18f9SSachin Kamat static struct fimd_driver_data exynos5_fimd_driver_data = { 138e2e13389SLeela Krishna Amudala .timing_base = 0x20000, 1393854fab2SYoungJun Cho .lcdblk_offset = 0x214, 1403854fab2SYoungJun Cho .lcdblk_vt_shift = 24, 1413854fab2SYoungJun Cho .lcdblk_bypass_shift = 15, 142de7af100STomasz Figa .has_shadowcon = 1, 1433854fab2SYoungJun Cho .has_vidoutcon = 1, 1443c3c9c1dSJoonyoung Shim .has_vtsel = 1, 145e2e13389SLeela Krishna Amudala }; 146e2e13389SLeela Krishna Amudala 1471c248b7dSInki Dae struct fimd_context { 148bb7704d6SSean Paul struct device *dev; 14940c8ab4bSSean Paul struct drm_device *drm_dev; 15093bca243SGustavo Padovan struct exynos_drm_crtc *crtc; 1517ee14cdcSGustavo Padovan struct exynos_drm_plane planes[WINDOWS_NR]; 1521c248b7dSInki Dae struct clk *bus_clk; 1531c248b7dSInki Dae struct clk *lcd_clk; 1541c248b7dSInki Dae void __iomem *regs; 1553854fab2SYoungJun Cho struct regmap *sysreg; 1561c248b7dSInki Dae unsigned int default_win; 1571c248b7dSInki Dae unsigned long irq_flags; 1583854fab2SYoungJun Cho u32 vidcon0; 1591c248b7dSInki Dae u32 vidcon1; 1603854fab2SYoungJun Cho u32 vidout_con; 1613854fab2SYoungJun Cho u32 i80ifcon; 1623854fab2SYoungJun Cho bool i80_if; 163cb91f6a0SJoonyoung Shim bool suspended; 164080be03dSSean Paul int pipe; 16501ce113cSPrathyush K wait_queue_head_t wait_vsync_queue; 16601ce113cSPrathyush K atomic_t wait_vsync_event; 1673854fab2SYoungJun Cho atomic_t win_updated; 1683854fab2SYoungJun Cho atomic_t triggering; 1691c248b7dSInki Dae 170562ad9f4SAndrzej Hajda struct exynos_drm_panel_info panel; 17118873465STomasz Figa struct fimd_driver_data *driver_data; 172000cc920SAndrzej Hajda struct exynos_drm_display *display; 1731c248b7dSInki Dae }; 1741c248b7dSInki Dae 175d636ead8SJoonyoung Shim static const struct of_device_id fimd_driver_dt_match[] = { 176725ddeadSTomasz Figa { .compatible = "samsung,s3c6400-fimd", 177725ddeadSTomasz Figa .data = &s3c64xx_fimd_driver_data }, 178d6ce7b58SInki Dae { .compatible = "samsung,exynos3250-fimd", 179d6ce7b58SInki Dae .data = &exynos3_fimd_driver_data }, 1805830daf8SVikas Sajjan { .compatible = "samsung,exynos4210-fimd", 181d636ead8SJoonyoung Shim .data = &exynos4_fimd_driver_data }, 182dcb622aaSYoungJun Cho { .compatible = "samsung,exynos4415-fimd", 183dcb622aaSYoungJun Cho .data = &exynos4415_fimd_driver_data }, 1845830daf8SVikas Sajjan { .compatible = "samsung,exynos5250-fimd", 185d636ead8SJoonyoung Shim .data = &exynos5_fimd_driver_data }, 186d636ead8SJoonyoung Shim {}, 187d636ead8SJoonyoung Shim }; 1880262ceebSSjoerd Simons MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 189d636ead8SJoonyoung Shim 190e2e13389SLeela Krishna Amudala static inline struct fimd_driver_data *drm_fimd_get_driver_data( 191e2e13389SLeela Krishna Amudala struct platform_device *pdev) 192e2e13389SLeela Krishna Amudala { 193d636ead8SJoonyoung Shim const struct of_device_id *of_id = 194d636ead8SJoonyoung Shim of_match_device(fimd_driver_dt_match, &pdev->dev); 195d636ead8SJoonyoung Shim 196d636ead8SJoonyoung Shim return (struct fimd_driver_data *)of_id->data; 197e2e13389SLeela Krishna Amudala } 198e2e13389SLeela Krishna Amudala 19993bca243SGustavo Padovan static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 200f13bdbd1SAkshu Agrawal { 20193bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 202f13bdbd1SAkshu Agrawal 203f13bdbd1SAkshu Agrawal if (ctx->suspended) 204f13bdbd1SAkshu Agrawal return; 205f13bdbd1SAkshu Agrawal 206f13bdbd1SAkshu Agrawal atomic_set(&ctx->wait_vsync_event, 1); 207f13bdbd1SAkshu Agrawal 208f13bdbd1SAkshu Agrawal /* 209f13bdbd1SAkshu Agrawal * wait for FIMD to signal VSYNC interrupt or return after 210f13bdbd1SAkshu Agrawal * timeout which is set to 50ms (refresh rate of 20). 211f13bdbd1SAkshu Agrawal */ 212f13bdbd1SAkshu Agrawal if (!wait_event_timeout(ctx->wait_vsync_queue, 213f13bdbd1SAkshu Agrawal !atomic_read(&ctx->wait_vsync_event), 214f13bdbd1SAkshu Agrawal HZ/20)) 215f13bdbd1SAkshu Agrawal DRM_DEBUG_KMS("vblank wait timed out.\n"); 216f13bdbd1SAkshu Agrawal } 217f13bdbd1SAkshu Agrawal 218f181a543SYoungJun Cho static void fimd_enable_video_output(struct fimd_context *ctx, int win, 219f181a543SYoungJun Cho bool enable) 220f181a543SYoungJun Cho { 221f181a543SYoungJun Cho u32 val = readl(ctx->regs + WINCON(win)); 222f181a543SYoungJun Cho 223f181a543SYoungJun Cho if (enable) 224f181a543SYoungJun Cho val |= WINCONx_ENWIN; 225f181a543SYoungJun Cho else 226f181a543SYoungJun Cho val &= ~WINCONx_ENWIN; 227f181a543SYoungJun Cho 228f181a543SYoungJun Cho writel(val, ctx->regs + WINCON(win)); 229f181a543SYoungJun Cho } 230f181a543SYoungJun Cho 231999d8b31SYoungJun Cho static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win, 232999d8b31SYoungJun Cho bool enable) 233999d8b31SYoungJun Cho { 234999d8b31SYoungJun Cho u32 val = readl(ctx->regs + SHADOWCON); 235999d8b31SYoungJun Cho 236999d8b31SYoungJun Cho if (enable) 237999d8b31SYoungJun Cho val |= SHADOWCON_CHx_ENABLE(win); 238999d8b31SYoungJun Cho else 239999d8b31SYoungJun Cho val &= ~SHADOWCON_CHx_ENABLE(win); 240999d8b31SYoungJun Cho 241999d8b31SYoungJun Cho writel(val, ctx->regs + SHADOWCON); 242999d8b31SYoungJun Cho } 243999d8b31SYoungJun Cho 24492dc7a04SJoonyoung Shim static void fimd_clear_channel(struct fimd_context *ctx) 245f13bdbd1SAkshu Agrawal { 246f13bdbd1SAkshu Agrawal int win, ch_enabled = 0; 247f13bdbd1SAkshu Agrawal 248f13bdbd1SAkshu Agrawal DRM_DEBUG_KMS("%s\n", __FILE__); 249f13bdbd1SAkshu Agrawal 250f13bdbd1SAkshu Agrawal /* Check if any channel is enabled. */ 251f13bdbd1SAkshu Agrawal for (win = 0; win < WINDOWS_NR; win++) { 252eb8a3bf7SMarek Szyprowski u32 val = readl(ctx->regs + WINCON(win)); 253eb8a3bf7SMarek Szyprowski 254eb8a3bf7SMarek Szyprowski if (val & WINCONx_ENWIN) { 255f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false); 256eb8a3bf7SMarek Szyprowski 257999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 258999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, 259999d8b31SYoungJun Cho false); 260999d8b31SYoungJun Cho 261f13bdbd1SAkshu Agrawal ch_enabled = 1; 262f13bdbd1SAkshu Agrawal } 263f13bdbd1SAkshu Agrawal } 264f13bdbd1SAkshu Agrawal 265f13bdbd1SAkshu Agrawal /* Wait for vsync, as disable channel takes effect at next vsync */ 266eb8a3bf7SMarek Szyprowski if (ch_enabled) { 267eb8a3bf7SMarek Szyprowski unsigned int state = ctx->suspended; 268eb8a3bf7SMarek Szyprowski 269eb8a3bf7SMarek Szyprowski ctx->suspended = 0; 27092dc7a04SJoonyoung Shim fimd_wait_for_vblank(ctx->crtc); 271eb8a3bf7SMarek Szyprowski ctx->suspended = state; 272eb8a3bf7SMarek Szyprowski } 273f13bdbd1SAkshu Agrawal } 274f13bdbd1SAkshu Agrawal 275cdbfca89SHyungwon Hwang static int fimd_iommu_attach_devices(struct fimd_context *ctx, 276f37cd5e8SInki Dae struct drm_device *drm_dev) 27740c8ab4bSSean Paul { 278080be03dSSean Paul 279080be03dSSean Paul /* attach this sub driver to iommu mapping if supported. */ 280f13bdbd1SAkshu Agrawal if (is_drm_iommu_supported(ctx->drm_dev)) { 281efa75bcdSAjay Kumar int ret; 282efa75bcdSAjay Kumar 283f13bdbd1SAkshu Agrawal /* 284f13bdbd1SAkshu Agrawal * If any channel is already active, iommu will throw 285f13bdbd1SAkshu Agrawal * a PAGE FAULT when enabled. So clear any channel if enabled. 286f13bdbd1SAkshu Agrawal */ 28792dc7a04SJoonyoung Shim fimd_clear_channel(ctx); 288efa75bcdSAjay Kumar ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev); 289efa75bcdSAjay Kumar if (ret) { 290efa75bcdSAjay Kumar DRM_ERROR("drm_iommu_attach failed.\n"); 291efa75bcdSAjay Kumar return ret; 292efa75bcdSAjay Kumar } 293efa75bcdSAjay Kumar 294f13bdbd1SAkshu Agrawal } 29540c8ab4bSSean Paul 29640c8ab4bSSean Paul return 0; 29740c8ab4bSSean Paul } 29840c8ab4bSSean Paul 299cdbfca89SHyungwon Hwang static void fimd_iommu_detach_devices(struct fimd_context *ctx) 300ec05da95SInki Dae { 301080be03dSSean Paul /* detach this sub driver from iommu mapping if supported. */ 302080be03dSSean Paul if (is_drm_iommu_supported(ctx->drm_dev)) 303080be03dSSean Paul drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 304ec05da95SInki Dae } 305ec05da95SInki Dae 306a968e727SSean Paul static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 307a968e727SSean Paul const struct drm_display_mode *mode) 308a968e727SSean Paul { 309a968e727SSean Paul unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 310a968e727SSean Paul u32 clkdiv; 311a968e727SSean Paul 3123854fab2SYoungJun Cho if (ctx->i80_if) { 3133854fab2SYoungJun Cho /* 3143854fab2SYoungJun Cho * The frame done interrupt should be occurred prior to the 3153854fab2SYoungJun Cho * next TE signal. 3163854fab2SYoungJun Cho */ 3173854fab2SYoungJun Cho ideal_clk *= 2; 3183854fab2SYoungJun Cho } 3193854fab2SYoungJun Cho 320a968e727SSean Paul /* Find the clock divider value that gets us closest to ideal_clk */ 321a968e727SSean Paul clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 322a968e727SSean Paul 323a968e727SSean Paul return (clkdiv < 0x100) ? clkdiv : 0xff; 324a968e727SSean Paul } 325a968e727SSean Paul 32693bca243SGustavo Padovan static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, 327a968e727SSean Paul const struct drm_display_mode *mode, 328a968e727SSean Paul struct drm_display_mode *adjusted_mode) 329a968e727SSean Paul { 330a968e727SSean Paul if (adjusted_mode->vrefresh == 0) 331a968e727SSean Paul adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 332a968e727SSean Paul 333a968e727SSean Paul return true; 334a968e727SSean Paul } 335a968e727SSean Paul 33693bca243SGustavo Padovan static void fimd_commit(struct exynos_drm_crtc *crtc) 3371c248b7dSInki Dae { 33893bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 339a8dc5ed6SGustavo Padovan struct drm_display_mode *mode = &crtc->base.mode; 3403854fab2SYoungJun Cho struct fimd_driver_data *driver_data = ctx->driver_data; 3413854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base; 3423854fab2SYoungJun Cho u32 val, clkdiv; 3431c248b7dSInki Dae 344e30d4bcfSInki Dae if (ctx->suspended) 345e30d4bcfSInki Dae return; 346e30d4bcfSInki Dae 347a968e727SSean Paul /* nothing to do if we haven't set the mode yet */ 348a968e727SSean Paul if (mode->htotal == 0 || mode->vtotal == 0) 349a968e727SSean Paul return; 350a968e727SSean Paul 3513854fab2SYoungJun Cho if (ctx->i80_if) { 3523854fab2SYoungJun Cho val = ctx->i80ifcon | I80IFEN_ENABLE; 3533854fab2SYoungJun Cho writel(val, timing_base + I80IFCONFAx(0)); 3543854fab2SYoungJun Cho 3553854fab2SYoungJun Cho /* disable auto frame rate */ 3563854fab2SYoungJun Cho writel(0, timing_base + I80IFCONFBx(0)); 3573854fab2SYoungJun Cho 3583854fab2SYoungJun Cho /* set video type selection to I80 interface */ 3593c3c9c1dSJoonyoung Shim if (driver_data->has_vtsel && ctx->sysreg && 3603c3c9c1dSJoonyoung Shim regmap_update_bits(ctx->sysreg, 3613854fab2SYoungJun Cho driver_data->lcdblk_offset, 3623854fab2SYoungJun Cho 0x3 << driver_data->lcdblk_vt_shift, 3633854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_vt_shift)) { 3643854fab2SYoungJun Cho DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 3653854fab2SYoungJun Cho return; 3663854fab2SYoungJun Cho } 3673854fab2SYoungJun Cho } else { 3683854fab2SYoungJun Cho int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 3693854fab2SYoungJun Cho u32 vidcon1; 3703854fab2SYoungJun Cho 3711417f109SSean Paul /* setup polarity values */ 3721417f109SSean Paul vidcon1 = ctx->vidcon1; 3731417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NVSYNC) 3741417f109SSean Paul vidcon1 |= VIDCON1_INV_VSYNC; 3751417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NHSYNC) 3761417f109SSean Paul vidcon1 |= VIDCON1_INV_HSYNC; 3771417f109SSean Paul writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 3781c248b7dSInki Dae 3791c248b7dSInki Dae /* setup vertical timing values. */ 380a968e727SSean Paul vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 3818b4cad23SAndrzej Hajda vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 3828b4cad23SAndrzej Hajda vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 383a968e727SSean Paul 384a968e727SSean Paul val = VIDTCON0_VBPD(vbpd - 1) | 385a968e727SSean Paul VIDTCON0_VFPD(vfpd - 1) | 386a968e727SSean Paul VIDTCON0_VSPW(vsync_len - 1); 387e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 3881c248b7dSInki Dae 3891c248b7dSInki Dae /* setup horizontal timing values. */ 390a968e727SSean Paul hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 3918b4cad23SAndrzej Hajda hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 3928b4cad23SAndrzej Hajda hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 393a968e727SSean Paul 394a968e727SSean Paul val = VIDTCON1_HBPD(hbpd - 1) | 395a968e727SSean Paul VIDTCON1_HFPD(hfpd - 1) | 396a968e727SSean Paul VIDTCON1_HSPW(hsync_len - 1); 397e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 3983854fab2SYoungJun Cho } 3993854fab2SYoungJun Cho 4003854fab2SYoungJun Cho if (driver_data->has_vidoutcon) 4013854fab2SYoungJun Cho writel(ctx->vidout_con, timing_base + VIDOUT_CON); 4023854fab2SYoungJun Cho 4033854fab2SYoungJun Cho /* set bypass selection */ 4043854fab2SYoungJun Cho if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 4053854fab2SYoungJun Cho driver_data->lcdblk_offset, 4063854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift, 4073854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift)) { 4083854fab2SYoungJun Cho DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 4093854fab2SYoungJun Cho return; 4103854fab2SYoungJun Cho } 4111c248b7dSInki Dae 4121c248b7dSInki Dae /* setup horizontal and vertical display size. */ 413a968e727SSean Paul val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 414a968e727SSean Paul VIDTCON2_HOZVAL(mode->hdisplay - 1) | 415a968e727SSean Paul VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 416a968e727SSean Paul VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 417e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 4181c248b7dSInki Dae 4191c248b7dSInki Dae /* 4201c248b7dSInki Dae * fields of register with prefix '_F' would be updated 4211c248b7dSInki Dae * at vsync(same as dma start) 4221c248b7dSInki Dae */ 4233854fab2SYoungJun Cho val = ctx->vidcon0; 4243854fab2SYoungJun Cho val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 4251d531062SAndrzej Hajda 4261d531062SAndrzej Hajda if (ctx->driver_data->has_clksel) 4271d531062SAndrzej Hajda val |= VIDCON0_CLKSEL_LCD; 4281d531062SAndrzej Hajda 4291d531062SAndrzej Hajda clkdiv = fimd_calc_clkdiv(ctx, mode); 4301d531062SAndrzej Hajda if (clkdiv > 1) 4311d531062SAndrzej Hajda val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 4321d531062SAndrzej Hajda 4331c248b7dSInki Dae writel(val, ctx->regs + VIDCON0); 4341c248b7dSInki Dae } 4351c248b7dSInki Dae 43693bca243SGustavo Padovan static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 4371c248b7dSInki Dae { 43893bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 4391c248b7dSInki Dae u32 val; 4401c248b7dSInki Dae 441cb91f6a0SJoonyoung Shim if (ctx->suspended) 442cb91f6a0SJoonyoung Shim return -EPERM; 443cb91f6a0SJoonyoung Shim 4441c248b7dSInki Dae if (!test_and_set_bit(0, &ctx->irq_flags)) { 4451c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON0); 4461c248b7dSInki Dae 4471c248b7dSInki Dae val |= VIDINTCON0_INT_ENABLE; 4481c905d95SYoungJun Cho 4491c905d95SYoungJun Cho if (ctx->i80_if) { 4501c905d95SYoungJun Cho val |= VIDINTCON0_INT_I80IFDONE; 4511c905d95SYoungJun Cho val |= VIDINTCON0_INT_SYSMAINCON; 4521c905d95SYoungJun Cho val &= ~VIDINTCON0_INT_SYSSUBCON; 4531c905d95SYoungJun Cho } else { 4541c248b7dSInki Dae val |= VIDINTCON0_INT_FRAME; 4551c248b7dSInki Dae 4561c248b7dSInki Dae val &= ~VIDINTCON0_FRAMESEL0_MASK; 4571c248b7dSInki Dae val |= VIDINTCON0_FRAMESEL0_VSYNC; 4581c248b7dSInki Dae val &= ~VIDINTCON0_FRAMESEL1_MASK; 4591c248b7dSInki Dae val |= VIDINTCON0_FRAMESEL1_NONE; 4601c905d95SYoungJun Cho } 4611c248b7dSInki Dae 4621c248b7dSInki Dae writel(val, ctx->regs + VIDINTCON0); 4631c248b7dSInki Dae } 4641c248b7dSInki Dae 4651c248b7dSInki Dae return 0; 4661c248b7dSInki Dae } 4671c248b7dSInki Dae 46893bca243SGustavo Padovan static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 4691c248b7dSInki Dae { 47093bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 4711c248b7dSInki Dae u32 val; 4721c248b7dSInki Dae 473cb91f6a0SJoonyoung Shim if (ctx->suspended) 474cb91f6a0SJoonyoung Shim return; 475cb91f6a0SJoonyoung Shim 4761c248b7dSInki Dae if (test_and_clear_bit(0, &ctx->irq_flags)) { 4771c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON0); 4781c248b7dSInki Dae 4791c248b7dSInki Dae val &= ~VIDINTCON0_INT_ENABLE; 4801c248b7dSInki Dae 4811c905d95SYoungJun Cho if (ctx->i80_if) { 4821c905d95SYoungJun Cho val &= ~VIDINTCON0_INT_I80IFDONE; 4831c905d95SYoungJun Cho val &= ~VIDINTCON0_INT_SYSMAINCON; 4841c905d95SYoungJun Cho val &= ~VIDINTCON0_INT_SYSSUBCON; 4851c905d95SYoungJun Cho } else 4861c905d95SYoungJun Cho val &= ~VIDINTCON0_INT_FRAME; 4871c905d95SYoungJun Cho 4881c248b7dSInki Dae writel(val, ctx->regs + VIDINTCON0); 4891c248b7dSInki Dae } 4901c248b7dSInki Dae } 4911c248b7dSInki Dae 492bb7704d6SSean Paul static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) 4931c248b7dSInki Dae { 4947ee14cdcSGustavo Padovan struct exynos_drm_plane *plane = &ctx->planes[win]; 4951c248b7dSInki Dae unsigned long val; 4961c248b7dSInki Dae 4971c248b7dSInki Dae val = WINCONx_ENWIN; 4981c248b7dSInki Dae 4995cc4621aSInki Dae /* 5005cc4621aSInki Dae * In case of s3c64xx, window 0 doesn't support alpha channel. 5015cc4621aSInki Dae * So the request format is ARGB8888 then change it to XRGB8888. 5025cc4621aSInki Dae */ 5035cc4621aSInki Dae if (ctx->driver_data->has_limited_fmt && !win) { 5047ee14cdcSGustavo Padovan if (plane->pixel_format == DRM_FORMAT_ARGB8888) 5057ee14cdcSGustavo Padovan plane->pixel_format = DRM_FORMAT_XRGB8888; 5065cc4621aSInki Dae } 5075cc4621aSInki Dae 5087ee14cdcSGustavo Padovan switch (plane->pixel_format) { 509a4f38a80SInki Dae case DRM_FORMAT_C8: 5101c248b7dSInki Dae val |= WINCON0_BPPMODE_8BPP_PALETTE; 5111c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 5121c248b7dSInki Dae val |= WINCONx_BYTSWP; 5131c248b7dSInki Dae break; 514a4f38a80SInki Dae case DRM_FORMAT_XRGB1555: 515a4f38a80SInki Dae val |= WINCON0_BPPMODE_16BPP_1555; 516a4f38a80SInki Dae val |= WINCONx_HAWSWP; 517a4f38a80SInki Dae val |= WINCONx_BURSTLEN_16WORD; 518a4f38a80SInki Dae break; 519a4f38a80SInki Dae case DRM_FORMAT_RGB565: 5201c248b7dSInki Dae val |= WINCON0_BPPMODE_16BPP_565; 5211c248b7dSInki Dae val |= WINCONx_HAWSWP; 5221c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5231c248b7dSInki Dae break; 524a4f38a80SInki Dae case DRM_FORMAT_XRGB8888: 5251c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 5261c248b7dSInki Dae val |= WINCONx_WSWP; 5271c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5281c248b7dSInki Dae break; 529a4f38a80SInki Dae case DRM_FORMAT_ARGB8888: 530a4f38a80SInki Dae val |= WINCON1_BPPMODE_25BPP_A1888 5311c248b7dSInki Dae | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 5321c248b7dSInki Dae val |= WINCONx_WSWP; 5331c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5341c248b7dSInki Dae break; 5351c248b7dSInki Dae default: 5361c248b7dSInki Dae DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 5371c248b7dSInki Dae 5381c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 5391c248b7dSInki Dae val |= WINCONx_WSWP; 5401c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5411c248b7dSInki Dae break; 5421c248b7dSInki Dae } 5431c248b7dSInki Dae 5447ee14cdcSGustavo Padovan DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); 5451c248b7dSInki Dae 54666367461SRahul Sharma /* 54766367461SRahul Sharma * In case of exynos, setting dma-burst to 16Word causes permanent 54866367461SRahul Sharma * tearing for very small buffers, e.g. cursor buffer. Burst Mode 5498837deeaSGustavo Padovan * switching which is based on plane size is not recommended as 5508837deeaSGustavo Padovan * plane size varies alot towards the end of the screen and rapid 55166367461SRahul Sharma * movement causes unstable DMA which results into iommu crash/tear. 55266367461SRahul Sharma */ 55366367461SRahul Sharma 5547ee14cdcSGustavo Padovan if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 55566367461SRahul Sharma val &= ~WINCONx_BURSTLEN_MASK; 55666367461SRahul Sharma val |= WINCONx_BURSTLEN_4WORD; 55766367461SRahul Sharma } 55866367461SRahul Sharma 5591c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 560453b44a3SGustavo Padovan 561453b44a3SGustavo Padovan /* hardware window 0 doesn't support alpha channel. */ 562453b44a3SGustavo Padovan if (win != 0) { 563453b44a3SGustavo Padovan /* OSD alpha */ 564453b44a3SGustavo Padovan val = VIDISD14C_ALPHA0_R(0xf) | 565453b44a3SGustavo Padovan VIDISD14C_ALPHA0_G(0xf) | 566453b44a3SGustavo Padovan VIDISD14C_ALPHA0_B(0xf) | 567453b44a3SGustavo Padovan VIDISD14C_ALPHA1_R(0xf) | 568453b44a3SGustavo Padovan VIDISD14C_ALPHA1_G(0xf) | 569453b44a3SGustavo Padovan VIDISD14C_ALPHA1_B(0xf); 570453b44a3SGustavo Padovan 571453b44a3SGustavo Padovan writel(val, ctx->regs + VIDOSD_C(win)); 572453b44a3SGustavo Padovan 573453b44a3SGustavo Padovan val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | 574453b44a3SGustavo Padovan VIDW_ALPHA_G(0xf); 575453b44a3SGustavo Padovan writel(val, ctx->regs + VIDWnALPHA0(win)); 576453b44a3SGustavo Padovan writel(val, ctx->regs + VIDWnALPHA1(win)); 577453b44a3SGustavo Padovan } 5781c248b7dSInki Dae } 5791c248b7dSInki Dae 580bb7704d6SSean Paul static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 5811c248b7dSInki Dae { 5821c248b7dSInki Dae unsigned int keycon0 = 0, keycon1 = 0; 5831c248b7dSInki Dae 5841c248b7dSInki Dae keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 5851c248b7dSInki Dae WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 5861c248b7dSInki Dae 5871c248b7dSInki Dae keycon1 = WxKEYCON1_COLVAL(0xffffffff); 5881c248b7dSInki Dae 5891c248b7dSInki Dae writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 5901c248b7dSInki Dae writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 5911c248b7dSInki Dae } 5921c248b7dSInki Dae 593de7af100STomasz Figa /** 594de7af100STomasz Figa * shadow_protect_win() - disable updating values from shadow registers at vsync 595de7af100STomasz Figa * 596de7af100STomasz Figa * @win: window to protect registers for 597de7af100STomasz Figa * @protect: 1 to protect (disable updates) 598de7af100STomasz Figa */ 599de7af100STomasz Figa static void fimd_shadow_protect_win(struct fimd_context *ctx, 6006e2a3b66SGustavo Padovan unsigned int win, bool protect) 601de7af100STomasz Figa { 602de7af100STomasz Figa u32 reg, bits, val; 603de7af100STomasz Figa 604de7af100STomasz Figa if (ctx->driver_data->has_shadowcon) { 605de7af100STomasz Figa reg = SHADOWCON; 606de7af100STomasz Figa bits = SHADOWCON_WINx_PROTECT(win); 607de7af100STomasz Figa } else { 608de7af100STomasz Figa reg = PRTCON; 609de7af100STomasz Figa bits = PRTCON_PROTECT; 610de7af100STomasz Figa } 611de7af100STomasz Figa 612de7af100STomasz Figa val = readl(ctx->regs + reg); 613de7af100STomasz Figa if (protect) 614de7af100STomasz Figa val |= bits; 615de7af100STomasz Figa else 616de7af100STomasz Figa val &= ~bits; 617de7af100STomasz Figa writel(val, ctx->regs + reg); 618de7af100STomasz Figa } 619de7af100STomasz Figa 6206e2a3b66SGustavo Padovan static void fimd_win_commit(struct exynos_drm_crtc *crtc, unsigned int win) 6211c248b7dSInki Dae { 62293bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 6237ee14cdcSGustavo Padovan struct exynos_drm_plane *plane; 6247ee14cdcSGustavo Padovan dma_addr_t dma_addr; 6257ee14cdcSGustavo Padovan unsigned long val, size, offset; 6267ee14cdcSGustavo Padovan unsigned int last_x, last_y, buf_offsize, line_size; 6271c248b7dSInki Dae 628e30d4bcfSInki Dae if (ctx->suspended) 629e30d4bcfSInki Dae return; 630e30d4bcfSInki Dae 63137b006e8SKrzysztof Kozlowski if (win < 0 || win >= WINDOWS_NR) 6321c248b7dSInki Dae return; 6331c248b7dSInki Dae 6347ee14cdcSGustavo Padovan plane = &ctx->planes[win]; 6351c248b7dSInki Dae 636a43b933bSSean Paul /* If suspended, enable this on resume */ 637a43b933bSSean Paul if (ctx->suspended) { 6387ee14cdcSGustavo Padovan plane->resume = true; 639a43b933bSSean Paul return; 640a43b933bSSean Paul } 641a43b933bSSean Paul 6421c248b7dSInki Dae /* 643de7af100STomasz Figa * SHADOWCON/PRTCON register is used for enabling timing. 6441c248b7dSInki Dae * 6451c248b7dSInki Dae * for example, once only width value of a register is set, 6461c248b7dSInki Dae * if the dma is started then fimd hardware could malfunction so 6471c248b7dSInki Dae * with protect window setting, the register fields with prefix '_F' 6481c248b7dSInki Dae * wouldn't be updated at vsync also but updated once unprotect window 6491c248b7dSInki Dae * is set. 6501c248b7dSInki Dae */ 6511c248b7dSInki Dae 6521c248b7dSInki Dae /* protect windows */ 653de7af100STomasz Figa fimd_shadow_protect_win(ctx, win, true); 6541c248b7dSInki Dae 6557ee14cdcSGustavo Padovan 656cb8a3db2SJoonyoung Shim offset = plane->src_x * (plane->bpp >> 3); 657cb8a3db2SJoonyoung Shim offset += plane->src_y * plane->pitch; 6587ee14cdcSGustavo Padovan 6591c248b7dSInki Dae /* buffer start address */ 6607ee14cdcSGustavo Padovan dma_addr = plane->dma_addr[0] + offset; 6617ee14cdcSGustavo Padovan val = (unsigned long)dma_addr; 6621c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 6631c248b7dSInki Dae 6641c248b7dSInki Dae /* buffer end address */ 66568a29134SDaniel Stone size = plane->pitch * plane->crtc_height; 6667ee14cdcSGustavo Padovan val = (unsigned long)(dma_addr + size); 6671c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 6681c248b7dSInki Dae 6691c248b7dSInki Dae DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 6707ee14cdcSGustavo Padovan (unsigned long)dma_addr, val, size); 67119c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 6727ee14cdcSGustavo Padovan plane->crtc_width, plane->crtc_height); 6731c248b7dSInki Dae 6741c248b7dSInki Dae /* buffer size */ 67568a29134SDaniel Stone buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3)); 6767ee14cdcSGustavo Padovan line_size = plane->crtc_width * (plane->bpp >> 3); 6777ee14cdcSGustavo Padovan val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 6787ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 6797ee14cdcSGustavo Padovan VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 6807ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 6811c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 6821c248b7dSInki Dae 6831c248b7dSInki Dae /* OSD position */ 6847ee14cdcSGustavo Padovan val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 6857ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | 6867ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | 6877ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); 6881c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_A(win)); 6891c248b7dSInki Dae 6907ee14cdcSGustavo Padovan last_x = plane->crtc_x + plane->crtc_width; 691f56aad3aSJoonyoung Shim if (last_x) 692f56aad3aSJoonyoung Shim last_x--; 6937ee14cdcSGustavo Padovan last_y = plane->crtc_y + plane->crtc_height; 694f56aad3aSJoonyoung Shim if (last_y) 695f56aad3aSJoonyoung Shim last_y--; 696f56aad3aSJoonyoung Shim 697ca555e5aSJoonyoung Shim val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 698ca555e5aSJoonyoung Shim VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 699ca555e5aSJoonyoung Shim 7001c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_B(win)); 7011c248b7dSInki Dae 70219c8b834SInki Dae DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 7037ee14cdcSGustavo Padovan plane->crtc_x, plane->crtc_y, last_x, last_y); 7041c248b7dSInki Dae 7051c248b7dSInki Dae /* OSD size */ 7061c248b7dSInki Dae if (win != 3 && win != 4) { 7071c248b7dSInki Dae u32 offset = VIDOSD_D(win); 7081c248b7dSInki Dae if (win == 0) 7090f10cf14SLeela Krishna Amudala offset = VIDOSD_C(win); 7107ee14cdcSGustavo Padovan val = plane->crtc_width * plane->crtc_height; 7111c248b7dSInki Dae writel(val, ctx->regs + offset); 7121c248b7dSInki Dae 7131c248b7dSInki Dae DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 7141c248b7dSInki Dae } 7151c248b7dSInki Dae 716bb7704d6SSean Paul fimd_win_set_pixfmt(ctx, win); 7171c248b7dSInki Dae 7181c248b7dSInki Dae /* hardware window 0 doesn't support color key. */ 7191c248b7dSInki Dae if (win != 0) 720bb7704d6SSean Paul fimd_win_set_colkey(ctx, win); 7211c248b7dSInki Dae 722f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, true); 723ec05da95SInki Dae 724999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 725999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, true); 726ec05da95SInki Dae 72774944a58SYoungJun Cho /* Enable DMA channel and unprotect windows */ 72874944a58SYoungJun Cho fimd_shadow_protect_win(ctx, win, false); 72974944a58SYoungJun Cho 7307ee14cdcSGustavo Padovan plane->enabled = true; 7313854fab2SYoungJun Cho 7323854fab2SYoungJun Cho if (ctx->i80_if) 7333854fab2SYoungJun Cho atomic_set(&ctx->win_updated, 1); 7341c248b7dSInki Dae } 7351c248b7dSInki Dae 7366e2a3b66SGustavo Padovan static void fimd_win_disable(struct exynos_drm_crtc *crtc, unsigned int win) 7371c248b7dSInki Dae { 73893bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 7397ee14cdcSGustavo Padovan struct exynos_drm_plane *plane; 740864ee9e6SJoonyoung Shim 74137b006e8SKrzysztof Kozlowski if (win < 0 || win >= WINDOWS_NR) 7421c248b7dSInki Dae return; 7431c248b7dSInki Dae 7447ee14cdcSGustavo Padovan plane = &ctx->planes[win]; 745ec05da95SInki Dae 746db7e55aeSPrathyush K if (ctx->suspended) { 747db7e55aeSPrathyush K /* do not resume this window*/ 7487ee14cdcSGustavo Padovan plane->resume = false; 749db7e55aeSPrathyush K return; 750db7e55aeSPrathyush K } 751db7e55aeSPrathyush K 7521c248b7dSInki Dae /* protect windows */ 753de7af100STomasz Figa fimd_shadow_protect_win(ctx, win, true); 7541c248b7dSInki Dae 755f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false); 7561c248b7dSInki Dae 757999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 758999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, false); 759de7af100STomasz Figa 760999d8b31SYoungJun Cho /* unprotect windows */ 761de7af100STomasz Figa fimd_shadow_protect_win(ctx, win, false); 762ec05da95SInki Dae 7637ee14cdcSGustavo Padovan plane->enabled = false; 7641c248b7dSInki Dae } 7651c248b7dSInki Dae 76692dc7a04SJoonyoung Shim static void fimd_window_suspend(struct fimd_context *ctx) 767a43b933bSSean Paul { 7687ee14cdcSGustavo Padovan struct exynos_drm_plane *plane; 769a43b933bSSean Paul int i; 770a43b933bSSean Paul 771a43b933bSSean Paul for (i = 0; i < WINDOWS_NR; i++) { 7727ee14cdcSGustavo Padovan plane = &ctx->planes[i]; 7737ee14cdcSGustavo Padovan plane->resume = plane->enabled; 7747ee14cdcSGustavo Padovan if (plane->enabled) 77592dc7a04SJoonyoung Shim fimd_win_disable(ctx->crtc, i); 776a43b933bSSean Paul } 777a43b933bSSean Paul } 778a43b933bSSean Paul 77992dc7a04SJoonyoung Shim static void fimd_window_resume(struct fimd_context *ctx) 780a43b933bSSean Paul { 7817ee14cdcSGustavo Padovan struct exynos_drm_plane *plane; 782a43b933bSSean Paul int i; 783a43b933bSSean Paul 784a43b933bSSean Paul for (i = 0; i < WINDOWS_NR; i++) { 7857ee14cdcSGustavo Padovan plane = &ctx->planes[i]; 7867ee14cdcSGustavo Padovan plane->enabled = plane->resume; 7877ee14cdcSGustavo Padovan plane->resume = false; 788a43b933bSSean Paul } 789a43b933bSSean Paul } 790a43b933bSSean Paul 79192dc7a04SJoonyoung Shim static void fimd_apply(struct fimd_context *ctx) 792a43b933bSSean Paul { 7937ee14cdcSGustavo Padovan struct exynos_drm_plane *plane; 794a43b933bSSean Paul int i; 795a43b933bSSean Paul 796a43b933bSSean Paul for (i = 0; i < WINDOWS_NR; i++) { 7977ee14cdcSGustavo Padovan plane = &ctx->planes[i]; 7987ee14cdcSGustavo Padovan if (plane->enabled) 79992dc7a04SJoonyoung Shim fimd_win_commit(ctx->crtc, i); 800d9b68d89SAndrzej Hajda else 80192dc7a04SJoonyoung Shim fimd_win_disable(ctx->crtc, i); 802a43b933bSSean Paul } 803a43b933bSSean Paul 80492dc7a04SJoonyoung Shim fimd_commit(ctx->crtc); 805a43b933bSSean Paul } 806a43b933bSSean Paul 80792dc7a04SJoonyoung Shim static int fimd_poweron(struct fimd_context *ctx) 808a43b933bSSean Paul { 809a43b933bSSean Paul int ret; 810a43b933bSSean Paul 811a43b933bSSean Paul if (!ctx->suspended) 812a43b933bSSean Paul return 0; 813a43b933bSSean Paul 814a43b933bSSean Paul ctx->suspended = false; 815a43b933bSSean Paul 816af65c804SSean Paul pm_runtime_get_sync(ctx->dev); 817af65c804SSean Paul 818a43b933bSSean Paul ret = clk_prepare_enable(ctx->bus_clk); 819a43b933bSSean Paul if (ret < 0) { 820a43b933bSSean Paul DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 821a43b933bSSean Paul goto bus_clk_err; 822a43b933bSSean Paul } 823a43b933bSSean Paul 824a43b933bSSean Paul ret = clk_prepare_enable(ctx->lcd_clk); 825a43b933bSSean Paul if (ret < 0) { 826a43b933bSSean Paul DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 827a43b933bSSean Paul goto lcd_clk_err; 828a43b933bSSean Paul } 829a43b933bSSean Paul 830a43b933bSSean Paul /* if vblank was enabled status, enable it again. */ 831a43b933bSSean Paul if (test_and_clear_bit(0, &ctx->irq_flags)) { 83292dc7a04SJoonyoung Shim ret = fimd_enable_vblank(ctx->crtc); 833a43b933bSSean Paul if (ret) { 834a43b933bSSean Paul DRM_ERROR("Failed to re-enable vblank [%d]\n", ret); 835a43b933bSSean Paul goto enable_vblank_err; 836a43b933bSSean Paul } 837a43b933bSSean Paul } 838a43b933bSSean Paul 83992dc7a04SJoonyoung Shim fimd_window_resume(ctx); 840a43b933bSSean Paul 84192dc7a04SJoonyoung Shim fimd_apply(ctx); 842a43b933bSSean Paul 843a43b933bSSean Paul return 0; 844a43b933bSSean Paul 845a43b933bSSean Paul enable_vblank_err: 846a43b933bSSean Paul clk_disable_unprepare(ctx->lcd_clk); 847a43b933bSSean Paul lcd_clk_err: 848a43b933bSSean Paul clk_disable_unprepare(ctx->bus_clk); 849a43b933bSSean Paul bus_clk_err: 850a43b933bSSean Paul ctx->suspended = true; 851a43b933bSSean Paul return ret; 852a43b933bSSean Paul } 853a43b933bSSean Paul 85492dc7a04SJoonyoung Shim static int fimd_poweroff(struct fimd_context *ctx) 855a43b933bSSean Paul { 856a43b933bSSean Paul if (ctx->suspended) 857a43b933bSSean Paul return 0; 858a43b933bSSean Paul 859a43b933bSSean Paul /* 860a43b933bSSean Paul * We need to make sure that all windows are disabled before we 861a43b933bSSean Paul * suspend that connector. Otherwise we might try to scan from 862a43b933bSSean Paul * a destroyed buffer later. 863a43b933bSSean Paul */ 86492dc7a04SJoonyoung Shim fimd_window_suspend(ctx); 865a43b933bSSean Paul 866a43b933bSSean Paul clk_disable_unprepare(ctx->lcd_clk); 867a43b933bSSean Paul clk_disable_unprepare(ctx->bus_clk); 868a43b933bSSean Paul 869af65c804SSean Paul pm_runtime_put_sync(ctx->dev); 870af65c804SSean Paul 871a43b933bSSean Paul ctx->suspended = true; 872a43b933bSSean Paul return 0; 873a43b933bSSean Paul } 874a43b933bSSean Paul 87593bca243SGustavo Padovan static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode) 876080be03dSSean Paul { 877af65c804SSean Paul DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); 878080be03dSSean Paul 879080be03dSSean Paul switch (mode) { 880080be03dSSean Paul case DRM_MODE_DPMS_ON: 88192dc7a04SJoonyoung Shim fimd_poweron(crtc->ctx); 882080be03dSSean Paul break; 883080be03dSSean Paul case DRM_MODE_DPMS_STANDBY: 884080be03dSSean Paul case DRM_MODE_DPMS_SUSPEND: 885080be03dSSean Paul case DRM_MODE_DPMS_OFF: 88692dc7a04SJoonyoung Shim fimd_poweroff(crtc->ctx); 887080be03dSSean Paul break; 888080be03dSSean Paul default: 889080be03dSSean Paul DRM_DEBUG_KMS("unspecified mode %d\n", mode); 890080be03dSSean Paul break; 891080be03dSSean Paul } 892080be03dSSean Paul } 893080be03dSSean Paul 8943854fab2SYoungJun Cho static void fimd_trigger(struct device *dev) 8953854fab2SYoungJun Cho { 896e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 8973854fab2SYoungJun Cho struct fimd_driver_data *driver_data = ctx->driver_data; 8983854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base; 8993854fab2SYoungJun Cho u32 reg; 9003854fab2SYoungJun Cho 9019b67eb73SJoonyoung Shim /* 9021c905d95SYoungJun Cho * Skips triggering if in triggering state, because multiple triggering 9039b67eb73SJoonyoung Shim * requests can cause panel reset. 9049b67eb73SJoonyoung Shim */ 9059b67eb73SJoonyoung Shim if (atomic_read(&ctx->triggering)) 9069b67eb73SJoonyoung Shim return; 9079b67eb73SJoonyoung Shim 9081c905d95SYoungJun Cho /* Enters triggering mode */ 9093854fab2SYoungJun Cho atomic_set(&ctx->triggering, 1); 9103854fab2SYoungJun Cho 9113854fab2SYoungJun Cho reg = readl(timing_base + TRIGCON); 9123854fab2SYoungJun Cho reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 9133854fab2SYoungJun Cho writel(reg, timing_base + TRIGCON); 91487ab85b3SYoungJun Cho 91587ab85b3SYoungJun Cho /* 91687ab85b3SYoungJun Cho * Exits triggering mode if vblank is not enabled yet, because when the 91787ab85b3SYoungJun Cho * VIDINTCON0 register is not set, it can not exit from triggering mode. 91887ab85b3SYoungJun Cho */ 91987ab85b3SYoungJun Cho if (!test_bit(0, &ctx->irq_flags)) 92087ab85b3SYoungJun Cho atomic_set(&ctx->triggering, 0); 9213854fab2SYoungJun Cho } 9223854fab2SYoungJun Cho 92393bca243SGustavo Padovan static void fimd_te_handler(struct exynos_drm_crtc *crtc) 9243854fab2SYoungJun Cho { 92593bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 9263854fab2SYoungJun Cho 9273854fab2SYoungJun Cho /* Checks the crtc is detached already from encoder */ 9283854fab2SYoungJun Cho if (ctx->pipe < 0 || !ctx->drm_dev) 9293854fab2SYoungJun Cho return; 9303854fab2SYoungJun Cho 9313854fab2SYoungJun Cho /* 9323854fab2SYoungJun Cho * If there is a page flip request, triggers and handles the page flip 9333854fab2SYoungJun Cho * event so that current fb can be updated into panel GRAM. 9343854fab2SYoungJun Cho */ 9353854fab2SYoungJun Cho if (atomic_add_unless(&ctx->win_updated, -1, 0)) 9363854fab2SYoungJun Cho fimd_trigger(ctx->dev); 9373854fab2SYoungJun Cho 9383854fab2SYoungJun Cho /* Wakes up vsync event queue */ 9393854fab2SYoungJun Cho if (atomic_read(&ctx->wait_vsync_event)) { 9403854fab2SYoungJun Cho atomic_set(&ctx->wait_vsync_event, 0); 9413854fab2SYoungJun Cho wake_up(&ctx->wait_vsync_queue); 942b301ae24SYoungJun Cho } 9433854fab2SYoungJun Cho 944adf67abfSJoonyoung Shim if (test_bit(0, &ctx->irq_flags)) 9453854fab2SYoungJun Cho drm_handle_vblank(ctx->drm_dev, ctx->pipe); 9463854fab2SYoungJun Cho } 9473854fab2SYoungJun Cho 94848107d7bSKrzysztof Kozlowski static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) 94948107d7bSKrzysztof Kozlowski { 95048107d7bSKrzysztof Kozlowski struct fimd_context *ctx = crtc->ctx; 95148107d7bSKrzysztof Kozlowski u32 val; 95248107d7bSKrzysztof Kozlowski 95348107d7bSKrzysztof Kozlowski /* 95448107d7bSKrzysztof Kozlowski * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE 95548107d7bSKrzysztof Kozlowski * clock. On these SoCs the bootloader may enable it but any 95648107d7bSKrzysztof Kozlowski * power domain off/on will reset it to disable state. 95748107d7bSKrzysztof Kozlowski */ 95848107d7bSKrzysztof Kozlowski if (ctx->driver_data != &exynos5_fimd_driver_data) 95948107d7bSKrzysztof Kozlowski return; 96048107d7bSKrzysztof Kozlowski 96148107d7bSKrzysztof Kozlowski val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 96248107d7bSKrzysztof Kozlowski writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); 96348107d7bSKrzysztof Kozlowski } 96448107d7bSKrzysztof Kozlowski 965f3aaf762SKrzysztof Kozlowski static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 9661c6244c3SSean Paul .dpms = fimd_dpms, 967a968e727SSean Paul .mode_fixup = fimd_mode_fixup, 9681c6244c3SSean Paul .commit = fimd_commit, 9691c6244c3SSean Paul .enable_vblank = fimd_enable_vblank, 9701c6244c3SSean Paul .disable_vblank = fimd_disable_vblank, 9711c6244c3SSean Paul .wait_for_vblank = fimd_wait_for_vblank, 9721c6244c3SSean Paul .win_commit = fimd_win_commit, 9731c6244c3SSean Paul .win_disable = fimd_win_disable, 9743854fab2SYoungJun Cho .te_handler = fimd_te_handler, 97548107d7bSKrzysztof Kozlowski .clock_enable = fimd_dp_clock_enable, 9761c248b7dSInki Dae }; 9771c248b7dSInki Dae 9781c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 9791c248b7dSInki Dae { 9801c248b7dSInki Dae struct fimd_context *ctx = (struct fimd_context *)dev_id; 9813854fab2SYoungJun Cho u32 val, clear_bit; 9821c248b7dSInki Dae 9831c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON1); 9841c248b7dSInki Dae 9853854fab2SYoungJun Cho clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 9863854fab2SYoungJun Cho if (val & clear_bit) 9873854fab2SYoungJun Cho writel(clear_bit, ctx->regs + VIDINTCON1); 9881c248b7dSInki Dae 989ec05da95SInki Dae /* check the crtc is detached already from encoder */ 990080be03dSSean Paul if (ctx->pipe < 0 || !ctx->drm_dev) 991ec05da95SInki Dae goto out; 992483b88f8SInki Dae 993adf67abfSJoonyoung Shim if (ctx->i80_if) { 9941c905d95SYoungJun Cho exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); 9951c905d95SYoungJun Cho 9961c905d95SYoungJun Cho /* Exits triggering mode */ 9973854fab2SYoungJun Cho atomic_set(&ctx->triggering, 0); 9983854fab2SYoungJun Cho } else { 999adf67abfSJoonyoung Shim drm_handle_vblank(ctx->drm_dev, ctx->pipe); 1000adf67abfSJoonyoung Shim exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); 1001adf67abfSJoonyoung Shim 100201ce113cSPrathyush K /* set wait vsync event to zero and wake up queue. */ 100301ce113cSPrathyush K if (atomic_read(&ctx->wait_vsync_event)) { 100401ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0); 10058dd9ad5dSSeung-Woo Kim wake_up(&ctx->wait_vsync_queue); 100601ce113cSPrathyush K } 10073854fab2SYoungJun Cho } 10083854fab2SYoungJun Cho 1009ec05da95SInki Dae out: 10101c248b7dSInki Dae return IRQ_HANDLED; 10111c248b7dSInki Dae } 10121c248b7dSInki Dae 1013f37cd5e8SInki Dae static int fimd_bind(struct device *dev, struct device *master, void *data) 1014562ad9f4SAndrzej Hajda { 1015e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 1016f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1017cdbfca89SHyungwon Hwang struct exynos_drm_private *priv = drm_dev->dev_private; 10187ee14cdcSGustavo Padovan struct exynos_drm_plane *exynos_plane; 10197ee14cdcSGustavo Padovan enum drm_plane_type type; 10206e2a3b66SGustavo Padovan unsigned int zpos; 10216e2a3b66SGustavo Padovan int ret; 1022000cc920SAndrzej Hajda 1023cdbfca89SHyungwon Hwang ctx->drm_dev = drm_dev; 1024cdbfca89SHyungwon Hwang ctx->pipe = priv->pipe++; 1025efa75bcdSAjay Kumar 10267ee14cdcSGustavo Padovan for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 10277ee14cdcSGustavo Padovan type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 10287ee14cdcSGustavo Padovan DRM_PLANE_TYPE_OVERLAY; 10297ee14cdcSGustavo Padovan ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 10306e2a3b66SGustavo Padovan 1 << ctx->pipe, type, zpos); 10317ee14cdcSGustavo Padovan if (ret) 10327ee14cdcSGustavo Padovan return ret; 10337ee14cdcSGustavo Padovan } 10347ee14cdcSGustavo Padovan 10357ee14cdcSGustavo Padovan exynos_plane = &ctx->planes[ctx->default_win]; 10367ee14cdcSGustavo Padovan ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 10377ee14cdcSGustavo Padovan ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 10380f04cf8dSJoonyoung Shim &fimd_crtc_ops, ctx); 1039d1222842SHyungwon Hwang if (IS_ERR(ctx->crtc)) 1040d1222842SHyungwon Hwang return PTR_ERR(ctx->crtc); 104193bca243SGustavo Padovan 1042000cc920SAndrzej Hajda if (ctx->display) 1043000cc920SAndrzej Hajda exynos_drm_create_enc_conn(drm_dev, ctx->display); 1044000cc920SAndrzej Hajda 1045cdbfca89SHyungwon Hwang ret = fimd_iommu_attach_devices(ctx, drm_dev); 1046cdbfca89SHyungwon Hwang if (ret) 1047cdbfca89SHyungwon Hwang return ret; 1048cdbfca89SHyungwon Hwang 1049000cc920SAndrzej Hajda return 0; 1050000cc920SAndrzej Hajda 1051000cc920SAndrzej Hajda } 1052000cc920SAndrzej Hajda 1053000cc920SAndrzej Hajda static void fimd_unbind(struct device *dev, struct device *master, 1054000cc920SAndrzej Hajda void *data) 1055000cc920SAndrzej Hajda { 1056e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 1057000cc920SAndrzej Hajda 105893bca243SGustavo Padovan fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF); 1059000cc920SAndrzej Hajda 1060cdbfca89SHyungwon Hwang fimd_iommu_detach_devices(ctx); 1061cdbfca89SHyungwon Hwang 1062000cc920SAndrzej Hajda if (ctx->display) 10634cfde1f2SAndrzej Hajda exynos_dpi_remove(ctx->display); 1064000cc920SAndrzej Hajda } 1065000cc920SAndrzej Hajda 1066000cc920SAndrzej Hajda static const struct component_ops fimd_component_ops = { 1067000cc920SAndrzej Hajda .bind = fimd_bind, 1068000cc920SAndrzej Hajda .unbind = fimd_unbind, 1069000cc920SAndrzej Hajda }; 1070000cc920SAndrzej Hajda 1071000cc920SAndrzej Hajda static int fimd_probe(struct platform_device *pdev) 1072000cc920SAndrzej Hajda { 1073000cc920SAndrzej Hajda struct device *dev = &pdev->dev; 1074000cc920SAndrzej Hajda struct fimd_context *ctx; 10753854fab2SYoungJun Cho struct device_node *i80_if_timings; 1076000cc920SAndrzej Hajda struct resource *res; 1077fe42cfb4SGustavo Padovan int ret; 1078562ad9f4SAndrzej Hajda 1079e152dbd7SAndrzej Hajda if (!dev->of_node) 1080e152dbd7SAndrzej Hajda return -ENODEV; 10812d3f173cSSachin Kamat 1082d873ab99SSeung-Woo Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1083e152dbd7SAndrzej Hajda if (!ctx) 1084e152dbd7SAndrzej Hajda return -ENOMEM; 1085e152dbd7SAndrzej Hajda 1086e152dbd7SAndrzej Hajda ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC, 10875d1741adSGustavo Padovan EXYNOS_DISPLAY_TYPE_LCD); 1088e152dbd7SAndrzej Hajda if (ret) 1089e152dbd7SAndrzej Hajda return ret; 10901c248b7dSInki Dae 1091bb7704d6SSean Paul ctx->dev = dev; 1092a43b933bSSean Paul ctx->suspended = true; 10933854fab2SYoungJun Cho ctx->driver_data = drm_fimd_get_driver_data(pdev); 1094bb7704d6SSean Paul 10951417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 10961417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VDEN; 10971417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 10981417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VCLK; 1099562ad9f4SAndrzej Hajda 11003854fab2SYoungJun Cho i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 11013854fab2SYoungJun Cho if (i80_if_timings) { 11023854fab2SYoungJun Cho u32 val; 11033854fab2SYoungJun Cho 11043854fab2SYoungJun Cho ctx->i80_if = true; 11053854fab2SYoungJun Cho 11063854fab2SYoungJun Cho if (ctx->driver_data->has_vidoutcon) 11073854fab2SYoungJun Cho ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 11083854fab2SYoungJun Cho else 11093854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 11103854fab2SYoungJun Cho /* 11113854fab2SYoungJun Cho * The user manual describes that this "DSI_EN" bit is required 11123854fab2SYoungJun Cho * to enable I80 24-bit data interface. 11133854fab2SYoungJun Cho */ 11143854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_DSI_EN; 11153854fab2SYoungJun Cho 11163854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 11173854fab2SYoungJun Cho val = 0; 11183854fab2SYoungJun Cho ctx->i80ifcon = LCD_CS_SETUP(val); 11193854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 11203854fab2SYoungJun Cho val = 0; 11213854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_SETUP(val); 11223854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 11233854fab2SYoungJun Cho val = 1; 11243854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_ACTIVE(val); 11253854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 11263854fab2SYoungJun Cho val = 0; 11273854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_HOLD(val); 11283854fab2SYoungJun Cho } 11293854fab2SYoungJun Cho of_node_put(i80_if_timings); 11303854fab2SYoungJun Cho 11313854fab2SYoungJun Cho ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 11323854fab2SYoungJun Cho "samsung,sysreg"); 11333854fab2SYoungJun Cho if (IS_ERR(ctx->sysreg)) { 11343854fab2SYoungJun Cho dev_warn(dev, "failed to get system register.\n"); 11353854fab2SYoungJun Cho ctx->sysreg = NULL; 11363854fab2SYoungJun Cho } 11373854fab2SYoungJun Cho 1138a968e727SSean Paul ctx->bus_clk = devm_clk_get(dev, "fimd"); 1139a968e727SSean Paul if (IS_ERR(ctx->bus_clk)) { 1140a968e727SSean Paul dev_err(dev, "failed to get bus clock\n"); 1141df5225bcSInki Dae ret = PTR_ERR(ctx->bus_clk); 1142df5225bcSInki Dae goto err_del_component; 1143a968e727SSean Paul } 1144a968e727SSean Paul 1145a968e727SSean Paul ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1146a968e727SSean Paul if (IS_ERR(ctx->lcd_clk)) { 1147a968e727SSean Paul dev_err(dev, "failed to get lcd clock\n"); 1148df5225bcSInki Dae ret = PTR_ERR(ctx->lcd_clk); 1149df5225bcSInki Dae goto err_del_component; 1150a968e727SSean Paul } 11511c248b7dSInki Dae 11521c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 11531c248b7dSInki Dae 1154d873ab99SSeung-Woo Kim ctx->regs = devm_ioremap_resource(dev, res); 1155df5225bcSInki Dae if (IS_ERR(ctx->regs)) { 1156df5225bcSInki Dae ret = PTR_ERR(ctx->regs); 1157df5225bcSInki Dae goto err_del_component; 1158df5225bcSInki Dae } 11591c248b7dSInki Dae 11603854fab2SYoungJun Cho res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 11613854fab2SYoungJun Cho ctx->i80_if ? "lcd_sys" : "vsync"); 11621c248b7dSInki Dae if (!res) { 11631c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 1164df5225bcSInki Dae ret = -ENXIO; 1165df5225bcSInki Dae goto err_del_component; 11661c248b7dSInki Dae } 11671c248b7dSInki Dae 1168055e0c06SSean Paul ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1169edc57266SSachin Kamat 0, "drm_fimd", ctx); 1170edc57266SSachin Kamat if (ret) { 11711c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 1172df5225bcSInki Dae goto err_del_component; 11731c248b7dSInki Dae } 11741c248b7dSInki Dae 117557ed0f7bSDaniel Vetter init_waitqueue_head(&ctx->wait_vsync_queue); 117601ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0); 11771c248b7dSInki Dae 1178e152dbd7SAndrzej Hajda platform_set_drvdata(pdev, ctx); 1179080be03dSSean Paul 1180000cc920SAndrzej Hajda ctx->display = exynos_dpi_probe(dev); 11815baf5d44SGustavo Padovan if (IS_ERR(ctx->display)) { 11825baf5d44SGustavo Padovan ret = PTR_ERR(ctx->display); 11835baf5d44SGustavo Padovan goto err_del_component; 11845baf5d44SGustavo Padovan } 1185f37cd5e8SInki Dae 1186e152dbd7SAndrzej Hajda pm_runtime_enable(dev); 1187f37cd5e8SInki Dae 1188e152dbd7SAndrzej Hajda ret = component_add(dev, &fimd_component_ops); 1189df5225bcSInki Dae if (ret) 1190df5225bcSInki Dae goto err_disable_pm_runtime; 1191df5225bcSInki Dae 1192df5225bcSInki Dae return ret; 1193df5225bcSInki Dae 1194df5225bcSInki Dae err_disable_pm_runtime: 1195e152dbd7SAndrzej Hajda pm_runtime_disable(dev); 1196df5225bcSInki Dae 1197df5225bcSInki Dae err_del_component: 1198e152dbd7SAndrzej Hajda exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC); 1199df5225bcSInki Dae return ret; 1200f37cd5e8SInki Dae } 1201f37cd5e8SInki Dae 1202f37cd5e8SInki Dae static int fimd_remove(struct platform_device *pdev) 1203f37cd5e8SInki Dae { 1204af65c804SSean Paul pm_runtime_disable(&pdev->dev); 1205cb91f6a0SJoonyoung Shim 1206df5225bcSInki Dae component_del(&pdev->dev, &fimd_component_ops); 1207df5225bcSInki Dae exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC); 1208df5225bcSInki Dae 12091c248b7dSInki Dae return 0; 12101c248b7dSInki Dae } 12111c248b7dSInki Dae 1212132a5b91SJoonyoung Shim struct platform_driver fimd_driver = { 12131c248b7dSInki Dae .probe = fimd_probe, 121456550d94SGreg Kroah-Hartman .remove = fimd_remove, 12151c248b7dSInki Dae .driver = { 12161c248b7dSInki Dae .name = "exynos4-fb", 12171c248b7dSInki Dae .owner = THIS_MODULE, 12182d3f173cSSachin Kamat .of_match_table = fimd_driver_dt_match, 12191c248b7dSInki Dae }, 12201c248b7dSInki Dae }; 1221