11c248b7dSInki Dae /* exynos_drm_fimd.c
21c248b7dSInki Dae  *
31c248b7dSInki Dae  * Copyright (C) 2011 Samsung Electronics Co.Ltd
41c248b7dSInki Dae  * Authors:
51c248b7dSInki Dae  *	Joonyoung Shim <jy0922.shim@samsung.com>
61c248b7dSInki Dae  *	Inki Dae <inki.dae@samsung.com>
71c248b7dSInki Dae  *
81c248b7dSInki Dae  * This program is free software; you can redistribute  it and/or modify it
91c248b7dSInki Dae  * under  the terms of  the GNU General  Public License as published by the
101c248b7dSInki Dae  * Free Software Foundation;  either version 2 of the  License, or (at your
111c248b7dSInki Dae  * option) any later version.
121c248b7dSInki Dae  *
131c248b7dSInki Dae  */
141c248b7dSInki Dae #include "drmP.h"
151c248b7dSInki Dae 
161c248b7dSInki Dae #include <linux/kernel.h>
171c248b7dSInki Dae #include <linux/module.h>
181c248b7dSInki Dae #include <linux/platform_device.h>
191c248b7dSInki Dae #include <linux/clk.h>
20cb91f6a0SJoonyoung Shim #include <linux/pm_runtime.h>
211c248b7dSInki Dae 
221c248b7dSInki Dae #include <drm/exynos_drm.h>
231c248b7dSInki Dae #include <plat/regs-fb-v4.h>
241c248b7dSInki Dae 
251c248b7dSInki Dae #include "exynos_drm_drv.h"
261c248b7dSInki Dae #include "exynos_drm_fbdev.h"
271c248b7dSInki Dae #include "exynos_drm_crtc.h"
281c248b7dSInki Dae 
291c248b7dSInki Dae /*
301c248b7dSInki Dae  * FIMD is stand for Fully Interactive Mobile Display and
311c248b7dSInki Dae  * as a display controller, it transfers contents drawn on memory
321c248b7dSInki Dae  * to a LCD Panel through Display Interfaces such as RGB or
331c248b7dSInki Dae  * CPU Interface.
341c248b7dSInki Dae  */
351c248b7dSInki Dae 
361c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/
371c248b7dSInki Dae #define VIDOSD_A(win)		(VIDOSD_BASE + 0x00 + (win) * 16)
381c248b7dSInki Dae #define VIDOSD_B(win)		(VIDOSD_BASE + 0x04 + (win) * 16)
391c248b7dSInki Dae /* size control register for hardware window 0. */
401c248b7dSInki Dae #define VIDOSD_C_SIZE_W0	(VIDOSD_BASE + 0x08)
411c248b7dSInki Dae /* alpha control register for hardware window 1 ~ 4. */
421c248b7dSInki Dae #define VIDOSD_C(win)		(VIDOSD_BASE + 0x18 + (win) * 16)
431c248b7dSInki Dae /* size control register for hardware window 1 ~ 4. */
441c248b7dSInki Dae #define VIDOSD_D(win)		(VIDOSD_BASE + 0x0C + (win) * 16)
451c248b7dSInki Dae 
461c248b7dSInki Dae #define VIDWx_BUF_START(win, buf)	(VIDW_BUF_START(buf) + (win) * 8)
471c248b7dSInki Dae #define VIDWx_BUF_END(win, buf)		(VIDW_BUF_END(buf) + (win) * 8)
481c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf)	(VIDW_BUF_SIZE(buf) + (win) * 4)
491c248b7dSInki Dae 
501c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */
511c248b7dSInki Dae #define WKEYCON0_BASE(x)		((WKEYCON0 + 0x140) + (x * 8))
521c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */
531c248b7dSInki Dae #define WKEYCON1_BASE(x)		((WKEYCON1 + 0x140) + (x * 8))
541c248b7dSInki Dae 
551c248b7dSInki Dae /* FIMD has totally five hardware windows. */
561c248b7dSInki Dae #define WINDOWS_NR	5
571c248b7dSInki Dae 
581c248b7dSInki Dae #define get_fimd_context(dev)	platform_get_drvdata(to_platform_device(dev))
591c248b7dSInki Dae 
601c248b7dSInki Dae struct fimd_win_data {
611c248b7dSInki Dae 	unsigned int		offset_x;
621c248b7dSInki Dae 	unsigned int		offset_y;
6319c8b834SInki Dae 	unsigned int		ovl_width;
6419c8b834SInki Dae 	unsigned int		ovl_height;
6519c8b834SInki Dae 	unsigned int		fb_width;
6619c8b834SInki Dae 	unsigned int		fb_height;
671c248b7dSInki Dae 	unsigned int		bpp;
682c871127SInki Dae 	dma_addr_t		dma_addr;
691c248b7dSInki Dae 	void __iomem		*vaddr;
701c248b7dSInki Dae 	unsigned int		buf_offsize;
711c248b7dSInki Dae 	unsigned int		line_size;	/* bytes */
72ec05da95SInki Dae 	bool			enabled;
731c248b7dSInki Dae };
741c248b7dSInki Dae 
751c248b7dSInki Dae struct fimd_context {
761c248b7dSInki Dae 	struct exynos_drm_subdrv	subdrv;
771c248b7dSInki Dae 	int				irq;
781c248b7dSInki Dae 	struct drm_crtc			*crtc;
791c248b7dSInki Dae 	struct clk			*bus_clk;
801c248b7dSInki Dae 	struct clk			*lcd_clk;
811c248b7dSInki Dae 	struct resource			*regs_res;
821c248b7dSInki Dae 	void __iomem			*regs;
831c248b7dSInki Dae 	struct fimd_win_data		win_data[WINDOWS_NR];
841c248b7dSInki Dae 	unsigned int			clkdiv;
851c248b7dSInki Dae 	unsigned int			default_win;
861c248b7dSInki Dae 	unsigned long			irq_flags;
871c248b7dSInki Dae 	u32				vidcon0;
881c248b7dSInki Dae 	u32				vidcon1;
89cb91f6a0SJoonyoung Shim 	bool				suspended;
901c248b7dSInki Dae 
911c248b7dSInki Dae 	struct fb_videomode		*timing;
921c248b7dSInki Dae };
931c248b7dSInki Dae 
941c248b7dSInki Dae static bool fimd_display_is_connected(struct device *dev)
951c248b7dSInki Dae {
961c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
971c248b7dSInki Dae 
981c248b7dSInki Dae 	/* TODO. */
991c248b7dSInki Dae 
1001c248b7dSInki Dae 	return true;
1011c248b7dSInki Dae }
1021c248b7dSInki Dae 
1031c248b7dSInki Dae static void *fimd_get_timing(struct device *dev)
1041c248b7dSInki Dae {
1051c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
1061c248b7dSInki Dae 
1071c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
1081c248b7dSInki Dae 
1091c248b7dSInki Dae 	return ctx->timing;
1101c248b7dSInki Dae }
1111c248b7dSInki Dae 
1121c248b7dSInki Dae static int fimd_check_timing(struct device *dev, void *timing)
1131c248b7dSInki Dae {
1141c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
1151c248b7dSInki Dae 
1161c248b7dSInki Dae 	/* TODO. */
1171c248b7dSInki Dae 
1181c248b7dSInki Dae 	return 0;
1191c248b7dSInki Dae }
1201c248b7dSInki Dae 
1211c248b7dSInki Dae static int fimd_display_power_on(struct device *dev, int mode)
1221c248b7dSInki Dae {
1231c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
1241c248b7dSInki Dae 
125ec05da95SInki Dae 	/* TODO */
1261c248b7dSInki Dae 
1271c248b7dSInki Dae 	return 0;
1281c248b7dSInki Dae }
1291c248b7dSInki Dae 
13074ccc539SInki Dae static struct exynos_drm_display_ops fimd_display_ops = {
1311c248b7dSInki Dae 	.type = EXYNOS_DISPLAY_TYPE_LCD,
1321c248b7dSInki Dae 	.is_connected = fimd_display_is_connected,
1331c248b7dSInki Dae 	.get_timing = fimd_get_timing,
1341c248b7dSInki Dae 	.check_timing = fimd_check_timing,
1351c248b7dSInki Dae 	.power_on = fimd_display_power_on,
1361c248b7dSInki Dae };
1371c248b7dSInki Dae 
138ec05da95SInki Dae static void fimd_dpms(struct device *subdrv_dev, int mode)
139ec05da95SInki Dae {
140ec05da95SInki Dae 	DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
141ec05da95SInki Dae 
142cb91f6a0SJoonyoung Shim 	switch (mode) {
143cb91f6a0SJoonyoung Shim 	case DRM_MODE_DPMS_ON:
144cb91f6a0SJoonyoung Shim 		pm_runtime_get_sync(subdrv_dev);
145cb91f6a0SJoonyoung Shim 		break;
146cb91f6a0SJoonyoung Shim 	case DRM_MODE_DPMS_STANDBY:
147cb91f6a0SJoonyoung Shim 	case DRM_MODE_DPMS_SUSPEND:
148cb91f6a0SJoonyoung Shim 	case DRM_MODE_DPMS_OFF:
149cb91f6a0SJoonyoung Shim 		pm_runtime_put_sync(subdrv_dev);
150cb91f6a0SJoonyoung Shim 		break;
151cb91f6a0SJoonyoung Shim 	default:
152cb91f6a0SJoonyoung Shim 		DRM_DEBUG_KMS("unspecified mode %d\n", mode);
153cb91f6a0SJoonyoung Shim 		break;
154cb91f6a0SJoonyoung Shim 	}
155ec05da95SInki Dae }
156ec05da95SInki Dae 
157ec05da95SInki Dae static void fimd_apply(struct device *subdrv_dev)
158ec05da95SInki Dae {
159ec05da95SInki Dae 	struct fimd_context *ctx = get_fimd_context(subdrv_dev);
160ec05da95SInki Dae 	struct exynos_drm_manager *mgr = &ctx->subdrv.manager;
161ec05da95SInki Dae 	struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
162ec05da95SInki Dae 	struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
163ec05da95SInki Dae 	struct fimd_win_data *win_data;
164864ee9e6SJoonyoung Shim 	int i;
165ec05da95SInki Dae 
166ec05da95SInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
167ec05da95SInki Dae 
168864ee9e6SJoonyoung Shim 	for (i = 0; i < WINDOWS_NR; i++) {
169864ee9e6SJoonyoung Shim 		win_data = &ctx->win_data[i];
170ec05da95SInki Dae 		if (win_data->enabled && (ovl_ops && ovl_ops->commit))
171864ee9e6SJoonyoung Shim 			ovl_ops->commit(subdrv_dev, i);
172864ee9e6SJoonyoung Shim 	}
173ec05da95SInki Dae 
174ec05da95SInki Dae 	if (mgr_ops && mgr_ops->commit)
175ec05da95SInki Dae 		mgr_ops->commit(subdrv_dev);
176ec05da95SInki Dae }
177ec05da95SInki Dae 
1781c248b7dSInki Dae static void fimd_commit(struct device *dev)
1791c248b7dSInki Dae {
1801c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
1811c248b7dSInki Dae 	struct fb_videomode *timing = ctx->timing;
1821c248b7dSInki Dae 	u32 val;
1831c248b7dSInki Dae 
184e30d4bcfSInki Dae 	if (ctx->suspended)
185e30d4bcfSInki Dae 		return;
186e30d4bcfSInki Dae 
1871c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
1881c248b7dSInki Dae 
1891c248b7dSInki Dae 	/* setup polarity values from machine code. */
1901c248b7dSInki Dae 	writel(ctx->vidcon1, ctx->regs + VIDCON1);
1911c248b7dSInki Dae 
1921c248b7dSInki Dae 	/* setup vertical timing values. */
1931c248b7dSInki Dae 	val = VIDTCON0_VBPD(timing->upper_margin - 1) |
1941c248b7dSInki Dae 	       VIDTCON0_VFPD(timing->lower_margin - 1) |
1951c248b7dSInki Dae 	       VIDTCON0_VSPW(timing->vsync_len - 1);
1961c248b7dSInki Dae 	writel(val, ctx->regs + VIDTCON0);
1971c248b7dSInki Dae 
1981c248b7dSInki Dae 	/* setup horizontal timing values.  */
1991c248b7dSInki Dae 	val = VIDTCON1_HBPD(timing->left_margin - 1) |
2001c248b7dSInki Dae 	       VIDTCON1_HFPD(timing->right_margin - 1) |
2011c248b7dSInki Dae 	       VIDTCON1_HSPW(timing->hsync_len - 1);
2021c248b7dSInki Dae 	writel(val, ctx->regs + VIDTCON1);
2031c248b7dSInki Dae 
2041c248b7dSInki Dae 	/* setup horizontal and vertical display size. */
2051c248b7dSInki Dae 	val = VIDTCON2_LINEVAL(timing->yres - 1) |
2061c248b7dSInki Dae 	       VIDTCON2_HOZVAL(timing->xres - 1);
2071c248b7dSInki Dae 	writel(val, ctx->regs + VIDTCON2);
2081c248b7dSInki Dae 
2091c248b7dSInki Dae 	/* setup clock source, clock divider, enable dma. */
2101c248b7dSInki Dae 	val = ctx->vidcon0;
2111c248b7dSInki Dae 	val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
2121c248b7dSInki Dae 
2131c248b7dSInki Dae 	if (ctx->clkdiv > 1)
2141c248b7dSInki Dae 		val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
2151c248b7dSInki Dae 	else
2161c248b7dSInki Dae 		val &= ~VIDCON0_CLKDIR;	/* 1:1 clock */
2171c248b7dSInki Dae 
2181c248b7dSInki Dae 	/*
2191c248b7dSInki Dae 	 * fields of register with prefix '_F' would be updated
2201c248b7dSInki Dae 	 * at vsync(same as dma start)
2211c248b7dSInki Dae 	 */
2221c248b7dSInki Dae 	val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
2231c248b7dSInki Dae 	writel(val, ctx->regs + VIDCON0);
2241c248b7dSInki Dae }
2251c248b7dSInki Dae 
2261c248b7dSInki Dae static int fimd_enable_vblank(struct device *dev)
2271c248b7dSInki Dae {
2281c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
2291c248b7dSInki Dae 	u32 val;
2301c248b7dSInki Dae 
2311c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
2321c248b7dSInki Dae 
233cb91f6a0SJoonyoung Shim 	if (ctx->suspended)
234cb91f6a0SJoonyoung Shim 		return -EPERM;
235cb91f6a0SJoonyoung Shim 
2361c248b7dSInki Dae 	if (!test_and_set_bit(0, &ctx->irq_flags)) {
2371c248b7dSInki Dae 		val = readl(ctx->regs + VIDINTCON0);
2381c248b7dSInki Dae 
2391c248b7dSInki Dae 		val |= VIDINTCON0_INT_ENABLE;
2401c248b7dSInki Dae 		val |= VIDINTCON0_INT_FRAME;
2411c248b7dSInki Dae 
2421c248b7dSInki Dae 		val &= ~VIDINTCON0_FRAMESEL0_MASK;
2431c248b7dSInki Dae 		val |= VIDINTCON0_FRAMESEL0_VSYNC;
2441c248b7dSInki Dae 		val &= ~VIDINTCON0_FRAMESEL1_MASK;
2451c248b7dSInki Dae 		val |= VIDINTCON0_FRAMESEL1_NONE;
2461c248b7dSInki Dae 
2471c248b7dSInki Dae 		writel(val, ctx->regs + VIDINTCON0);
2481c248b7dSInki Dae 	}
2491c248b7dSInki Dae 
2501c248b7dSInki Dae 	return 0;
2511c248b7dSInki Dae }
2521c248b7dSInki Dae 
2531c248b7dSInki Dae static void fimd_disable_vblank(struct device *dev)
2541c248b7dSInki Dae {
2551c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
2561c248b7dSInki Dae 	u32 val;
2571c248b7dSInki Dae 
2581c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
2591c248b7dSInki Dae 
260cb91f6a0SJoonyoung Shim 	if (ctx->suspended)
261cb91f6a0SJoonyoung Shim 		return;
262cb91f6a0SJoonyoung Shim 
2631c248b7dSInki Dae 	if (test_and_clear_bit(0, &ctx->irq_flags)) {
2641c248b7dSInki Dae 		val = readl(ctx->regs + VIDINTCON0);
2651c248b7dSInki Dae 
2661c248b7dSInki Dae 		val &= ~VIDINTCON0_INT_FRAME;
2671c248b7dSInki Dae 		val &= ~VIDINTCON0_INT_ENABLE;
2681c248b7dSInki Dae 
2691c248b7dSInki Dae 		writel(val, ctx->regs + VIDINTCON0);
2701c248b7dSInki Dae 	}
2711c248b7dSInki Dae }
2721c248b7dSInki Dae 
2731c248b7dSInki Dae static struct exynos_drm_manager_ops fimd_manager_ops = {
274ec05da95SInki Dae 	.dpms = fimd_dpms,
275ec05da95SInki Dae 	.apply = fimd_apply,
2761c248b7dSInki Dae 	.commit = fimd_commit,
2771c248b7dSInki Dae 	.enable_vblank = fimd_enable_vblank,
2781c248b7dSInki Dae 	.disable_vblank = fimd_disable_vblank,
2791c248b7dSInki Dae };
2801c248b7dSInki Dae 
2811c248b7dSInki Dae static void fimd_win_mode_set(struct device *dev,
2821c248b7dSInki Dae 			      struct exynos_drm_overlay *overlay)
2831c248b7dSInki Dae {
2841c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
2851c248b7dSInki Dae 	struct fimd_win_data *win_data;
286864ee9e6SJoonyoung Shim 	int win;
28719c8b834SInki Dae 	unsigned long offset;
2881c248b7dSInki Dae 
2891c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
2901c248b7dSInki Dae 
2911c248b7dSInki Dae 	if (!overlay) {
2921c248b7dSInki Dae 		dev_err(dev, "overlay is NULL\n");
2931c248b7dSInki Dae 		return;
2941c248b7dSInki Dae 	}
2951c248b7dSInki Dae 
296864ee9e6SJoonyoung Shim 	win = overlay->zpos;
297864ee9e6SJoonyoung Shim 	if (win == DEFAULT_ZPOS)
298864ee9e6SJoonyoung Shim 		win = ctx->default_win;
299864ee9e6SJoonyoung Shim 
300864ee9e6SJoonyoung Shim 	if (win < 0 || win > WINDOWS_NR)
301864ee9e6SJoonyoung Shim 		return;
302864ee9e6SJoonyoung Shim 
30319c8b834SInki Dae 	offset = overlay->fb_x * (overlay->bpp >> 3);
30419c8b834SInki Dae 	offset += overlay->fb_y * overlay->pitch;
30519c8b834SInki Dae 
30619c8b834SInki Dae 	DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
30719c8b834SInki Dae 
308864ee9e6SJoonyoung Shim 	win_data = &ctx->win_data[win];
3091c248b7dSInki Dae 
31019c8b834SInki Dae 	win_data->offset_x = overlay->crtc_x;
31119c8b834SInki Dae 	win_data->offset_y = overlay->crtc_y;
31219c8b834SInki Dae 	win_data->ovl_width = overlay->crtc_width;
31319c8b834SInki Dae 	win_data->ovl_height = overlay->crtc_height;
31419c8b834SInki Dae 	win_data->fb_width = overlay->fb_width;
31519c8b834SInki Dae 	win_data->fb_height = overlay->fb_height;
3162c871127SInki Dae 	win_data->dma_addr = overlay->dma_addr + offset;
31719c8b834SInki Dae 	win_data->vaddr = overlay->vaddr + offset;
3181c248b7dSInki Dae 	win_data->bpp = overlay->bpp;
31919c8b834SInki Dae 	win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
32019c8b834SInki Dae 				(overlay->bpp >> 3);
32119c8b834SInki Dae 	win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
32219c8b834SInki Dae 
32319c8b834SInki Dae 	DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
32419c8b834SInki Dae 			win_data->offset_x, win_data->offset_y);
32519c8b834SInki Dae 	DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
32619c8b834SInki Dae 			win_data->ovl_width, win_data->ovl_height);
32719c8b834SInki Dae 	DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
3282c871127SInki Dae 			(unsigned long)win_data->dma_addr,
32919c8b834SInki Dae 			(unsigned long)win_data->vaddr);
33019c8b834SInki Dae 	DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
33119c8b834SInki Dae 			overlay->fb_width, overlay->crtc_width);
3321c248b7dSInki Dae }
3331c248b7dSInki Dae 
3341c248b7dSInki Dae static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
3351c248b7dSInki Dae {
3361c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
3371c248b7dSInki Dae 	struct fimd_win_data *win_data = &ctx->win_data[win];
3381c248b7dSInki Dae 	unsigned long val;
3391c248b7dSInki Dae 
3401c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
3411c248b7dSInki Dae 
3421c248b7dSInki Dae 	val = WINCONx_ENWIN;
3431c248b7dSInki Dae 
3441c248b7dSInki Dae 	switch (win_data->bpp) {
3451c248b7dSInki Dae 	case 1:
3461c248b7dSInki Dae 		val |= WINCON0_BPPMODE_1BPP;
3471c248b7dSInki Dae 		val |= WINCONx_BITSWP;
3481c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_4WORD;
3491c248b7dSInki Dae 		break;
3501c248b7dSInki Dae 	case 2:
3511c248b7dSInki Dae 		val |= WINCON0_BPPMODE_2BPP;
3521c248b7dSInki Dae 		val |= WINCONx_BITSWP;
3531c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_8WORD;
3541c248b7dSInki Dae 		break;
3551c248b7dSInki Dae 	case 4:
3561c248b7dSInki Dae 		val |= WINCON0_BPPMODE_4BPP;
3571c248b7dSInki Dae 		val |= WINCONx_BITSWP;
3581c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_8WORD;
3591c248b7dSInki Dae 		break;
3601c248b7dSInki Dae 	case 8:
3611c248b7dSInki Dae 		val |= WINCON0_BPPMODE_8BPP_PALETTE;
3621c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_8WORD;
3631c248b7dSInki Dae 		val |= WINCONx_BYTSWP;
3641c248b7dSInki Dae 		break;
3651c248b7dSInki Dae 	case 16:
3661c248b7dSInki Dae 		val |= WINCON0_BPPMODE_16BPP_565;
3671c248b7dSInki Dae 		val |= WINCONx_HAWSWP;
3681c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_16WORD;
3691c248b7dSInki Dae 		break;
3701c248b7dSInki Dae 	case 24:
3711c248b7dSInki Dae 		val |= WINCON0_BPPMODE_24BPP_888;
3721c248b7dSInki Dae 		val |= WINCONx_WSWP;
3731c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_16WORD;
3741c248b7dSInki Dae 		break;
3751c248b7dSInki Dae 	case 32:
3761c248b7dSInki Dae 		val |= WINCON1_BPPMODE_28BPP_A4888
3771c248b7dSInki Dae 			| WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
3781c248b7dSInki Dae 		val |= WINCONx_WSWP;
3791c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_16WORD;
3801c248b7dSInki Dae 		break;
3811c248b7dSInki Dae 	default:
3821c248b7dSInki Dae 		DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
3831c248b7dSInki Dae 
3841c248b7dSInki Dae 		val |= WINCON0_BPPMODE_24BPP_888;
3851c248b7dSInki Dae 		val |= WINCONx_WSWP;
3861c248b7dSInki Dae 		val |= WINCONx_BURSTLEN_16WORD;
3871c248b7dSInki Dae 		break;
3881c248b7dSInki Dae 	}
3891c248b7dSInki Dae 
3901c248b7dSInki Dae 	DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
3911c248b7dSInki Dae 
3921c248b7dSInki Dae 	writel(val, ctx->regs + WINCON(win));
3931c248b7dSInki Dae }
3941c248b7dSInki Dae 
3951c248b7dSInki Dae static void fimd_win_set_colkey(struct device *dev, unsigned int win)
3961c248b7dSInki Dae {
3971c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
3981c248b7dSInki Dae 	unsigned int keycon0 = 0, keycon1 = 0;
3991c248b7dSInki Dae 
4001c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
4011c248b7dSInki Dae 
4021c248b7dSInki Dae 	keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
4031c248b7dSInki Dae 			WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
4041c248b7dSInki Dae 
4051c248b7dSInki Dae 	keycon1 = WxKEYCON1_COLVAL(0xffffffff);
4061c248b7dSInki Dae 
4071c248b7dSInki Dae 	writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
4081c248b7dSInki Dae 	writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
4091c248b7dSInki Dae }
4101c248b7dSInki Dae 
411864ee9e6SJoonyoung Shim static void fimd_win_commit(struct device *dev, int zpos)
4121c248b7dSInki Dae {
4131c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
4141c248b7dSInki Dae 	struct fimd_win_data *win_data;
415864ee9e6SJoonyoung Shim 	int win = zpos;
4161c248b7dSInki Dae 	unsigned long val, alpha, size;
4171c248b7dSInki Dae 
4181c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
4191c248b7dSInki Dae 
420e30d4bcfSInki Dae 	if (ctx->suspended)
421e30d4bcfSInki Dae 		return;
422e30d4bcfSInki Dae 
423864ee9e6SJoonyoung Shim 	if (win == DEFAULT_ZPOS)
424864ee9e6SJoonyoung Shim 		win = ctx->default_win;
425864ee9e6SJoonyoung Shim 
4261c248b7dSInki Dae 	if (win < 0 || win > WINDOWS_NR)
4271c248b7dSInki Dae 		return;
4281c248b7dSInki Dae 
4291c248b7dSInki Dae 	win_data = &ctx->win_data[win];
4301c248b7dSInki Dae 
4311c248b7dSInki Dae 	/*
4321c248b7dSInki Dae 	 * SHADOWCON register is used for enabling timing.
4331c248b7dSInki Dae 	 *
4341c248b7dSInki Dae 	 * for example, once only width value of a register is set,
4351c248b7dSInki Dae 	 * if the dma is started then fimd hardware could malfunction so
4361c248b7dSInki Dae 	 * with protect window setting, the register fields with prefix '_F'
4371c248b7dSInki Dae 	 * wouldn't be updated at vsync also but updated once unprotect window
4381c248b7dSInki Dae 	 * is set.
4391c248b7dSInki Dae 	 */
4401c248b7dSInki Dae 
4411c248b7dSInki Dae 	/* protect windows */
4421c248b7dSInki Dae 	val = readl(ctx->regs + SHADOWCON);
4431c248b7dSInki Dae 	val |= SHADOWCON_WINx_PROTECT(win);
4441c248b7dSInki Dae 	writel(val, ctx->regs + SHADOWCON);
4451c248b7dSInki Dae 
4461c248b7dSInki Dae 	/* buffer start address */
4472c871127SInki Dae 	val = (unsigned long)win_data->dma_addr;
4481c248b7dSInki Dae 	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
4491c248b7dSInki Dae 
4501c248b7dSInki Dae 	/* buffer end address */
45119c8b834SInki Dae 	size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
4522c871127SInki Dae 	val = (unsigned long)(win_data->dma_addr + size);
4531c248b7dSInki Dae 	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
4541c248b7dSInki Dae 
4551c248b7dSInki Dae 	DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
4562c871127SInki Dae 			(unsigned long)win_data->dma_addr, val, size);
45719c8b834SInki Dae 	DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
45819c8b834SInki Dae 			win_data->ovl_width, win_data->ovl_height);
4591c248b7dSInki Dae 
4601c248b7dSInki Dae 	/* buffer size */
4611c248b7dSInki Dae 	val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
4621c248b7dSInki Dae 		VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
4631c248b7dSInki Dae 	writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
4641c248b7dSInki Dae 
4651c248b7dSInki Dae 	/* OSD position */
4661c248b7dSInki Dae 	val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
4671c248b7dSInki Dae 		VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
4681c248b7dSInki Dae 	writel(val, ctx->regs + VIDOSD_A(win));
4691c248b7dSInki Dae 
47019c8b834SInki Dae 	val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
47119c8b834SInki Dae 					win_data->ovl_width - 1) |
47219c8b834SInki Dae 		VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
47319c8b834SInki Dae 					win_data->ovl_height - 1);
4741c248b7dSInki Dae 	writel(val, ctx->regs + VIDOSD_B(win));
4751c248b7dSInki Dae 
47619c8b834SInki Dae 	DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
4771c248b7dSInki Dae 			win_data->offset_x, win_data->offset_y,
47819c8b834SInki Dae 			win_data->offset_x + win_data->ovl_width - 1,
47919c8b834SInki Dae 			win_data->offset_y + win_data->ovl_height - 1);
4801c248b7dSInki Dae 
4811c248b7dSInki Dae 	/* hardware window 0 doesn't support alpha channel. */
4821c248b7dSInki Dae 	if (win != 0) {
4831c248b7dSInki Dae 		/* OSD alpha */
4841c248b7dSInki Dae 		alpha = VIDISD14C_ALPHA1_R(0xf) |
4851c248b7dSInki Dae 			VIDISD14C_ALPHA1_G(0xf) |
4861c248b7dSInki Dae 			VIDISD14C_ALPHA1_B(0xf);
4871c248b7dSInki Dae 
4881c248b7dSInki Dae 		writel(alpha, ctx->regs + VIDOSD_C(win));
4891c248b7dSInki Dae 	}
4901c248b7dSInki Dae 
4911c248b7dSInki Dae 	/* OSD size */
4921c248b7dSInki Dae 	if (win != 3 && win != 4) {
4931c248b7dSInki Dae 		u32 offset = VIDOSD_D(win);
4941c248b7dSInki Dae 		if (win == 0)
4951c248b7dSInki Dae 			offset = VIDOSD_C_SIZE_W0;
49619c8b834SInki Dae 		val = win_data->ovl_width * win_data->ovl_height;
4971c248b7dSInki Dae 		writel(val, ctx->regs + offset);
4981c248b7dSInki Dae 
4991c248b7dSInki Dae 		DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
5001c248b7dSInki Dae 	}
5011c248b7dSInki Dae 
5021c248b7dSInki Dae 	fimd_win_set_pixfmt(dev, win);
5031c248b7dSInki Dae 
5041c248b7dSInki Dae 	/* hardware window 0 doesn't support color key. */
5051c248b7dSInki Dae 	if (win != 0)
5061c248b7dSInki Dae 		fimd_win_set_colkey(dev, win);
5071c248b7dSInki Dae 
508ec05da95SInki Dae 	/* wincon */
509ec05da95SInki Dae 	val = readl(ctx->regs + WINCON(win));
510ec05da95SInki Dae 	val |= WINCONx_ENWIN;
511ec05da95SInki Dae 	writel(val, ctx->regs + WINCON(win));
512ec05da95SInki Dae 
5131c248b7dSInki Dae 	/* Enable DMA channel and unprotect windows */
5141c248b7dSInki Dae 	val = readl(ctx->regs + SHADOWCON);
5151c248b7dSInki Dae 	val |= SHADOWCON_CHx_ENABLE(win);
5161c248b7dSInki Dae 	val &= ~SHADOWCON_WINx_PROTECT(win);
5171c248b7dSInki Dae 	writel(val, ctx->regs + SHADOWCON);
518ec05da95SInki Dae 
519ec05da95SInki Dae 	win_data->enabled = true;
5201c248b7dSInki Dae }
5211c248b7dSInki Dae 
522864ee9e6SJoonyoung Shim static void fimd_win_disable(struct device *dev, int zpos)
5231c248b7dSInki Dae {
5241c248b7dSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
525ec05da95SInki Dae 	struct fimd_win_data *win_data;
526864ee9e6SJoonyoung Shim 	int win = zpos;
5271c248b7dSInki Dae 	u32 val;
5281c248b7dSInki Dae 
5291c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
5301c248b7dSInki Dae 
531864ee9e6SJoonyoung Shim 	if (win == DEFAULT_ZPOS)
532864ee9e6SJoonyoung Shim 		win = ctx->default_win;
533864ee9e6SJoonyoung Shim 
5341c248b7dSInki Dae 	if (win < 0 || win > WINDOWS_NR)
5351c248b7dSInki Dae 		return;
5361c248b7dSInki Dae 
537ec05da95SInki Dae 	win_data = &ctx->win_data[win];
538ec05da95SInki Dae 
5391c248b7dSInki Dae 	/* protect windows */
5401c248b7dSInki Dae 	val = readl(ctx->regs + SHADOWCON);
5411c248b7dSInki Dae 	val |= SHADOWCON_WINx_PROTECT(win);
5421c248b7dSInki Dae 	writel(val, ctx->regs + SHADOWCON);
5431c248b7dSInki Dae 
5441c248b7dSInki Dae 	/* wincon */
5451c248b7dSInki Dae 	val = readl(ctx->regs + WINCON(win));
5461c248b7dSInki Dae 	val &= ~WINCONx_ENWIN;
5471c248b7dSInki Dae 	writel(val, ctx->regs + WINCON(win));
5481c248b7dSInki Dae 
5491c248b7dSInki Dae 	/* unprotect windows */
5501c248b7dSInki Dae 	val = readl(ctx->regs + SHADOWCON);
5511c248b7dSInki Dae 	val &= ~SHADOWCON_CHx_ENABLE(win);
5521c248b7dSInki Dae 	val &= ~SHADOWCON_WINx_PROTECT(win);
5531c248b7dSInki Dae 	writel(val, ctx->regs + SHADOWCON);
554ec05da95SInki Dae 
555ec05da95SInki Dae 	win_data->enabled = false;
5561c248b7dSInki Dae }
5571c248b7dSInki Dae 
5581c248b7dSInki Dae static struct exynos_drm_overlay_ops fimd_overlay_ops = {
5591c248b7dSInki Dae 	.mode_set = fimd_win_mode_set,
5601c248b7dSInki Dae 	.commit = fimd_win_commit,
5611c248b7dSInki Dae 	.disable = fimd_win_disable,
5621c248b7dSInki Dae };
5631c248b7dSInki Dae 
5641c248b7dSInki Dae static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
5651c248b7dSInki Dae {
5661c248b7dSInki Dae 	struct exynos_drm_private *dev_priv = drm_dev->dev_private;
5671c248b7dSInki Dae 	struct drm_pending_vblank_event *e, *t;
5681c248b7dSInki Dae 	struct timeval now;
5691c248b7dSInki Dae 	unsigned long flags;
570ccf4d883SInki Dae 	bool is_checked = false;
5711c248b7dSInki Dae 
5721c248b7dSInki Dae 	spin_lock_irqsave(&drm_dev->event_lock, flags);
5731c248b7dSInki Dae 
5741c248b7dSInki Dae 	list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
5751c248b7dSInki Dae 			base.link) {
576a88cab2bSInki Dae 		/* if event's pipe isn't same as crtc then ignore it. */
577ccf4d883SInki Dae 		if (crtc != e->pipe)
578ccf4d883SInki Dae 			continue;
579ccf4d883SInki Dae 
580ccf4d883SInki Dae 		is_checked = true;
581ccf4d883SInki Dae 
5821c248b7dSInki Dae 		do_gettimeofday(&now);
5831c248b7dSInki Dae 		e->event.sequence = 0;
5841c248b7dSInki Dae 		e->event.tv_sec = now.tv_sec;
5851c248b7dSInki Dae 		e->event.tv_usec = now.tv_usec;
5861c248b7dSInki Dae 
5871c248b7dSInki Dae 		list_move_tail(&e->base.link, &e->base.file_priv->event_list);
5881c248b7dSInki Dae 		wake_up_interruptible(&e->base.file_priv->event_wait);
5891c248b7dSInki Dae 	}
5901c248b7dSInki Dae 
591ec05da95SInki Dae 	if (is_checked) {
5921c248b7dSInki Dae 		drm_vblank_put(drm_dev, crtc);
5931c248b7dSInki Dae 
594ec05da95SInki Dae 		/*
595ec05da95SInki Dae 		 * don't off vblank if vblank_disable_allowed is 1,
596ec05da95SInki Dae 		 * because vblank would be off by timer handler.
597ec05da95SInki Dae 		 */
598ec05da95SInki Dae 		if (!drm_dev->vblank_disable_allowed)
599ec05da95SInki Dae 			drm_vblank_off(drm_dev, crtc);
600ec05da95SInki Dae 	}
601ec05da95SInki Dae 
6021c248b7dSInki Dae 	spin_unlock_irqrestore(&drm_dev->event_lock, flags);
6031c248b7dSInki Dae }
6041c248b7dSInki Dae 
6051c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
6061c248b7dSInki Dae {
6071c248b7dSInki Dae 	struct fimd_context *ctx = (struct fimd_context *)dev_id;
6081c248b7dSInki Dae 	struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
6091c248b7dSInki Dae 	struct drm_device *drm_dev = subdrv->drm_dev;
6101c248b7dSInki Dae 	struct exynos_drm_manager *manager = &subdrv->manager;
6111c248b7dSInki Dae 	u32 val;
6121c248b7dSInki Dae 
6131c248b7dSInki Dae 	val = readl(ctx->regs + VIDINTCON1);
6141c248b7dSInki Dae 
6151c248b7dSInki Dae 	if (val & VIDINTCON1_INT_FRAME)
6161c248b7dSInki Dae 		/* VSYNC interrupt */
6171c248b7dSInki Dae 		writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
6181c248b7dSInki Dae 
619ec05da95SInki Dae 	/* check the crtc is detached already from encoder */
620ec05da95SInki Dae 	if (manager->pipe < 0)
621ec05da95SInki Dae 		goto out;
622483b88f8SInki Dae 
6231c248b7dSInki Dae 	drm_handle_vblank(drm_dev, manager->pipe);
6241c248b7dSInki Dae 	fimd_finish_pageflip(drm_dev, manager->pipe);
6251c248b7dSInki Dae 
626ec05da95SInki Dae out:
6271c248b7dSInki Dae 	return IRQ_HANDLED;
6281c248b7dSInki Dae }
6291c248b7dSInki Dae 
63041c24346SInki Dae static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
6311c248b7dSInki Dae {
6321c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
6331c248b7dSInki Dae 
6341c248b7dSInki Dae 	/*
6351c248b7dSInki Dae 	 * enable drm irq mode.
6361c248b7dSInki Dae 	 * - with irq_enabled = 1, we can use the vblank feature.
6371c248b7dSInki Dae 	 *
6381c248b7dSInki Dae 	 * P.S. note that we wouldn't use drm irq handler but
6391c248b7dSInki Dae 	 *	just specific driver own one instead because
6401c248b7dSInki Dae 	 *	drm framework supports only one irq handler.
6411c248b7dSInki Dae 	 */
6421c248b7dSInki Dae 	drm_dev->irq_enabled = 1;
6431c248b7dSInki Dae 
644ec05da95SInki Dae 	/*
645ec05da95SInki Dae 	 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
646ec05da95SInki Dae 	 * by drm timer once a current process gives up ownership of
647ec05da95SInki Dae 	 * vblank event.(after drm_vblank_put function is called)
648ec05da95SInki Dae 	 */
649ec05da95SInki Dae 	drm_dev->vblank_disable_allowed = 1;
650ec05da95SInki Dae 
6511c248b7dSInki Dae 	return 0;
6521c248b7dSInki Dae }
6531c248b7dSInki Dae 
6541c248b7dSInki Dae static void fimd_subdrv_remove(struct drm_device *drm_dev)
6551c248b7dSInki Dae {
6561c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
6571c248b7dSInki Dae 
6581c248b7dSInki Dae 	/* TODO. */
6591c248b7dSInki Dae }
6601c248b7dSInki Dae 
6611c248b7dSInki Dae static int fimd_calc_clkdiv(struct fimd_context *ctx,
6621c248b7dSInki Dae 			    struct fb_videomode *timing)
6631c248b7dSInki Dae {
6641c248b7dSInki Dae 	unsigned long clk = clk_get_rate(ctx->lcd_clk);
6651c248b7dSInki Dae 	u32 retrace;
6661c248b7dSInki Dae 	u32 clkdiv;
6671c248b7dSInki Dae 	u32 best_framerate = 0;
6681c248b7dSInki Dae 	u32 framerate;
6691c248b7dSInki Dae 
6701c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
6711c248b7dSInki Dae 
6721c248b7dSInki Dae 	retrace = timing->left_margin + timing->hsync_len +
6731c248b7dSInki Dae 				timing->right_margin + timing->xres;
6741c248b7dSInki Dae 	retrace *= timing->upper_margin + timing->vsync_len +
6751c248b7dSInki Dae 				timing->lower_margin + timing->yres;
6761c248b7dSInki Dae 
6771c248b7dSInki Dae 	/* default framerate is 60Hz */
6781c248b7dSInki Dae 	if (!timing->refresh)
6791c248b7dSInki Dae 		timing->refresh = 60;
6801c248b7dSInki Dae 
6811c248b7dSInki Dae 	clk /= retrace;
6821c248b7dSInki Dae 
6831c248b7dSInki Dae 	for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
6841c248b7dSInki Dae 		int tmp;
6851c248b7dSInki Dae 
6861c248b7dSInki Dae 		/* get best framerate */
6871c248b7dSInki Dae 		framerate = clk / clkdiv;
6881c248b7dSInki Dae 		tmp = timing->refresh - framerate;
6891c248b7dSInki Dae 		if (tmp < 0) {
6901c248b7dSInki Dae 			best_framerate = framerate;
6911c248b7dSInki Dae 			continue;
6921c248b7dSInki Dae 		} else {
6931c248b7dSInki Dae 			if (!best_framerate)
6941c248b7dSInki Dae 				best_framerate = framerate;
6951c248b7dSInki Dae 			else if (tmp < (best_framerate - framerate))
6961c248b7dSInki Dae 				best_framerate = framerate;
6971c248b7dSInki Dae 			break;
6981c248b7dSInki Dae 		}
6991c248b7dSInki Dae 	}
7001c248b7dSInki Dae 
7011c248b7dSInki Dae 	return clkdiv;
7021c248b7dSInki Dae }
7031c248b7dSInki Dae 
7041c248b7dSInki Dae static void fimd_clear_win(struct fimd_context *ctx, int win)
7051c248b7dSInki Dae {
7061c248b7dSInki Dae 	u32 val;
7071c248b7dSInki Dae 
7081c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
7091c248b7dSInki Dae 
7101c248b7dSInki Dae 	writel(0, ctx->regs + WINCON(win));
7111c248b7dSInki Dae 	writel(0, ctx->regs + VIDOSD_A(win));
7121c248b7dSInki Dae 	writel(0, ctx->regs + VIDOSD_B(win));
7131c248b7dSInki Dae 	writel(0, ctx->regs + VIDOSD_C(win));
7141c248b7dSInki Dae 
7151c248b7dSInki Dae 	if (win == 1 || win == 2)
7161c248b7dSInki Dae 		writel(0, ctx->regs + VIDOSD_D(win));
7171c248b7dSInki Dae 
7181c248b7dSInki Dae 	val = readl(ctx->regs + SHADOWCON);
7191c248b7dSInki Dae 	val &= ~SHADOWCON_WINx_PROTECT(win);
7201c248b7dSInki Dae 	writel(val, ctx->regs + SHADOWCON);
7211c248b7dSInki Dae }
7221c248b7dSInki Dae 
7231c248b7dSInki Dae static int __devinit fimd_probe(struct platform_device *pdev)
7241c248b7dSInki Dae {
7251c248b7dSInki Dae 	struct device *dev = &pdev->dev;
7261c248b7dSInki Dae 	struct fimd_context *ctx;
7271c248b7dSInki Dae 	struct exynos_drm_subdrv *subdrv;
7281c248b7dSInki Dae 	struct exynos_drm_fimd_pdata *pdata;
7291c248b7dSInki Dae 	struct fb_videomode *timing;
7301c248b7dSInki Dae 	struct resource *res;
7311c248b7dSInki Dae 	int win;
7321c248b7dSInki Dae 	int ret = -EINVAL;
7331c248b7dSInki Dae 
7341c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
7351c248b7dSInki Dae 
7361c248b7dSInki Dae 	pdata = pdev->dev.platform_data;
7371c248b7dSInki Dae 	if (!pdata) {
7381c248b7dSInki Dae 		dev_err(dev, "no platform data specified\n");
7391c248b7dSInki Dae 		return -EINVAL;
7401c248b7dSInki Dae 	}
7411c248b7dSInki Dae 
7421c248b7dSInki Dae 	timing = &pdata->timing;
7431c248b7dSInki Dae 	if (!timing) {
7441c248b7dSInki Dae 		dev_err(dev, "timing is null.\n");
7451c248b7dSInki Dae 		return -EINVAL;
7461c248b7dSInki Dae 	}
7471c248b7dSInki Dae 
7481c248b7dSInki Dae 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
7491c248b7dSInki Dae 	if (!ctx)
7501c248b7dSInki Dae 		return -ENOMEM;
7511c248b7dSInki Dae 
7521c248b7dSInki Dae 	ctx->bus_clk = clk_get(dev, "fimd");
7531c248b7dSInki Dae 	if (IS_ERR(ctx->bus_clk)) {
7541c248b7dSInki Dae 		dev_err(dev, "failed to get bus clock\n");
7551c248b7dSInki Dae 		ret = PTR_ERR(ctx->bus_clk);
7561c248b7dSInki Dae 		goto err_clk_get;
7571c248b7dSInki Dae 	}
7581c248b7dSInki Dae 
7591c248b7dSInki Dae 	clk_enable(ctx->bus_clk);
7601c248b7dSInki Dae 
7611c248b7dSInki Dae 	ctx->lcd_clk = clk_get(dev, "sclk_fimd");
7621c248b7dSInki Dae 	if (IS_ERR(ctx->lcd_clk)) {
7631c248b7dSInki Dae 		dev_err(dev, "failed to get lcd clock\n");
7641c248b7dSInki Dae 		ret = PTR_ERR(ctx->lcd_clk);
7651c248b7dSInki Dae 		goto err_bus_clk;
7661c248b7dSInki Dae 	}
7671c248b7dSInki Dae 
7681c248b7dSInki Dae 	clk_enable(ctx->lcd_clk);
7691c248b7dSInki Dae 
7701c248b7dSInki Dae 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7711c248b7dSInki Dae 	if (!res) {
7721c248b7dSInki Dae 		dev_err(dev, "failed to find registers\n");
7731c248b7dSInki Dae 		ret = -ENOENT;
7741c248b7dSInki Dae 		goto err_clk;
7751c248b7dSInki Dae 	}
7761c248b7dSInki Dae 
7771c248b7dSInki Dae 	ctx->regs_res = request_mem_region(res->start, resource_size(res),
7781c248b7dSInki Dae 					   dev_name(dev));
7791c248b7dSInki Dae 	if (!ctx->regs_res) {
7801c248b7dSInki Dae 		dev_err(dev, "failed to claim register region\n");
7811c248b7dSInki Dae 		ret = -ENOENT;
7821c248b7dSInki Dae 		goto err_clk;
7831c248b7dSInki Dae 	}
7841c248b7dSInki Dae 
7851c248b7dSInki Dae 	ctx->regs = ioremap(res->start, resource_size(res));
7861c248b7dSInki Dae 	if (!ctx->regs) {
7871c248b7dSInki Dae 		dev_err(dev, "failed to map registers\n");
7881c248b7dSInki Dae 		ret = -ENXIO;
7891c248b7dSInki Dae 		goto err_req_region_io;
7901c248b7dSInki Dae 	}
7911c248b7dSInki Dae 
7921c248b7dSInki Dae 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
7931c248b7dSInki Dae 	if (!res) {
7941c248b7dSInki Dae 		dev_err(dev, "irq request failed.\n");
7951c248b7dSInki Dae 		goto err_req_region_irq;
7961c248b7dSInki Dae 	}
7971c248b7dSInki Dae 
7981c248b7dSInki Dae 	ctx->irq = res->start;
7991c248b7dSInki Dae 
8001c248b7dSInki Dae 	ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
8011c248b7dSInki Dae 	if (ret < 0) {
8021c248b7dSInki Dae 		dev_err(dev, "irq request failed.\n");
8031c248b7dSInki Dae 		goto err_req_irq;
8041c248b7dSInki Dae 	}
8051c248b7dSInki Dae 
806cb91f6a0SJoonyoung Shim 	pm_runtime_set_active(dev);
807cb91f6a0SJoonyoung Shim 	pm_runtime_enable(dev);
808cb91f6a0SJoonyoung Shim 	pm_runtime_get_sync(dev);
809cb91f6a0SJoonyoung Shim 
810ec05da95SInki Dae 	for (win = 0; win < WINDOWS_NR; win++)
811ec05da95SInki Dae 		fimd_clear_win(ctx, win);
812ec05da95SInki Dae 
8131c248b7dSInki Dae 	ctx->clkdiv = fimd_calc_clkdiv(ctx, timing);
8141c248b7dSInki Dae 	ctx->vidcon0 = pdata->vidcon0;
8151c248b7dSInki Dae 	ctx->vidcon1 = pdata->vidcon1;
8161c248b7dSInki Dae 	ctx->default_win = pdata->default_win;
8171c248b7dSInki Dae 	ctx->timing = timing;
8181c248b7dSInki Dae 
8191c248b7dSInki Dae 	timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
8201c248b7dSInki Dae 
8211c248b7dSInki Dae 	DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
8221c248b7dSInki Dae 			timing->pixclock, ctx->clkdiv);
8231c248b7dSInki Dae 
8241c248b7dSInki Dae 	subdrv = &ctx->subdrv;
8251c248b7dSInki Dae 
8261c248b7dSInki Dae 	subdrv->probe = fimd_subdrv_probe;
8271c248b7dSInki Dae 	subdrv->remove = fimd_subdrv_remove;
8281c248b7dSInki Dae 	subdrv->manager.pipe = -1;
8291c248b7dSInki Dae 	subdrv->manager.ops = &fimd_manager_ops;
8301c248b7dSInki Dae 	subdrv->manager.overlay_ops = &fimd_overlay_ops;
83174ccc539SInki Dae 	subdrv->manager.display_ops = &fimd_display_ops;
8321c248b7dSInki Dae 	subdrv->manager.dev = dev;
8331c248b7dSInki Dae 
8341c248b7dSInki Dae 	platform_set_drvdata(pdev, ctx);
8351c248b7dSInki Dae 	exynos_drm_subdrv_register(subdrv);
8361c248b7dSInki Dae 
8371c248b7dSInki Dae 	return 0;
8381c248b7dSInki Dae 
8391c248b7dSInki Dae err_req_irq:
8401c248b7dSInki Dae err_req_region_irq:
8411c248b7dSInki Dae 	iounmap(ctx->regs);
8421c248b7dSInki Dae 
8431c248b7dSInki Dae err_req_region_io:
8441c248b7dSInki Dae 	release_resource(ctx->regs_res);
8451c248b7dSInki Dae 	kfree(ctx->regs_res);
8461c248b7dSInki Dae 
8471c248b7dSInki Dae err_clk:
8481c248b7dSInki Dae 	clk_disable(ctx->lcd_clk);
8491c248b7dSInki Dae 	clk_put(ctx->lcd_clk);
8501c248b7dSInki Dae 
8511c248b7dSInki Dae err_bus_clk:
8521c248b7dSInki Dae 	clk_disable(ctx->bus_clk);
8531c248b7dSInki Dae 	clk_put(ctx->bus_clk);
8541c248b7dSInki Dae 
8551c248b7dSInki Dae err_clk_get:
8561c248b7dSInki Dae 	kfree(ctx);
8571c248b7dSInki Dae 	return ret;
8581c248b7dSInki Dae }
8591c248b7dSInki Dae 
8601c248b7dSInki Dae static int __devexit fimd_remove(struct platform_device *pdev)
8611c248b7dSInki Dae {
862cb91f6a0SJoonyoung Shim 	struct device *dev = &pdev->dev;
8631c248b7dSInki Dae 	struct fimd_context *ctx = platform_get_drvdata(pdev);
8641c248b7dSInki Dae 
8651c248b7dSInki Dae 	DRM_DEBUG_KMS("%s\n", __FILE__);
8661c248b7dSInki Dae 
8671c248b7dSInki Dae 	exynos_drm_subdrv_unregister(&ctx->subdrv);
8681c248b7dSInki Dae 
869cb91f6a0SJoonyoung Shim 	if (ctx->suspended)
870cb91f6a0SJoonyoung Shim 		goto out;
871cb91f6a0SJoonyoung Shim 
8721c248b7dSInki Dae 	clk_disable(ctx->lcd_clk);
8731c248b7dSInki Dae 	clk_disable(ctx->bus_clk);
874cb91f6a0SJoonyoung Shim 
875cb91f6a0SJoonyoung Shim 	pm_runtime_set_suspended(dev);
876cb91f6a0SJoonyoung Shim 	pm_runtime_put_sync(dev);
877cb91f6a0SJoonyoung Shim 
878cb91f6a0SJoonyoung Shim out:
879cb91f6a0SJoonyoung Shim 	pm_runtime_disable(dev);
880cb91f6a0SJoonyoung Shim 
8811c248b7dSInki Dae 	clk_put(ctx->lcd_clk);
8821c248b7dSInki Dae 	clk_put(ctx->bus_clk);
8831c248b7dSInki Dae 
8841c248b7dSInki Dae 	iounmap(ctx->regs);
8851c248b7dSInki Dae 	release_resource(ctx->regs_res);
8861c248b7dSInki Dae 	kfree(ctx->regs_res);
8871c248b7dSInki Dae 	free_irq(ctx->irq, ctx);
8881c248b7dSInki Dae 
8891c248b7dSInki Dae 	kfree(ctx);
8901c248b7dSInki Dae 
8911c248b7dSInki Dae 	return 0;
8921c248b7dSInki Dae }
8931c248b7dSInki Dae 
894e30d4bcfSInki Dae #ifdef CONFIG_PM_SLEEP
895e30d4bcfSInki Dae static int fimd_suspend(struct device *dev)
896e30d4bcfSInki Dae {
897e30d4bcfSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
898e30d4bcfSInki Dae 	int ret;
899e30d4bcfSInki Dae 
900e30d4bcfSInki Dae 	if (pm_runtime_suspended(dev))
901e30d4bcfSInki Dae 		return 0;
902e30d4bcfSInki Dae 
903e30d4bcfSInki Dae 	ret = pm_runtime_suspend(dev);
904e30d4bcfSInki Dae 	if (ret < 0)
905e30d4bcfSInki Dae 		return ret;
906e30d4bcfSInki Dae 
907e30d4bcfSInki Dae 	ctx->suspended = true;
908e30d4bcfSInki Dae 	return 0;
909e30d4bcfSInki Dae }
910e30d4bcfSInki Dae 
911e30d4bcfSInki Dae static int fimd_resume(struct device *dev)
912e30d4bcfSInki Dae {
913e30d4bcfSInki Dae 	struct fimd_context *ctx = get_fimd_context(dev);
914e30d4bcfSInki Dae 	int ret;
915e30d4bcfSInki Dae 
916e30d4bcfSInki Dae 	ret = pm_runtime_resume(dev);
917e30d4bcfSInki Dae 	if (ret < 0) {
918e30d4bcfSInki Dae 		DRM_ERROR("failed to resume runtime pm.\n");
919e30d4bcfSInki Dae 		return ret;
920e30d4bcfSInki Dae 	}
921e30d4bcfSInki Dae 
922e30d4bcfSInki Dae 	pm_runtime_disable(dev);
923e30d4bcfSInki Dae 
924e30d4bcfSInki Dae 	ret = pm_runtime_set_active(dev);
925e30d4bcfSInki Dae 	if (ret < 0) {
926e30d4bcfSInki Dae 		DRM_ERROR("failed to active runtime pm.\n");
927e30d4bcfSInki Dae 		pm_runtime_enable(dev);
928e30d4bcfSInki Dae 		pm_runtime_suspend(dev);
929e30d4bcfSInki Dae 		return ret;
930e30d4bcfSInki Dae 	}
931e30d4bcfSInki Dae 
932e30d4bcfSInki Dae 	pm_runtime_enable(dev);
933e30d4bcfSInki Dae 
934e30d4bcfSInki Dae 	ctx->suspended = false;
935e30d4bcfSInki Dae 	return 0;
936e30d4bcfSInki Dae }
937e30d4bcfSInki Dae #endif
938e30d4bcfSInki Dae 
939cb91f6a0SJoonyoung Shim #ifdef CONFIG_PM_RUNTIME
940cb91f6a0SJoonyoung Shim static int fimd_runtime_suspend(struct device *dev)
941cb91f6a0SJoonyoung Shim {
942cb91f6a0SJoonyoung Shim 	struct fimd_context *ctx = get_fimd_context(dev);
943cb91f6a0SJoonyoung Shim 
944cb91f6a0SJoonyoung Shim 	DRM_DEBUG_KMS("%s\n", __FILE__);
945cb91f6a0SJoonyoung Shim 
946cb91f6a0SJoonyoung Shim 	clk_disable(ctx->lcd_clk);
947cb91f6a0SJoonyoung Shim 	clk_disable(ctx->bus_clk);
948cb91f6a0SJoonyoung Shim 
949cb91f6a0SJoonyoung Shim 	ctx->suspended = true;
950cb91f6a0SJoonyoung Shim 	return 0;
951cb91f6a0SJoonyoung Shim }
952cb91f6a0SJoonyoung Shim 
953cb91f6a0SJoonyoung Shim static int fimd_runtime_resume(struct device *dev)
954cb91f6a0SJoonyoung Shim {
955cb91f6a0SJoonyoung Shim 	struct fimd_context *ctx = get_fimd_context(dev);
956cb91f6a0SJoonyoung Shim 	int ret;
957cb91f6a0SJoonyoung Shim 
958cb91f6a0SJoonyoung Shim 	DRM_DEBUG_KMS("%s\n", __FILE__);
959cb91f6a0SJoonyoung Shim 
960cb91f6a0SJoonyoung Shim 	ret = clk_enable(ctx->bus_clk);
961cb91f6a0SJoonyoung Shim 	if (ret < 0)
962cb91f6a0SJoonyoung Shim 		return ret;
963cb91f6a0SJoonyoung Shim 
964cb91f6a0SJoonyoung Shim 	ret = clk_enable(ctx->lcd_clk);
965cb91f6a0SJoonyoung Shim 	if  (ret < 0) {
966cb91f6a0SJoonyoung Shim 		clk_disable(ctx->bus_clk);
967cb91f6a0SJoonyoung Shim 		return ret;
968cb91f6a0SJoonyoung Shim 	}
969cb91f6a0SJoonyoung Shim 
970cb91f6a0SJoonyoung Shim 	ctx->suspended = false;
971e30d4bcfSInki Dae 
972e30d4bcfSInki Dae 	/* if vblank was enabled status, enable it again. */
973e30d4bcfSInki Dae 	if (test_and_clear_bit(0, &ctx->irq_flags))
974e30d4bcfSInki Dae 		fimd_enable_vblank(dev);
975e30d4bcfSInki Dae 
976e30d4bcfSInki Dae 	fimd_apply(dev);
977e30d4bcfSInki Dae 
978cb91f6a0SJoonyoung Shim 	return 0;
979cb91f6a0SJoonyoung Shim }
980cb91f6a0SJoonyoung Shim #endif
981cb91f6a0SJoonyoung Shim 
982cb91f6a0SJoonyoung Shim static const struct dev_pm_ops fimd_pm_ops = {
983e30d4bcfSInki Dae 	SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
984cb91f6a0SJoonyoung Shim 	SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
985cb91f6a0SJoonyoung Shim };
986cb91f6a0SJoonyoung Shim 
9871c248b7dSInki Dae static struct platform_driver fimd_driver = {
9881c248b7dSInki Dae 	.probe		= fimd_probe,
9891c248b7dSInki Dae 	.remove		= __devexit_p(fimd_remove),
9901c248b7dSInki Dae 	.driver		= {
9911c248b7dSInki Dae 		.name	= "exynos4-fb",
9921c248b7dSInki Dae 		.owner	= THIS_MODULE,
993cb91f6a0SJoonyoung Shim 		.pm	= &fimd_pm_ops,
9941c248b7dSInki Dae 	},
9951c248b7dSInki Dae };
9961c248b7dSInki Dae 
9971c248b7dSInki Dae static int __init fimd_init(void)
9981c248b7dSInki Dae {
9991c248b7dSInki Dae 	return platform_driver_register(&fimd_driver);
10001c248b7dSInki Dae }
10011c248b7dSInki Dae 
10021c248b7dSInki Dae static void __exit fimd_exit(void)
10031c248b7dSInki Dae {
10041c248b7dSInki Dae 	platform_driver_unregister(&fimd_driver);
10051c248b7dSInki Dae }
10061c248b7dSInki Dae 
10071c248b7dSInki Dae module_init(fimd_init);
10081c248b7dSInki Dae module_exit(fimd_exit);
10091c248b7dSInki Dae 
10101c248b7dSInki Dae MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
10111c248b7dSInki Dae MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
10121c248b7dSInki Dae MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
10131c248b7dSInki Dae MODULE_LICENSE("GPL");
1014