11c248b7dSInki Dae /* exynos_drm_fimd.c 21c248b7dSInki Dae * 31c248b7dSInki Dae * Copyright (C) 2011 Samsung Electronics Co.Ltd 41c248b7dSInki Dae * Authors: 51c248b7dSInki Dae * Joonyoung Shim <jy0922.shim@samsung.com> 61c248b7dSInki Dae * Inki Dae <inki.dae@samsung.com> 71c248b7dSInki Dae * 81c248b7dSInki Dae * This program is free software; you can redistribute it and/or modify it 91c248b7dSInki Dae * under the terms of the GNU General Public License as published by the 101c248b7dSInki Dae * Free Software Foundation; either version 2 of the License, or (at your 111c248b7dSInki Dae * option) any later version. 121c248b7dSInki Dae * 131c248b7dSInki Dae */ 14760285e7SDavid Howells #include <drm/drmP.h> 151c248b7dSInki Dae 161c248b7dSInki Dae #include <linux/kernel.h> 171c248b7dSInki Dae #include <linux/platform_device.h> 181c248b7dSInki Dae #include <linux/clk.h> 193f1c781dSSachin Kamat #include <linux/of.h> 20d636ead8SJoonyoung Shim #include <linux/of_device.h> 21cb91f6a0SJoonyoung Shim #include <linux/pm_runtime.h> 22f37cd5e8SInki Dae #include <linux/component.h> 233854fab2SYoungJun Cho #include <linux/mfd/syscon.h> 243854fab2SYoungJun Cho #include <linux/regmap.h> 251c248b7dSInki Dae 267f4596f4SVikas Sajjan #include <video/of_display_timing.h> 27111e6055SAndrzej Hajda #include <video/of_videomode.h> 285a213a55SLeela Krishna Amudala #include <video/samsung_fimd.h> 291c248b7dSInki Dae #include <drm/exynos_drm.h> 301c248b7dSInki Dae 311c248b7dSInki Dae #include "exynos_drm_drv.h" 321c248b7dSInki Dae #include "exynos_drm_fbdev.h" 331c248b7dSInki Dae #include "exynos_drm_crtc.h" 347ee14cdcSGustavo Padovan #include "exynos_drm_plane.h" 35bcc5cd1cSInki Dae #include "exynos_drm_iommu.h" 361c248b7dSInki Dae 371c248b7dSInki Dae /* 38b8654b37SSachin Kamat * FIMD stands for Fully Interactive Mobile Display and 391c248b7dSInki Dae * as a display controller, it transfers contents drawn on memory 401c248b7dSInki Dae * to a LCD Panel through Display Interfaces such as RGB or 411c248b7dSInki Dae * CPU Interface. 421c248b7dSInki Dae */ 431c248b7dSInki Dae 44111e6055SAndrzej Hajda #define FIMD_DEFAULT_FRAMERATE 60 4566367461SRahul Sharma #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 46111e6055SAndrzej Hajda 471c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/ 481c248b7dSInki Dae #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 491c248b7dSInki Dae #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 500f10cf14SLeela Krishna Amudala /* 510f10cf14SLeela Krishna Amudala * size control register for hardware windows 0 and alpha control register 520f10cf14SLeela Krishna Amudala * for hardware windows 1 ~ 4 530f10cf14SLeela Krishna Amudala */ 540f10cf14SLeela Krishna Amudala #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 550f10cf14SLeela Krishna Amudala /* size control register for hardware windows 1 ~ 2. */ 561c248b7dSInki Dae #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 571c248b7dSInki Dae 58453b44a3SGustavo Padovan #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 59453b44a3SGustavo Padovan #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 60453b44a3SGustavo Padovan 611c248b7dSInki Dae #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 62cb11b3f1SGustavo Padovan #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8) 631c248b7dSInki Dae #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 641c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 651c248b7dSInki Dae 661c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */ 670f10cf14SLeela Krishna Amudala #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 681c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */ 690f10cf14SLeela Krishna Amudala #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 701c248b7dSInki Dae 713854fab2SYoungJun Cho /* I80 / RGB trigger control register */ 723854fab2SYoungJun Cho #define TRIGCON 0x1A4 733854fab2SYoungJun Cho #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 743854fab2SYoungJun Cho #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 753854fab2SYoungJun Cho 763854fab2SYoungJun Cho /* display mode change control register except exynos4 */ 773854fab2SYoungJun Cho #define VIDOUT_CON 0x000 783854fab2SYoungJun Cho #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 793854fab2SYoungJun Cho 803854fab2SYoungJun Cho /* I80 interface control for main LDI register */ 813854fab2SYoungJun Cho #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 823854fab2SYoungJun Cho #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 833854fab2SYoungJun Cho #define LCD_CS_SETUP(x) ((x) << 16) 843854fab2SYoungJun Cho #define LCD_WR_SETUP(x) ((x) << 12) 853854fab2SYoungJun Cho #define LCD_WR_ACTIVE(x) ((x) << 8) 863854fab2SYoungJun Cho #define LCD_WR_HOLD(x) ((x) << 4) 873854fab2SYoungJun Cho #define I80IFEN_ENABLE (1 << 0) 883854fab2SYoungJun Cho 891c248b7dSInki Dae /* FIMD has totally five hardware windows. */ 901c248b7dSInki Dae #define WINDOWS_NR 5 911c248b7dSInki Dae 92e2e13389SLeela Krishna Amudala struct fimd_driver_data { 93e2e13389SLeela Krishna Amudala unsigned int timing_base; 943854fab2SYoungJun Cho unsigned int lcdblk_offset; 953854fab2SYoungJun Cho unsigned int lcdblk_vt_shift; 963854fab2SYoungJun Cho unsigned int lcdblk_bypass_shift; 97de7af100STomasz Figa 98de7af100STomasz Figa unsigned int has_shadowcon:1; 99411d9ed4STomasz Figa unsigned int has_clksel:1; 1005cc4621aSInki Dae unsigned int has_limited_fmt:1; 1013854fab2SYoungJun Cho unsigned int has_vidoutcon:1; 1023c3c9c1dSJoonyoung Shim unsigned int has_vtsel:1; 103e2e13389SLeela Krishna Amudala }; 104e2e13389SLeela Krishna Amudala 105725ddeadSTomasz Figa static struct fimd_driver_data s3c64xx_fimd_driver_data = { 106725ddeadSTomasz Figa .timing_base = 0x0, 107725ddeadSTomasz Figa .has_clksel = 1, 1085cc4621aSInki Dae .has_limited_fmt = 1, 109725ddeadSTomasz Figa }; 110725ddeadSTomasz Figa 111d6ce7b58SInki Dae static struct fimd_driver_data exynos3_fimd_driver_data = { 112d6ce7b58SInki Dae .timing_base = 0x20000, 113d6ce7b58SInki Dae .lcdblk_offset = 0x210, 114d6ce7b58SInki Dae .lcdblk_bypass_shift = 1, 115d6ce7b58SInki Dae .has_shadowcon = 1, 116d6ce7b58SInki Dae .has_vidoutcon = 1, 117d6ce7b58SInki Dae }; 118d6ce7b58SInki Dae 1196ecf18f9SSachin Kamat static struct fimd_driver_data exynos4_fimd_driver_data = { 120e2e13389SLeela Krishna Amudala .timing_base = 0x0, 1213854fab2SYoungJun Cho .lcdblk_offset = 0x210, 1223854fab2SYoungJun Cho .lcdblk_vt_shift = 10, 1233854fab2SYoungJun Cho .lcdblk_bypass_shift = 1, 124de7af100STomasz Figa .has_shadowcon = 1, 1253c3c9c1dSJoonyoung Shim .has_vtsel = 1, 126e2e13389SLeela Krishna Amudala }; 127e2e13389SLeela Krishna Amudala 128dcb622aaSYoungJun Cho static struct fimd_driver_data exynos4415_fimd_driver_data = { 129dcb622aaSYoungJun Cho .timing_base = 0x20000, 130dcb622aaSYoungJun Cho .lcdblk_offset = 0x210, 131dcb622aaSYoungJun Cho .lcdblk_vt_shift = 10, 132dcb622aaSYoungJun Cho .lcdblk_bypass_shift = 1, 133dcb622aaSYoungJun Cho .has_shadowcon = 1, 134dcb622aaSYoungJun Cho .has_vidoutcon = 1, 1353c3c9c1dSJoonyoung Shim .has_vtsel = 1, 136dcb622aaSYoungJun Cho }; 137dcb622aaSYoungJun Cho 1386ecf18f9SSachin Kamat static struct fimd_driver_data exynos5_fimd_driver_data = { 139e2e13389SLeela Krishna Amudala .timing_base = 0x20000, 1403854fab2SYoungJun Cho .lcdblk_offset = 0x214, 1413854fab2SYoungJun Cho .lcdblk_vt_shift = 24, 1423854fab2SYoungJun Cho .lcdblk_bypass_shift = 15, 143de7af100STomasz Figa .has_shadowcon = 1, 1443854fab2SYoungJun Cho .has_vidoutcon = 1, 1453c3c9c1dSJoonyoung Shim .has_vtsel = 1, 146e2e13389SLeela Krishna Amudala }; 147e2e13389SLeela Krishna Amudala 1481c248b7dSInki Dae struct fimd_context { 149bb7704d6SSean Paul struct device *dev; 15040c8ab4bSSean Paul struct drm_device *drm_dev; 15193bca243SGustavo Padovan struct exynos_drm_crtc *crtc; 1527ee14cdcSGustavo Padovan struct exynos_drm_plane planes[WINDOWS_NR]; 1531c248b7dSInki Dae struct clk *bus_clk; 1541c248b7dSInki Dae struct clk *lcd_clk; 1551c248b7dSInki Dae void __iomem *regs; 1563854fab2SYoungJun Cho struct regmap *sysreg; 1571c248b7dSInki Dae unsigned int default_win; 1581c248b7dSInki Dae unsigned long irq_flags; 1593854fab2SYoungJun Cho u32 vidcon0; 1601c248b7dSInki Dae u32 vidcon1; 1613854fab2SYoungJun Cho u32 vidout_con; 1623854fab2SYoungJun Cho u32 i80ifcon; 1633854fab2SYoungJun Cho bool i80_if; 164cb91f6a0SJoonyoung Shim bool suspended; 165080be03dSSean Paul int pipe; 16601ce113cSPrathyush K wait_queue_head_t wait_vsync_queue; 16701ce113cSPrathyush K atomic_t wait_vsync_event; 1683854fab2SYoungJun Cho atomic_t win_updated; 1693854fab2SYoungJun Cho atomic_t triggering; 1701c248b7dSInki Dae 171562ad9f4SAndrzej Hajda struct exynos_drm_panel_info panel; 17218873465STomasz Figa struct fimd_driver_data *driver_data; 1732b8376c8SGustavo Padovan struct drm_encoder *encoder; 1741c248b7dSInki Dae }; 1751c248b7dSInki Dae 176d636ead8SJoonyoung Shim static const struct of_device_id fimd_driver_dt_match[] = { 177725ddeadSTomasz Figa { .compatible = "samsung,s3c6400-fimd", 178725ddeadSTomasz Figa .data = &s3c64xx_fimd_driver_data }, 179d6ce7b58SInki Dae { .compatible = "samsung,exynos3250-fimd", 180d6ce7b58SInki Dae .data = &exynos3_fimd_driver_data }, 1815830daf8SVikas Sajjan { .compatible = "samsung,exynos4210-fimd", 182d636ead8SJoonyoung Shim .data = &exynos4_fimd_driver_data }, 183dcb622aaSYoungJun Cho { .compatible = "samsung,exynos4415-fimd", 184dcb622aaSYoungJun Cho .data = &exynos4415_fimd_driver_data }, 1855830daf8SVikas Sajjan { .compatible = "samsung,exynos5250-fimd", 186d636ead8SJoonyoung Shim .data = &exynos5_fimd_driver_data }, 187d636ead8SJoonyoung Shim {}, 188d636ead8SJoonyoung Shim }; 1890262ceebSSjoerd Simons MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 190d636ead8SJoonyoung Shim 191e2e13389SLeela Krishna Amudala static inline struct fimd_driver_data *drm_fimd_get_driver_data( 192e2e13389SLeela Krishna Amudala struct platform_device *pdev) 193e2e13389SLeela Krishna Amudala { 194d636ead8SJoonyoung Shim const struct of_device_id *of_id = 195d636ead8SJoonyoung Shim of_match_device(fimd_driver_dt_match, &pdev->dev); 196d636ead8SJoonyoung Shim 197d636ead8SJoonyoung Shim return (struct fimd_driver_data *)of_id->data; 198e2e13389SLeela Krishna Amudala } 199e2e13389SLeela Krishna Amudala 200fb88e214SMarek Szyprowski static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 201fb88e214SMarek Szyprowski { 202fb88e214SMarek Szyprowski struct fimd_context *ctx = crtc->ctx; 203fb88e214SMarek Szyprowski u32 val; 204fb88e214SMarek Szyprowski 205fb88e214SMarek Szyprowski if (ctx->suspended) 206fb88e214SMarek Szyprowski return -EPERM; 207fb88e214SMarek Szyprowski 208fb88e214SMarek Szyprowski if (!test_and_set_bit(0, &ctx->irq_flags)) { 209fb88e214SMarek Szyprowski val = readl(ctx->regs + VIDINTCON0); 210fb88e214SMarek Szyprowski 211fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_ENABLE; 212fb88e214SMarek Szyprowski 213fb88e214SMarek Szyprowski if (ctx->i80_if) { 214fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_I80IFDONE; 215fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_SYSMAINCON; 216fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSSUBCON; 217fb88e214SMarek Szyprowski } else { 218fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_FRAME; 219fb88e214SMarek Szyprowski 220fb88e214SMarek Szyprowski val &= ~VIDINTCON0_FRAMESEL0_MASK; 221fb88e214SMarek Szyprowski val |= VIDINTCON0_FRAMESEL0_VSYNC; 222fb88e214SMarek Szyprowski val &= ~VIDINTCON0_FRAMESEL1_MASK; 223fb88e214SMarek Szyprowski val |= VIDINTCON0_FRAMESEL1_NONE; 224fb88e214SMarek Szyprowski } 225fb88e214SMarek Szyprowski 226fb88e214SMarek Szyprowski writel(val, ctx->regs + VIDINTCON0); 227fb88e214SMarek Szyprowski } 228fb88e214SMarek Szyprowski 229fb88e214SMarek Szyprowski return 0; 230fb88e214SMarek Szyprowski } 231fb88e214SMarek Szyprowski 232fb88e214SMarek Szyprowski static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 233fb88e214SMarek Szyprowski { 234fb88e214SMarek Szyprowski struct fimd_context *ctx = crtc->ctx; 235fb88e214SMarek Szyprowski u32 val; 236fb88e214SMarek Szyprowski 237fb88e214SMarek Szyprowski if (ctx->suspended) 238fb88e214SMarek Szyprowski return; 239fb88e214SMarek Szyprowski 240fb88e214SMarek Szyprowski if (test_and_clear_bit(0, &ctx->irq_flags)) { 241fb88e214SMarek Szyprowski val = readl(ctx->regs + VIDINTCON0); 242fb88e214SMarek Szyprowski 243fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_ENABLE; 244fb88e214SMarek Szyprowski 245fb88e214SMarek Szyprowski if (ctx->i80_if) { 246fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_I80IFDONE; 247fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSMAINCON; 248fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSSUBCON; 249fb88e214SMarek Szyprowski } else 250fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_FRAME; 251fb88e214SMarek Szyprowski 252fb88e214SMarek Szyprowski writel(val, ctx->regs + VIDINTCON0); 253fb88e214SMarek Szyprowski } 254fb88e214SMarek Szyprowski } 255fb88e214SMarek Szyprowski 25693bca243SGustavo Padovan static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 257f13bdbd1SAkshu Agrawal { 25893bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 259f13bdbd1SAkshu Agrawal 260f13bdbd1SAkshu Agrawal if (ctx->suspended) 261f13bdbd1SAkshu Agrawal return; 262f13bdbd1SAkshu Agrawal 263f13bdbd1SAkshu Agrawal atomic_set(&ctx->wait_vsync_event, 1); 264f13bdbd1SAkshu Agrawal 265f13bdbd1SAkshu Agrawal /* 266f13bdbd1SAkshu Agrawal * wait for FIMD to signal VSYNC interrupt or return after 267f13bdbd1SAkshu Agrawal * timeout which is set to 50ms (refresh rate of 20). 268f13bdbd1SAkshu Agrawal */ 269f13bdbd1SAkshu Agrawal if (!wait_event_timeout(ctx->wait_vsync_queue, 270f13bdbd1SAkshu Agrawal !atomic_read(&ctx->wait_vsync_event), 271f13bdbd1SAkshu Agrawal HZ/20)) 272f13bdbd1SAkshu Agrawal DRM_DEBUG_KMS("vblank wait timed out.\n"); 273f13bdbd1SAkshu Agrawal } 274f13bdbd1SAkshu Agrawal 2755b1d5bc6STobias Jakobi static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 276f181a543SYoungJun Cho bool enable) 277f181a543SYoungJun Cho { 278f181a543SYoungJun Cho u32 val = readl(ctx->regs + WINCON(win)); 279f181a543SYoungJun Cho 280f181a543SYoungJun Cho if (enable) 281f181a543SYoungJun Cho val |= WINCONx_ENWIN; 282f181a543SYoungJun Cho else 283f181a543SYoungJun Cho val &= ~WINCONx_ENWIN; 284f181a543SYoungJun Cho 285f181a543SYoungJun Cho writel(val, ctx->regs + WINCON(win)); 286f181a543SYoungJun Cho } 287f181a543SYoungJun Cho 2885b1d5bc6STobias Jakobi static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 2895b1d5bc6STobias Jakobi unsigned int win, 290999d8b31SYoungJun Cho bool enable) 291999d8b31SYoungJun Cho { 292999d8b31SYoungJun Cho u32 val = readl(ctx->regs + SHADOWCON); 293999d8b31SYoungJun Cho 294999d8b31SYoungJun Cho if (enable) 295999d8b31SYoungJun Cho val |= SHADOWCON_CHx_ENABLE(win); 296999d8b31SYoungJun Cho else 297999d8b31SYoungJun Cho val &= ~SHADOWCON_CHx_ENABLE(win); 298999d8b31SYoungJun Cho 299999d8b31SYoungJun Cho writel(val, ctx->regs + SHADOWCON); 300999d8b31SYoungJun Cho } 301999d8b31SYoungJun Cho 302fc2e013fSHyungwon Hwang static void fimd_clear_channels(struct exynos_drm_crtc *crtc) 303f13bdbd1SAkshu Agrawal { 304fc2e013fSHyungwon Hwang struct fimd_context *ctx = crtc->ctx; 3055b1d5bc6STobias Jakobi unsigned int win, ch_enabled = 0; 306f13bdbd1SAkshu Agrawal 307f13bdbd1SAkshu Agrawal DRM_DEBUG_KMS("%s\n", __FILE__); 308f13bdbd1SAkshu Agrawal 309fb88e214SMarek Szyprowski /* Hardware is in unknown state, so ensure it gets enabled properly */ 310fb88e214SMarek Szyprowski pm_runtime_get_sync(ctx->dev); 311fb88e214SMarek Szyprowski 312fb88e214SMarek Szyprowski clk_prepare_enable(ctx->bus_clk); 313fb88e214SMarek Szyprowski clk_prepare_enable(ctx->lcd_clk); 314fb88e214SMarek Szyprowski 315f13bdbd1SAkshu Agrawal /* Check if any channel is enabled. */ 316f13bdbd1SAkshu Agrawal for (win = 0; win < WINDOWS_NR; win++) { 317eb8a3bf7SMarek Szyprowski u32 val = readl(ctx->regs + WINCON(win)); 318eb8a3bf7SMarek Szyprowski 319eb8a3bf7SMarek Szyprowski if (val & WINCONx_ENWIN) { 320f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false); 321eb8a3bf7SMarek Szyprowski 322999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 323999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, 324999d8b31SYoungJun Cho false); 325999d8b31SYoungJun Cho 326f13bdbd1SAkshu Agrawal ch_enabled = 1; 327f13bdbd1SAkshu Agrawal } 328f13bdbd1SAkshu Agrawal } 329f13bdbd1SAkshu Agrawal 330f13bdbd1SAkshu Agrawal /* Wait for vsync, as disable channel takes effect at next vsync */ 331eb8a3bf7SMarek Szyprowski if (ch_enabled) { 332fb88e214SMarek Szyprowski int pipe = ctx->pipe; 333eb8a3bf7SMarek Szyprowski 334fb88e214SMarek Szyprowski /* ensure that vblank interrupt won't be reported to core */ 335fb88e214SMarek Szyprowski ctx->suspended = false; 336fb88e214SMarek Szyprowski ctx->pipe = -1; 337fb88e214SMarek Szyprowski 338fb88e214SMarek Szyprowski fimd_enable_vblank(ctx->crtc); 33992dc7a04SJoonyoung Shim fimd_wait_for_vblank(ctx->crtc); 340fb88e214SMarek Szyprowski fimd_disable_vblank(ctx->crtc); 341fb88e214SMarek Szyprowski 342fb88e214SMarek Szyprowski ctx->suspended = true; 343fb88e214SMarek Szyprowski ctx->pipe = pipe; 344eb8a3bf7SMarek Szyprowski } 345fb88e214SMarek Szyprowski 346fb88e214SMarek Szyprowski clk_disable_unprepare(ctx->lcd_clk); 347fb88e214SMarek Szyprowski clk_disable_unprepare(ctx->bus_clk); 348fb88e214SMarek Szyprowski 349fb88e214SMarek Szyprowski pm_runtime_put(ctx->dev); 350f13bdbd1SAkshu Agrawal } 351f13bdbd1SAkshu Agrawal 352a968e727SSean Paul static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 353a968e727SSean Paul const struct drm_display_mode *mode) 354a968e727SSean Paul { 355a968e727SSean Paul unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 356a968e727SSean Paul u32 clkdiv; 357a968e727SSean Paul 3583854fab2SYoungJun Cho if (ctx->i80_if) { 3593854fab2SYoungJun Cho /* 3603854fab2SYoungJun Cho * The frame done interrupt should be occurred prior to the 3613854fab2SYoungJun Cho * next TE signal. 3623854fab2SYoungJun Cho */ 3633854fab2SYoungJun Cho ideal_clk *= 2; 3643854fab2SYoungJun Cho } 3653854fab2SYoungJun Cho 366a968e727SSean Paul /* Find the clock divider value that gets us closest to ideal_clk */ 367a968e727SSean Paul clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 368a968e727SSean Paul 369a968e727SSean Paul return (clkdiv < 0x100) ? clkdiv : 0xff; 370a968e727SSean Paul } 371a968e727SSean Paul 37293bca243SGustavo Padovan static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, 373a968e727SSean Paul const struct drm_display_mode *mode, 374a968e727SSean Paul struct drm_display_mode *adjusted_mode) 375a968e727SSean Paul { 376a968e727SSean Paul if (adjusted_mode->vrefresh == 0) 377a968e727SSean Paul adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 378a968e727SSean Paul 379a968e727SSean Paul return true; 380a968e727SSean Paul } 381a968e727SSean Paul 38293bca243SGustavo Padovan static void fimd_commit(struct exynos_drm_crtc *crtc) 3831c248b7dSInki Dae { 38493bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 385020e79deSJoonyoung Shim struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 3863854fab2SYoungJun Cho struct fimd_driver_data *driver_data = ctx->driver_data; 3873854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base; 3883854fab2SYoungJun Cho u32 val, clkdiv; 3891c248b7dSInki Dae 390e30d4bcfSInki Dae if (ctx->suspended) 391e30d4bcfSInki Dae return; 392e30d4bcfSInki Dae 393a968e727SSean Paul /* nothing to do if we haven't set the mode yet */ 394a968e727SSean Paul if (mode->htotal == 0 || mode->vtotal == 0) 395a968e727SSean Paul return; 396a968e727SSean Paul 3973854fab2SYoungJun Cho if (ctx->i80_if) { 3983854fab2SYoungJun Cho val = ctx->i80ifcon | I80IFEN_ENABLE; 3993854fab2SYoungJun Cho writel(val, timing_base + I80IFCONFAx(0)); 4003854fab2SYoungJun Cho 4013854fab2SYoungJun Cho /* disable auto frame rate */ 4023854fab2SYoungJun Cho writel(0, timing_base + I80IFCONFBx(0)); 4033854fab2SYoungJun Cho 4043854fab2SYoungJun Cho /* set video type selection to I80 interface */ 4053c3c9c1dSJoonyoung Shim if (driver_data->has_vtsel && ctx->sysreg && 4063c3c9c1dSJoonyoung Shim regmap_update_bits(ctx->sysreg, 4073854fab2SYoungJun Cho driver_data->lcdblk_offset, 4083854fab2SYoungJun Cho 0x3 << driver_data->lcdblk_vt_shift, 4093854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_vt_shift)) { 4103854fab2SYoungJun Cho DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 4113854fab2SYoungJun Cho return; 4123854fab2SYoungJun Cho } 4133854fab2SYoungJun Cho } else { 4143854fab2SYoungJun Cho int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 4153854fab2SYoungJun Cho u32 vidcon1; 4163854fab2SYoungJun Cho 4171417f109SSean Paul /* setup polarity values */ 4181417f109SSean Paul vidcon1 = ctx->vidcon1; 4191417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NVSYNC) 4201417f109SSean Paul vidcon1 |= VIDCON1_INV_VSYNC; 4211417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NHSYNC) 4221417f109SSean Paul vidcon1 |= VIDCON1_INV_HSYNC; 4231417f109SSean Paul writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 4241c248b7dSInki Dae 4251c248b7dSInki Dae /* setup vertical timing values. */ 426a968e727SSean Paul vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 4278b4cad23SAndrzej Hajda vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 4288b4cad23SAndrzej Hajda vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 429a968e727SSean Paul 430a968e727SSean Paul val = VIDTCON0_VBPD(vbpd - 1) | 431a968e727SSean Paul VIDTCON0_VFPD(vfpd - 1) | 432a968e727SSean Paul VIDTCON0_VSPW(vsync_len - 1); 433e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 4341c248b7dSInki Dae 4351c248b7dSInki Dae /* setup horizontal timing values. */ 436a968e727SSean Paul hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 4378b4cad23SAndrzej Hajda hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 4388b4cad23SAndrzej Hajda hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 439a968e727SSean Paul 440a968e727SSean Paul val = VIDTCON1_HBPD(hbpd - 1) | 441a968e727SSean Paul VIDTCON1_HFPD(hfpd - 1) | 442a968e727SSean Paul VIDTCON1_HSPW(hsync_len - 1); 443e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 4443854fab2SYoungJun Cho } 4453854fab2SYoungJun Cho 4463854fab2SYoungJun Cho if (driver_data->has_vidoutcon) 4473854fab2SYoungJun Cho writel(ctx->vidout_con, timing_base + VIDOUT_CON); 4483854fab2SYoungJun Cho 4493854fab2SYoungJun Cho /* set bypass selection */ 4503854fab2SYoungJun Cho if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 4513854fab2SYoungJun Cho driver_data->lcdblk_offset, 4523854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift, 4533854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift)) { 4543854fab2SYoungJun Cho DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 4553854fab2SYoungJun Cho return; 4563854fab2SYoungJun Cho } 4571c248b7dSInki Dae 4581c248b7dSInki Dae /* setup horizontal and vertical display size. */ 459a968e727SSean Paul val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 460a968e727SSean Paul VIDTCON2_HOZVAL(mode->hdisplay - 1) | 461a968e727SSean Paul VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 462a968e727SSean Paul VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 463e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 4641c248b7dSInki Dae 4651c248b7dSInki Dae /* 4661c248b7dSInki Dae * fields of register with prefix '_F' would be updated 4671c248b7dSInki Dae * at vsync(same as dma start) 4681c248b7dSInki Dae */ 4693854fab2SYoungJun Cho val = ctx->vidcon0; 4703854fab2SYoungJun Cho val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 4711d531062SAndrzej Hajda 4721d531062SAndrzej Hajda if (ctx->driver_data->has_clksel) 4731d531062SAndrzej Hajda val |= VIDCON0_CLKSEL_LCD; 4741d531062SAndrzej Hajda 4751d531062SAndrzej Hajda clkdiv = fimd_calc_clkdiv(ctx, mode); 4761d531062SAndrzej Hajda if (clkdiv > 1) 4771d531062SAndrzej Hajda val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 4781d531062SAndrzej Hajda 4791c248b7dSInki Dae writel(val, ctx->regs + VIDCON0); 4801c248b7dSInki Dae } 4811c248b7dSInki Dae 4821c248b7dSInki Dae 4832eeb2e5eSGustavo Padovan static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win, 4842eeb2e5eSGustavo Padovan struct drm_framebuffer *fb) 4851c248b7dSInki Dae { 4861c248b7dSInki Dae unsigned long val; 4871c248b7dSInki Dae 4881c248b7dSInki Dae val = WINCONx_ENWIN; 4891c248b7dSInki Dae 4905cc4621aSInki Dae /* 4915cc4621aSInki Dae * In case of s3c64xx, window 0 doesn't support alpha channel. 4925cc4621aSInki Dae * So the request format is ARGB8888 then change it to XRGB8888. 4935cc4621aSInki Dae */ 4945cc4621aSInki Dae if (ctx->driver_data->has_limited_fmt && !win) { 4952eeb2e5eSGustavo Padovan if (fb->pixel_format == DRM_FORMAT_ARGB8888) 4962eeb2e5eSGustavo Padovan fb->pixel_format = DRM_FORMAT_XRGB8888; 4975cc4621aSInki Dae } 4985cc4621aSInki Dae 4992eeb2e5eSGustavo Padovan switch (fb->pixel_format) { 500a4f38a80SInki Dae case DRM_FORMAT_C8: 5011c248b7dSInki Dae val |= WINCON0_BPPMODE_8BPP_PALETTE; 5021c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 5031c248b7dSInki Dae val |= WINCONx_BYTSWP; 5041c248b7dSInki Dae break; 505a4f38a80SInki Dae case DRM_FORMAT_XRGB1555: 506a4f38a80SInki Dae val |= WINCON0_BPPMODE_16BPP_1555; 507a4f38a80SInki Dae val |= WINCONx_HAWSWP; 508a4f38a80SInki Dae val |= WINCONx_BURSTLEN_16WORD; 509a4f38a80SInki Dae break; 510a4f38a80SInki Dae case DRM_FORMAT_RGB565: 5111c248b7dSInki Dae val |= WINCON0_BPPMODE_16BPP_565; 5121c248b7dSInki Dae val |= WINCONx_HAWSWP; 5131c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5141c248b7dSInki Dae break; 515a4f38a80SInki Dae case DRM_FORMAT_XRGB8888: 5161c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 5171c248b7dSInki Dae val |= WINCONx_WSWP; 5181c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5191c248b7dSInki Dae break; 520a4f38a80SInki Dae case DRM_FORMAT_ARGB8888: 521a4f38a80SInki Dae val |= WINCON1_BPPMODE_25BPP_A1888 5221c248b7dSInki Dae | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 5231c248b7dSInki Dae val |= WINCONx_WSWP; 5241c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5251c248b7dSInki Dae break; 5261c248b7dSInki Dae default: 5271c248b7dSInki Dae DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 5281c248b7dSInki Dae 5291c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 5301c248b7dSInki Dae val |= WINCONx_WSWP; 5311c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5321c248b7dSInki Dae break; 5331c248b7dSInki Dae } 5341c248b7dSInki Dae 5352eeb2e5eSGustavo Padovan DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); 5361c248b7dSInki Dae 53766367461SRahul Sharma /* 53866367461SRahul Sharma * In case of exynos, setting dma-burst to 16Word causes permanent 53966367461SRahul Sharma * tearing for very small buffers, e.g. cursor buffer. Burst Mode 5408837deeaSGustavo Padovan * switching which is based on plane size is not recommended as 5418837deeaSGustavo Padovan * plane size varies alot towards the end of the screen and rapid 54266367461SRahul Sharma * movement causes unstable DMA which results into iommu crash/tear. 54366367461SRahul Sharma */ 54466367461SRahul Sharma 5452eeb2e5eSGustavo Padovan if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 54666367461SRahul Sharma val &= ~WINCONx_BURSTLEN_MASK; 54766367461SRahul Sharma val |= WINCONx_BURSTLEN_4WORD; 54866367461SRahul Sharma } 54966367461SRahul Sharma 5501c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 551453b44a3SGustavo Padovan 552453b44a3SGustavo Padovan /* hardware window 0 doesn't support alpha channel. */ 553453b44a3SGustavo Padovan if (win != 0) { 554453b44a3SGustavo Padovan /* OSD alpha */ 555453b44a3SGustavo Padovan val = VIDISD14C_ALPHA0_R(0xf) | 556453b44a3SGustavo Padovan VIDISD14C_ALPHA0_G(0xf) | 557453b44a3SGustavo Padovan VIDISD14C_ALPHA0_B(0xf) | 558453b44a3SGustavo Padovan VIDISD14C_ALPHA1_R(0xf) | 559453b44a3SGustavo Padovan VIDISD14C_ALPHA1_G(0xf) | 560453b44a3SGustavo Padovan VIDISD14C_ALPHA1_B(0xf); 561453b44a3SGustavo Padovan 562453b44a3SGustavo Padovan writel(val, ctx->regs + VIDOSD_C(win)); 563453b44a3SGustavo Padovan 564453b44a3SGustavo Padovan val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | 565453b44a3SGustavo Padovan VIDW_ALPHA_G(0xf); 566453b44a3SGustavo Padovan writel(val, ctx->regs + VIDWnALPHA0(win)); 567453b44a3SGustavo Padovan writel(val, ctx->regs + VIDWnALPHA1(win)); 568453b44a3SGustavo Padovan } 5691c248b7dSInki Dae } 5701c248b7dSInki Dae 571bb7704d6SSean Paul static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 5721c248b7dSInki Dae { 5731c248b7dSInki Dae unsigned int keycon0 = 0, keycon1 = 0; 5741c248b7dSInki Dae 5751c248b7dSInki Dae keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 5761c248b7dSInki Dae WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 5771c248b7dSInki Dae 5781c248b7dSInki Dae keycon1 = WxKEYCON1_COLVAL(0xffffffff); 5791c248b7dSInki Dae 5801c248b7dSInki Dae writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 5811c248b7dSInki Dae writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 5821c248b7dSInki Dae } 5831c248b7dSInki Dae 584de7af100STomasz Figa /** 585de7af100STomasz Figa * shadow_protect_win() - disable updating values from shadow registers at vsync 586de7af100STomasz Figa * 587de7af100STomasz Figa * @win: window to protect registers for 588de7af100STomasz Figa * @protect: 1 to protect (disable updates) 589de7af100STomasz Figa */ 590de7af100STomasz Figa static void fimd_shadow_protect_win(struct fimd_context *ctx, 5916e2a3b66SGustavo Padovan unsigned int win, bool protect) 592de7af100STomasz Figa { 593de7af100STomasz Figa u32 reg, bits, val; 594de7af100STomasz Figa 595ce3ff36bSGustavo Padovan /* 596ce3ff36bSGustavo Padovan * SHADOWCON/PRTCON register is used for enabling timing. 597ce3ff36bSGustavo Padovan * 598ce3ff36bSGustavo Padovan * for example, once only width value of a register is set, 599ce3ff36bSGustavo Padovan * if the dma is started then fimd hardware could malfunction so 600ce3ff36bSGustavo Padovan * with protect window setting, the register fields with prefix '_F' 601ce3ff36bSGustavo Padovan * wouldn't be updated at vsync also but updated once unprotect window 602ce3ff36bSGustavo Padovan * is set. 603ce3ff36bSGustavo Padovan */ 604ce3ff36bSGustavo Padovan 605de7af100STomasz Figa if (ctx->driver_data->has_shadowcon) { 606de7af100STomasz Figa reg = SHADOWCON; 607de7af100STomasz Figa bits = SHADOWCON_WINx_PROTECT(win); 608de7af100STomasz Figa } else { 609de7af100STomasz Figa reg = PRTCON; 610de7af100STomasz Figa bits = PRTCON_PROTECT; 611de7af100STomasz Figa } 612de7af100STomasz Figa 613de7af100STomasz Figa val = readl(ctx->regs + reg); 614de7af100STomasz Figa if (protect) 615de7af100STomasz Figa val |= bits; 616de7af100STomasz Figa else 617de7af100STomasz Figa val &= ~bits; 618de7af100STomasz Figa writel(val, ctx->regs + reg); 619de7af100STomasz Figa } 620de7af100STomasz Figa 621ce3ff36bSGustavo Padovan static void fimd_atomic_begin(struct exynos_drm_crtc *crtc, 622ce3ff36bSGustavo Padovan struct exynos_drm_plane *plane) 623ce3ff36bSGustavo Padovan { 624ce3ff36bSGustavo Padovan struct fimd_context *ctx = crtc->ctx; 625ce3ff36bSGustavo Padovan 626ce3ff36bSGustavo Padovan if (ctx->suspended) 627ce3ff36bSGustavo Padovan return; 628ce3ff36bSGustavo Padovan 629ce3ff36bSGustavo Padovan fimd_shadow_protect_win(ctx, plane->zpos, true); 630ce3ff36bSGustavo Padovan } 631ce3ff36bSGustavo Padovan 632ce3ff36bSGustavo Padovan static void fimd_atomic_flush(struct exynos_drm_crtc *crtc, 633ce3ff36bSGustavo Padovan struct exynos_drm_plane *plane) 634ce3ff36bSGustavo Padovan { 635ce3ff36bSGustavo Padovan struct fimd_context *ctx = crtc->ctx; 636ce3ff36bSGustavo Padovan 637ce3ff36bSGustavo Padovan if (ctx->suspended) 638ce3ff36bSGustavo Padovan return; 639ce3ff36bSGustavo Padovan 640ce3ff36bSGustavo Padovan fimd_shadow_protect_win(ctx, plane->zpos, false); 641ce3ff36bSGustavo Padovan } 642ce3ff36bSGustavo Padovan 6431e1d1393SGustavo Padovan static void fimd_update_plane(struct exynos_drm_crtc *crtc, 6441e1d1393SGustavo Padovan struct exynos_drm_plane *plane) 6451c248b7dSInki Dae { 64693bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 6472eeb2e5eSGustavo Padovan struct drm_plane_state *state = plane->base.state; 6487ee14cdcSGustavo Padovan dma_addr_t dma_addr; 6497ee14cdcSGustavo Padovan unsigned long val, size, offset; 6507ee14cdcSGustavo Padovan unsigned int last_x, last_y, buf_offsize, line_size; 6511e1d1393SGustavo Padovan unsigned int win = plane->zpos; 6522eeb2e5eSGustavo Padovan unsigned int bpp = state->fb->bits_per_pixel >> 3; 6532eeb2e5eSGustavo Padovan unsigned int pitch = state->fb->pitches[0]; 6541c248b7dSInki Dae 655e30d4bcfSInki Dae if (ctx->suspended) 656e30d4bcfSInki Dae return; 657e30d4bcfSInki Dae 6582eeb2e5eSGustavo Padovan offset = plane->src_x * bpp; 6592eeb2e5eSGustavo Padovan offset += plane->src_y * pitch; 6607ee14cdcSGustavo Padovan 6611c248b7dSInki Dae /* buffer start address */ 6627ee14cdcSGustavo Padovan dma_addr = plane->dma_addr[0] + offset; 6637ee14cdcSGustavo Padovan val = (unsigned long)dma_addr; 6641c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 6651c248b7dSInki Dae 6661c248b7dSInki Dae /* buffer end address */ 667d88d2463SGustavo Padovan size = pitch * plane->crtc_h; 6687ee14cdcSGustavo Padovan val = (unsigned long)(dma_addr + size); 6691c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 6701c248b7dSInki Dae 6711c248b7dSInki Dae DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 6727ee14cdcSGustavo Padovan (unsigned long)dma_addr, val, size); 67319c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 674d88d2463SGustavo Padovan plane->crtc_w, plane->crtc_h); 6751c248b7dSInki Dae 6761c248b7dSInki Dae /* buffer size */ 677d88d2463SGustavo Padovan buf_offsize = pitch - (plane->crtc_w * bpp); 678d88d2463SGustavo Padovan line_size = plane->crtc_w * bpp; 6797ee14cdcSGustavo Padovan val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 6807ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 6817ee14cdcSGustavo Padovan VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 6827ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 6831c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 6841c248b7dSInki Dae 6851c248b7dSInki Dae /* OSD position */ 6867ee14cdcSGustavo Padovan val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 6877ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | 6887ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | 6897ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); 6901c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_A(win)); 6911c248b7dSInki Dae 692d88d2463SGustavo Padovan last_x = plane->crtc_x + plane->crtc_w; 693f56aad3aSJoonyoung Shim if (last_x) 694f56aad3aSJoonyoung Shim last_x--; 695d88d2463SGustavo Padovan last_y = plane->crtc_y + plane->crtc_h; 696f56aad3aSJoonyoung Shim if (last_y) 697f56aad3aSJoonyoung Shim last_y--; 698f56aad3aSJoonyoung Shim 699ca555e5aSJoonyoung Shim val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 700ca555e5aSJoonyoung Shim VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 701ca555e5aSJoonyoung Shim 7021c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_B(win)); 7031c248b7dSInki Dae 70419c8b834SInki Dae DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 7057ee14cdcSGustavo Padovan plane->crtc_x, plane->crtc_y, last_x, last_y); 7061c248b7dSInki Dae 7071c248b7dSInki Dae /* OSD size */ 7081c248b7dSInki Dae if (win != 3 && win != 4) { 7091c248b7dSInki Dae u32 offset = VIDOSD_D(win); 7101c248b7dSInki Dae if (win == 0) 7110f10cf14SLeela Krishna Amudala offset = VIDOSD_C(win); 712d88d2463SGustavo Padovan val = plane->crtc_w * plane->crtc_h; 7131c248b7dSInki Dae writel(val, ctx->regs + offset); 7141c248b7dSInki Dae 7151c248b7dSInki Dae DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 7161c248b7dSInki Dae } 7171c248b7dSInki Dae 7182eeb2e5eSGustavo Padovan fimd_win_set_pixfmt(ctx, win, state->fb); 7191c248b7dSInki Dae 7201c248b7dSInki Dae /* hardware window 0 doesn't support color key. */ 7211c248b7dSInki Dae if (win != 0) 722bb7704d6SSean Paul fimd_win_set_colkey(ctx, win); 7231c248b7dSInki Dae 724f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, true); 725ec05da95SInki Dae 726999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 727999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, true); 728ec05da95SInki Dae 7293854fab2SYoungJun Cho if (ctx->i80_if) 7303854fab2SYoungJun Cho atomic_set(&ctx->win_updated, 1); 7311c248b7dSInki Dae } 7321c248b7dSInki Dae 7331e1d1393SGustavo Padovan static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 7341e1d1393SGustavo Padovan struct exynos_drm_plane *plane) 7351c248b7dSInki Dae { 73693bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 7371e1d1393SGustavo Padovan unsigned int win = plane->zpos; 738ec05da95SInki Dae 739c329f667SJoonyoung Shim if (ctx->suspended) 740db7e55aeSPrathyush K return; 741db7e55aeSPrathyush K 742f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false); 7431c248b7dSInki Dae 744999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 745999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, false); 746a43b933bSSean Paul } 747a43b933bSSean Paul 7483cecda03SGustavo Padovan static void fimd_enable(struct exynos_drm_crtc *crtc) 749a43b933bSSean Paul { 7503cecda03SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 75138000dbbSGustavo Padovan int ret; 752a43b933bSSean Paul 753a43b933bSSean Paul if (!ctx->suspended) 7543cecda03SGustavo Padovan return; 755a43b933bSSean Paul 756a43b933bSSean Paul ctx->suspended = false; 757a43b933bSSean Paul 758af65c804SSean Paul pm_runtime_get_sync(ctx->dev); 759af65c804SSean Paul 76038000dbbSGustavo Padovan ret = clk_prepare_enable(ctx->bus_clk); 76138000dbbSGustavo Padovan if (ret < 0) { 76238000dbbSGustavo Padovan DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 76338000dbbSGustavo Padovan return; 76438000dbbSGustavo Padovan } 76538000dbbSGustavo Padovan 76638000dbbSGustavo Padovan ret = clk_prepare_enable(ctx->lcd_clk); 76738000dbbSGustavo Padovan if (ret < 0) { 76838000dbbSGustavo Padovan DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 76938000dbbSGustavo Padovan return; 77038000dbbSGustavo Padovan } 771a43b933bSSean Paul 772a43b933bSSean Paul /* if vblank was enabled status, enable it again. */ 7733cecda03SGustavo Padovan if (test_and_clear_bit(0, &ctx->irq_flags)) 7743cecda03SGustavo Padovan fimd_enable_vblank(ctx->crtc); 775a43b933bSSean Paul 776c329f667SJoonyoung Shim fimd_commit(ctx->crtc); 777a43b933bSSean Paul } 778a43b933bSSean Paul 7793cecda03SGustavo Padovan static void fimd_disable(struct exynos_drm_crtc *crtc) 780a43b933bSSean Paul { 7813cecda03SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 782c329f667SJoonyoung Shim int i; 7833cecda03SGustavo Padovan 784a43b933bSSean Paul if (ctx->suspended) 7853cecda03SGustavo Padovan return; 786a43b933bSSean Paul 787a43b933bSSean Paul /* 788a43b933bSSean Paul * We need to make sure that all windows are disabled before we 789a43b933bSSean Paul * suspend that connector. Otherwise we might try to scan from 790a43b933bSSean Paul * a destroyed buffer later. 791a43b933bSSean Paul */ 792c329f667SJoonyoung Shim for (i = 0; i < WINDOWS_NR; i++) 7931e1d1393SGustavo Padovan fimd_disable_plane(crtc, &ctx->planes[i]); 794a43b933bSSean Paul 79594ab95a9SInki Dae fimd_enable_vblank(crtc); 79694ab95a9SInki Dae fimd_wait_for_vblank(crtc); 79794ab95a9SInki Dae fimd_disable_vblank(crtc); 79894ab95a9SInki Dae 799b74f14fdSJoonyoung Shim writel(0, ctx->regs + VIDCON0); 800b74f14fdSJoonyoung Shim 801a43b933bSSean Paul clk_disable_unprepare(ctx->lcd_clk); 802a43b933bSSean Paul clk_disable_unprepare(ctx->bus_clk); 803a43b933bSSean Paul 804af65c804SSean Paul pm_runtime_put_sync(ctx->dev); 805af65c804SSean Paul 806a43b933bSSean Paul ctx->suspended = true; 807080be03dSSean Paul } 808080be03dSSean Paul 8093854fab2SYoungJun Cho static void fimd_trigger(struct device *dev) 8103854fab2SYoungJun Cho { 811e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 8123854fab2SYoungJun Cho struct fimd_driver_data *driver_data = ctx->driver_data; 8133854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base; 8143854fab2SYoungJun Cho u32 reg; 8153854fab2SYoungJun Cho 8169b67eb73SJoonyoung Shim /* 8171c905d95SYoungJun Cho * Skips triggering if in triggering state, because multiple triggering 8189b67eb73SJoonyoung Shim * requests can cause panel reset. 8199b67eb73SJoonyoung Shim */ 8209b67eb73SJoonyoung Shim if (atomic_read(&ctx->triggering)) 8219b67eb73SJoonyoung Shim return; 8229b67eb73SJoonyoung Shim 8231c905d95SYoungJun Cho /* Enters triggering mode */ 8243854fab2SYoungJun Cho atomic_set(&ctx->triggering, 1); 8253854fab2SYoungJun Cho 8263854fab2SYoungJun Cho reg = readl(timing_base + TRIGCON); 8273854fab2SYoungJun Cho reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 8283854fab2SYoungJun Cho writel(reg, timing_base + TRIGCON); 82987ab85b3SYoungJun Cho 83087ab85b3SYoungJun Cho /* 83187ab85b3SYoungJun Cho * Exits triggering mode if vblank is not enabled yet, because when the 83287ab85b3SYoungJun Cho * VIDINTCON0 register is not set, it can not exit from triggering mode. 83387ab85b3SYoungJun Cho */ 83487ab85b3SYoungJun Cho if (!test_bit(0, &ctx->irq_flags)) 83587ab85b3SYoungJun Cho atomic_set(&ctx->triggering, 0); 8363854fab2SYoungJun Cho } 8373854fab2SYoungJun Cho 83893bca243SGustavo Padovan static void fimd_te_handler(struct exynos_drm_crtc *crtc) 8393854fab2SYoungJun Cho { 84093bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 8413854fab2SYoungJun Cho 8423854fab2SYoungJun Cho /* Checks the crtc is detached already from encoder */ 8433854fab2SYoungJun Cho if (ctx->pipe < 0 || !ctx->drm_dev) 8443854fab2SYoungJun Cho return; 8453854fab2SYoungJun Cho 8463854fab2SYoungJun Cho /* 8473854fab2SYoungJun Cho * If there is a page flip request, triggers and handles the page flip 8483854fab2SYoungJun Cho * event so that current fb can be updated into panel GRAM. 8493854fab2SYoungJun Cho */ 8503854fab2SYoungJun Cho if (atomic_add_unless(&ctx->win_updated, -1, 0)) 8513854fab2SYoungJun Cho fimd_trigger(ctx->dev); 8523854fab2SYoungJun Cho 8533854fab2SYoungJun Cho /* Wakes up vsync event queue */ 8543854fab2SYoungJun Cho if (atomic_read(&ctx->wait_vsync_event)) { 8553854fab2SYoungJun Cho atomic_set(&ctx->wait_vsync_event, 0); 8563854fab2SYoungJun Cho wake_up(&ctx->wait_vsync_queue); 857b301ae24SYoungJun Cho } 8583854fab2SYoungJun Cho 859adf67abfSJoonyoung Shim if (test_bit(0, &ctx->irq_flags)) 860eafd540aSGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base); 8613854fab2SYoungJun Cho } 8623854fab2SYoungJun Cho 86348107d7bSKrzysztof Kozlowski static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) 86448107d7bSKrzysztof Kozlowski { 86548107d7bSKrzysztof Kozlowski struct fimd_context *ctx = crtc->ctx; 86648107d7bSKrzysztof Kozlowski u32 val; 86748107d7bSKrzysztof Kozlowski 86848107d7bSKrzysztof Kozlowski /* 86948107d7bSKrzysztof Kozlowski * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE 87048107d7bSKrzysztof Kozlowski * clock. On these SoCs the bootloader may enable it but any 87148107d7bSKrzysztof Kozlowski * power domain off/on will reset it to disable state. 87248107d7bSKrzysztof Kozlowski */ 87348107d7bSKrzysztof Kozlowski if (ctx->driver_data != &exynos5_fimd_driver_data) 87448107d7bSKrzysztof Kozlowski return; 87548107d7bSKrzysztof Kozlowski 87648107d7bSKrzysztof Kozlowski val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 87748107d7bSKrzysztof Kozlowski writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); 87848107d7bSKrzysztof Kozlowski } 87948107d7bSKrzysztof Kozlowski 880f3aaf762SKrzysztof Kozlowski static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 8813cecda03SGustavo Padovan .enable = fimd_enable, 8823cecda03SGustavo Padovan .disable = fimd_disable, 883a968e727SSean Paul .mode_fixup = fimd_mode_fixup, 8841c6244c3SSean Paul .commit = fimd_commit, 8851c6244c3SSean Paul .enable_vblank = fimd_enable_vblank, 8861c6244c3SSean Paul .disable_vblank = fimd_disable_vblank, 8871c6244c3SSean Paul .wait_for_vblank = fimd_wait_for_vblank, 888ce3ff36bSGustavo Padovan .atomic_begin = fimd_atomic_begin, 8899cc7610aSGustavo Padovan .update_plane = fimd_update_plane, 8909cc7610aSGustavo Padovan .disable_plane = fimd_disable_plane, 891ce3ff36bSGustavo Padovan .atomic_flush = fimd_atomic_flush, 8923854fab2SYoungJun Cho .te_handler = fimd_te_handler, 89348107d7bSKrzysztof Kozlowski .clock_enable = fimd_dp_clock_enable, 8941c248b7dSInki Dae }; 8951c248b7dSInki Dae 8961c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 8971c248b7dSInki Dae { 8981c248b7dSInki Dae struct fimd_context *ctx = (struct fimd_context *)dev_id; 899cb11b3f1SGustavo Padovan u32 val, clear_bit, start, start_s; 900822f6dfdSGustavo Padovan int win; 9011c248b7dSInki Dae 9021c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON1); 9031c248b7dSInki Dae 9043854fab2SYoungJun Cho clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 9053854fab2SYoungJun Cho if (val & clear_bit) 9063854fab2SYoungJun Cho writel(clear_bit, ctx->regs + VIDINTCON1); 9071c248b7dSInki Dae 908ec05da95SInki Dae /* check the crtc is detached already from encoder */ 909080be03dSSean Paul if (ctx->pipe < 0 || !ctx->drm_dev) 910ec05da95SInki Dae goto out; 911483b88f8SInki Dae 912fc75f710SGustavo Padovan if (!ctx->i80_if) 913fc75f710SGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base); 914fc75f710SGustavo Padovan 915822f6dfdSGustavo Padovan for (win = 0 ; win < WINDOWS_NR ; win++) { 916822f6dfdSGustavo Padovan struct exynos_drm_plane *plane = &ctx->planes[win]; 917822f6dfdSGustavo Padovan 918822f6dfdSGustavo Padovan if (!plane->pending_fb) 919822f6dfdSGustavo Padovan continue; 920822f6dfdSGustavo Padovan 921cb11b3f1SGustavo Padovan start = readl(ctx->regs + VIDWx_BUF_START(win, 0)); 922cb11b3f1SGustavo Padovan start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0)); 923cb11b3f1SGustavo Padovan if (start == start_s) 924822f6dfdSGustavo Padovan exynos_drm_crtc_finish_update(ctx->crtc, plane); 925822f6dfdSGustavo Padovan } 9261c905d95SYoungJun Cho 927fc75f710SGustavo Padovan if (ctx->i80_if) { 9281c905d95SYoungJun Cho /* Exits triggering mode */ 9293854fab2SYoungJun Cho atomic_set(&ctx->triggering, 0); 9303854fab2SYoungJun Cho } else { 93101ce113cSPrathyush K /* set wait vsync event to zero and wake up queue. */ 93201ce113cSPrathyush K if (atomic_read(&ctx->wait_vsync_event)) { 93301ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0); 9348dd9ad5dSSeung-Woo Kim wake_up(&ctx->wait_vsync_queue); 93501ce113cSPrathyush K } 9363854fab2SYoungJun Cho } 9373854fab2SYoungJun Cho 938ec05da95SInki Dae out: 9391c248b7dSInki Dae return IRQ_HANDLED; 9401c248b7dSInki Dae } 9411c248b7dSInki Dae 942f37cd5e8SInki Dae static int fimd_bind(struct device *dev, struct device *master, void *data) 943562ad9f4SAndrzej Hajda { 944e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 945f37cd5e8SInki Dae struct drm_device *drm_dev = data; 946cdbfca89SHyungwon Hwang struct exynos_drm_private *priv = drm_dev->dev_private; 9477ee14cdcSGustavo Padovan struct exynos_drm_plane *exynos_plane; 9487ee14cdcSGustavo Padovan enum drm_plane_type type; 9496e2a3b66SGustavo Padovan unsigned int zpos; 9506e2a3b66SGustavo Padovan int ret; 951000cc920SAndrzej Hajda 952cdbfca89SHyungwon Hwang ctx->drm_dev = drm_dev; 953cdbfca89SHyungwon Hwang ctx->pipe = priv->pipe++; 954efa75bcdSAjay Kumar 9557ee14cdcSGustavo Padovan for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 9567ee14cdcSGustavo Padovan type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 9577ee14cdcSGustavo Padovan DRM_PLANE_TYPE_OVERLAY; 9587ee14cdcSGustavo Padovan ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 9596e2a3b66SGustavo Padovan 1 << ctx->pipe, type, zpos); 9607ee14cdcSGustavo Padovan if (ret) 9617ee14cdcSGustavo Padovan return ret; 9627ee14cdcSGustavo Padovan } 9637ee14cdcSGustavo Padovan 9647ee14cdcSGustavo Padovan exynos_plane = &ctx->planes[ctx->default_win]; 9657ee14cdcSGustavo Padovan ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 9667ee14cdcSGustavo Padovan ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 9670f04cf8dSJoonyoung Shim &fimd_crtc_ops, ctx); 968d1222842SHyungwon Hwang if (IS_ERR(ctx->crtc)) 969d1222842SHyungwon Hwang return PTR_ERR(ctx->crtc); 97093bca243SGustavo Padovan 971cf67cc9aSGustavo Padovan if (ctx->encoder) 972a2986e80SGustavo Padovan exynos_dpi_bind(drm_dev, ctx->encoder); 973000cc920SAndrzej Hajda 97443a3b866SJoonyoung Shim if (is_drm_iommu_supported(drm_dev)) 975eb7a3fc7SJoonyoung Shim fimd_clear_channels(ctx->crtc); 976eb7a3fc7SJoonyoung Shim 977eb7a3fc7SJoonyoung Shim ret = drm_iommu_attach_device(drm_dev, dev); 978fc2e013fSHyungwon Hwang if (ret) 979fc2e013fSHyungwon Hwang priv->pipe--; 980fc2e013fSHyungwon Hwang 981fc2e013fSHyungwon Hwang return ret; 982000cc920SAndrzej Hajda } 983000cc920SAndrzej Hajda 984000cc920SAndrzej Hajda static void fimd_unbind(struct device *dev, struct device *master, 985000cc920SAndrzej Hajda void *data) 986000cc920SAndrzej Hajda { 987e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 988000cc920SAndrzej Hajda 9893cecda03SGustavo Padovan fimd_disable(ctx->crtc); 990000cc920SAndrzej Hajda 991bf56608aSJoonyoung Shim drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 992cdbfca89SHyungwon Hwang 993cf67cc9aSGustavo Padovan if (ctx->encoder) 994cf67cc9aSGustavo Padovan exynos_dpi_remove(ctx->encoder); 995000cc920SAndrzej Hajda } 996000cc920SAndrzej Hajda 997000cc920SAndrzej Hajda static const struct component_ops fimd_component_ops = { 998000cc920SAndrzej Hajda .bind = fimd_bind, 999000cc920SAndrzej Hajda .unbind = fimd_unbind, 1000000cc920SAndrzej Hajda }; 1001000cc920SAndrzej Hajda 1002000cc920SAndrzej Hajda static int fimd_probe(struct platform_device *pdev) 1003000cc920SAndrzej Hajda { 1004000cc920SAndrzej Hajda struct device *dev = &pdev->dev; 1005000cc920SAndrzej Hajda struct fimd_context *ctx; 10063854fab2SYoungJun Cho struct device_node *i80_if_timings; 1007000cc920SAndrzej Hajda struct resource *res; 1008fe42cfb4SGustavo Padovan int ret; 1009562ad9f4SAndrzej Hajda 1010e152dbd7SAndrzej Hajda if (!dev->of_node) 1011e152dbd7SAndrzej Hajda return -ENODEV; 10122d3f173cSSachin Kamat 1013d873ab99SSeung-Woo Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1014e152dbd7SAndrzej Hajda if (!ctx) 1015e152dbd7SAndrzej Hajda return -ENOMEM; 1016e152dbd7SAndrzej Hajda 1017bb7704d6SSean Paul ctx->dev = dev; 1018a43b933bSSean Paul ctx->suspended = true; 10193854fab2SYoungJun Cho ctx->driver_data = drm_fimd_get_driver_data(pdev); 1020bb7704d6SSean Paul 10211417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 10221417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VDEN; 10231417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 10241417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VCLK; 1025562ad9f4SAndrzej Hajda 10263854fab2SYoungJun Cho i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 10273854fab2SYoungJun Cho if (i80_if_timings) { 10283854fab2SYoungJun Cho u32 val; 10293854fab2SYoungJun Cho 10303854fab2SYoungJun Cho ctx->i80_if = true; 10313854fab2SYoungJun Cho 10323854fab2SYoungJun Cho if (ctx->driver_data->has_vidoutcon) 10333854fab2SYoungJun Cho ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 10343854fab2SYoungJun Cho else 10353854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 10363854fab2SYoungJun Cho /* 10373854fab2SYoungJun Cho * The user manual describes that this "DSI_EN" bit is required 10383854fab2SYoungJun Cho * to enable I80 24-bit data interface. 10393854fab2SYoungJun Cho */ 10403854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_DSI_EN; 10413854fab2SYoungJun Cho 10423854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 10433854fab2SYoungJun Cho val = 0; 10443854fab2SYoungJun Cho ctx->i80ifcon = LCD_CS_SETUP(val); 10453854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 10463854fab2SYoungJun Cho val = 0; 10473854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_SETUP(val); 10483854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 10493854fab2SYoungJun Cho val = 1; 10503854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_ACTIVE(val); 10513854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 10523854fab2SYoungJun Cho val = 0; 10533854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_HOLD(val); 10543854fab2SYoungJun Cho } 10553854fab2SYoungJun Cho of_node_put(i80_if_timings); 10563854fab2SYoungJun Cho 10573854fab2SYoungJun Cho ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 10583854fab2SYoungJun Cho "samsung,sysreg"); 10593854fab2SYoungJun Cho if (IS_ERR(ctx->sysreg)) { 10603854fab2SYoungJun Cho dev_warn(dev, "failed to get system register.\n"); 10613854fab2SYoungJun Cho ctx->sysreg = NULL; 10623854fab2SYoungJun Cho } 10633854fab2SYoungJun Cho 1064a968e727SSean Paul ctx->bus_clk = devm_clk_get(dev, "fimd"); 1065a968e727SSean Paul if (IS_ERR(ctx->bus_clk)) { 1066a968e727SSean Paul dev_err(dev, "failed to get bus clock\n"); 106786650408SAndrzej Hajda return PTR_ERR(ctx->bus_clk); 1068a968e727SSean Paul } 1069a968e727SSean Paul 1070a968e727SSean Paul ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1071a968e727SSean Paul if (IS_ERR(ctx->lcd_clk)) { 1072a968e727SSean Paul dev_err(dev, "failed to get lcd clock\n"); 107386650408SAndrzej Hajda return PTR_ERR(ctx->lcd_clk); 1074a968e727SSean Paul } 10751c248b7dSInki Dae 10761c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 10771c248b7dSInki Dae 1078d873ab99SSeung-Woo Kim ctx->regs = devm_ioremap_resource(dev, res); 107986650408SAndrzej Hajda if (IS_ERR(ctx->regs)) 108086650408SAndrzej Hajda return PTR_ERR(ctx->regs); 10811c248b7dSInki Dae 10823854fab2SYoungJun Cho res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 10833854fab2SYoungJun Cho ctx->i80_if ? "lcd_sys" : "vsync"); 10841c248b7dSInki Dae if (!res) { 10851c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 108686650408SAndrzej Hajda return -ENXIO; 10871c248b7dSInki Dae } 10881c248b7dSInki Dae 1089055e0c06SSean Paul ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1090edc57266SSachin Kamat 0, "drm_fimd", ctx); 1091edc57266SSachin Kamat if (ret) { 10921c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 109386650408SAndrzej Hajda return ret; 10941c248b7dSInki Dae } 10951c248b7dSInki Dae 109657ed0f7bSDaniel Vetter init_waitqueue_head(&ctx->wait_vsync_queue); 109701ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0); 10981c248b7dSInki Dae 1099e152dbd7SAndrzej Hajda platform_set_drvdata(pdev, ctx); 1100080be03dSSean Paul 1101cf67cc9aSGustavo Padovan ctx->encoder = exynos_dpi_probe(dev); 1102cf67cc9aSGustavo Padovan if (IS_ERR(ctx->encoder)) 1103cf67cc9aSGustavo Padovan return PTR_ERR(ctx->encoder); 1104f37cd5e8SInki Dae 1105e152dbd7SAndrzej Hajda pm_runtime_enable(dev); 1106f37cd5e8SInki Dae 1107e152dbd7SAndrzej Hajda ret = component_add(dev, &fimd_component_ops); 1108df5225bcSInki Dae if (ret) 1109df5225bcSInki Dae goto err_disable_pm_runtime; 1110df5225bcSInki Dae 1111df5225bcSInki Dae return ret; 1112df5225bcSInki Dae 1113df5225bcSInki Dae err_disable_pm_runtime: 1114e152dbd7SAndrzej Hajda pm_runtime_disable(dev); 1115df5225bcSInki Dae 1116df5225bcSInki Dae return ret; 1117f37cd5e8SInki Dae } 1118f37cd5e8SInki Dae 1119f37cd5e8SInki Dae static int fimd_remove(struct platform_device *pdev) 1120f37cd5e8SInki Dae { 1121af65c804SSean Paul pm_runtime_disable(&pdev->dev); 1122cb91f6a0SJoonyoung Shim 1123df5225bcSInki Dae component_del(&pdev->dev, &fimd_component_ops); 1124df5225bcSInki Dae 11251c248b7dSInki Dae return 0; 11261c248b7dSInki Dae } 11271c248b7dSInki Dae 1128132a5b91SJoonyoung Shim struct platform_driver fimd_driver = { 11291c248b7dSInki Dae .probe = fimd_probe, 113056550d94SGreg Kroah-Hartman .remove = fimd_remove, 11311c248b7dSInki Dae .driver = { 11321c248b7dSInki Dae .name = "exynos4-fb", 11331c248b7dSInki Dae .owner = THIS_MODULE, 11342d3f173cSSachin Kamat .of_match_table = fimd_driver_dt_match, 11351c248b7dSInki Dae }, 11361c248b7dSInki Dae }; 1137