11c248b7dSInki Dae /* exynos_drm_fimd.c 21c248b7dSInki Dae * 31c248b7dSInki Dae * Copyright (C) 2011 Samsung Electronics Co.Ltd 41c248b7dSInki Dae * Authors: 51c248b7dSInki Dae * Joonyoung Shim <jy0922.shim@samsung.com> 61c248b7dSInki Dae * Inki Dae <inki.dae@samsung.com> 71c248b7dSInki Dae * 81c248b7dSInki Dae * This program is free software; you can redistribute it and/or modify it 91c248b7dSInki Dae * under the terms of the GNU General Public License as published by the 101c248b7dSInki Dae * Free Software Foundation; either version 2 of the License, or (at your 111c248b7dSInki Dae * option) any later version. 121c248b7dSInki Dae * 131c248b7dSInki Dae */ 141c248b7dSInki Dae #include "drmP.h" 151c248b7dSInki Dae 161c248b7dSInki Dae #include <linux/kernel.h> 171c248b7dSInki Dae #include <linux/module.h> 181c248b7dSInki Dae #include <linux/platform_device.h> 191c248b7dSInki Dae #include <linux/clk.h> 20cb91f6a0SJoonyoung Shim #include <linux/pm_runtime.h> 211c248b7dSInki Dae 221c248b7dSInki Dae #include <drm/exynos_drm.h> 231c248b7dSInki Dae #include <plat/regs-fb-v4.h> 241c248b7dSInki Dae 251c248b7dSInki Dae #include "exynos_drm_drv.h" 261c248b7dSInki Dae #include "exynos_drm_fbdev.h" 271c248b7dSInki Dae #include "exynos_drm_crtc.h" 281c248b7dSInki Dae 291c248b7dSInki Dae /* 301c248b7dSInki Dae * FIMD is stand for Fully Interactive Mobile Display and 311c248b7dSInki Dae * as a display controller, it transfers contents drawn on memory 321c248b7dSInki Dae * to a LCD Panel through Display Interfaces such as RGB or 331c248b7dSInki Dae * CPU Interface. 341c248b7dSInki Dae */ 351c248b7dSInki Dae 361c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/ 371c248b7dSInki Dae #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 381c248b7dSInki Dae #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 391c248b7dSInki Dae /* size control register for hardware window 0. */ 401c248b7dSInki Dae #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08) 411c248b7dSInki Dae /* alpha control register for hardware window 1 ~ 4. */ 421c248b7dSInki Dae #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16) 431c248b7dSInki Dae /* size control register for hardware window 1 ~ 4. */ 441c248b7dSInki Dae #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 451c248b7dSInki Dae 461c248b7dSInki Dae #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 471c248b7dSInki Dae #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 481c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 491c248b7dSInki Dae 501c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */ 511c248b7dSInki Dae #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8)) 521c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */ 531c248b7dSInki Dae #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8)) 541c248b7dSInki Dae 551c248b7dSInki Dae /* FIMD has totally five hardware windows. */ 561c248b7dSInki Dae #define WINDOWS_NR 5 571c248b7dSInki Dae 581c248b7dSInki Dae #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) 591c248b7dSInki Dae 601c248b7dSInki Dae struct fimd_win_data { 611c248b7dSInki Dae unsigned int offset_x; 621c248b7dSInki Dae unsigned int offset_y; 6319c8b834SInki Dae unsigned int ovl_width; 6419c8b834SInki Dae unsigned int ovl_height; 6519c8b834SInki Dae unsigned int fb_width; 6619c8b834SInki Dae unsigned int fb_height; 671c248b7dSInki Dae unsigned int bpp; 682c871127SInki Dae dma_addr_t dma_addr; 691c248b7dSInki Dae void __iomem *vaddr; 701c248b7dSInki Dae unsigned int buf_offsize; 711c248b7dSInki Dae unsigned int line_size; /* bytes */ 72ec05da95SInki Dae bool enabled; 731c248b7dSInki Dae }; 741c248b7dSInki Dae 751c248b7dSInki Dae struct fimd_context { 761c248b7dSInki Dae struct exynos_drm_subdrv subdrv; 771c248b7dSInki Dae int irq; 781c248b7dSInki Dae struct drm_crtc *crtc; 791c248b7dSInki Dae struct clk *bus_clk; 801c248b7dSInki Dae struct clk *lcd_clk; 811c248b7dSInki Dae struct resource *regs_res; 821c248b7dSInki Dae void __iomem *regs; 831c248b7dSInki Dae struct fimd_win_data win_data[WINDOWS_NR]; 841c248b7dSInki Dae unsigned int clkdiv; 851c248b7dSInki Dae unsigned int default_win; 861c248b7dSInki Dae unsigned long irq_flags; 871c248b7dSInki Dae u32 vidcon0; 881c248b7dSInki Dae u32 vidcon1; 89cb91f6a0SJoonyoung Shim bool suspended; 901c248b7dSInki Dae 911c248b7dSInki Dae struct fb_videomode *timing; 921c248b7dSInki Dae }; 931c248b7dSInki Dae 941c248b7dSInki Dae static bool fimd_display_is_connected(struct device *dev) 951c248b7dSInki Dae { 961c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 971c248b7dSInki Dae 981c248b7dSInki Dae /* TODO. */ 991c248b7dSInki Dae 1001c248b7dSInki Dae return true; 1011c248b7dSInki Dae } 1021c248b7dSInki Dae 1031c248b7dSInki Dae static void *fimd_get_timing(struct device *dev) 1041c248b7dSInki Dae { 1051c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 1061c248b7dSInki Dae 1071c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1081c248b7dSInki Dae 1091c248b7dSInki Dae return ctx->timing; 1101c248b7dSInki Dae } 1111c248b7dSInki Dae 1121c248b7dSInki Dae static int fimd_check_timing(struct device *dev, void *timing) 1131c248b7dSInki Dae { 1141c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1151c248b7dSInki Dae 1161c248b7dSInki Dae /* TODO. */ 1171c248b7dSInki Dae 1181c248b7dSInki Dae return 0; 1191c248b7dSInki Dae } 1201c248b7dSInki Dae 1211c248b7dSInki Dae static int fimd_display_power_on(struct device *dev, int mode) 1221c248b7dSInki Dae { 1231c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1241c248b7dSInki Dae 125ec05da95SInki Dae /* TODO */ 1261c248b7dSInki Dae 1271c248b7dSInki Dae return 0; 1281c248b7dSInki Dae } 1291c248b7dSInki Dae 13074ccc539SInki Dae static struct exynos_drm_display_ops fimd_display_ops = { 1311c248b7dSInki Dae .type = EXYNOS_DISPLAY_TYPE_LCD, 1321c248b7dSInki Dae .is_connected = fimd_display_is_connected, 1331c248b7dSInki Dae .get_timing = fimd_get_timing, 1341c248b7dSInki Dae .check_timing = fimd_check_timing, 1351c248b7dSInki Dae .power_on = fimd_display_power_on, 1361c248b7dSInki Dae }; 1371c248b7dSInki Dae 138ec05da95SInki Dae static void fimd_dpms(struct device *subdrv_dev, int mode) 139ec05da95SInki Dae { 140ec05da95SInki Dae DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); 141ec05da95SInki Dae 142cb91f6a0SJoonyoung Shim switch (mode) { 143cb91f6a0SJoonyoung Shim case DRM_MODE_DPMS_ON: 144cb91f6a0SJoonyoung Shim pm_runtime_get_sync(subdrv_dev); 145cb91f6a0SJoonyoung Shim break; 146cb91f6a0SJoonyoung Shim case DRM_MODE_DPMS_STANDBY: 147cb91f6a0SJoonyoung Shim case DRM_MODE_DPMS_SUSPEND: 148cb91f6a0SJoonyoung Shim case DRM_MODE_DPMS_OFF: 149cb91f6a0SJoonyoung Shim pm_runtime_put_sync(subdrv_dev); 150cb91f6a0SJoonyoung Shim break; 151cb91f6a0SJoonyoung Shim default: 152cb91f6a0SJoonyoung Shim DRM_DEBUG_KMS("unspecified mode %d\n", mode); 153cb91f6a0SJoonyoung Shim break; 154cb91f6a0SJoonyoung Shim } 155ec05da95SInki Dae } 156ec05da95SInki Dae 157ec05da95SInki Dae static void fimd_apply(struct device *subdrv_dev) 158ec05da95SInki Dae { 159ec05da95SInki Dae struct fimd_context *ctx = get_fimd_context(subdrv_dev); 160ec05da95SInki Dae struct exynos_drm_manager *mgr = &ctx->subdrv.manager; 161ec05da95SInki Dae struct exynos_drm_manager_ops *mgr_ops = mgr->ops; 162ec05da95SInki Dae struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops; 163ec05da95SInki Dae struct fimd_win_data *win_data; 164864ee9e6SJoonyoung Shim int i; 165ec05da95SInki Dae 166ec05da95SInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 167ec05da95SInki Dae 168864ee9e6SJoonyoung Shim for (i = 0; i < WINDOWS_NR; i++) { 169864ee9e6SJoonyoung Shim win_data = &ctx->win_data[i]; 170ec05da95SInki Dae if (win_data->enabled && (ovl_ops && ovl_ops->commit)) 171864ee9e6SJoonyoung Shim ovl_ops->commit(subdrv_dev, i); 172864ee9e6SJoonyoung Shim } 173ec05da95SInki Dae 174ec05da95SInki Dae if (mgr_ops && mgr_ops->commit) 175ec05da95SInki Dae mgr_ops->commit(subdrv_dev); 176ec05da95SInki Dae } 177ec05da95SInki Dae 1781c248b7dSInki Dae static void fimd_commit(struct device *dev) 1791c248b7dSInki Dae { 1801c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 1811c248b7dSInki Dae struct fb_videomode *timing = ctx->timing; 1821c248b7dSInki Dae u32 val; 1831c248b7dSInki Dae 1841c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1851c248b7dSInki Dae 1861c248b7dSInki Dae /* setup polarity values from machine code. */ 1871c248b7dSInki Dae writel(ctx->vidcon1, ctx->regs + VIDCON1); 1881c248b7dSInki Dae 1891c248b7dSInki Dae /* setup vertical timing values. */ 1901c248b7dSInki Dae val = VIDTCON0_VBPD(timing->upper_margin - 1) | 1911c248b7dSInki Dae VIDTCON0_VFPD(timing->lower_margin - 1) | 1921c248b7dSInki Dae VIDTCON0_VSPW(timing->vsync_len - 1); 1931c248b7dSInki Dae writel(val, ctx->regs + VIDTCON0); 1941c248b7dSInki Dae 1951c248b7dSInki Dae /* setup horizontal timing values. */ 1961c248b7dSInki Dae val = VIDTCON1_HBPD(timing->left_margin - 1) | 1971c248b7dSInki Dae VIDTCON1_HFPD(timing->right_margin - 1) | 1981c248b7dSInki Dae VIDTCON1_HSPW(timing->hsync_len - 1); 1991c248b7dSInki Dae writel(val, ctx->regs + VIDTCON1); 2001c248b7dSInki Dae 2011c248b7dSInki Dae /* setup horizontal and vertical display size. */ 2021c248b7dSInki Dae val = VIDTCON2_LINEVAL(timing->yres - 1) | 2031c248b7dSInki Dae VIDTCON2_HOZVAL(timing->xres - 1); 2041c248b7dSInki Dae writel(val, ctx->regs + VIDTCON2); 2051c248b7dSInki Dae 2061c248b7dSInki Dae /* setup clock source, clock divider, enable dma. */ 2071c248b7dSInki Dae val = ctx->vidcon0; 2081c248b7dSInki Dae val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); 2091c248b7dSInki Dae 2101c248b7dSInki Dae if (ctx->clkdiv > 1) 2111c248b7dSInki Dae val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; 2121c248b7dSInki Dae else 2131c248b7dSInki Dae val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ 2141c248b7dSInki Dae 2151c248b7dSInki Dae /* 2161c248b7dSInki Dae * fields of register with prefix '_F' would be updated 2171c248b7dSInki Dae * at vsync(same as dma start) 2181c248b7dSInki Dae */ 2191c248b7dSInki Dae val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 2201c248b7dSInki Dae writel(val, ctx->regs + VIDCON0); 2211c248b7dSInki Dae } 2221c248b7dSInki Dae 2231c248b7dSInki Dae static int fimd_enable_vblank(struct device *dev) 2241c248b7dSInki Dae { 2251c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 2261c248b7dSInki Dae u32 val; 2271c248b7dSInki Dae 2281c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 2291c248b7dSInki Dae 230cb91f6a0SJoonyoung Shim if (ctx->suspended) 231cb91f6a0SJoonyoung Shim return -EPERM; 232cb91f6a0SJoonyoung Shim 2331c248b7dSInki Dae if (!test_and_set_bit(0, &ctx->irq_flags)) { 2341c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON0); 2351c248b7dSInki Dae 2361c248b7dSInki Dae val |= VIDINTCON0_INT_ENABLE; 2371c248b7dSInki Dae val |= VIDINTCON0_INT_FRAME; 2381c248b7dSInki Dae 2391c248b7dSInki Dae val &= ~VIDINTCON0_FRAMESEL0_MASK; 2401c248b7dSInki Dae val |= VIDINTCON0_FRAMESEL0_VSYNC; 2411c248b7dSInki Dae val &= ~VIDINTCON0_FRAMESEL1_MASK; 2421c248b7dSInki Dae val |= VIDINTCON0_FRAMESEL1_NONE; 2431c248b7dSInki Dae 2441c248b7dSInki Dae writel(val, ctx->regs + VIDINTCON0); 2451c248b7dSInki Dae } 2461c248b7dSInki Dae 2471c248b7dSInki Dae return 0; 2481c248b7dSInki Dae } 2491c248b7dSInki Dae 2501c248b7dSInki Dae static void fimd_disable_vblank(struct device *dev) 2511c248b7dSInki Dae { 2521c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 2531c248b7dSInki Dae u32 val; 2541c248b7dSInki Dae 2551c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 2561c248b7dSInki Dae 257cb91f6a0SJoonyoung Shim if (ctx->suspended) 258cb91f6a0SJoonyoung Shim return; 259cb91f6a0SJoonyoung Shim 2601c248b7dSInki Dae if (test_and_clear_bit(0, &ctx->irq_flags)) { 2611c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON0); 2621c248b7dSInki Dae 2631c248b7dSInki Dae val &= ~VIDINTCON0_INT_FRAME; 2641c248b7dSInki Dae val &= ~VIDINTCON0_INT_ENABLE; 2651c248b7dSInki Dae 2661c248b7dSInki Dae writel(val, ctx->regs + VIDINTCON0); 2671c248b7dSInki Dae } 2681c248b7dSInki Dae } 2691c248b7dSInki Dae 2701c248b7dSInki Dae static struct exynos_drm_manager_ops fimd_manager_ops = { 271ec05da95SInki Dae .dpms = fimd_dpms, 272ec05da95SInki Dae .apply = fimd_apply, 2731c248b7dSInki Dae .commit = fimd_commit, 2741c248b7dSInki Dae .enable_vblank = fimd_enable_vblank, 2751c248b7dSInki Dae .disable_vblank = fimd_disable_vblank, 2761c248b7dSInki Dae }; 2771c248b7dSInki Dae 2781c248b7dSInki Dae static void fimd_win_mode_set(struct device *dev, 2791c248b7dSInki Dae struct exynos_drm_overlay *overlay) 2801c248b7dSInki Dae { 2811c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 2821c248b7dSInki Dae struct fimd_win_data *win_data; 283864ee9e6SJoonyoung Shim int win; 28419c8b834SInki Dae unsigned long offset; 2851c248b7dSInki Dae 2861c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 2871c248b7dSInki Dae 2881c248b7dSInki Dae if (!overlay) { 2891c248b7dSInki Dae dev_err(dev, "overlay is NULL\n"); 2901c248b7dSInki Dae return; 2911c248b7dSInki Dae } 2921c248b7dSInki Dae 293864ee9e6SJoonyoung Shim win = overlay->zpos; 294864ee9e6SJoonyoung Shim if (win == DEFAULT_ZPOS) 295864ee9e6SJoonyoung Shim win = ctx->default_win; 296864ee9e6SJoonyoung Shim 297864ee9e6SJoonyoung Shim if (win < 0 || win > WINDOWS_NR) 298864ee9e6SJoonyoung Shim return; 299864ee9e6SJoonyoung Shim 30019c8b834SInki Dae offset = overlay->fb_x * (overlay->bpp >> 3); 30119c8b834SInki Dae offset += overlay->fb_y * overlay->pitch; 30219c8b834SInki Dae 30319c8b834SInki Dae DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); 30419c8b834SInki Dae 305864ee9e6SJoonyoung Shim win_data = &ctx->win_data[win]; 3061c248b7dSInki Dae 30719c8b834SInki Dae win_data->offset_x = overlay->crtc_x; 30819c8b834SInki Dae win_data->offset_y = overlay->crtc_y; 30919c8b834SInki Dae win_data->ovl_width = overlay->crtc_width; 31019c8b834SInki Dae win_data->ovl_height = overlay->crtc_height; 31119c8b834SInki Dae win_data->fb_width = overlay->fb_width; 31219c8b834SInki Dae win_data->fb_height = overlay->fb_height; 3132c871127SInki Dae win_data->dma_addr = overlay->dma_addr + offset; 31419c8b834SInki Dae win_data->vaddr = overlay->vaddr + offset; 3151c248b7dSInki Dae win_data->bpp = overlay->bpp; 31619c8b834SInki Dae win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * 31719c8b834SInki Dae (overlay->bpp >> 3); 31819c8b834SInki Dae win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); 31919c8b834SInki Dae 32019c8b834SInki Dae DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", 32119c8b834SInki Dae win_data->offset_x, win_data->offset_y); 32219c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 32319c8b834SInki Dae win_data->ovl_width, win_data->ovl_height); 32419c8b834SInki Dae DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n", 3252c871127SInki Dae (unsigned long)win_data->dma_addr, 32619c8b834SInki Dae (unsigned long)win_data->vaddr); 32719c8b834SInki Dae DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", 32819c8b834SInki Dae overlay->fb_width, overlay->crtc_width); 3291c248b7dSInki Dae } 3301c248b7dSInki Dae 3311c248b7dSInki Dae static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) 3321c248b7dSInki Dae { 3331c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 3341c248b7dSInki Dae struct fimd_win_data *win_data = &ctx->win_data[win]; 3351c248b7dSInki Dae unsigned long val; 3361c248b7dSInki Dae 3371c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 3381c248b7dSInki Dae 3391c248b7dSInki Dae val = WINCONx_ENWIN; 3401c248b7dSInki Dae 3411c248b7dSInki Dae switch (win_data->bpp) { 3421c248b7dSInki Dae case 1: 3431c248b7dSInki Dae val |= WINCON0_BPPMODE_1BPP; 3441c248b7dSInki Dae val |= WINCONx_BITSWP; 3451c248b7dSInki Dae val |= WINCONx_BURSTLEN_4WORD; 3461c248b7dSInki Dae break; 3471c248b7dSInki Dae case 2: 3481c248b7dSInki Dae val |= WINCON0_BPPMODE_2BPP; 3491c248b7dSInki Dae val |= WINCONx_BITSWP; 3501c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 3511c248b7dSInki Dae break; 3521c248b7dSInki Dae case 4: 3531c248b7dSInki Dae val |= WINCON0_BPPMODE_4BPP; 3541c248b7dSInki Dae val |= WINCONx_BITSWP; 3551c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 3561c248b7dSInki Dae break; 3571c248b7dSInki Dae case 8: 3581c248b7dSInki Dae val |= WINCON0_BPPMODE_8BPP_PALETTE; 3591c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 3601c248b7dSInki Dae val |= WINCONx_BYTSWP; 3611c248b7dSInki Dae break; 3621c248b7dSInki Dae case 16: 3631c248b7dSInki Dae val |= WINCON0_BPPMODE_16BPP_565; 3641c248b7dSInki Dae val |= WINCONx_HAWSWP; 3651c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3661c248b7dSInki Dae break; 3671c248b7dSInki Dae case 24: 3681c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 3691c248b7dSInki Dae val |= WINCONx_WSWP; 3701c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3711c248b7dSInki Dae break; 3721c248b7dSInki Dae case 32: 3731c248b7dSInki Dae val |= WINCON1_BPPMODE_28BPP_A4888 3741c248b7dSInki Dae | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 3751c248b7dSInki Dae val |= WINCONx_WSWP; 3761c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3771c248b7dSInki Dae break; 3781c248b7dSInki Dae default: 3791c248b7dSInki Dae DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 3801c248b7dSInki Dae 3811c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 3821c248b7dSInki Dae val |= WINCONx_WSWP; 3831c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3841c248b7dSInki Dae break; 3851c248b7dSInki Dae } 3861c248b7dSInki Dae 3871c248b7dSInki Dae DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); 3881c248b7dSInki Dae 3891c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 3901c248b7dSInki Dae } 3911c248b7dSInki Dae 3921c248b7dSInki Dae static void fimd_win_set_colkey(struct device *dev, unsigned int win) 3931c248b7dSInki Dae { 3941c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 3951c248b7dSInki Dae unsigned int keycon0 = 0, keycon1 = 0; 3961c248b7dSInki Dae 3971c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 3981c248b7dSInki Dae 3991c248b7dSInki Dae keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 4001c248b7dSInki Dae WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 4011c248b7dSInki Dae 4021c248b7dSInki Dae keycon1 = WxKEYCON1_COLVAL(0xffffffff); 4031c248b7dSInki Dae 4041c248b7dSInki Dae writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 4051c248b7dSInki Dae writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 4061c248b7dSInki Dae } 4071c248b7dSInki Dae 408864ee9e6SJoonyoung Shim static void fimd_win_commit(struct device *dev, int zpos) 4091c248b7dSInki Dae { 4101c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 4111c248b7dSInki Dae struct fimd_win_data *win_data; 412864ee9e6SJoonyoung Shim int win = zpos; 4131c248b7dSInki Dae unsigned long val, alpha, size; 4141c248b7dSInki Dae 4151c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 4161c248b7dSInki Dae 417864ee9e6SJoonyoung Shim if (win == DEFAULT_ZPOS) 418864ee9e6SJoonyoung Shim win = ctx->default_win; 419864ee9e6SJoonyoung Shim 4201c248b7dSInki Dae if (win < 0 || win > WINDOWS_NR) 4211c248b7dSInki Dae return; 4221c248b7dSInki Dae 4231c248b7dSInki Dae win_data = &ctx->win_data[win]; 4241c248b7dSInki Dae 4251c248b7dSInki Dae /* 4261c248b7dSInki Dae * SHADOWCON register is used for enabling timing. 4271c248b7dSInki Dae * 4281c248b7dSInki Dae * for example, once only width value of a register is set, 4291c248b7dSInki Dae * if the dma is started then fimd hardware could malfunction so 4301c248b7dSInki Dae * with protect window setting, the register fields with prefix '_F' 4311c248b7dSInki Dae * wouldn't be updated at vsync also but updated once unprotect window 4321c248b7dSInki Dae * is set. 4331c248b7dSInki Dae */ 4341c248b7dSInki Dae 4351c248b7dSInki Dae /* protect windows */ 4361c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 4371c248b7dSInki Dae val |= SHADOWCON_WINx_PROTECT(win); 4381c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 4391c248b7dSInki Dae 4401c248b7dSInki Dae /* buffer start address */ 4412c871127SInki Dae val = (unsigned long)win_data->dma_addr; 4421c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 4431c248b7dSInki Dae 4441c248b7dSInki Dae /* buffer end address */ 44519c8b834SInki Dae size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); 4462c871127SInki Dae val = (unsigned long)(win_data->dma_addr + size); 4471c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 4481c248b7dSInki Dae 4491c248b7dSInki Dae DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 4502c871127SInki Dae (unsigned long)win_data->dma_addr, val, size); 45119c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 45219c8b834SInki Dae win_data->ovl_width, win_data->ovl_height); 4531c248b7dSInki Dae 4541c248b7dSInki Dae /* buffer size */ 4551c248b7dSInki Dae val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | 4561c248b7dSInki Dae VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size); 4571c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 4581c248b7dSInki Dae 4591c248b7dSInki Dae /* OSD position */ 4601c248b7dSInki Dae val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | 4611c248b7dSInki Dae VIDOSDxA_TOPLEFT_Y(win_data->offset_y); 4621c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_A(win)); 4631c248b7dSInki Dae 46419c8b834SInki Dae val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x + 46519c8b834SInki Dae win_data->ovl_width - 1) | 46619c8b834SInki Dae VIDOSDxB_BOTRIGHT_Y(win_data->offset_y + 46719c8b834SInki Dae win_data->ovl_height - 1); 4681c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_B(win)); 4691c248b7dSInki Dae 47019c8b834SInki Dae DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 4711c248b7dSInki Dae win_data->offset_x, win_data->offset_y, 47219c8b834SInki Dae win_data->offset_x + win_data->ovl_width - 1, 47319c8b834SInki Dae win_data->offset_y + win_data->ovl_height - 1); 4741c248b7dSInki Dae 4751c248b7dSInki Dae /* hardware window 0 doesn't support alpha channel. */ 4761c248b7dSInki Dae if (win != 0) { 4771c248b7dSInki Dae /* OSD alpha */ 4781c248b7dSInki Dae alpha = VIDISD14C_ALPHA1_R(0xf) | 4791c248b7dSInki Dae VIDISD14C_ALPHA1_G(0xf) | 4801c248b7dSInki Dae VIDISD14C_ALPHA1_B(0xf); 4811c248b7dSInki Dae 4821c248b7dSInki Dae writel(alpha, ctx->regs + VIDOSD_C(win)); 4831c248b7dSInki Dae } 4841c248b7dSInki Dae 4851c248b7dSInki Dae /* OSD size */ 4861c248b7dSInki Dae if (win != 3 && win != 4) { 4871c248b7dSInki Dae u32 offset = VIDOSD_D(win); 4881c248b7dSInki Dae if (win == 0) 4891c248b7dSInki Dae offset = VIDOSD_C_SIZE_W0; 49019c8b834SInki Dae val = win_data->ovl_width * win_data->ovl_height; 4911c248b7dSInki Dae writel(val, ctx->regs + offset); 4921c248b7dSInki Dae 4931c248b7dSInki Dae DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 4941c248b7dSInki Dae } 4951c248b7dSInki Dae 4961c248b7dSInki Dae fimd_win_set_pixfmt(dev, win); 4971c248b7dSInki Dae 4981c248b7dSInki Dae /* hardware window 0 doesn't support color key. */ 4991c248b7dSInki Dae if (win != 0) 5001c248b7dSInki Dae fimd_win_set_colkey(dev, win); 5011c248b7dSInki Dae 502ec05da95SInki Dae /* wincon */ 503ec05da95SInki Dae val = readl(ctx->regs + WINCON(win)); 504ec05da95SInki Dae val |= WINCONx_ENWIN; 505ec05da95SInki Dae writel(val, ctx->regs + WINCON(win)); 506ec05da95SInki Dae 5071c248b7dSInki Dae /* Enable DMA channel and unprotect windows */ 5081c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 5091c248b7dSInki Dae val |= SHADOWCON_CHx_ENABLE(win); 5101c248b7dSInki Dae val &= ~SHADOWCON_WINx_PROTECT(win); 5111c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 512ec05da95SInki Dae 513ec05da95SInki Dae win_data->enabled = true; 5141c248b7dSInki Dae } 5151c248b7dSInki Dae 516864ee9e6SJoonyoung Shim static void fimd_win_disable(struct device *dev, int zpos) 5171c248b7dSInki Dae { 5181c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 519ec05da95SInki Dae struct fimd_win_data *win_data; 520864ee9e6SJoonyoung Shim int win = zpos; 5211c248b7dSInki Dae u32 val; 5221c248b7dSInki Dae 5231c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 5241c248b7dSInki Dae 525864ee9e6SJoonyoung Shim if (win == DEFAULT_ZPOS) 526864ee9e6SJoonyoung Shim win = ctx->default_win; 527864ee9e6SJoonyoung Shim 5281c248b7dSInki Dae if (win < 0 || win > WINDOWS_NR) 5291c248b7dSInki Dae return; 5301c248b7dSInki Dae 531ec05da95SInki Dae win_data = &ctx->win_data[win]; 532ec05da95SInki Dae 5331c248b7dSInki Dae /* protect windows */ 5341c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 5351c248b7dSInki Dae val |= SHADOWCON_WINx_PROTECT(win); 5361c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 5371c248b7dSInki Dae 5381c248b7dSInki Dae /* wincon */ 5391c248b7dSInki Dae val = readl(ctx->regs + WINCON(win)); 5401c248b7dSInki Dae val &= ~WINCONx_ENWIN; 5411c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 5421c248b7dSInki Dae 5431c248b7dSInki Dae /* unprotect windows */ 5441c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 5451c248b7dSInki Dae val &= ~SHADOWCON_CHx_ENABLE(win); 5461c248b7dSInki Dae val &= ~SHADOWCON_WINx_PROTECT(win); 5471c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 548ec05da95SInki Dae 549ec05da95SInki Dae win_data->enabled = false; 5501c248b7dSInki Dae } 5511c248b7dSInki Dae 5521c248b7dSInki Dae static struct exynos_drm_overlay_ops fimd_overlay_ops = { 5531c248b7dSInki Dae .mode_set = fimd_win_mode_set, 5541c248b7dSInki Dae .commit = fimd_win_commit, 5551c248b7dSInki Dae .disable = fimd_win_disable, 5561c248b7dSInki Dae }; 5571c248b7dSInki Dae 5581c248b7dSInki Dae static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc) 5591c248b7dSInki Dae { 5601c248b7dSInki Dae struct exynos_drm_private *dev_priv = drm_dev->dev_private; 5611c248b7dSInki Dae struct drm_pending_vblank_event *e, *t; 5621c248b7dSInki Dae struct timeval now; 5631c248b7dSInki Dae unsigned long flags; 564ccf4d883SInki Dae bool is_checked = false; 5651c248b7dSInki Dae 5661c248b7dSInki Dae spin_lock_irqsave(&drm_dev->event_lock, flags); 5671c248b7dSInki Dae 5681c248b7dSInki Dae list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list, 5691c248b7dSInki Dae base.link) { 570a88cab2bSInki Dae /* if event's pipe isn't same as crtc then ignore it. */ 571ccf4d883SInki Dae if (crtc != e->pipe) 572ccf4d883SInki Dae continue; 573ccf4d883SInki Dae 574ccf4d883SInki Dae is_checked = true; 575ccf4d883SInki Dae 5761c248b7dSInki Dae do_gettimeofday(&now); 5771c248b7dSInki Dae e->event.sequence = 0; 5781c248b7dSInki Dae e->event.tv_sec = now.tv_sec; 5791c248b7dSInki Dae e->event.tv_usec = now.tv_usec; 5801c248b7dSInki Dae 5811c248b7dSInki Dae list_move_tail(&e->base.link, &e->base.file_priv->event_list); 5821c248b7dSInki Dae wake_up_interruptible(&e->base.file_priv->event_wait); 5831c248b7dSInki Dae } 5841c248b7dSInki Dae 585ec05da95SInki Dae if (is_checked) { 5861c248b7dSInki Dae drm_vblank_put(drm_dev, crtc); 5871c248b7dSInki Dae 588ec05da95SInki Dae /* 589ec05da95SInki Dae * don't off vblank if vblank_disable_allowed is 1, 590ec05da95SInki Dae * because vblank would be off by timer handler. 591ec05da95SInki Dae */ 592ec05da95SInki Dae if (!drm_dev->vblank_disable_allowed) 593ec05da95SInki Dae drm_vblank_off(drm_dev, crtc); 594ec05da95SInki Dae } 595ec05da95SInki Dae 5961c248b7dSInki Dae spin_unlock_irqrestore(&drm_dev->event_lock, flags); 5971c248b7dSInki Dae } 5981c248b7dSInki Dae 5991c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 6001c248b7dSInki Dae { 6011c248b7dSInki Dae struct fimd_context *ctx = (struct fimd_context *)dev_id; 6021c248b7dSInki Dae struct exynos_drm_subdrv *subdrv = &ctx->subdrv; 6031c248b7dSInki Dae struct drm_device *drm_dev = subdrv->drm_dev; 6041c248b7dSInki Dae struct exynos_drm_manager *manager = &subdrv->manager; 6051c248b7dSInki Dae u32 val; 6061c248b7dSInki Dae 6071c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON1); 6081c248b7dSInki Dae 6091c248b7dSInki Dae if (val & VIDINTCON1_INT_FRAME) 6101c248b7dSInki Dae /* VSYNC interrupt */ 6111c248b7dSInki Dae writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); 6121c248b7dSInki Dae 613ec05da95SInki Dae /* check the crtc is detached already from encoder */ 614ec05da95SInki Dae if (manager->pipe < 0) 615ec05da95SInki Dae goto out; 616483b88f8SInki Dae 6171c248b7dSInki Dae drm_handle_vblank(drm_dev, manager->pipe); 6181c248b7dSInki Dae fimd_finish_pageflip(drm_dev, manager->pipe); 6191c248b7dSInki Dae 620ec05da95SInki Dae out: 6211c248b7dSInki Dae return IRQ_HANDLED; 6221c248b7dSInki Dae } 6231c248b7dSInki Dae 62441c24346SInki Dae static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) 6251c248b7dSInki Dae { 6261c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 6271c248b7dSInki Dae 6281c248b7dSInki Dae /* 6291c248b7dSInki Dae * enable drm irq mode. 6301c248b7dSInki Dae * - with irq_enabled = 1, we can use the vblank feature. 6311c248b7dSInki Dae * 6321c248b7dSInki Dae * P.S. note that we wouldn't use drm irq handler but 6331c248b7dSInki Dae * just specific driver own one instead because 6341c248b7dSInki Dae * drm framework supports only one irq handler. 6351c248b7dSInki Dae */ 6361c248b7dSInki Dae drm_dev->irq_enabled = 1; 6371c248b7dSInki Dae 638ec05da95SInki Dae /* 639ec05da95SInki Dae * with vblank_disable_allowed = 1, vblank interrupt will be disabled 640ec05da95SInki Dae * by drm timer once a current process gives up ownership of 641ec05da95SInki Dae * vblank event.(after drm_vblank_put function is called) 642ec05da95SInki Dae */ 643ec05da95SInki Dae drm_dev->vblank_disable_allowed = 1; 644ec05da95SInki Dae 6451c248b7dSInki Dae return 0; 6461c248b7dSInki Dae } 6471c248b7dSInki Dae 6481c248b7dSInki Dae static void fimd_subdrv_remove(struct drm_device *drm_dev) 6491c248b7dSInki Dae { 6501c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 6511c248b7dSInki Dae 6521c248b7dSInki Dae /* TODO. */ 6531c248b7dSInki Dae } 6541c248b7dSInki Dae 6551c248b7dSInki Dae static int fimd_calc_clkdiv(struct fimd_context *ctx, 6561c248b7dSInki Dae struct fb_videomode *timing) 6571c248b7dSInki Dae { 6581c248b7dSInki Dae unsigned long clk = clk_get_rate(ctx->lcd_clk); 6591c248b7dSInki Dae u32 retrace; 6601c248b7dSInki Dae u32 clkdiv; 6611c248b7dSInki Dae u32 best_framerate = 0; 6621c248b7dSInki Dae u32 framerate; 6631c248b7dSInki Dae 6641c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 6651c248b7dSInki Dae 6661c248b7dSInki Dae retrace = timing->left_margin + timing->hsync_len + 6671c248b7dSInki Dae timing->right_margin + timing->xres; 6681c248b7dSInki Dae retrace *= timing->upper_margin + timing->vsync_len + 6691c248b7dSInki Dae timing->lower_margin + timing->yres; 6701c248b7dSInki Dae 6711c248b7dSInki Dae /* default framerate is 60Hz */ 6721c248b7dSInki Dae if (!timing->refresh) 6731c248b7dSInki Dae timing->refresh = 60; 6741c248b7dSInki Dae 6751c248b7dSInki Dae clk /= retrace; 6761c248b7dSInki Dae 6771c248b7dSInki Dae for (clkdiv = 1; clkdiv < 0x100; clkdiv++) { 6781c248b7dSInki Dae int tmp; 6791c248b7dSInki Dae 6801c248b7dSInki Dae /* get best framerate */ 6811c248b7dSInki Dae framerate = clk / clkdiv; 6821c248b7dSInki Dae tmp = timing->refresh - framerate; 6831c248b7dSInki Dae if (tmp < 0) { 6841c248b7dSInki Dae best_framerate = framerate; 6851c248b7dSInki Dae continue; 6861c248b7dSInki Dae } else { 6871c248b7dSInki Dae if (!best_framerate) 6881c248b7dSInki Dae best_framerate = framerate; 6891c248b7dSInki Dae else if (tmp < (best_framerate - framerate)) 6901c248b7dSInki Dae best_framerate = framerate; 6911c248b7dSInki Dae break; 6921c248b7dSInki Dae } 6931c248b7dSInki Dae } 6941c248b7dSInki Dae 6951c248b7dSInki Dae return clkdiv; 6961c248b7dSInki Dae } 6971c248b7dSInki Dae 6981c248b7dSInki Dae static void fimd_clear_win(struct fimd_context *ctx, int win) 6991c248b7dSInki Dae { 7001c248b7dSInki Dae u32 val; 7011c248b7dSInki Dae 7021c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 7031c248b7dSInki Dae 7041c248b7dSInki Dae writel(0, ctx->regs + WINCON(win)); 7051c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_A(win)); 7061c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_B(win)); 7071c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_C(win)); 7081c248b7dSInki Dae 7091c248b7dSInki Dae if (win == 1 || win == 2) 7101c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_D(win)); 7111c248b7dSInki Dae 7121c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 7131c248b7dSInki Dae val &= ~SHADOWCON_WINx_PROTECT(win); 7141c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 7151c248b7dSInki Dae } 7161c248b7dSInki Dae 7171c248b7dSInki Dae static int __devinit fimd_probe(struct platform_device *pdev) 7181c248b7dSInki Dae { 7191c248b7dSInki Dae struct device *dev = &pdev->dev; 7201c248b7dSInki Dae struct fimd_context *ctx; 7211c248b7dSInki Dae struct exynos_drm_subdrv *subdrv; 7221c248b7dSInki Dae struct exynos_drm_fimd_pdata *pdata; 7231c248b7dSInki Dae struct fb_videomode *timing; 7241c248b7dSInki Dae struct resource *res; 7251c248b7dSInki Dae int win; 7261c248b7dSInki Dae int ret = -EINVAL; 7271c248b7dSInki Dae 7281c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 7291c248b7dSInki Dae 7301c248b7dSInki Dae pdata = pdev->dev.platform_data; 7311c248b7dSInki Dae if (!pdata) { 7321c248b7dSInki Dae dev_err(dev, "no platform data specified\n"); 7331c248b7dSInki Dae return -EINVAL; 7341c248b7dSInki Dae } 7351c248b7dSInki Dae 7361c248b7dSInki Dae timing = &pdata->timing; 7371c248b7dSInki Dae if (!timing) { 7381c248b7dSInki Dae dev_err(dev, "timing is null.\n"); 7391c248b7dSInki Dae return -EINVAL; 7401c248b7dSInki Dae } 7411c248b7dSInki Dae 7421c248b7dSInki Dae ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 7431c248b7dSInki Dae if (!ctx) 7441c248b7dSInki Dae return -ENOMEM; 7451c248b7dSInki Dae 7461c248b7dSInki Dae ctx->bus_clk = clk_get(dev, "fimd"); 7471c248b7dSInki Dae if (IS_ERR(ctx->bus_clk)) { 7481c248b7dSInki Dae dev_err(dev, "failed to get bus clock\n"); 7491c248b7dSInki Dae ret = PTR_ERR(ctx->bus_clk); 7501c248b7dSInki Dae goto err_clk_get; 7511c248b7dSInki Dae } 7521c248b7dSInki Dae 7531c248b7dSInki Dae clk_enable(ctx->bus_clk); 7541c248b7dSInki Dae 7551c248b7dSInki Dae ctx->lcd_clk = clk_get(dev, "sclk_fimd"); 7561c248b7dSInki Dae if (IS_ERR(ctx->lcd_clk)) { 7571c248b7dSInki Dae dev_err(dev, "failed to get lcd clock\n"); 7581c248b7dSInki Dae ret = PTR_ERR(ctx->lcd_clk); 7591c248b7dSInki Dae goto err_bus_clk; 7601c248b7dSInki Dae } 7611c248b7dSInki Dae 7621c248b7dSInki Dae clk_enable(ctx->lcd_clk); 7631c248b7dSInki Dae 7641c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 7651c248b7dSInki Dae if (!res) { 7661c248b7dSInki Dae dev_err(dev, "failed to find registers\n"); 7671c248b7dSInki Dae ret = -ENOENT; 7681c248b7dSInki Dae goto err_clk; 7691c248b7dSInki Dae } 7701c248b7dSInki Dae 7711c248b7dSInki Dae ctx->regs_res = request_mem_region(res->start, resource_size(res), 7721c248b7dSInki Dae dev_name(dev)); 7731c248b7dSInki Dae if (!ctx->regs_res) { 7741c248b7dSInki Dae dev_err(dev, "failed to claim register region\n"); 7751c248b7dSInki Dae ret = -ENOENT; 7761c248b7dSInki Dae goto err_clk; 7771c248b7dSInki Dae } 7781c248b7dSInki Dae 7791c248b7dSInki Dae ctx->regs = ioremap(res->start, resource_size(res)); 7801c248b7dSInki Dae if (!ctx->regs) { 7811c248b7dSInki Dae dev_err(dev, "failed to map registers\n"); 7821c248b7dSInki Dae ret = -ENXIO; 7831c248b7dSInki Dae goto err_req_region_io; 7841c248b7dSInki Dae } 7851c248b7dSInki Dae 7861c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 7871c248b7dSInki Dae if (!res) { 7881c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 7891c248b7dSInki Dae goto err_req_region_irq; 7901c248b7dSInki Dae } 7911c248b7dSInki Dae 7921c248b7dSInki Dae ctx->irq = res->start; 7931c248b7dSInki Dae 7941c248b7dSInki Dae ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx); 7951c248b7dSInki Dae if (ret < 0) { 7961c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 7971c248b7dSInki Dae goto err_req_irq; 7981c248b7dSInki Dae } 7991c248b7dSInki Dae 800cb91f6a0SJoonyoung Shim pm_runtime_set_active(dev); 801cb91f6a0SJoonyoung Shim pm_runtime_enable(dev); 802cb91f6a0SJoonyoung Shim pm_runtime_get_sync(dev); 803cb91f6a0SJoonyoung Shim 804ec05da95SInki Dae for (win = 0; win < WINDOWS_NR; win++) 805ec05da95SInki Dae fimd_clear_win(ctx, win); 806ec05da95SInki Dae 8071c248b7dSInki Dae ctx->clkdiv = fimd_calc_clkdiv(ctx, timing); 8081c248b7dSInki Dae ctx->vidcon0 = pdata->vidcon0; 8091c248b7dSInki Dae ctx->vidcon1 = pdata->vidcon1; 8101c248b7dSInki Dae ctx->default_win = pdata->default_win; 8111c248b7dSInki Dae ctx->timing = timing; 8121c248b7dSInki Dae 8131c248b7dSInki Dae timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv; 8141c248b7dSInki Dae 8151c248b7dSInki Dae DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n", 8161c248b7dSInki Dae timing->pixclock, ctx->clkdiv); 8171c248b7dSInki Dae 8181c248b7dSInki Dae subdrv = &ctx->subdrv; 8191c248b7dSInki Dae 8201c248b7dSInki Dae subdrv->probe = fimd_subdrv_probe; 8211c248b7dSInki Dae subdrv->remove = fimd_subdrv_remove; 8221c248b7dSInki Dae subdrv->manager.pipe = -1; 8231c248b7dSInki Dae subdrv->manager.ops = &fimd_manager_ops; 8241c248b7dSInki Dae subdrv->manager.overlay_ops = &fimd_overlay_ops; 82574ccc539SInki Dae subdrv->manager.display_ops = &fimd_display_ops; 8261c248b7dSInki Dae subdrv->manager.dev = dev; 8271c248b7dSInki Dae 8281c248b7dSInki Dae platform_set_drvdata(pdev, ctx); 8291c248b7dSInki Dae exynos_drm_subdrv_register(subdrv); 8301c248b7dSInki Dae 8311c248b7dSInki Dae return 0; 8321c248b7dSInki Dae 8331c248b7dSInki Dae err_req_irq: 8341c248b7dSInki Dae err_req_region_irq: 8351c248b7dSInki Dae iounmap(ctx->regs); 8361c248b7dSInki Dae 8371c248b7dSInki Dae err_req_region_io: 8381c248b7dSInki Dae release_resource(ctx->regs_res); 8391c248b7dSInki Dae kfree(ctx->regs_res); 8401c248b7dSInki Dae 8411c248b7dSInki Dae err_clk: 8421c248b7dSInki Dae clk_disable(ctx->lcd_clk); 8431c248b7dSInki Dae clk_put(ctx->lcd_clk); 8441c248b7dSInki Dae 8451c248b7dSInki Dae err_bus_clk: 8461c248b7dSInki Dae clk_disable(ctx->bus_clk); 8471c248b7dSInki Dae clk_put(ctx->bus_clk); 8481c248b7dSInki Dae 8491c248b7dSInki Dae err_clk_get: 8501c248b7dSInki Dae kfree(ctx); 8511c248b7dSInki Dae return ret; 8521c248b7dSInki Dae } 8531c248b7dSInki Dae 8541c248b7dSInki Dae static int __devexit fimd_remove(struct platform_device *pdev) 8551c248b7dSInki Dae { 856cb91f6a0SJoonyoung Shim struct device *dev = &pdev->dev; 8571c248b7dSInki Dae struct fimd_context *ctx = platform_get_drvdata(pdev); 8581c248b7dSInki Dae 8591c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 8601c248b7dSInki Dae 8611c248b7dSInki Dae exynos_drm_subdrv_unregister(&ctx->subdrv); 8621c248b7dSInki Dae 863cb91f6a0SJoonyoung Shim if (ctx->suspended) 864cb91f6a0SJoonyoung Shim goto out; 865cb91f6a0SJoonyoung Shim 8661c248b7dSInki Dae clk_disable(ctx->lcd_clk); 8671c248b7dSInki Dae clk_disable(ctx->bus_clk); 868cb91f6a0SJoonyoung Shim 869cb91f6a0SJoonyoung Shim pm_runtime_set_suspended(dev); 870cb91f6a0SJoonyoung Shim pm_runtime_put_sync(dev); 871cb91f6a0SJoonyoung Shim 872cb91f6a0SJoonyoung Shim out: 873cb91f6a0SJoonyoung Shim pm_runtime_disable(dev); 874cb91f6a0SJoonyoung Shim 8751c248b7dSInki Dae clk_put(ctx->lcd_clk); 8761c248b7dSInki Dae clk_put(ctx->bus_clk); 8771c248b7dSInki Dae 8781c248b7dSInki Dae iounmap(ctx->regs); 8791c248b7dSInki Dae release_resource(ctx->regs_res); 8801c248b7dSInki Dae kfree(ctx->regs_res); 8811c248b7dSInki Dae free_irq(ctx->irq, ctx); 8821c248b7dSInki Dae 8831c248b7dSInki Dae kfree(ctx); 8841c248b7dSInki Dae 8851c248b7dSInki Dae return 0; 8861c248b7dSInki Dae } 8871c248b7dSInki Dae 888cb91f6a0SJoonyoung Shim #ifdef CONFIG_PM_RUNTIME 889cb91f6a0SJoonyoung Shim static int fimd_runtime_suspend(struct device *dev) 890cb91f6a0SJoonyoung Shim { 891cb91f6a0SJoonyoung Shim struct fimd_context *ctx = get_fimd_context(dev); 892cb91f6a0SJoonyoung Shim 893cb91f6a0SJoonyoung Shim DRM_DEBUG_KMS("%s\n", __FILE__); 894cb91f6a0SJoonyoung Shim 895cb91f6a0SJoonyoung Shim clk_disable(ctx->lcd_clk); 896cb91f6a0SJoonyoung Shim clk_disable(ctx->bus_clk); 897cb91f6a0SJoonyoung Shim 898cb91f6a0SJoonyoung Shim ctx->suspended = true; 899cb91f6a0SJoonyoung Shim return 0; 900cb91f6a0SJoonyoung Shim } 901cb91f6a0SJoonyoung Shim 902cb91f6a0SJoonyoung Shim static int fimd_runtime_resume(struct device *dev) 903cb91f6a0SJoonyoung Shim { 904cb91f6a0SJoonyoung Shim struct fimd_context *ctx = get_fimd_context(dev); 905cb91f6a0SJoonyoung Shim int ret; 906cb91f6a0SJoonyoung Shim 907cb91f6a0SJoonyoung Shim DRM_DEBUG_KMS("%s\n", __FILE__); 908cb91f6a0SJoonyoung Shim 909cb91f6a0SJoonyoung Shim ret = clk_enable(ctx->bus_clk); 910cb91f6a0SJoonyoung Shim if (ret < 0) 911cb91f6a0SJoonyoung Shim return ret; 912cb91f6a0SJoonyoung Shim 913cb91f6a0SJoonyoung Shim ret = clk_enable(ctx->lcd_clk); 914cb91f6a0SJoonyoung Shim if (ret < 0) { 915cb91f6a0SJoonyoung Shim clk_disable(ctx->bus_clk); 916cb91f6a0SJoonyoung Shim return ret; 917cb91f6a0SJoonyoung Shim } 918cb91f6a0SJoonyoung Shim 919cb91f6a0SJoonyoung Shim ctx->suspended = false; 920cb91f6a0SJoonyoung Shim return 0; 921cb91f6a0SJoonyoung Shim } 922cb91f6a0SJoonyoung Shim #endif 923cb91f6a0SJoonyoung Shim 924cb91f6a0SJoonyoung Shim static const struct dev_pm_ops fimd_pm_ops = { 925cb91f6a0SJoonyoung Shim SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) 926cb91f6a0SJoonyoung Shim }; 927cb91f6a0SJoonyoung Shim 9281c248b7dSInki Dae static struct platform_driver fimd_driver = { 9291c248b7dSInki Dae .probe = fimd_probe, 9301c248b7dSInki Dae .remove = __devexit_p(fimd_remove), 9311c248b7dSInki Dae .driver = { 9321c248b7dSInki Dae .name = "exynos4-fb", 9331c248b7dSInki Dae .owner = THIS_MODULE, 934cb91f6a0SJoonyoung Shim .pm = &fimd_pm_ops, 9351c248b7dSInki Dae }, 9361c248b7dSInki Dae }; 9371c248b7dSInki Dae 9381c248b7dSInki Dae static int __init fimd_init(void) 9391c248b7dSInki Dae { 9401c248b7dSInki Dae return platform_driver_register(&fimd_driver); 9411c248b7dSInki Dae } 9421c248b7dSInki Dae 9431c248b7dSInki Dae static void __exit fimd_exit(void) 9441c248b7dSInki Dae { 9451c248b7dSInki Dae platform_driver_unregister(&fimd_driver); 9461c248b7dSInki Dae } 9471c248b7dSInki Dae 9481c248b7dSInki Dae module_init(fimd_init); 9491c248b7dSInki Dae module_exit(fimd_exit); 9501c248b7dSInki Dae 9511c248b7dSInki Dae MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>"); 9521c248b7dSInki Dae MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>"); 9531c248b7dSInki Dae MODULE_DESCRIPTION("Samsung DRM FIMD Driver"); 9541c248b7dSInki Dae MODULE_LICENSE("GPL"); 955