11c248b7dSInki Dae /* exynos_drm_fimd.c 21c248b7dSInki Dae * 31c248b7dSInki Dae * Copyright (C) 2011 Samsung Electronics Co.Ltd 41c248b7dSInki Dae * Authors: 51c248b7dSInki Dae * Joonyoung Shim <jy0922.shim@samsung.com> 61c248b7dSInki Dae * Inki Dae <inki.dae@samsung.com> 71c248b7dSInki Dae * 81c248b7dSInki Dae * This program is free software; you can redistribute it and/or modify it 91c248b7dSInki Dae * under the terms of the GNU General Public License as published by the 101c248b7dSInki Dae * Free Software Foundation; either version 2 of the License, or (at your 111c248b7dSInki Dae * option) any later version. 121c248b7dSInki Dae * 131c248b7dSInki Dae */ 141c248b7dSInki Dae #include "drmP.h" 151c248b7dSInki Dae 161c248b7dSInki Dae #include <linux/kernel.h> 171c248b7dSInki Dae #include <linux/module.h> 181c248b7dSInki Dae #include <linux/platform_device.h> 191c248b7dSInki Dae #include <linux/clk.h> 201c248b7dSInki Dae 211c248b7dSInki Dae #include <drm/exynos_drm.h> 221c248b7dSInki Dae #include <plat/regs-fb-v4.h> 231c248b7dSInki Dae 241c248b7dSInki Dae #include "exynos_drm_drv.h" 251c248b7dSInki Dae #include "exynos_drm_fbdev.h" 261c248b7dSInki Dae #include "exynos_drm_crtc.h" 271c248b7dSInki Dae 281c248b7dSInki Dae /* 291c248b7dSInki Dae * FIMD is stand for Fully Interactive Mobile Display and 301c248b7dSInki Dae * as a display controller, it transfers contents drawn on memory 311c248b7dSInki Dae * to a LCD Panel through Display Interfaces such as RGB or 321c248b7dSInki Dae * CPU Interface. 331c248b7dSInki Dae */ 341c248b7dSInki Dae 351c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/ 361c248b7dSInki Dae #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 371c248b7dSInki Dae #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 381c248b7dSInki Dae /* size control register for hardware window 0. */ 391c248b7dSInki Dae #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08) 401c248b7dSInki Dae /* alpha control register for hardware window 1 ~ 4. */ 411c248b7dSInki Dae #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16) 421c248b7dSInki Dae /* size control register for hardware window 1 ~ 4. */ 431c248b7dSInki Dae #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 441c248b7dSInki Dae 451c248b7dSInki Dae #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 461c248b7dSInki Dae #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 471c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 481c248b7dSInki Dae 491c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */ 501c248b7dSInki Dae #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8)) 511c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */ 521c248b7dSInki Dae #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8)) 531c248b7dSInki Dae 541c248b7dSInki Dae /* FIMD has totally five hardware windows. */ 551c248b7dSInki Dae #define WINDOWS_NR 5 561c248b7dSInki Dae 571c248b7dSInki Dae #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) 581c248b7dSInki Dae 591c248b7dSInki Dae struct fimd_win_data { 601c248b7dSInki Dae unsigned int offset_x; 611c248b7dSInki Dae unsigned int offset_y; 6219c8b834SInki Dae unsigned int ovl_width; 6319c8b834SInki Dae unsigned int ovl_height; 6419c8b834SInki Dae unsigned int fb_width; 6519c8b834SInki Dae unsigned int fb_height; 661c248b7dSInki Dae unsigned int bpp; 671c248b7dSInki Dae dma_addr_t paddr; 681c248b7dSInki Dae void __iomem *vaddr; 691c248b7dSInki Dae unsigned int buf_offsize; 701c248b7dSInki Dae unsigned int line_size; /* bytes */ 711c248b7dSInki Dae }; 721c248b7dSInki Dae 731c248b7dSInki Dae struct fimd_context { 741c248b7dSInki Dae struct exynos_drm_subdrv subdrv; 751c248b7dSInki Dae int irq; 761c248b7dSInki Dae struct drm_crtc *crtc; 771c248b7dSInki Dae struct clk *bus_clk; 781c248b7dSInki Dae struct clk *lcd_clk; 791c248b7dSInki Dae struct resource *regs_res; 801c248b7dSInki Dae void __iomem *regs; 811c248b7dSInki Dae struct fimd_win_data win_data[WINDOWS_NR]; 821c248b7dSInki Dae unsigned int clkdiv; 831c248b7dSInki Dae unsigned int default_win; 841c248b7dSInki Dae unsigned long irq_flags; 851c248b7dSInki Dae u32 vidcon0; 861c248b7dSInki Dae u32 vidcon1; 871c248b7dSInki Dae 881c248b7dSInki Dae struct fb_videomode *timing; 891c248b7dSInki Dae }; 901c248b7dSInki Dae 911c248b7dSInki Dae static bool fimd_display_is_connected(struct device *dev) 921c248b7dSInki Dae { 931c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 941c248b7dSInki Dae 951c248b7dSInki Dae /* TODO. */ 961c248b7dSInki Dae 971c248b7dSInki Dae return true; 981c248b7dSInki Dae } 991c248b7dSInki Dae 1001c248b7dSInki Dae static void *fimd_get_timing(struct device *dev) 1011c248b7dSInki Dae { 1021c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 1031c248b7dSInki Dae 1041c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1051c248b7dSInki Dae 1061c248b7dSInki Dae return ctx->timing; 1071c248b7dSInki Dae } 1081c248b7dSInki Dae 1091c248b7dSInki Dae static int fimd_check_timing(struct device *dev, void *timing) 1101c248b7dSInki Dae { 1111c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1121c248b7dSInki Dae 1131c248b7dSInki Dae /* TODO. */ 1141c248b7dSInki Dae 1151c248b7dSInki Dae return 0; 1161c248b7dSInki Dae } 1171c248b7dSInki Dae 1181c248b7dSInki Dae static int fimd_display_power_on(struct device *dev, int mode) 1191c248b7dSInki Dae { 1201c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1211c248b7dSInki Dae 1221c248b7dSInki Dae /* TODO. */ 1231c248b7dSInki Dae 1241c248b7dSInki Dae return 0; 1251c248b7dSInki Dae } 1261c248b7dSInki Dae 12774ccc539SInki Dae static struct exynos_drm_display_ops fimd_display_ops = { 1281c248b7dSInki Dae .type = EXYNOS_DISPLAY_TYPE_LCD, 1291c248b7dSInki Dae .is_connected = fimd_display_is_connected, 1301c248b7dSInki Dae .get_timing = fimd_get_timing, 1311c248b7dSInki Dae .check_timing = fimd_check_timing, 1321c248b7dSInki Dae .power_on = fimd_display_power_on, 1331c248b7dSInki Dae }; 1341c248b7dSInki Dae 1351c248b7dSInki Dae static void fimd_commit(struct device *dev) 1361c248b7dSInki Dae { 1371c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 1381c248b7dSInki Dae struct fb_videomode *timing = ctx->timing; 1391c248b7dSInki Dae u32 val; 1401c248b7dSInki Dae 1411c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1421c248b7dSInki Dae 1431c248b7dSInki Dae /* setup polarity values from machine code. */ 1441c248b7dSInki Dae writel(ctx->vidcon1, ctx->regs + VIDCON1); 1451c248b7dSInki Dae 1461c248b7dSInki Dae /* setup vertical timing values. */ 1471c248b7dSInki Dae val = VIDTCON0_VBPD(timing->upper_margin - 1) | 1481c248b7dSInki Dae VIDTCON0_VFPD(timing->lower_margin - 1) | 1491c248b7dSInki Dae VIDTCON0_VSPW(timing->vsync_len - 1); 1501c248b7dSInki Dae writel(val, ctx->regs + VIDTCON0); 1511c248b7dSInki Dae 1521c248b7dSInki Dae /* setup horizontal timing values. */ 1531c248b7dSInki Dae val = VIDTCON1_HBPD(timing->left_margin - 1) | 1541c248b7dSInki Dae VIDTCON1_HFPD(timing->right_margin - 1) | 1551c248b7dSInki Dae VIDTCON1_HSPW(timing->hsync_len - 1); 1561c248b7dSInki Dae writel(val, ctx->regs + VIDTCON1); 1571c248b7dSInki Dae 1581c248b7dSInki Dae /* setup horizontal and vertical display size. */ 1591c248b7dSInki Dae val = VIDTCON2_LINEVAL(timing->yres - 1) | 1601c248b7dSInki Dae VIDTCON2_HOZVAL(timing->xres - 1); 1611c248b7dSInki Dae writel(val, ctx->regs + VIDTCON2); 1621c248b7dSInki Dae 1631c248b7dSInki Dae /* setup clock source, clock divider, enable dma. */ 1641c248b7dSInki Dae val = ctx->vidcon0; 1651c248b7dSInki Dae val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); 1661c248b7dSInki Dae 1671c248b7dSInki Dae if (ctx->clkdiv > 1) 1681c248b7dSInki Dae val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; 1691c248b7dSInki Dae else 1701c248b7dSInki Dae val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ 1711c248b7dSInki Dae 1721c248b7dSInki Dae /* 1731c248b7dSInki Dae * fields of register with prefix '_F' would be updated 1741c248b7dSInki Dae * at vsync(same as dma start) 1751c248b7dSInki Dae */ 1761c248b7dSInki Dae val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 1771c248b7dSInki Dae writel(val, ctx->regs + VIDCON0); 1781c248b7dSInki Dae } 1791c248b7dSInki Dae 1801c248b7dSInki Dae static int fimd_enable_vblank(struct device *dev) 1811c248b7dSInki Dae { 1821c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 1831c248b7dSInki Dae u32 val; 1841c248b7dSInki Dae 1851c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 1861c248b7dSInki Dae 1871c248b7dSInki Dae if (!test_and_set_bit(0, &ctx->irq_flags)) { 1881c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON0); 1891c248b7dSInki Dae 1901c248b7dSInki Dae val |= VIDINTCON0_INT_ENABLE; 1911c248b7dSInki Dae val |= VIDINTCON0_INT_FRAME; 1921c248b7dSInki Dae 1931c248b7dSInki Dae val &= ~VIDINTCON0_FRAMESEL0_MASK; 1941c248b7dSInki Dae val |= VIDINTCON0_FRAMESEL0_VSYNC; 1951c248b7dSInki Dae val &= ~VIDINTCON0_FRAMESEL1_MASK; 1961c248b7dSInki Dae val |= VIDINTCON0_FRAMESEL1_NONE; 1971c248b7dSInki Dae 1981c248b7dSInki Dae writel(val, ctx->regs + VIDINTCON0); 1991c248b7dSInki Dae } 2001c248b7dSInki Dae 2011c248b7dSInki Dae return 0; 2021c248b7dSInki Dae } 2031c248b7dSInki Dae 2041c248b7dSInki Dae static void fimd_disable_vblank(struct device *dev) 2051c248b7dSInki Dae { 2061c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 2071c248b7dSInki Dae u32 val; 2081c248b7dSInki Dae 2091c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 2101c248b7dSInki Dae 2111c248b7dSInki Dae if (test_and_clear_bit(0, &ctx->irq_flags)) { 2121c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON0); 2131c248b7dSInki Dae 2141c248b7dSInki Dae val &= ~VIDINTCON0_INT_FRAME; 2151c248b7dSInki Dae val &= ~VIDINTCON0_INT_ENABLE; 2161c248b7dSInki Dae 2171c248b7dSInki Dae writel(val, ctx->regs + VIDINTCON0); 2181c248b7dSInki Dae } 2191c248b7dSInki Dae } 2201c248b7dSInki Dae 2211c248b7dSInki Dae static struct exynos_drm_manager_ops fimd_manager_ops = { 2221c248b7dSInki Dae .commit = fimd_commit, 2231c248b7dSInki Dae .enable_vblank = fimd_enable_vblank, 2241c248b7dSInki Dae .disable_vblank = fimd_disable_vblank, 2251c248b7dSInki Dae }; 2261c248b7dSInki Dae 2271c248b7dSInki Dae static void fimd_win_mode_set(struct device *dev, 2281c248b7dSInki Dae struct exynos_drm_overlay *overlay) 2291c248b7dSInki Dae { 2301c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 2311c248b7dSInki Dae struct fimd_win_data *win_data; 23219c8b834SInki Dae unsigned long offset; 2331c248b7dSInki Dae 2341c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 2351c248b7dSInki Dae 2361c248b7dSInki Dae if (!overlay) { 2371c248b7dSInki Dae dev_err(dev, "overlay is NULL\n"); 2381c248b7dSInki Dae return; 2391c248b7dSInki Dae } 2401c248b7dSInki Dae 24119c8b834SInki Dae offset = overlay->fb_x * (overlay->bpp >> 3); 24219c8b834SInki Dae offset += overlay->fb_y * overlay->pitch; 24319c8b834SInki Dae 24419c8b834SInki Dae DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); 24519c8b834SInki Dae 2461c248b7dSInki Dae win_data = &ctx->win_data[ctx->default_win]; 2471c248b7dSInki Dae 24819c8b834SInki Dae win_data->offset_x = overlay->crtc_x; 24919c8b834SInki Dae win_data->offset_y = overlay->crtc_y; 25019c8b834SInki Dae win_data->ovl_width = overlay->crtc_width; 25119c8b834SInki Dae win_data->ovl_height = overlay->crtc_height; 25219c8b834SInki Dae win_data->fb_width = overlay->fb_width; 25319c8b834SInki Dae win_data->fb_height = overlay->fb_height; 25419c8b834SInki Dae win_data->paddr = overlay->paddr + offset; 25519c8b834SInki Dae win_data->vaddr = overlay->vaddr + offset; 2561c248b7dSInki Dae win_data->bpp = overlay->bpp; 25719c8b834SInki Dae win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * 25819c8b834SInki Dae (overlay->bpp >> 3); 25919c8b834SInki Dae win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); 26019c8b834SInki Dae 26119c8b834SInki Dae DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", 26219c8b834SInki Dae win_data->offset_x, win_data->offset_y); 26319c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 26419c8b834SInki Dae win_data->ovl_width, win_data->ovl_height); 26519c8b834SInki Dae DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n", 26619c8b834SInki Dae (unsigned long)win_data->paddr, 26719c8b834SInki Dae (unsigned long)win_data->vaddr); 26819c8b834SInki Dae DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", 26919c8b834SInki Dae overlay->fb_width, overlay->crtc_width); 2701c248b7dSInki Dae } 2711c248b7dSInki Dae 2721c248b7dSInki Dae static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) 2731c248b7dSInki Dae { 2741c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 2751c248b7dSInki Dae struct fimd_win_data *win_data = &ctx->win_data[win]; 2761c248b7dSInki Dae unsigned long val; 2771c248b7dSInki Dae 2781c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 2791c248b7dSInki Dae 2801c248b7dSInki Dae val = WINCONx_ENWIN; 2811c248b7dSInki Dae 2821c248b7dSInki Dae switch (win_data->bpp) { 2831c248b7dSInki Dae case 1: 2841c248b7dSInki Dae val |= WINCON0_BPPMODE_1BPP; 2851c248b7dSInki Dae val |= WINCONx_BITSWP; 2861c248b7dSInki Dae val |= WINCONx_BURSTLEN_4WORD; 2871c248b7dSInki Dae break; 2881c248b7dSInki Dae case 2: 2891c248b7dSInki Dae val |= WINCON0_BPPMODE_2BPP; 2901c248b7dSInki Dae val |= WINCONx_BITSWP; 2911c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 2921c248b7dSInki Dae break; 2931c248b7dSInki Dae case 4: 2941c248b7dSInki Dae val |= WINCON0_BPPMODE_4BPP; 2951c248b7dSInki Dae val |= WINCONx_BITSWP; 2961c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 2971c248b7dSInki Dae break; 2981c248b7dSInki Dae case 8: 2991c248b7dSInki Dae val |= WINCON0_BPPMODE_8BPP_PALETTE; 3001c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 3011c248b7dSInki Dae val |= WINCONx_BYTSWP; 3021c248b7dSInki Dae break; 3031c248b7dSInki Dae case 16: 3041c248b7dSInki Dae val |= WINCON0_BPPMODE_16BPP_565; 3051c248b7dSInki Dae val |= WINCONx_HAWSWP; 3061c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3071c248b7dSInki Dae break; 3081c248b7dSInki Dae case 24: 3091c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 3101c248b7dSInki Dae val |= WINCONx_WSWP; 3111c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3121c248b7dSInki Dae break; 3131c248b7dSInki Dae case 32: 3141c248b7dSInki Dae val |= WINCON1_BPPMODE_28BPP_A4888 3151c248b7dSInki Dae | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 3161c248b7dSInki Dae val |= WINCONx_WSWP; 3171c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3181c248b7dSInki Dae break; 3191c248b7dSInki Dae default: 3201c248b7dSInki Dae DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 3211c248b7dSInki Dae 3221c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 3231c248b7dSInki Dae val |= WINCONx_WSWP; 3241c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 3251c248b7dSInki Dae break; 3261c248b7dSInki Dae } 3271c248b7dSInki Dae 3281c248b7dSInki Dae DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); 3291c248b7dSInki Dae 3301c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 3311c248b7dSInki Dae } 3321c248b7dSInki Dae 3331c248b7dSInki Dae static void fimd_win_set_colkey(struct device *dev, unsigned int win) 3341c248b7dSInki Dae { 3351c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 3361c248b7dSInki Dae unsigned int keycon0 = 0, keycon1 = 0; 3371c248b7dSInki Dae 3381c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 3391c248b7dSInki Dae 3401c248b7dSInki Dae keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 3411c248b7dSInki Dae WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 3421c248b7dSInki Dae 3431c248b7dSInki Dae keycon1 = WxKEYCON1_COLVAL(0xffffffff); 3441c248b7dSInki Dae 3451c248b7dSInki Dae writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 3461c248b7dSInki Dae writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 3471c248b7dSInki Dae } 3481c248b7dSInki Dae 3491c248b7dSInki Dae static void fimd_win_commit(struct device *dev) 3501c248b7dSInki Dae { 3511c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 3521c248b7dSInki Dae struct fimd_win_data *win_data; 3531c248b7dSInki Dae int win = ctx->default_win; 3541c248b7dSInki Dae unsigned long val, alpha, size; 3551c248b7dSInki Dae 3561c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 3571c248b7dSInki Dae 3581c248b7dSInki Dae if (win < 0 || win > WINDOWS_NR) 3591c248b7dSInki Dae return; 3601c248b7dSInki Dae 3611c248b7dSInki Dae win_data = &ctx->win_data[win]; 3621c248b7dSInki Dae 3631c248b7dSInki Dae /* 3641c248b7dSInki Dae * SHADOWCON register is used for enabling timing. 3651c248b7dSInki Dae * 3661c248b7dSInki Dae * for example, once only width value of a register is set, 3671c248b7dSInki Dae * if the dma is started then fimd hardware could malfunction so 3681c248b7dSInki Dae * with protect window setting, the register fields with prefix '_F' 3691c248b7dSInki Dae * wouldn't be updated at vsync also but updated once unprotect window 3701c248b7dSInki Dae * is set. 3711c248b7dSInki Dae */ 3721c248b7dSInki Dae 3731c248b7dSInki Dae /* protect windows */ 3741c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 3751c248b7dSInki Dae val |= SHADOWCON_WINx_PROTECT(win); 3761c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 3771c248b7dSInki Dae 3781c248b7dSInki Dae /* buffer start address */ 3791c248b7dSInki Dae val = win_data->paddr; 3801c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 3811c248b7dSInki Dae 3821c248b7dSInki Dae /* buffer end address */ 38319c8b834SInki Dae size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); 3841c248b7dSInki Dae val = win_data->paddr + size; 3851c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 3861c248b7dSInki Dae 3871c248b7dSInki Dae DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 3881c248b7dSInki Dae (unsigned long)win_data->paddr, val, size); 38919c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 39019c8b834SInki Dae win_data->ovl_width, win_data->ovl_height); 3911c248b7dSInki Dae 3921c248b7dSInki Dae /* buffer size */ 3931c248b7dSInki Dae val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | 3941c248b7dSInki Dae VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size); 3951c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 3961c248b7dSInki Dae 3971c248b7dSInki Dae /* OSD position */ 3981c248b7dSInki Dae val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | 3991c248b7dSInki Dae VIDOSDxA_TOPLEFT_Y(win_data->offset_y); 4001c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_A(win)); 4011c248b7dSInki Dae 40219c8b834SInki Dae val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x + 40319c8b834SInki Dae win_data->ovl_width - 1) | 40419c8b834SInki Dae VIDOSDxB_BOTRIGHT_Y(win_data->offset_y + 40519c8b834SInki Dae win_data->ovl_height - 1); 4061c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_B(win)); 4071c248b7dSInki Dae 40819c8b834SInki Dae DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 4091c248b7dSInki Dae win_data->offset_x, win_data->offset_y, 41019c8b834SInki Dae win_data->offset_x + win_data->ovl_width - 1, 41119c8b834SInki Dae win_data->offset_y + win_data->ovl_height - 1); 4121c248b7dSInki Dae 4131c248b7dSInki Dae /* hardware window 0 doesn't support alpha channel. */ 4141c248b7dSInki Dae if (win != 0) { 4151c248b7dSInki Dae /* OSD alpha */ 4161c248b7dSInki Dae alpha = VIDISD14C_ALPHA1_R(0xf) | 4171c248b7dSInki Dae VIDISD14C_ALPHA1_G(0xf) | 4181c248b7dSInki Dae VIDISD14C_ALPHA1_B(0xf); 4191c248b7dSInki Dae 4201c248b7dSInki Dae writel(alpha, ctx->regs + VIDOSD_C(win)); 4211c248b7dSInki Dae } 4221c248b7dSInki Dae 4231c248b7dSInki Dae /* OSD size */ 4241c248b7dSInki Dae if (win != 3 && win != 4) { 4251c248b7dSInki Dae u32 offset = VIDOSD_D(win); 4261c248b7dSInki Dae if (win == 0) 4271c248b7dSInki Dae offset = VIDOSD_C_SIZE_W0; 42819c8b834SInki Dae val = win_data->ovl_width * win_data->ovl_height; 4291c248b7dSInki Dae writel(val, ctx->regs + offset); 4301c248b7dSInki Dae 4311c248b7dSInki Dae DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 4321c248b7dSInki Dae } 4331c248b7dSInki Dae 4341c248b7dSInki Dae fimd_win_set_pixfmt(dev, win); 4351c248b7dSInki Dae 4361c248b7dSInki Dae /* hardware window 0 doesn't support color key. */ 4371c248b7dSInki Dae if (win != 0) 4381c248b7dSInki Dae fimd_win_set_colkey(dev, win); 4391c248b7dSInki Dae 4401c248b7dSInki Dae /* Enable DMA channel and unprotect windows */ 4411c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 4421c248b7dSInki Dae val |= SHADOWCON_CHx_ENABLE(win); 4431c248b7dSInki Dae val &= ~SHADOWCON_WINx_PROTECT(win); 4441c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 4451c248b7dSInki Dae } 4461c248b7dSInki Dae 4471c248b7dSInki Dae static void fimd_win_disable(struct device *dev) 4481c248b7dSInki Dae { 4491c248b7dSInki Dae struct fimd_context *ctx = get_fimd_context(dev); 4501c248b7dSInki Dae struct fimd_win_data *win_data; 4511c248b7dSInki Dae int win = ctx->default_win; 4521c248b7dSInki Dae u32 val; 4531c248b7dSInki Dae 4541c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 4551c248b7dSInki Dae 4561c248b7dSInki Dae if (win < 0 || win > WINDOWS_NR) 4571c248b7dSInki Dae return; 4581c248b7dSInki Dae 4591c248b7dSInki Dae win_data = &ctx->win_data[win]; 4601c248b7dSInki Dae 4611c248b7dSInki Dae /* protect windows */ 4621c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 4631c248b7dSInki Dae val |= SHADOWCON_WINx_PROTECT(win); 4641c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 4651c248b7dSInki Dae 4661c248b7dSInki Dae /* wincon */ 4671c248b7dSInki Dae val = readl(ctx->regs + WINCON(win)); 4681c248b7dSInki Dae val &= ~WINCONx_ENWIN; 4691c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 4701c248b7dSInki Dae 4711c248b7dSInki Dae /* unprotect windows */ 4721c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 4731c248b7dSInki Dae val &= ~SHADOWCON_CHx_ENABLE(win); 4741c248b7dSInki Dae val &= ~SHADOWCON_WINx_PROTECT(win); 4751c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 4761c248b7dSInki Dae } 4771c248b7dSInki Dae 4781c248b7dSInki Dae static struct exynos_drm_overlay_ops fimd_overlay_ops = { 4791c248b7dSInki Dae .mode_set = fimd_win_mode_set, 4801c248b7dSInki Dae .commit = fimd_win_commit, 4811c248b7dSInki Dae .disable = fimd_win_disable, 4821c248b7dSInki Dae }; 4831c248b7dSInki Dae 4841c248b7dSInki Dae static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc) 4851c248b7dSInki Dae { 4861c248b7dSInki Dae struct exynos_drm_private *dev_priv = drm_dev->dev_private; 4871c248b7dSInki Dae struct drm_pending_vblank_event *e, *t; 4881c248b7dSInki Dae struct timeval now; 4891c248b7dSInki Dae unsigned long flags; 490ccf4d883SInki Dae bool is_checked = false; 4911c248b7dSInki Dae 4921c248b7dSInki Dae spin_lock_irqsave(&drm_dev->event_lock, flags); 4931c248b7dSInki Dae 4941c248b7dSInki Dae list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list, 4951c248b7dSInki Dae base.link) { 496a88cab2bSInki Dae /* if event's pipe isn't same as crtc then ignore it. */ 497ccf4d883SInki Dae if (crtc != e->pipe) 498ccf4d883SInki Dae continue; 499ccf4d883SInki Dae 500ccf4d883SInki Dae is_checked = true; 501ccf4d883SInki Dae 5021c248b7dSInki Dae do_gettimeofday(&now); 5031c248b7dSInki Dae e->event.sequence = 0; 5041c248b7dSInki Dae e->event.tv_sec = now.tv_sec; 5051c248b7dSInki Dae e->event.tv_usec = now.tv_usec; 5061c248b7dSInki Dae 5071c248b7dSInki Dae list_move_tail(&e->base.link, &e->base.file_priv->event_list); 5081c248b7dSInki Dae wake_up_interruptible(&e->base.file_priv->event_wait); 5091c248b7dSInki Dae } 5101c248b7dSInki Dae 511ccf4d883SInki Dae if (is_checked) 5121c248b7dSInki Dae drm_vblank_put(drm_dev, crtc); 5131c248b7dSInki Dae 5141c248b7dSInki Dae spin_unlock_irqrestore(&drm_dev->event_lock, flags); 5151c248b7dSInki Dae } 5161c248b7dSInki Dae 5171c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 5181c248b7dSInki Dae { 5191c248b7dSInki Dae struct fimd_context *ctx = (struct fimd_context *)dev_id; 5201c248b7dSInki Dae struct exynos_drm_subdrv *subdrv = &ctx->subdrv; 5211c248b7dSInki Dae struct drm_device *drm_dev = subdrv->drm_dev; 5221c248b7dSInki Dae struct exynos_drm_manager *manager = &subdrv->manager; 5231c248b7dSInki Dae u32 val; 5241c248b7dSInki Dae 5251c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON1); 5261c248b7dSInki Dae 5271c248b7dSInki Dae if (val & VIDINTCON1_INT_FRAME) 5281c248b7dSInki Dae /* VSYNC interrupt */ 5291c248b7dSInki Dae writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); 5301c248b7dSInki Dae 5311c248b7dSInki Dae drm_handle_vblank(drm_dev, manager->pipe); 5321c248b7dSInki Dae fimd_finish_pageflip(drm_dev, manager->pipe); 5331c248b7dSInki Dae 5341c248b7dSInki Dae return IRQ_HANDLED; 5351c248b7dSInki Dae } 5361c248b7dSInki Dae 53741c24346SInki Dae static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) 5381c248b7dSInki Dae { 5391c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 5401c248b7dSInki Dae 5411c248b7dSInki Dae /* 5421c248b7dSInki Dae * enable drm irq mode. 5431c248b7dSInki Dae * - with irq_enabled = 1, we can use the vblank feature. 5441c248b7dSInki Dae * 5451c248b7dSInki Dae * P.S. note that we wouldn't use drm irq handler but 5461c248b7dSInki Dae * just specific driver own one instead because 5471c248b7dSInki Dae * drm framework supports only one irq handler. 5481c248b7dSInki Dae */ 5491c248b7dSInki Dae drm_dev->irq_enabled = 1; 5501c248b7dSInki Dae 5511c248b7dSInki Dae /* 5521c248b7dSInki Dae * with vblank_disable_allowed = 1, vblank interrupt will be disabled 5531c248b7dSInki Dae * by drm timer once a current process gives up ownership of 5541c248b7dSInki Dae * vblank event.(drm_vblank_put function was called) 5551c248b7dSInki Dae */ 5561c248b7dSInki Dae drm_dev->vblank_disable_allowed = 1; 5571c248b7dSInki Dae 5581c248b7dSInki Dae return 0; 5591c248b7dSInki Dae } 5601c248b7dSInki Dae 5611c248b7dSInki Dae static void fimd_subdrv_remove(struct drm_device *drm_dev) 5621c248b7dSInki Dae { 5631c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 5641c248b7dSInki Dae 5651c248b7dSInki Dae /* TODO. */ 5661c248b7dSInki Dae } 5671c248b7dSInki Dae 5681c248b7dSInki Dae static int fimd_calc_clkdiv(struct fimd_context *ctx, 5691c248b7dSInki Dae struct fb_videomode *timing) 5701c248b7dSInki Dae { 5711c248b7dSInki Dae unsigned long clk = clk_get_rate(ctx->lcd_clk); 5721c248b7dSInki Dae u32 retrace; 5731c248b7dSInki Dae u32 clkdiv; 5741c248b7dSInki Dae u32 best_framerate = 0; 5751c248b7dSInki Dae u32 framerate; 5761c248b7dSInki Dae 5771c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 5781c248b7dSInki Dae 5791c248b7dSInki Dae retrace = timing->left_margin + timing->hsync_len + 5801c248b7dSInki Dae timing->right_margin + timing->xres; 5811c248b7dSInki Dae retrace *= timing->upper_margin + timing->vsync_len + 5821c248b7dSInki Dae timing->lower_margin + timing->yres; 5831c248b7dSInki Dae 5841c248b7dSInki Dae /* default framerate is 60Hz */ 5851c248b7dSInki Dae if (!timing->refresh) 5861c248b7dSInki Dae timing->refresh = 60; 5871c248b7dSInki Dae 5881c248b7dSInki Dae clk /= retrace; 5891c248b7dSInki Dae 5901c248b7dSInki Dae for (clkdiv = 1; clkdiv < 0x100; clkdiv++) { 5911c248b7dSInki Dae int tmp; 5921c248b7dSInki Dae 5931c248b7dSInki Dae /* get best framerate */ 5941c248b7dSInki Dae framerate = clk / clkdiv; 5951c248b7dSInki Dae tmp = timing->refresh - framerate; 5961c248b7dSInki Dae if (tmp < 0) { 5971c248b7dSInki Dae best_framerate = framerate; 5981c248b7dSInki Dae continue; 5991c248b7dSInki Dae } else { 6001c248b7dSInki Dae if (!best_framerate) 6011c248b7dSInki Dae best_framerate = framerate; 6021c248b7dSInki Dae else if (tmp < (best_framerate - framerate)) 6031c248b7dSInki Dae best_framerate = framerate; 6041c248b7dSInki Dae break; 6051c248b7dSInki Dae } 6061c248b7dSInki Dae } 6071c248b7dSInki Dae 6081c248b7dSInki Dae return clkdiv; 6091c248b7dSInki Dae } 6101c248b7dSInki Dae 6111c248b7dSInki Dae static void fimd_clear_win(struct fimd_context *ctx, int win) 6121c248b7dSInki Dae { 6131c248b7dSInki Dae u32 val; 6141c248b7dSInki Dae 6151c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 6161c248b7dSInki Dae 6171c248b7dSInki Dae writel(0, ctx->regs + WINCON(win)); 6181c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_A(win)); 6191c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_B(win)); 6201c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_C(win)); 6211c248b7dSInki Dae 6221c248b7dSInki Dae if (win == 1 || win == 2) 6231c248b7dSInki Dae writel(0, ctx->regs + VIDOSD_D(win)); 6241c248b7dSInki Dae 6251c248b7dSInki Dae val = readl(ctx->regs + SHADOWCON); 6261c248b7dSInki Dae val &= ~SHADOWCON_WINx_PROTECT(win); 6271c248b7dSInki Dae writel(val, ctx->regs + SHADOWCON); 6281c248b7dSInki Dae } 6291c248b7dSInki Dae 6301c248b7dSInki Dae static int __devinit fimd_probe(struct platform_device *pdev) 6311c248b7dSInki Dae { 6321c248b7dSInki Dae struct device *dev = &pdev->dev; 6331c248b7dSInki Dae struct fimd_context *ctx; 6341c248b7dSInki Dae struct exynos_drm_subdrv *subdrv; 6351c248b7dSInki Dae struct exynos_drm_fimd_pdata *pdata; 6361c248b7dSInki Dae struct fb_videomode *timing; 6371c248b7dSInki Dae struct resource *res; 6381c248b7dSInki Dae int win; 6391c248b7dSInki Dae int ret = -EINVAL; 6401c248b7dSInki Dae 6411c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 6421c248b7dSInki Dae 6431c248b7dSInki Dae pdata = pdev->dev.platform_data; 6441c248b7dSInki Dae if (!pdata) { 6451c248b7dSInki Dae dev_err(dev, "no platform data specified\n"); 6461c248b7dSInki Dae return -EINVAL; 6471c248b7dSInki Dae } 6481c248b7dSInki Dae 6491c248b7dSInki Dae timing = &pdata->timing; 6501c248b7dSInki Dae if (!timing) { 6511c248b7dSInki Dae dev_err(dev, "timing is null.\n"); 6521c248b7dSInki Dae return -EINVAL; 6531c248b7dSInki Dae } 6541c248b7dSInki Dae 6551c248b7dSInki Dae ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 6561c248b7dSInki Dae if (!ctx) 6571c248b7dSInki Dae return -ENOMEM; 6581c248b7dSInki Dae 6591c248b7dSInki Dae ctx->bus_clk = clk_get(dev, "fimd"); 6601c248b7dSInki Dae if (IS_ERR(ctx->bus_clk)) { 6611c248b7dSInki Dae dev_err(dev, "failed to get bus clock\n"); 6621c248b7dSInki Dae ret = PTR_ERR(ctx->bus_clk); 6631c248b7dSInki Dae goto err_clk_get; 6641c248b7dSInki Dae } 6651c248b7dSInki Dae 6661c248b7dSInki Dae clk_enable(ctx->bus_clk); 6671c248b7dSInki Dae 6681c248b7dSInki Dae ctx->lcd_clk = clk_get(dev, "sclk_fimd"); 6691c248b7dSInki Dae if (IS_ERR(ctx->lcd_clk)) { 6701c248b7dSInki Dae dev_err(dev, "failed to get lcd clock\n"); 6711c248b7dSInki Dae ret = PTR_ERR(ctx->lcd_clk); 6721c248b7dSInki Dae goto err_bus_clk; 6731c248b7dSInki Dae } 6741c248b7dSInki Dae 6751c248b7dSInki Dae clk_enable(ctx->lcd_clk); 6761c248b7dSInki Dae 6771c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 6781c248b7dSInki Dae if (!res) { 6791c248b7dSInki Dae dev_err(dev, "failed to find registers\n"); 6801c248b7dSInki Dae ret = -ENOENT; 6811c248b7dSInki Dae goto err_clk; 6821c248b7dSInki Dae } 6831c248b7dSInki Dae 6841c248b7dSInki Dae ctx->regs_res = request_mem_region(res->start, resource_size(res), 6851c248b7dSInki Dae dev_name(dev)); 6861c248b7dSInki Dae if (!ctx->regs_res) { 6871c248b7dSInki Dae dev_err(dev, "failed to claim register region\n"); 6881c248b7dSInki Dae ret = -ENOENT; 6891c248b7dSInki Dae goto err_clk; 6901c248b7dSInki Dae } 6911c248b7dSInki Dae 6921c248b7dSInki Dae ctx->regs = ioremap(res->start, resource_size(res)); 6931c248b7dSInki Dae if (!ctx->regs) { 6941c248b7dSInki Dae dev_err(dev, "failed to map registers\n"); 6951c248b7dSInki Dae ret = -ENXIO; 6961c248b7dSInki Dae goto err_req_region_io; 6971c248b7dSInki Dae } 6981c248b7dSInki Dae 6991c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 7001c248b7dSInki Dae if (!res) { 7011c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 7021c248b7dSInki Dae goto err_req_region_irq; 7031c248b7dSInki Dae } 7041c248b7dSInki Dae 7051c248b7dSInki Dae ctx->irq = res->start; 7061c248b7dSInki Dae 7071c248b7dSInki Dae for (win = 0; win < WINDOWS_NR; win++) 7081c248b7dSInki Dae fimd_clear_win(ctx, win); 7091c248b7dSInki Dae 7101c248b7dSInki Dae ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx); 7111c248b7dSInki Dae if (ret < 0) { 7121c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 7131c248b7dSInki Dae goto err_req_irq; 7141c248b7dSInki Dae } 7151c248b7dSInki Dae 7161c248b7dSInki Dae ctx->clkdiv = fimd_calc_clkdiv(ctx, timing); 7171c248b7dSInki Dae ctx->vidcon0 = pdata->vidcon0; 7181c248b7dSInki Dae ctx->vidcon1 = pdata->vidcon1; 7191c248b7dSInki Dae ctx->default_win = pdata->default_win; 7201c248b7dSInki Dae ctx->timing = timing; 7211c248b7dSInki Dae 7221c248b7dSInki Dae timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv; 7231c248b7dSInki Dae 7241c248b7dSInki Dae DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n", 7251c248b7dSInki Dae timing->pixclock, ctx->clkdiv); 7261c248b7dSInki Dae 7271c248b7dSInki Dae subdrv = &ctx->subdrv; 7281c248b7dSInki Dae 7291c248b7dSInki Dae subdrv->probe = fimd_subdrv_probe; 7301c248b7dSInki Dae subdrv->remove = fimd_subdrv_remove; 7311c248b7dSInki Dae subdrv->manager.pipe = -1; 7321c248b7dSInki Dae subdrv->manager.ops = &fimd_manager_ops; 7331c248b7dSInki Dae subdrv->manager.overlay_ops = &fimd_overlay_ops; 73474ccc539SInki Dae subdrv->manager.display_ops = &fimd_display_ops; 7351c248b7dSInki Dae subdrv->manager.dev = dev; 7361c248b7dSInki Dae 7371c248b7dSInki Dae platform_set_drvdata(pdev, ctx); 7381c248b7dSInki Dae exynos_drm_subdrv_register(subdrv); 7391c248b7dSInki Dae 7401c248b7dSInki Dae return 0; 7411c248b7dSInki Dae 7421c248b7dSInki Dae err_req_irq: 7431c248b7dSInki Dae err_req_region_irq: 7441c248b7dSInki Dae iounmap(ctx->regs); 7451c248b7dSInki Dae 7461c248b7dSInki Dae err_req_region_io: 7471c248b7dSInki Dae release_resource(ctx->regs_res); 7481c248b7dSInki Dae kfree(ctx->regs_res); 7491c248b7dSInki Dae 7501c248b7dSInki Dae err_clk: 7511c248b7dSInki Dae clk_disable(ctx->lcd_clk); 7521c248b7dSInki Dae clk_put(ctx->lcd_clk); 7531c248b7dSInki Dae 7541c248b7dSInki Dae err_bus_clk: 7551c248b7dSInki Dae clk_disable(ctx->bus_clk); 7561c248b7dSInki Dae clk_put(ctx->bus_clk); 7571c248b7dSInki Dae 7581c248b7dSInki Dae err_clk_get: 7591c248b7dSInki Dae kfree(ctx); 7601c248b7dSInki Dae return ret; 7611c248b7dSInki Dae } 7621c248b7dSInki Dae 7631c248b7dSInki Dae static int __devexit fimd_remove(struct platform_device *pdev) 7641c248b7dSInki Dae { 7651c248b7dSInki Dae struct fimd_context *ctx = platform_get_drvdata(pdev); 7661c248b7dSInki Dae 7671c248b7dSInki Dae DRM_DEBUG_KMS("%s\n", __FILE__); 7681c248b7dSInki Dae 7691c248b7dSInki Dae exynos_drm_subdrv_unregister(&ctx->subdrv); 7701c248b7dSInki Dae 7711c248b7dSInki Dae clk_disable(ctx->lcd_clk); 7721c248b7dSInki Dae clk_disable(ctx->bus_clk); 7731c248b7dSInki Dae clk_put(ctx->lcd_clk); 7741c248b7dSInki Dae clk_put(ctx->bus_clk); 7751c248b7dSInki Dae 7761c248b7dSInki Dae iounmap(ctx->regs); 7771c248b7dSInki Dae release_resource(ctx->regs_res); 7781c248b7dSInki Dae kfree(ctx->regs_res); 7791c248b7dSInki Dae free_irq(ctx->irq, ctx); 7801c248b7dSInki Dae 7811c248b7dSInki Dae kfree(ctx); 7821c248b7dSInki Dae 7831c248b7dSInki Dae return 0; 7841c248b7dSInki Dae } 7851c248b7dSInki Dae 7861c248b7dSInki Dae static struct platform_driver fimd_driver = { 7871c248b7dSInki Dae .probe = fimd_probe, 7881c248b7dSInki Dae .remove = __devexit_p(fimd_remove), 7891c248b7dSInki Dae .driver = { 7901c248b7dSInki Dae .name = "exynos4-fb", 7911c248b7dSInki Dae .owner = THIS_MODULE, 7921c248b7dSInki Dae }, 7931c248b7dSInki Dae }; 7941c248b7dSInki Dae 7951c248b7dSInki Dae static int __init fimd_init(void) 7961c248b7dSInki Dae { 7971c248b7dSInki Dae return platform_driver_register(&fimd_driver); 7981c248b7dSInki Dae } 7991c248b7dSInki Dae 8001c248b7dSInki Dae static void __exit fimd_exit(void) 8011c248b7dSInki Dae { 8021c248b7dSInki Dae platform_driver_unregister(&fimd_driver); 8031c248b7dSInki Dae } 8041c248b7dSInki Dae 8051c248b7dSInki Dae module_init(fimd_init); 8061c248b7dSInki Dae module_exit(fimd_exit); 8071c248b7dSInki Dae 8081c248b7dSInki Dae MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>"); 8091c248b7dSInki Dae MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>"); 8101c248b7dSInki Dae MODULE_DESCRIPTION("Samsung DRM FIMD Driver"); 8111c248b7dSInki Dae MODULE_LICENSE("GPL"); 812