11c248b7dSInki Dae /* exynos_drm_fimd.c 21c248b7dSInki Dae * 31c248b7dSInki Dae * Copyright (C) 2011 Samsung Electronics Co.Ltd 41c248b7dSInki Dae * Authors: 51c248b7dSInki Dae * Joonyoung Shim <jy0922.shim@samsung.com> 61c248b7dSInki Dae * Inki Dae <inki.dae@samsung.com> 71c248b7dSInki Dae * 81c248b7dSInki Dae * This program is free software; you can redistribute it and/or modify it 91c248b7dSInki Dae * under the terms of the GNU General Public License as published by the 101c248b7dSInki Dae * Free Software Foundation; either version 2 of the License, or (at your 111c248b7dSInki Dae * option) any later version. 121c248b7dSInki Dae * 131c248b7dSInki Dae */ 14760285e7SDavid Howells #include <drm/drmP.h> 151c248b7dSInki Dae 161c248b7dSInki Dae #include <linux/kernel.h> 171c248b7dSInki Dae #include <linux/platform_device.h> 181c248b7dSInki Dae #include <linux/clk.h> 193f1c781dSSachin Kamat #include <linux/of.h> 20d636ead8SJoonyoung Shim #include <linux/of_device.h> 21cb91f6a0SJoonyoung Shim #include <linux/pm_runtime.h> 22f37cd5e8SInki Dae #include <linux/component.h> 233854fab2SYoungJun Cho #include <linux/mfd/syscon.h> 243854fab2SYoungJun Cho #include <linux/regmap.h> 251c248b7dSInki Dae 267f4596f4SVikas Sajjan #include <video/of_display_timing.h> 27111e6055SAndrzej Hajda #include <video/of_videomode.h> 285a213a55SLeela Krishna Amudala #include <video/samsung_fimd.h> 291c248b7dSInki Dae #include <drm/exynos_drm.h> 301c248b7dSInki Dae 311c248b7dSInki Dae #include "exynos_drm_drv.h" 321c248b7dSInki Dae #include "exynos_drm_fbdev.h" 331c248b7dSInki Dae #include "exynos_drm_crtc.h" 347ee14cdcSGustavo Padovan #include "exynos_drm_plane.h" 35bcc5cd1cSInki Dae #include "exynos_drm_iommu.h" 361c248b7dSInki Dae 371c248b7dSInki Dae /* 38b8654b37SSachin Kamat * FIMD stands for Fully Interactive Mobile Display and 391c248b7dSInki Dae * as a display controller, it transfers contents drawn on memory 401c248b7dSInki Dae * to a LCD Panel through Display Interfaces such as RGB or 411c248b7dSInki Dae * CPU Interface. 421c248b7dSInki Dae */ 431c248b7dSInki Dae 44111e6055SAndrzej Hajda #define FIMD_DEFAULT_FRAMERATE 60 4566367461SRahul Sharma #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 46111e6055SAndrzej Hajda 471c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/ 481c248b7dSInki Dae #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) 491c248b7dSInki Dae #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) 500f10cf14SLeela Krishna Amudala /* 510f10cf14SLeela Krishna Amudala * size control register for hardware windows 0 and alpha control register 520f10cf14SLeela Krishna Amudala * for hardware windows 1 ~ 4 530f10cf14SLeela Krishna Amudala */ 540f10cf14SLeela Krishna Amudala #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16) 550f10cf14SLeela Krishna Amudala /* size control register for hardware windows 1 ~ 2. */ 561c248b7dSInki Dae #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) 571c248b7dSInki Dae 58453b44a3SGustavo Padovan #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8) 59453b44a3SGustavo Padovan #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8) 60453b44a3SGustavo Padovan 611c248b7dSInki Dae #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) 621c248b7dSInki Dae #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) 631c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) 641c248b7dSInki Dae 651c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */ 660f10cf14SLeela Krishna Amudala #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8)) 671c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */ 680f10cf14SLeela Krishna Amudala #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8)) 691c248b7dSInki Dae 703854fab2SYoungJun Cho /* I80 / RGB trigger control register */ 713854fab2SYoungJun Cho #define TRIGCON 0x1A4 723854fab2SYoungJun Cho #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) 733854fab2SYoungJun Cho #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) 743854fab2SYoungJun Cho 753854fab2SYoungJun Cho /* display mode change control register except exynos4 */ 763854fab2SYoungJun Cho #define VIDOUT_CON 0x000 773854fab2SYoungJun Cho #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8) 783854fab2SYoungJun Cho 793854fab2SYoungJun Cho /* I80 interface control for main LDI register */ 803854fab2SYoungJun Cho #define I80IFCONFAx(x) (0x1B0 + (x) * 4) 813854fab2SYoungJun Cho #define I80IFCONFBx(x) (0x1B8 + (x) * 4) 823854fab2SYoungJun Cho #define LCD_CS_SETUP(x) ((x) << 16) 833854fab2SYoungJun Cho #define LCD_WR_SETUP(x) ((x) << 12) 843854fab2SYoungJun Cho #define LCD_WR_ACTIVE(x) ((x) << 8) 853854fab2SYoungJun Cho #define LCD_WR_HOLD(x) ((x) << 4) 863854fab2SYoungJun Cho #define I80IFEN_ENABLE (1 << 0) 873854fab2SYoungJun Cho 881c248b7dSInki Dae /* FIMD has totally five hardware windows. */ 891c248b7dSInki Dae #define WINDOWS_NR 5 901c248b7dSInki Dae 91e2e13389SLeela Krishna Amudala struct fimd_driver_data { 92e2e13389SLeela Krishna Amudala unsigned int timing_base; 933854fab2SYoungJun Cho unsigned int lcdblk_offset; 943854fab2SYoungJun Cho unsigned int lcdblk_vt_shift; 953854fab2SYoungJun Cho unsigned int lcdblk_bypass_shift; 96de7af100STomasz Figa 97de7af100STomasz Figa unsigned int has_shadowcon:1; 98411d9ed4STomasz Figa unsigned int has_clksel:1; 995cc4621aSInki Dae unsigned int has_limited_fmt:1; 1003854fab2SYoungJun Cho unsigned int has_vidoutcon:1; 1013c3c9c1dSJoonyoung Shim unsigned int has_vtsel:1; 102e2e13389SLeela Krishna Amudala }; 103e2e13389SLeela Krishna Amudala 104725ddeadSTomasz Figa static struct fimd_driver_data s3c64xx_fimd_driver_data = { 105725ddeadSTomasz Figa .timing_base = 0x0, 106725ddeadSTomasz Figa .has_clksel = 1, 1075cc4621aSInki Dae .has_limited_fmt = 1, 108725ddeadSTomasz Figa }; 109725ddeadSTomasz Figa 110d6ce7b58SInki Dae static struct fimd_driver_data exynos3_fimd_driver_data = { 111d6ce7b58SInki Dae .timing_base = 0x20000, 112d6ce7b58SInki Dae .lcdblk_offset = 0x210, 113d6ce7b58SInki Dae .lcdblk_bypass_shift = 1, 114d6ce7b58SInki Dae .has_shadowcon = 1, 115d6ce7b58SInki Dae .has_vidoutcon = 1, 116d6ce7b58SInki Dae }; 117d6ce7b58SInki Dae 1186ecf18f9SSachin Kamat static struct fimd_driver_data exynos4_fimd_driver_data = { 119e2e13389SLeela Krishna Amudala .timing_base = 0x0, 1203854fab2SYoungJun Cho .lcdblk_offset = 0x210, 1213854fab2SYoungJun Cho .lcdblk_vt_shift = 10, 1223854fab2SYoungJun Cho .lcdblk_bypass_shift = 1, 123de7af100STomasz Figa .has_shadowcon = 1, 1243c3c9c1dSJoonyoung Shim .has_vtsel = 1, 125e2e13389SLeela Krishna Amudala }; 126e2e13389SLeela Krishna Amudala 127dcb622aaSYoungJun Cho static struct fimd_driver_data exynos4415_fimd_driver_data = { 128dcb622aaSYoungJun Cho .timing_base = 0x20000, 129dcb622aaSYoungJun Cho .lcdblk_offset = 0x210, 130dcb622aaSYoungJun Cho .lcdblk_vt_shift = 10, 131dcb622aaSYoungJun Cho .lcdblk_bypass_shift = 1, 132dcb622aaSYoungJun Cho .has_shadowcon = 1, 133dcb622aaSYoungJun Cho .has_vidoutcon = 1, 1343c3c9c1dSJoonyoung Shim .has_vtsel = 1, 135dcb622aaSYoungJun Cho }; 136dcb622aaSYoungJun Cho 1376ecf18f9SSachin Kamat static struct fimd_driver_data exynos5_fimd_driver_data = { 138e2e13389SLeela Krishna Amudala .timing_base = 0x20000, 1393854fab2SYoungJun Cho .lcdblk_offset = 0x214, 1403854fab2SYoungJun Cho .lcdblk_vt_shift = 24, 1413854fab2SYoungJun Cho .lcdblk_bypass_shift = 15, 142de7af100STomasz Figa .has_shadowcon = 1, 1433854fab2SYoungJun Cho .has_vidoutcon = 1, 1443c3c9c1dSJoonyoung Shim .has_vtsel = 1, 145e2e13389SLeela Krishna Amudala }; 146e2e13389SLeela Krishna Amudala 1471c248b7dSInki Dae struct fimd_context { 148bb7704d6SSean Paul struct device *dev; 14940c8ab4bSSean Paul struct drm_device *drm_dev; 15093bca243SGustavo Padovan struct exynos_drm_crtc *crtc; 1517ee14cdcSGustavo Padovan struct exynos_drm_plane planes[WINDOWS_NR]; 1521c248b7dSInki Dae struct clk *bus_clk; 1531c248b7dSInki Dae struct clk *lcd_clk; 1541c248b7dSInki Dae void __iomem *regs; 1553854fab2SYoungJun Cho struct regmap *sysreg; 1561c248b7dSInki Dae unsigned int default_win; 1571c248b7dSInki Dae unsigned long irq_flags; 1583854fab2SYoungJun Cho u32 vidcon0; 1591c248b7dSInki Dae u32 vidcon1; 1603854fab2SYoungJun Cho u32 vidout_con; 1613854fab2SYoungJun Cho u32 i80ifcon; 1623854fab2SYoungJun Cho bool i80_if; 163cb91f6a0SJoonyoung Shim bool suspended; 164080be03dSSean Paul int pipe; 16501ce113cSPrathyush K wait_queue_head_t wait_vsync_queue; 16601ce113cSPrathyush K atomic_t wait_vsync_event; 1673854fab2SYoungJun Cho atomic_t win_updated; 1683854fab2SYoungJun Cho atomic_t triggering; 1691c248b7dSInki Dae 170562ad9f4SAndrzej Hajda struct exynos_drm_panel_info panel; 17118873465STomasz Figa struct fimd_driver_data *driver_data; 172000cc920SAndrzej Hajda struct exynos_drm_display *display; 1731c248b7dSInki Dae }; 1741c248b7dSInki Dae 175d636ead8SJoonyoung Shim static const struct of_device_id fimd_driver_dt_match[] = { 176725ddeadSTomasz Figa { .compatible = "samsung,s3c6400-fimd", 177725ddeadSTomasz Figa .data = &s3c64xx_fimd_driver_data }, 178d6ce7b58SInki Dae { .compatible = "samsung,exynos3250-fimd", 179d6ce7b58SInki Dae .data = &exynos3_fimd_driver_data }, 1805830daf8SVikas Sajjan { .compatible = "samsung,exynos4210-fimd", 181d636ead8SJoonyoung Shim .data = &exynos4_fimd_driver_data }, 182dcb622aaSYoungJun Cho { .compatible = "samsung,exynos4415-fimd", 183dcb622aaSYoungJun Cho .data = &exynos4415_fimd_driver_data }, 1845830daf8SVikas Sajjan { .compatible = "samsung,exynos5250-fimd", 185d636ead8SJoonyoung Shim .data = &exynos5_fimd_driver_data }, 186d636ead8SJoonyoung Shim {}, 187d636ead8SJoonyoung Shim }; 1880262ceebSSjoerd Simons MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); 189d636ead8SJoonyoung Shim 190e2e13389SLeela Krishna Amudala static inline struct fimd_driver_data *drm_fimd_get_driver_data( 191e2e13389SLeela Krishna Amudala struct platform_device *pdev) 192e2e13389SLeela Krishna Amudala { 193d636ead8SJoonyoung Shim const struct of_device_id *of_id = 194d636ead8SJoonyoung Shim of_match_device(fimd_driver_dt_match, &pdev->dev); 195d636ead8SJoonyoung Shim 196d636ead8SJoonyoung Shim return (struct fimd_driver_data *)of_id->data; 197e2e13389SLeela Krishna Amudala } 198e2e13389SLeela Krishna Amudala 199fb88e214SMarek Szyprowski static int fimd_enable_vblank(struct exynos_drm_crtc *crtc) 200fb88e214SMarek Szyprowski { 201fb88e214SMarek Szyprowski struct fimd_context *ctx = crtc->ctx; 202fb88e214SMarek Szyprowski u32 val; 203fb88e214SMarek Szyprowski 204fb88e214SMarek Szyprowski if (ctx->suspended) 205fb88e214SMarek Szyprowski return -EPERM; 206fb88e214SMarek Szyprowski 207fb88e214SMarek Szyprowski if (!test_and_set_bit(0, &ctx->irq_flags)) { 208fb88e214SMarek Szyprowski val = readl(ctx->regs + VIDINTCON0); 209fb88e214SMarek Szyprowski 210fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_ENABLE; 211fb88e214SMarek Szyprowski 212fb88e214SMarek Szyprowski if (ctx->i80_if) { 213fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_I80IFDONE; 214fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_SYSMAINCON; 215fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSSUBCON; 216fb88e214SMarek Szyprowski } else { 217fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_FRAME; 218fb88e214SMarek Szyprowski 219fb88e214SMarek Szyprowski val &= ~VIDINTCON0_FRAMESEL0_MASK; 220fb88e214SMarek Szyprowski val |= VIDINTCON0_FRAMESEL0_VSYNC; 221fb88e214SMarek Szyprowski val &= ~VIDINTCON0_FRAMESEL1_MASK; 222fb88e214SMarek Szyprowski val |= VIDINTCON0_FRAMESEL1_NONE; 223fb88e214SMarek Szyprowski } 224fb88e214SMarek Szyprowski 225fb88e214SMarek Szyprowski writel(val, ctx->regs + VIDINTCON0); 226fb88e214SMarek Szyprowski } 227fb88e214SMarek Szyprowski 228fb88e214SMarek Szyprowski return 0; 229fb88e214SMarek Szyprowski } 230fb88e214SMarek Szyprowski 231fb88e214SMarek Szyprowski static void fimd_disable_vblank(struct exynos_drm_crtc *crtc) 232fb88e214SMarek Szyprowski { 233fb88e214SMarek Szyprowski struct fimd_context *ctx = crtc->ctx; 234fb88e214SMarek Szyprowski u32 val; 235fb88e214SMarek Szyprowski 236fb88e214SMarek Szyprowski if (ctx->suspended) 237fb88e214SMarek Szyprowski return; 238fb88e214SMarek Szyprowski 239fb88e214SMarek Szyprowski if (test_and_clear_bit(0, &ctx->irq_flags)) { 240fb88e214SMarek Szyprowski val = readl(ctx->regs + VIDINTCON0); 241fb88e214SMarek Szyprowski 242fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_ENABLE; 243fb88e214SMarek Szyprowski 244fb88e214SMarek Szyprowski if (ctx->i80_if) { 245fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_I80IFDONE; 246fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSMAINCON; 247fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSSUBCON; 248fb88e214SMarek Szyprowski } else 249fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_FRAME; 250fb88e214SMarek Szyprowski 251fb88e214SMarek Szyprowski writel(val, ctx->regs + VIDINTCON0); 252fb88e214SMarek Szyprowski } 253fb88e214SMarek Szyprowski } 254fb88e214SMarek Szyprowski 25593bca243SGustavo Padovan static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc) 256f13bdbd1SAkshu Agrawal { 25793bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 258f13bdbd1SAkshu Agrawal 259f13bdbd1SAkshu Agrawal if (ctx->suspended) 260f13bdbd1SAkshu Agrawal return; 261f13bdbd1SAkshu Agrawal 262f13bdbd1SAkshu Agrawal atomic_set(&ctx->wait_vsync_event, 1); 263f13bdbd1SAkshu Agrawal 264f13bdbd1SAkshu Agrawal /* 265f13bdbd1SAkshu Agrawal * wait for FIMD to signal VSYNC interrupt or return after 266f13bdbd1SAkshu Agrawal * timeout which is set to 50ms (refresh rate of 20). 267f13bdbd1SAkshu Agrawal */ 268f13bdbd1SAkshu Agrawal if (!wait_event_timeout(ctx->wait_vsync_queue, 269f13bdbd1SAkshu Agrawal !atomic_read(&ctx->wait_vsync_event), 270f13bdbd1SAkshu Agrawal HZ/20)) 271f13bdbd1SAkshu Agrawal DRM_DEBUG_KMS("vblank wait timed out.\n"); 272f13bdbd1SAkshu Agrawal } 273f13bdbd1SAkshu Agrawal 2745b1d5bc6STobias Jakobi static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win, 275f181a543SYoungJun Cho bool enable) 276f181a543SYoungJun Cho { 277f181a543SYoungJun Cho u32 val = readl(ctx->regs + WINCON(win)); 278f181a543SYoungJun Cho 279f181a543SYoungJun Cho if (enable) 280f181a543SYoungJun Cho val |= WINCONx_ENWIN; 281f181a543SYoungJun Cho else 282f181a543SYoungJun Cho val &= ~WINCONx_ENWIN; 283f181a543SYoungJun Cho 284f181a543SYoungJun Cho writel(val, ctx->regs + WINCON(win)); 285f181a543SYoungJun Cho } 286f181a543SYoungJun Cho 2875b1d5bc6STobias Jakobi static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, 2885b1d5bc6STobias Jakobi unsigned int win, 289999d8b31SYoungJun Cho bool enable) 290999d8b31SYoungJun Cho { 291999d8b31SYoungJun Cho u32 val = readl(ctx->regs + SHADOWCON); 292999d8b31SYoungJun Cho 293999d8b31SYoungJun Cho if (enable) 294999d8b31SYoungJun Cho val |= SHADOWCON_CHx_ENABLE(win); 295999d8b31SYoungJun Cho else 296999d8b31SYoungJun Cho val &= ~SHADOWCON_CHx_ENABLE(win); 297999d8b31SYoungJun Cho 298999d8b31SYoungJun Cho writel(val, ctx->regs + SHADOWCON); 299999d8b31SYoungJun Cho } 300999d8b31SYoungJun Cho 301fc2e013fSHyungwon Hwang static void fimd_clear_channels(struct exynos_drm_crtc *crtc) 302f13bdbd1SAkshu Agrawal { 303fc2e013fSHyungwon Hwang struct fimd_context *ctx = crtc->ctx; 3045b1d5bc6STobias Jakobi unsigned int win, ch_enabled = 0; 305f13bdbd1SAkshu Agrawal 306f13bdbd1SAkshu Agrawal DRM_DEBUG_KMS("%s\n", __FILE__); 307f13bdbd1SAkshu Agrawal 308fb88e214SMarek Szyprowski /* Hardware is in unknown state, so ensure it gets enabled properly */ 309fb88e214SMarek Szyprowski pm_runtime_get_sync(ctx->dev); 310fb88e214SMarek Szyprowski 311fb88e214SMarek Szyprowski clk_prepare_enable(ctx->bus_clk); 312fb88e214SMarek Szyprowski clk_prepare_enable(ctx->lcd_clk); 313fb88e214SMarek Szyprowski 314f13bdbd1SAkshu Agrawal /* Check if any channel is enabled. */ 315f13bdbd1SAkshu Agrawal for (win = 0; win < WINDOWS_NR; win++) { 316eb8a3bf7SMarek Szyprowski u32 val = readl(ctx->regs + WINCON(win)); 317eb8a3bf7SMarek Szyprowski 318eb8a3bf7SMarek Szyprowski if (val & WINCONx_ENWIN) { 319f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false); 320eb8a3bf7SMarek Szyprowski 321999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 322999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, 323999d8b31SYoungJun Cho false); 324999d8b31SYoungJun Cho 325f13bdbd1SAkshu Agrawal ch_enabled = 1; 326f13bdbd1SAkshu Agrawal } 327f13bdbd1SAkshu Agrawal } 328f13bdbd1SAkshu Agrawal 329f13bdbd1SAkshu Agrawal /* Wait for vsync, as disable channel takes effect at next vsync */ 330eb8a3bf7SMarek Szyprowski if (ch_enabled) { 331fb88e214SMarek Szyprowski int pipe = ctx->pipe; 332eb8a3bf7SMarek Szyprowski 333fb88e214SMarek Szyprowski /* ensure that vblank interrupt won't be reported to core */ 334fb88e214SMarek Szyprowski ctx->suspended = false; 335fb88e214SMarek Szyprowski ctx->pipe = -1; 336fb88e214SMarek Szyprowski 337fb88e214SMarek Szyprowski fimd_enable_vblank(ctx->crtc); 33892dc7a04SJoonyoung Shim fimd_wait_for_vblank(ctx->crtc); 339fb88e214SMarek Szyprowski fimd_disable_vblank(ctx->crtc); 340fb88e214SMarek Szyprowski 341fb88e214SMarek Szyprowski ctx->suspended = true; 342fb88e214SMarek Szyprowski ctx->pipe = pipe; 343eb8a3bf7SMarek Szyprowski } 344fb88e214SMarek Szyprowski 345fb88e214SMarek Szyprowski clk_disable_unprepare(ctx->lcd_clk); 346fb88e214SMarek Szyprowski clk_disable_unprepare(ctx->bus_clk); 347fb88e214SMarek Szyprowski 348fb88e214SMarek Szyprowski pm_runtime_put(ctx->dev); 349f13bdbd1SAkshu Agrawal } 350f13bdbd1SAkshu Agrawal 351a968e727SSean Paul static u32 fimd_calc_clkdiv(struct fimd_context *ctx, 352a968e727SSean Paul const struct drm_display_mode *mode) 353a968e727SSean Paul { 354a968e727SSean Paul unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 355a968e727SSean Paul u32 clkdiv; 356a968e727SSean Paul 3573854fab2SYoungJun Cho if (ctx->i80_if) { 3583854fab2SYoungJun Cho /* 3593854fab2SYoungJun Cho * The frame done interrupt should be occurred prior to the 3603854fab2SYoungJun Cho * next TE signal. 3613854fab2SYoungJun Cho */ 3623854fab2SYoungJun Cho ideal_clk *= 2; 3633854fab2SYoungJun Cho } 3643854fab2SYoungJun Cho 365a968e727SSean Paul /* Find the clock divider value that gets us closest to ideal_clk */ 366a968e727SSean Paul clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk); 367a968e727SSean Paul 368a968e727SSean Paul return (clkdiv < 0x100) ? clkdiv : 0xff; 369a968e727SSean Paul } 370a968e727SSean Paul 37193bca243SGustavo Padovan static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, 372a968e727SSean Paul const struct drm_display_mode *mode, 373a968e727SSean Paul struct drm_display_mode *adjusted_mode) 374a968e727SSean Paul { 375a968e727SSean Paul if (adjusted_mode->vrefresh == 0) 376a968e727SSean Paul adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; 377a968e727SSean Paul 378a968e727SSean Paul return true; 379a968e727SSean Paul } 380a968e727SSean Paul 38193bca243SGustavo Padovan static void fimd_commit(struct exynos_drm_crtc *crtc) 3821c248b7dSInki Dae { 38393bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 384020e79deSJoonyoung Shim struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 3853854fab2SYoungJun Cho struct fimd_driver_data *driver_data = ctx->driver_data; 3863854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base; 3873854fab2SYoungJun Cho u32 val, clkdiv; 3881c248b7dSInki Dae 389e30d4bcfSInki Dae if (ctx->suspended) 390e30d4bcfSInki Dae return; 391e30d4bcfSInki Dae 392a968e727SSean Paul /* nothing to do if we haven't set the mode yet */ 393a968e727SSean Paul if (mode->htotal == 0 || mode->vtotal == 0) 394a968e727SSean Paul return; 395a968e727SSean Paul 3963854fab2SYoungJun Cho if (ctx->i80_if) { 3973854fab2SYoungJun Cho val = ctx->i80ifcon | I80IFEN_ENABLE; 3983854fab2SYoungJun Cho writel(val, timing_base + I80IFCONFAx(0)); 3993854fab2SYoungJun Cho 4003854fab2SYoungJun Cho /* disable auto frame rate */ 4013854fab2SYoungJun Cho writel(0, timing_base + I80IFCONFBx(0)); 4023854fab2SYoungJun Cho 4033854fab2SYoungJun Cho /* set video type selection to I80 interface */ 4043c3c9c1dSJoonyoung Shim if (driver_data->has_vtsel && ctx->sysreg && 4053c3c9c1dSJoonyoung Shim regmap_update_bits(ctx->sysreg, 4063854fab2SYoungJun Cho driver_data->lcdblk_offset, 4073854fab2SYoungJun Cho 0x3 << driver_data->lcdblk_vt_shift, 4083854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_vt_shift)) { 4093854fab2SYoungJun Cho DRM_ERROR("Failed to update sysreg for I80 i/f.\n"); 4103854fab2SYoungJun Cho return; 4113854fab2SYoungJun Cho } 4123854fab2SYoungJun Cho } else { 4133854fab2SYoungJun Cho int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 4143854fab2SYoungJun Cho u32 vidcon1; 4153854fab2SYoungJun Cho 4161417f109SSean Paul /* setup polarity values */ 4171417f109SSean Paul vidcon1 = ctx->vidcon1; 4181417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NVSYNC) 4191417f109SSean Paul vidcon1 |= VIDCON1_INV_VSYNC; 4201417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NHSYNC) 4211417f109SSean Paul vidcon1 |= VIDCON1_INV_HSYNC; 4221417f109SSean Paul writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); 4231c248b7dSInki Dae 4241c248b7dSInki Dae /* setup vertical timing values. */ 425a968e727SSean Paul vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 4268b4cad23SAndrzej Hajda vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 4278b4cad23SAndrzej Hajda vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 428a968e727SSean Paul 429a968e727SSean Paul val = VIDTCON0_VBPD(vbpd - 1) | 430a968e727SSean Paul VIDTCON0_VFPD(vfpd - 1) | 431a968e727SSean Paul VIDTCON0_VSPW(vsync_len - 1); 432e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); 4331c248b7dSInki Dae 4341c248b7dSInki Dae /* setup horizontal timing values. */ 435a968e727SSean Paul hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 4368b4cad23SAndrzej Hajda hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 4378b4cad23SAndrzej Hajda hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 438a968e727SSean Paul 439a968e727SSean Paul val = VIDTCON1_HBPD(hbpd - 1) | 440a968e727SSean Paul VIDTCON1_HFPD(hfpd - 1) | 441a968e727SSean Paul VIDTCON1_HSPW(hsync_len - 1); 442e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); 4433854fab2SYoungJun Cho } 4443854fab2SYoungJun Cho 4453854fab2SYoungJun Cho if (driver_data->has_vidoutcon) 4463854fab2SYoungJun Cho writel(ctx->vidout_con, timing_base + VIDOUT_CON); 4473854fab2SYoungJun Cho 4483854fab2SYoungJun Cho /* set bypass selection */ 4493854fab2SYoungJun Cho if (ctx->sysreg && regmap_update_bits(ctx->sysreg, 4503854fab2SYoungJun Cho driver_data->lcdblk_offset, 4513854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift, 4523854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift)) { 4533854fab2SYoungJun Cho DRM_ERROR("Failed to update sysreg for bypass setting.\n"); 4543854fab2SYoungJun Cho return; 4553854fab2SYoungJun Cho } 4561c248b7dSInki Dae 4571c248b7dSInki Dae /* setup horizontal and vertical display size. */ 458a968e727SSean Paul val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 459a968e727SSean Paul VIDTCON2_HOZVAL(mode->hdisplay - 1) | 460a968e727SSean Paul VIDTCON2_LINEVAL_E(mode->vdisplay - 1) | 461a968e727SSean Paul VIDTCON2_HOZVAL_E(mode->hdisplay - 1); 462e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); 4631c248b7dSInki Dae 4641c248b7dSInki Dae /* 4651c248b7dSInki Dae * fields of register with prefix '_F' would be updated 4661c248b7dSInki Dae * at vsync(same as dma start) 4671c248b7dSInki Dae */ 4683854fab2SYoungJun Cho val = ctx->vidcon0; 4693854fab2SYoungJun Cho val |= VIDCON0_ENVID | VIDCON0_ENVID_F; 4701d531062SAndrzej Hajda 4711d531062SAndrzej Hajda if (ctx->driver_data->has_clksel) 4721d531062SAndrzej Hajda val |= VIDCON0_CLKSEL_LCD; 4731d531062SAndrzej Hajda 4741d531062SAndrzej Hajda clkdiv = fimd_calc_clkdiv(ctx, mode); 4751d531062SAndrzej Hajda if (clkdiv > 1) 4761d531062SAndrzej Hajda val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; 4771d531062SAndrzej Hajda 4781c248b7dSInki Dae writel(val, ctx->regs + VIDCON0); 4791c248b7dSInki Dae } 4801c248b7dSInki Dae 4811c248b7dSInki Dae 482bb7704d6SSean Paul static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win) 4831c248b7dSInki Dae { 4847ee14cdcSGustavo Padovan struct exynos_drm_plane *plane = &ctx->planes[win]; 4851c248b7dSInki Dae unsigned long val; 4861c248b7dSInki Dae 4871c248b7dSInki Dae val = WINCONx_ENWIN; 4881c248b7dSInki Dae 4895cc4621aSInki Dae /* 4905cc4621aSInki Dae * In case of s3c64xx, window 0 doesn't support alpha channel. 4915cc4621aSInki Dae * So the request format is ARGB8888 then change it to XRGB8888. 4925cc4621aSInki Dae */ 4935cc4621aSInki Dae if (ctx->driver_data->has_limited_fmt && !win) { 4947ee14cdcSGustavo Padovan if (plane->pixel_format == DRM_FORMAT_ARGB8888) 4957ee14cdcSGustavo Padovan plane->pixel_format = DRM_FORMAT_XRGB8888; 4965cc4621aSInki Dae } 4975cc4621aSInki Dae 4987ee14cdcSGustavo Padovan switch (plane->pixel_format) { 499a4f38a80SInki Dae case DRM_FORMAT_C8: 5001c248b7dSInki Dae val |= WINCON0_BPPMODE_8BPP_PALETTE; 5011c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD; 5021c248b7dSInki Dae val |= WINCONx_BYTSWP; 5031c248b7dSInki Dae break; 504a4f38a80SInki Dae case DRM_FORMAT_XRGB1555: 505a4f38a80SInki Dae val |= WINCON0_BPPMODE_16BPP_1555; 506a4f38a80SInki Dae val |= WINCONx_HAWSWP; 507a4f38a80SInki Dae val |= WINCONx_BURSTLEN_16WORD; 508a4f38a80SInki Dae break; 509a4f38a80SInki Dae case DRM_FORMAT_RGB565: 5101c248b7dSInki Dae val |= WINCON0_BPPMODE_16BPP_565; 5111c248b7dSInki Dae val |= WINCONx_HAWSWP; 5121c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5131c248b7dSInki Dae break; 514a4f38a80SInki Dae case DRM_FORMAT_XRGB8888: 5151c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 5161c248b7dSInki Dae val |= WINCONx_WSWP; 5171c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5181c248b7dSInki Dae break; 519a4f38a80SInki Dae case DRM_FORMAT_ARGB8888: 520a4f38a80SInki Dae val |= WINCON1_BPPMODE_25BPP_A1888 5211c248b7dSInki Dae | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; 5221c248b7dSInki Dae val |= WINCONx_WSWP; 5231c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5241c248b7dSInki Dae break; 5251c248b7dSInki Dae default: 5261c248b7dSInki Dae DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 5271c248b7dSInki Dae 5281c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888; 5291c248b7dSInki Dae val |= WINCONx_WSWP; 5301c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD; 5311c248b7dSInki Dae break; 5321c248b7dSInki Dae } 5331c248b7dSInki Dae 5347ee14cdcSGustavo Padovan DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); 5351c248b7dSInki Dae 53666367461SRahul Sharma /* 53766367461SRahul Sharma * In case of exynos, setting dma-burst to 16Word causes permanent 53866367461SRahul Sharma * tearing for very small buffers, e.g. cursor buffer. Burst Mode 5398837deeaSGustavo Padovan * switching which is based on plane size is not recommended as 5408837deeaSGustavo Padovan * plane size varies alot towards the end of the screen and rapid 54166367461SRahul Sharma * movement causes unstable DMA which results into iommu crash/tear. 54266367461SRahul Sharma */ 54366367461SRahul Sharma 5447ee14cdcSGustavo Padovan if (plane->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 54566367461SRahul Sharma val &= ~WINCONx_BURSTLEN_MASK; 54666367461SRahul Sharma val |= WINCONx_BURSTLEN_4WORD; 54766367461SRahul Sharma } 54866367461SRahul Sharma 5491c248b7dSInki Dae writel(val, ctx->regs + WINCON(win)); 550453b44a3SGustavo Padovan 551453b44a3SGustavo Padovan /* hardware window 0 doesn't support alpha channel. */ 552453b44a3SGustavo Padovan if (win != 0) { 553453b44a3SGustavo Padovan /* OSD alpha */ 554453b44a3SGustavo Padovan val = VIDISD14C_ALPHA0_R(0xf) | 555453b44a3SGustavo Padovan VIDISD14C_ALPHA0_G(0xf) | 556453b44a3SGustavo Padovan VIDISD14C_ALPHA0_B(0xf) | 557453b44a3SGustavo Padovan VIDISD14C_ALPHA1_R(0xf) | 558453b44a3SGustavo Padovan VIDISD14C_ALPHA1_G(0xf) | 559453b44a3SGustavo Padovan VIDISD14C_ALPHA1_B(0xf); 560453b44a3SGustavo Padovan 561453b44a3SGustavo Padovan writel(val, ctx->regs + VIDOSD_C(win)); 562453b44a3SGustavo Padovan 563453b44a3SGustavo Padovan val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | 564453b44a3SGustavo Padovan VIDW_ALPHA_G(0xf); 565453b44a3SGustavo Padovan writel(val, ctx->regs + VIDWnALPHA0(win)); 566453b44a3SGustavo Padovan writel(val, ctx->regs + VIDWnALPHA1(win)); 567453b44a3SGustavo Padovan } 5681c248b7dSInki Dae } 5691c248b7dSInki Dae 570bb7704d6SSean Paul static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win) 5711c248b7dSInki Dae { 5721c248b7dSInki Dae unsigned int keycon0 = 0, keycon1 = 0; 5731c248b7dSInki Dae 5741c248b7dSInki Dae keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 5751c248b7dSInki Dae WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 5761c248b7dSInki Dae 5771c248b7dSInki Dae keycon1 = WxKEYCON1_COLVAL(0xffffffff); 5781c248b7dSInki Dae 5791c248b7dSInki Dae writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 5801c248b7dSInki Dae writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 5811c248b7dSInki Dae } 5821c248b7dSInki Dae 583de7af100STomasz Figa /** 584de7af100STomasz Figa * shadow_protect_win() - disable updating values from shadow registers at vsync 585de7af100STomasz Figa * 586de7af100STomasz Figa * @win: window to protect registers for 587de7af100STomasz Figa * @protect: 1 to protect (disable updates) 588de7af100STomasz Figa */ 589de7af100STomasz Figa static void fimd_shadow_protect_win(struct fimd_context *ctx, 5906e2a3b66SGustavo Padovan unsigned int win, bool protect) 591de7af100STomasz Figa { 592de7af100STomasz Figa u32 reg, bits, val; 593de7af100STomasz Figa 594de7af100STomasz Figa if (ctx->driver_data->has_shadowcon) { 595de7af100STomasz Figa reg = SHADOWCON; 596de7af100STomasz Figa bits = SHADOWCON_WINx_PROTECT(win); 597de7af100STomasz Figa } else { 598de7af100STomasz Figa reg = PRTCON; 599de7af100STomasz Figa bits = PRTCON_PROTECT; 600de7af100STomasz Figa } 601de7af100STomasz Figa 602de7af100STomasz Figa val = readl(ctx->regs + reg); 603de7af100STomasz Figa if (protect) 604de7af100STomasz Figa val |= bits; 605de7af100STomasz Figa else 606de7af100STomasz Figa val &= ~bits; 607de7af100STomasz Figa writel(val, ctx->regs + reg); 608de7af100STomasz Figa } 609de7af100STomasz Figa 6101e1d1393SGustavo Padovan static void fimd_update_plane(struct exynos_drm_crtc *crtc, 6111e1d1393SGustavo Padovan struct exynos_drm_plane *plane) 6121c248b7dSInki Dae { 61393bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 6147ee14cdcSGustavo Padovan dma_addr_t dma_addr; 6157ee14cdcSGustavo Padovan unsigned long val, size, offset; 6167ee14cdcSGustavo Padovan unsigned int last_x, last_y, buf_offsize, line_size; 6171e1d1393SGustavo Padovan unsigned int win = plane->zpos; 6181c248b7dSInki Dae 619e30d4bcfSInki Dae if (ctx->suspended) 620e30d4bcfSInki Dae return; 621e30d4bcfSInki Dae 6221c248b7dSInki Dae /* 623de7af100STomasz Figa * SHADOWCON/PRTCON register is used for enabling timing. 6241c248b7dSInki Dae * 6251c248b7dSInki Dae * for example, once only width value of a register is set, 6261c248b7dSInki Dae * if the dma is started then fimd hardware could malfunction so 6271c248b7dSInki Dae * with protect window setting, the register fields with prefix '_F' 6281c248b7dSInki Dae * wouldn't be updated at vsync also but updated once unprotect window 6291c248b7dSInki Dae * is set. 6301c248b7dSInki Dae */ 6311c248b7dSInki Dae 6321c248b7dSInki Dae /* protect windows */ 633de7af100STomasz Figa fimd_shadow_protect_win(ctx, win, true); 6341c248b7dSInki Dae 6357ee14cdcSGustavo Padovan 636cb8a3db2SJoonyoung Shim offset = plane->src_x * (plane->bpp >> 3); 637cb8a3db2SJoonyoung Shim offset += plane->src_y * plane->pitch; 6387ee14cdcSGustavo Padovan 6391c248b7dSInki Dae /* buffer start address */ 6407ee14cdcSGustavo Padovan dma_addr = plane->dma_addr[0] + offset; 6417ee14cdcSGustavo Padovan val = (unsigned long)dma_addr; 6421c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); 6431c248b7dSInki Dae 6441c248b7dSInki Dae /* buffer end address */ 64568a29134SDaniel Stone size = plane->pitch * plane->crtc_height; 6467ee14cdcSGustavo Padovan val = (unsigned long)(dma_addr + size); 6471c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); 6481c248b7dSInki Dae 6491c248b7dSInki Dae DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", 6507ee14cdcSGustavo Padovan (unsigned long)dma_addr, val, size); 65119c8b834SInki Dae DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 6527ee14cdcSGustavo Padovan plane->crtc_width, plane->crtc_height); 6531c248b7dSInki Dae 6541c248b7dSInki Dae /* buffer size */ 65568a29134SDaniel Stone buf_offsize = plane->pitch - (plane->crtc_width * (plane->bpp >> 3)); 6567ee14cdcSGustavo Padovan line_size = plane->crtc_width * (plane->bpp >> 3); 6577ee14cdcSGustavo Padovan val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | 6587ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH(line_size) | 6597ee14cdcSGustavo Padovan VIDW_BUF_SIZE_OFFSET_E(buf_offsize) | 6607ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH_E(line_size); 6611c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); 6621c248b7dSInki Dae 6631c248b7dSInki Dae /* OSD position */ 6647ee14cdcSGustavo Padovan val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 6657ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_Y(plane->crtc_y) | 6667ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_X_E(plane->crtc_x) | 6677ee14cdcSGustavo Padovan VIDOSDxA_TOPLEFT_Y_E(plane->crtc_y); 6681c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_A(win)); 6691c248b7dSInki Dae 6707ee14cdcSGustavo Padovan last_x = plane->crtc_x + plane->crtc_width; 671f56aad3aSJoonyoung Shim if (last_x) 672f56aad3aSJoonyoung Shim last_x--; 6737ee14cdcSGustavo Padovan last_y = plane->crtc_y + plane->crtc_height; 674f56aad3aSJoonyoung Shim if (last_y) 675f56aad3aSJoonyoung Shim last_y--; 676f56aad3aSJoonyoung Shim 677ca555e5aSJoonyoung Shim val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | 678ca555e5aSJoonyoung Shim VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); 679ca555e5aSJoonyoung Shim 6801c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_B(win)); 6811c248b7dSInki Dae 68219c8b834SInki Dae DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 6837ee14cdcSGustavo Padovan plane->crtc_x, plane->crtc_y, last_x, last_y); 6841c248b7dSInki Dae 6851c248b7dSInki Dae /* OSD size */ 6861c248b7dSInki Dae if (win != 3 && win != 4) { 6871c248b7dSInki Dae u32 offset = VIDOSD_D(win); 6881c248b7dSInki Dae if (win == 0) 6890f10cf14SLeela Krishna Amudala offset = VIDOSD_C(win); 6907ee14cdcSGustavo Padovan val = plane->crtc_width * plane->crtc_height; 6911c248b7dSInki Dae writel(val, ctx->regs + offset); 6921c248b7dSInki Dae 6931c248b7dSInki Dae DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); 6941c248b7dSInki Dae } 6951c248b7dSInki Dae 696bb7704d6SSean Paul fimd_win_set_pixfmt(ctx, win); 6971c248b7dSInki Dae 6981c248b7dSInki Dae /* hardware window 0 doesn't support color key. */ 6991c248b7dSInki Dae if (win != 0) 700bb7704d6SSean Paul fimd_win_set_colkey(ctx, win); 7011c248b7dSInki Dae 702f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, true); 703ec05da95SInki Dae 704999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 705999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, true); 706ec05da95SInki Dae 70774944a58SYoungJun Cho /* Enable DMA channel and unprotect windows */ 70874944a58SYoungJun Cho fimd_shadow_protect_win(ctx, win, false); 70974944a58SYoungJun Cho 7103854fab2SYoungJun Cho if (ctx->i80_if) 7113854fab2SYoungJun Cho atomic_set(&ctx->win_updated, 1); 7121c248b7dSInki Dae } 7131c248b7dSInki Dae 7141e1d1393SGustavo Padovan static void fimd_disable_plane(struct exynos_drm_crtc *crtc, 7151e1d1393SGustavo Padovan struct exynos_drm_plane *plane) 7161c248b7dSInki Dae { 71793bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 7181e1d1393SGustavo Padovan unsigned int win = plane->zpos; 719ec05da95SInki Dae 720c329f667SJoonyoung Shim if (ctx->suspended) 721db7e55aeSPrathyush K return; 722db7e55aeSPrathyush K 7231c248b7dSInki Dae /* protect windows */ 724de7af100STomasz Figa fimd_shadow_protect_win(ctx, win, true); 7251c248b7dSInki Dae 726f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false); 7271c248b7dSInki Dae 728999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon) 729999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, false); 730de7af100STomasz Figa 731999d8b31SYoungJun Cho /* unprotect windows */ 732de7af100STomasz Figa fimd_shadow_protect_win(ctx, win, false); 733a43b933bSSean Paul } 734a43b933bSSean Paul 7353cecda03SGustavo Padovan static void fimd_enable(struct exynos_drm_crtc *crtc) 736a43b933bSSean Paul { 7373cecda03SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 73838000dbbSGustavo Padovan int ret; 739a43b933bSSean Paul 740a43b933bSSean Paul if (!ctx->suspended) 7413cecda03SGustavo Padovan return; 742a43b933bSSean Paul 743a43b933bSSean Paul ctx->suspended = false; 744a43b933bSSean Paul 745af65c804SSean Paul pm_runtime_get_sync(ctx->dev); 746af65c804SSean Paul 74738000dbbSGustavo Padovan ret = clk_prepare_enable(ctx->bus_clk); 74838000dbbSGustavo Padovan if (ret < 0) { 74938000dbbSGustavo Padovan DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret); 75038000dbbSGustavo Padovan return; 75138000dbbSGustavo Padovan } 75238000dbbSGustavo Padovan 75338000dbbSGustavo Padovan ret = clk_prepare_enable(ctx->lcd_clk); 75438000dbbSGustavo Padovan if (ret < 0) { 75538000dbbSGustavo Padovan DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret); 75638000dbbSGustavo Padovan return; 75738000dbbSGustavo Padovan } 758a43b933bSSean Paul 759a43b933bSSean Paul /* if vblank was enabled status, enable it again. */ 7603cecda03SGustavo Padovan if (test_and_clear_bit(0, &ctx->irq_flags)) 7613cecda03SGustavo Padovan fimd_enable_vblank(ctx->crtc); 762a43b933bSSean Paul 763c329f667SJoonyoung Shim fimd_commit(ctx->crtc); 764a43b933bSSean Paul } 765a43b933bSSean Paul 7663cecda03SGustavo Padovan static void fimd_disable(struct exynos_drm_crtc *crtc) 767a43b933bSSean Paul { 7683cecda03SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 769c329f667SJoonyoung Shim int i; 7703cecda03SGustavo Padovan 771a43b933bSSean Paul if (ctx->suspended) 7723cecda03SGustavo Padovan return; 773a43b933bSSean Paul 774a43b933bSSean Paul /* 775a43b933bSSean Paul * We need to make sure that all windows are disabled before we 776a43b933bSSean Paul * suspend that connector. Otherwise we might try to scan from 777a43b933bSSean Paul * a destroyed buffer later. 778a43b933bSSean Paul */ 779c329f667SJoonyoung Shim for (i = 0; i < WINDOWS_NR; i++) 7801e1d1393SGustavo Padovan fimd_disable_plane(crtc, &ctx->planes[i]); 781a43b933bSSean Paul 78294ab95a9SInki Dae fimd_enable_vblank(crtc); 78394ab95a9SInki Dae fimd_wait_for_vblank(crtc); 78494ab95a9SInki Dae fimd_disable_vblank(crtc); 78594ab95a9SInki Dae 786b74f14fdSJoonyoung Shim writel(0, ctx->regs + VIDCON0); 787b74f14fdSJoonyoung Shim 788a43b933bSSean Paul clk_disable_unprepare(ctx->lcd_clk); 789a43b933bSSean Paul clk_disable_unprepare(ctx->bus_clk); 790a43b933bSSean Paul 791af65c804SSean Paul pm_runtime_put_sync(ctx->dev); 792af65c804SSean Paul 793a43b933bSSean Paul ctx->suspended = true; 794080be03dSSean Paul } 795080be03dSSean Paul 7963854fab2SYoungJun Cho static void fimd_trigger(struct device *dev) 7973854fab2SYoungJun Cho { 798e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 7993854fab2SYoungJun Cho struct fimd_driver_data *driver_data = ctx->driver_data; 8003854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base; 8013854fab2SYoungJun Cho u32 reg; 8023854fab2SYoungJun Cho 8039b67eb73SJoonyoung Shim /* 8041c905d95SYoungJun Cho * Skips triggering if in triggering state, because multiple triggering 8059b67eb73SJoonyoung Shim * requests can cause panel reset. 8069b67eb73SJoonyoung Shim */ 8079b67eb73SJoonyoung Shim if (atomic_read(&ctx->triggering)) 8089b67eb73SJoonyoung Shim return; 8099b67eb73SJoonyoung Shim 8101c905d95SYoungJun Cho /* Enters triggering mode */ 8113854fab2SYoungJun Cho atomic_set(&ctx->triggering, 1); 8123854fab2SYoungJun Cho 8133854fab2SYoungJun Cho reg = readl(timing_base + TRIGCON); 8143854fab2SYoungJun Cho reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE); 8153854fab2SYoungJun Cho writel(reg, timing_base + TRIGCON); 81687ab85b3SYoungJun Cho 81787ab85b3SYoungJun Cho /* 81887ab85b3SYoungJun Cho * Exits triggering mode if vblank is not enabled yet, because when the 81987ab85b3SYoungJun Cho * VIDINTCON0 register is not set, it can not exit from triggering mode. 82087ab85b3SYoungJun Cho */ 82187ab85b3SYoungJun Cho if (!test_bit(0, &ctx->irq_flags)) 82287ab85b3SYoungJun Cho atomic_set(&ctx->triggering, 0); 8233854fab2SYoungJun Cho } 8243854fab2SYoungJun Cho 82593bca243SGustavo Padovan static void fimd_te_handler(struct exynos_drm_crtc *crtc) 8263854fab2SYoungJun Cho { 82793bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx; 8283854fab2SYoungJun Cho 8293854fab2SYoungJun Cho /* Checks the crtc is detached already from encoder */ 8303854fab2SYoungJun Cho if (ctx->pipe < 0 || !ctx->drm_dev) 8313854fab2SYoungJun Cho return; 8323854fab2SYoungJun Cho 8333854fab2SYoungJun Cho /* 8343854fab2SYoungJun Cho * If there is a page flip request, triggers and handles the page flip 8353854fab2SYoungJun Cho * event so that current fb can be updated into panel GRAM. 8363854fab2SYoungJun Cho */ 8373854fab2SYoungJun Cho if (atomic_add_unless(&ctx->win_updated, -1, 0)) 8383854fab2SYoungJun Cho fimd_trigger(ctx->dev); 8393854fab2SYoungJun Cho 8403854fab2SYoungJun Cho /* Wakes up vsync event queue */ 8413854fab2SYoungJun Cho if (atomic_read(&ctx->wait_vsync_event)) { 8423854fab2SYoungJun Cho atomic_set(&ctx->wait_vsync_event, 0); 8433854fab2SYoungJun Cho wake_up(&ctx->wait_vsync_queue); 844b301ae24SYoungJun Cho } 8453854fab2SYoungJun Cho 846adf67abfSJoonyoung Shim if (test_bit(0, &ctx->irq_flags)) 847eafd540aSGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base); 8483854fab2SYoungJun Cho } 8493854fab2SYoungJun Cho 85048107d7bSKrzysztof Kozlowski static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) 85148107d7bSKrzysztof Kozlowski { 85248107d7bSKrzysztof Kozlowski struct fimd_context *ctx = crtc->ctx; 85348107d7bSKrzysztof Kozlowski u32 val; 85448107d7bSKrzysztof Kozlowski 85548107d7bSKrzysztof Kozlowski /* 85648107d7bSKrzysztof Kozlowski * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE 85748107d7bSKrzysztof Kozlowski * clock. On these SoCs the bootloader may enable it but any 85848107d7bSKrzysztof Kozlowski * power domain off/on will reset it to disable state. 85948107d7bSKrzysztof Kozlowski */ 86048107d7bSKrzysztof Kozlowski if (ctx->driver_data != &exynos5_fimd_driver_data) 86148107d7bSKrzysztof Kozlowski return; 86248107d7bSKrzysztof Kozlowski 86348107d7bSKrzysztof Kozlowski val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; 86448107d7bSKrzysztof Kozlowski writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); 86548107d7bSKrzysztof Kozlowski } 86648107d7bSKrzysztof Kozlowski 867f3aaf762SKrzysztof Kozlowski static const struct exynos_drm_crtc_ops fimd_crtc_ops = { 8683cecda03SGustavo Padovan .enable = fimd_enable, 8693cecda03SGustavo Padovan .disable = fimd_disable, 870a968e727SSean Paul .mode_fixup = fimd_mode_fixup, 8711c6244c3SSean Paul .commit = fimd_commit, 8721c6244c3SSean Paul .enable_vblank = fimd_enable_vblank, 8731c6244c3SSean Paul .disable_vblank = fimd_disable_vblank, 8741c6244c3SSean Paul .wait_for_vblank = fimd_wait_for_vblank, 8759cc7610aSGustavo Padovan .update_plane = fimd_update_plane, 8769cc7610aSGustavo Padovan .disable_plane = fimd_disable_plane, 8773854fab2SYoungJun Cho .te_handler = fimd_te_handler, 87848107d7bSKrzysztof Kozlowski .clock_enable = fimd_dp_clock_enable, 8791c248b7dSInki Dae }; 8801c248b7dSInki Dae 8811c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id) 8821c248b7dSInki Dae { 8831c248b7dSInki Dae struct fimd_context *ctx = (struct fimd_context *)dev_id; 8843854fab2SYoungJun Cho u32 val, clear_bit; 8851c248b7dSInki Dae 8861c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON1); 8871c248b7dSInki Dae 8883854fab2SYoungJun Cho clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 8893854fab2SYoungJun Cho if (val & clear_bit) 8903854fab2SYoungJun Cho writel(clear_bit, ctx->regs + VIDINTCON1); 8911c248b7dSInki Dae 892ec05da95SInki Dae /* check the crtc is detached already from encoder */ 893080be03dSSean Paul if (ctx->pipe < 0 || !ctx->drm_dev) 894ec05da95SInki Dae goto out; 895483b88f8SInki Dae 896adf67abfSJoonyoung Shim if (ctx->i80_if) { 897eafd540aSGustavo Padovan exynos_drm_crtc_finish_pageflip(ctx->crtc); 8981c905d95SYoungJun Cho 8991c905d95SYoungJun Cho /* Exits triggering mode */ 9003854fab2SYoungJun Cho atomic_set(&ctx->triggering, 0); 9013854fab2SYoungJun Cho } else { 902eafd540aSGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base); 903eafd540aSGustavo Padovan exynos_drm_crtc_finish_pageflip(ctx->crtc); 904adf67abfSJoonyoung Shim 90501ce113cSPrathyush K /* set wait vsync event to zero and wake up queue. */ 90601ce113cSPrathyush K if (atomic_read(&ctx->wait_vsync_event)) { 90701ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0); 9088dd9ad5dSSeung-Woo Kim wake_up(&ctx->wait_vsync_queue); 90901ce113cSPrathyush K } 9103854fab2SYoungJun Cho } 9113854fab2SYoungJun Cho 912ec05da95SInki Dae out: 9131c248b7dSInki Dae return IRQ_HANDLED; 9141c248b7dSInki Dae } 9151c248b7dSInki Dae 916f37cd5e8SInki Dae static int fimd_bind(struct device *dev, struct device *master, void *data) 917562ad9f4SAndrzej Hajda { 918e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 919f37cd5e8SInki Dae struct drm_device *drm_dev = data; 920cdbfca89SHyungwon Hwang struct exynos_drm_private *priv = drm_dev->dev_private; 9217ee14cdcSGustavo Padovan struct exynos_drm_plane *exynos_plane; 9227ee14cdcSGustavo Padovan enum drm_plane_type type; 9236e2a3b66SGustavo Padovan unsigned int zpos; 9246e2a3b66SGustavo Padovan int ret; 925000cc920SAndrzej Hajda 926cdbfca89SHyungwon Hwang ctx->drm_dev = drm_dev; 927cdbfca89SHyungwon Hwang ctx->pipe = priv->pipe++; 928efa75bcdSAjay Kumar 9297ee14cdcSGustavo Padovan for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 9307ee14cdcSGustavo Padovan type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 9317ee14cdcSGustavo Padovan DRM_PLANE_TYPE_OVERLAY; 9327ee14cdcSGustavo Padovan ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 9336e2a3b66SGustavo Padovan 1 << ctx->pipe, type, zpos); 9347ee14cdcSGustavo Padovan if (ret) 9357ee14cdcSGustavo Padovan return ret; 9367ee14cdcSGustavo Padovan } 9377ee14cdcSGustavo Padovan 9387ee14cdcSGustavo Padovan exynos_plane = &ctx->planes[ctx->default_win]; 9397ee14cdcSGustavo Padovan ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 9407ee14cdcSGustavo Padovan ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 9410f04cf8dSJoonyoung Shim &fimd_crtc_ops, ctx); 942d1222842SHyungwon Hwang if (IS_ERR(ctx->crtc)) 943d1222842SHyungwon Hwang return PTR_ERR(ctx->crtc); 94493bca243SGustavo Padovan 945000cc920SAndrzej Hajda if (ctx->display) 946000cc920SAndrzej Hajda exynos_drm_create_enc_conn(drm_dev, ctx->display); 947000cc920SAndrzej Hajda 94843a3b866SJoonyoung Shim if (is_drm_iommu_supported(drm_dev)) 949eb7a3fc7SJoonyoung Shim fimd_clear_channels(ctx->crtc); 950eb7a3fc7SJoonyoung Shim 951eb7a3fc7SJoonyoung Shim ret = drm_iommu_attach_device(drm_dev, dev); 952fc2e013fSHyungwon Hwang if (ret) 953fc2e013fSHyungwon Hwang priv->pipe--; 954fc2e013fSHyungwon Hwang 955fc2e013fSHyungwon Hwang return ret; 956000cc920SAndrzej Hajda } 957000cc920SAndrzej Hajda 958000cc920SAndrzej Hajda static void fimd_unbind(struct device *dev, struct device *master, 959000cc920SAndrzej Hajda void *data) 960000cc920SAndrzej Hajda { 961e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev); 962000cc920SAndrzej Hajda 9633cecda03SGustavo Padovan fimd_disable(ctx->crtc); 964000cc920SAndrzej Hajda 965bf56608aSJoonyoung Shim drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 966cdbfca89SHyungwon Hwang 967000cc920SAndrzej Hajda if (ctx->display) 9684cfde1f2SAndrzej Hajda exynos_dpi_remove(ctx->display); 969000cc920SAndrzej Hajda } 970000cc920SAndrzej Hajda 971000cc920SAndrzej Hajda static const struct component_ops fimd_component_ops = { 972000cc920SAndrzej Hajda .bind = fimd_bind, 973000cc920SAndrzej Hajda .unbind = fimd_unbind, 974000cc920SAndrzej Hajda }; 975000cc920SAndrzej Hajda 976000cc920SAndrzej Hajda static int fimd_probe(struct platform_device *pdev) 977000cc920SAndrzej Hajda { 978000cc920SAndrzej Hajda struct device *dev = &pdev->dev; 979000cc920SAndrzej Hajda struct fimd_context *ctx; 9803854fab2SYoungJun Cho struct device_node *i80_if_timings; 981000cc920SAndrzej Hajda struct resource *res; 982fe42cfb4SGustavo Padovan int ret; 983562ad9f4SAndrzej Hajda 984e152dbd7SAndrzej Hajda if (!dev->of_node) 985e152dbd7SAndrzej Hajda return -ENODEV; 9862d3f173cSSachin Kamat 987d873ab99SSeung-Woo Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 988e152dbd7SAndrzej Hajda if (!ctx) 989e152dbd7SAndrzej Hajda return -ENOMEM; 990e152dbd7SAndrzej Hajda 991bb7704d6SSean Paul ctx->dev = dev; 992a43b933bSSean Paul ctx->suspended = true; 9933854fab2SYoungJun Cho ctx->driver_data = drm_fimd_get_driver_data(pdev); 994bb7704d6SSean Paul 9951417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vden")) 9961417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VDEN; 9971417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vclk")) 9981417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VCLK; 999562ad9f4SAndrzej Hajda 10003854fab2SYoungJun Cho i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 10013854fab2SYoungJun Cho if (i80_if_timings) { 10023854fab2SYoungJun Cho u32 val; 10033854fab2SYoungJun Cho 10043854fab2SYoungJun Cho ctx->i80_if = true; 10053854fab2SYoungJun Cho 10063854fab2SYoungJun Cho if (ctx->driver_data->has_vidoutcon) 10073854fab2SYoungJun Cho ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0; 10083854fab2SYoungJun Cho else 10093854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0; 10103854fab2SYoungJun Cho /* 10113854fab2SYoungJun Cho * The user manual describes that this "DSI_EN" bit is required 10123854fab2SYoungJun Cho * to enable I80 24-bit data interface. 10133854fab2SYoungJun Cho */ 10143854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_DSI_EN; 10153854fab2SYoungJun Cho 10163854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) 10173854fab2SYoungJun Cho val = 0; 10183854fab2SYoungJun Cho ctx->i80ifcon = LCD_CS_SETUP(val); 10193854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) 10203854fab2SYoungJun Cho val = 0; 10213854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_SETUP(val); 10223854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-active", &val)) 10233854fab2SYoungJun Cho val = 1; 10243854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_ACTIVE(val); 10253854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) 10263854fab2SYoungJun Cho val = 0; 10273854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_HOLD(val); 10283854fab2SYoungJun Cho } 10293854fab2SYoungJun Cho of_node_put(i80_if_timings); 10303854fab2SYoungJun Cho 10313854fab2SYoungJun Cho ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 10323854fab2SYoungJun Cho "samsung,sysreg"); 10333854fab2SYoungJun Cho if (IS_ERR(ctx->sysreg)) { 10343854fab2SYoungJun Cho dev_warn(dev, "failed to get system register.\n"); 10353854fab2SYoungJun Cho ctx->sysreg = NULL; 10363854fab2SYoungJun Cho } 10373854fab2SYoungJun Cho 1038a968e727SSean Paul ctx->bus_clk = devm_clk_get(dev, "fimd"); 1039a968e727SSean Paul if (IS_ERR(ctx->bus_clk)) { 1040a968e727SSean Paul dev_err(dev, "failed to get bus clock\n"); 104186650408SAndrzej Hajda return PTR_ERR(ctx->bus_clk); 1042a968e727SSean Paul } 1043a968e727SSean Paul 1044a968e727SSean Paul ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); 1045a968e727SSean Paul if (IS_ERR(ctx->lcd_clk)) { 1046a968e727SSean Paul dev_err(dev, "failed to get lcd clock\n"); 104786650408SAndrzej Hajda return PTR_ERR(ctx->lcd_clk); 1048a968e727SSean Paul } 10491c248b7dSInki Dae 10501c248b7dSInki Dae res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 10511c248b7dSInki Dae 1052d873ab99SSeung-Woo Kim ctx->regs = devm_ioremap_resource(dev, res); 105386650408SAndrzej Hajda if (IS_ERR(ctx->regs)) 105486650408SAndrzej Hajda return PTR_ERR(ctx->regs); 10551c248b7dSInki Dae 10563854fab2SYoungJun Cho res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 10573854fab2SYoungJun Cho ctx->i80_if ? "lcd_sys" : "vsync"); 10581c248b7dSInki Dae if (!res) { 10591c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 106086650408SAndrzej Hajda return -ENXIO; 10611c248b7dSInki Dae } 10621c248b7dSInki Dae 1063055e0c06SSean Paul ret = devm_request_irq(dev, res->start, fimd_irq_handler, 1064edc57266SSachin Kamat 0, "drm_fimd", ctx); 1065edc57266SSachin Kamat if (ret) { 10661c248b7dSInki Dae dev_err(dev, "irq request failed.\n"); 106786650408SAndrzej Hajda return ret; 10681c248b7dSInki Dae } 10691c248b7dSInki Dae 107057ed0f7bSDaniel Vetter init_waitqueue_head(&ctx->wait_vsync_queue); 107101ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0); 10721c248b7dSInki Dae 1073e152dbd7SAndrzej Hajda platform_set_drvdata(pdev, ctx); 1074080be03dSSean Paul 1075000cc920SAndrzej Hajda ctx->display = exynos_dpi_probe(dev); 10765baf5d44SGustavo Padovan if (IS_ERR(ctx->display)) { 107786650408SAndrzej Hajda return PTR_ERR(ctx->display); 10785baf5d44SGustavo Padovan } 1079f37cd5e8SInki Dae 1080e152dbd7SAndrzej Hajda pm_runtime_enable(dev); 1081f37cd5e8SInki Dae 1082e152dbd7SAndrzej Hajda ret = component_add(dev, &fimd_component_ops); 1083df5225bcSInki Dae if (ret) 1084df5225bcSInki Dae goto err_disable_pm_runtime; 1085df5225bcSInki Dae 1086df5225bcSInki Dae return ret; 1087df5225bcSInki Dae 1088df5225bcSInki Dae err_disable_pm_runtime: 1089e152dbd7SAndrzej Hajda pm_runtime_disable(dev); 1090df5225bcSInki Dae 1091df5225bcSInki Dae return ret; 1092f37cd5e8SInki Dae } 1093f37cd5e8SInki Dae 1094f37cd5e8SInki Dae static int fimd_remove(struct platform_device *pdev) 1095f37cd5e8SInki Dae { 1096af65c804SSean Paul pm_runtime_disable(&pdev->dev); 1097cb91f6a0SJoonyoung Shim 1098df5225bcSInki Dae component_del(&pdev->dev, &fimd_component_ops); 1099df5225bcSInki Dae 11001c248b7dSInki Dae return 0; 11011c248b7dSInki Dae } 11021c248b7dSInki Dae 1103132a5b91SJoonyoung Shim struct platform_driver fimd_driver = { 11041c248b7dSInki Dae .probe = fimd_probe, 110556550d94SGreg Kroah-Hartman .remove = fimd_remove, 11061c248b7dSInki Dae .driver = { 11071c248b7dSInki Dae .name = "exynos4-fb", 11081c248b7dSInki Dae .owner = THIS_MODULE, 11092d3f173cSSachin Kamat .of_match_table = fimd_driver_dt_match, 11101c248b7dSInki Dae }, 11111c248b7dSInki Dae }; 1112