1 /* 2 * Copyright (C) 2012 Samsung Electronics Co.Ltd 3 * Authors: 4 * Eunchul Kim <chulspro.kim@samsung.com> 5 * Jinyoung Jeon <jy0.jeon@samsung.com> 6 * Sangmin Lee <lsmin.lee@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <linux/kernel.h> 15 #include <linux/component.h> 16 #include <linux/platform_device.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/regmap.h> 19 #include <linux/clk.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/of.h> 22 #include <linux/spinlock.h> 23 24 #include <drm/drmP.h> 25 #include <drm/exynos_drm.h> 26 #include "regs-fimc.h" 27 #include "exynos_drm_drv.h" 28 #include "exynos_drm_iommu.h" 29 #include "exynos_drm_ipp.h" 30 31 /* 32 * FIMC stands for Fully Interactive Mobile Camera and 33 * supports image scaler/rotator and input/output DMA operations. 34 * input DMA reads image data from the memory. 35 * output DMA writes image data to memory. 36 * FIMC supports image rotation and image effect functions. 37 */ 38 39 #define FIMC_MAX_DEVS 4 40 #define FIMC_MAX_SRC 2 41 #define FIMC_MAX_DST 32 42 #define FIMC_SHFACTOR 10 43 #define FIMC_BUF_STOP 1 44 #define FIMC_BUF_START 2 45 #define FIMC_WIDTH_ITU_709 1280 46 #define FIMC_AUTOSUSPEND_DELAY 2000 47 48 static unsigned int fimc_mask = 0xc; 49 module_param_named(fimc_devs, fimc_mask, uint, 0644); 50 MODULE_PARM_DESC(fimc_devs, "Alias mask for assigning FIMC devices to Exynos DRM"); 51 52 #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) 53 54 enum { 55 FIMC_CLK_LCLK, 56 FIMC_CLK_GATE, 57 FIMC_CLK_WB_A, 58 FIMC_CLK_WB_B, 59 FIMC_CLKS_MAX 60 }; 61 62 static const char * const fimc_clock_names[] = { 63 [FIMC_CLK_LCLK] = "sclk_fimc", 64 [FIMC_CLK_GATE] = "fimc", 65 [FIMC_CLK_WB_A] = "pxl_async0", 66 [FIMC_CLK_WB_B] = "pxl_async1", 67 }; 68 69 /* 70 * A structure of scaler. 71 * 72 * @range: narrow, wide. 73 * @bypass: unused scaler path. 74 * @up_h: horizontal scale up. 75 * @up_v: vertical scale up. 76 * @hratio: horizontal ratio. 77 * @vratio: vertical ratio. 78 */ 79 struct fimc_scaler { 80 bool range; 81 bool bypass; 82 bool up_h; 83 bool up_v; 84 u32 hratio; 85 u32 vratio; 86 }; 87 88 /* 89 * A structure of fimc context. 90 * 91 * @regs_res: register resources. 92 * @regs: memory mapped io registers. 93 * @lock: locking of operations. 94 * @clocks: fimc clocks. 95 * @sc: scaler infomations. 96 * @pol: porarity of writeback. 97 * @id: fimc id. 98 * @irq: irq number. 99 */ 100 struct fimc_context { 101 struct exynos_drm_ipp ipp; 102 struct drm_device *drm_dev; 103 struct device *dev; 104 struct exynos_drm_ipp_task *task; 105 struct exynos_drm_ipp_formats *formats; 106 unsigned int num_formats; 107 108 struct resource *regs_res; 109 void __iomem *regs; 110 spinlock_t lock; 111 struct clk *clocks[FIMC_CLKS_MAX]; 112 struct fimc_scaler sc; 113 int id; 114 int irq; 115 }; 116 117 static u32 fimc_read(struct fimc_context *ctx, u32 reg) 118 { 119 return readl(ctx->regs + reg); 120 } 121 122 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg) 123 { 124 writel(val, ctx->regs + reg); 125 } 126 127 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits) 128 { 129 void __iomem *r = ctx->regs + reg; 130 131 writel(readl(r) | bits, r); 132 } 133 134 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits) 135 { 136 void __iomem *r = ctx->regs + reg; 137 138 writel(readl(r) & ~bits, r); 139 } 140 141 static void fimc_sw_reset(struct fimc_context *ctx) 142 { 143 u32 cfg; 144 145 /* stop dma operation */ 146 cfg = fimc_read(ctx, EXYNOS_CISTATUS); 147 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) 148 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); 149 150 fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT); 151 152 /* disable image capture */ 153 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT, 154 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 155 156 /* s/w reset */ 157 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST); 158 159 /* s/w reset complete */ 160 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST); 161 162 /* reset sequence */ 163 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ); 164 } 165 166 static void fimc_set_type_ctrl(struct fimc_context *ctx) 167 { 168 u32 cfg; 169 170 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 171 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | 172 EXYNOS_CIGCTRL_SELCAM_ITU_MASK | 173 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK | 174 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK | 175 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK | 176 EXYNOS_CIGCTRL_SELWRITEBACK_MASK); 177 178 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | 179 EXYNOS_CIGCTRL_SELWRITEBACK_A | 180 EXYNOS_CIGCTRL_SELCAM_MIPI_A | 181 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU); 182 183 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 184 } 185 186 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) 187 { 188 u32 cfg; 189 190 DRM_DEBUG_KMS("enable[%d]\n", enable); 191 192 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 193 if (enable) 194 cfg |= EXYNOS_CIGCTRL_CAM_JPEG; 195 else 196 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG; 197 198 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 199 } 200 201 static void fimc_mask_irq(struct fimc_context *ctx, bool enable) 202 { 203 u32 cfg; 204 205 DRM_DEBUG_KMS("enable[%d]\n", enable); 206 207 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 208 if (enable) { 209 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN; 210 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL; 211 } else 212 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE; 213 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 214 } 215 216 static void fimc_clear_irq(struct fimc_context *ctx) 217 { 218 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR); 219 } 220 221 static bool fimc_check_ovf(struct fimc_context *ctx) 222 { 223 u32 status, flag; 224 225 status = fimc_read(ctx, EXYNOS_CISTATUS); 226 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB | 227 EXYNOS_CISTATUS_OVFICR; 228 229 DRM_DEBUG_KMS("flag[0x%x]\n", flag); 230 231 if (status & flag) { 232 fimc_set_bits(ctx, EXYNOS_CIWDOFST, 233 EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 234 EXYNOS_CIWDOFST_CLROVFICR); 235 236 dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n", 237 ctx->id, status); 238 return true; 239 } 240 241 return false; 242 } 243 244 static bool fimc_check_frame_end(struct fimc_context *ctx) 245 { 246 u32 cfg; 247 248 cfg = fimc_read(ctx, EXYNOS_CISTATUS); 249 250 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg); 251 252 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND)) 253 return false; 254 255 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND); 256 fimc_write(ctx, cfg, EXYNOS_CISTATUS); 257 258 return true; 259 } 260 261 static int fimc_get_buf_id(struct fimc_context *ctx) 262 { 263 u32 cfg; 264 int frame_cnt, buf_id; 265 266 cfg = fimc_read(ctx, EXYNOS_CISTATUS2); 267 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg); 268 269 if (frame_cnt == 0) 270 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg); 271 272 DRM_DEBUG_KMS("present[%d]before[%d]\n", 273 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg), 274 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg)); 275 276 if (frame_cnt == 0) { 277 DRM_ERROR("failed to get frame count.\n"); 278 return -EIO; 279 } 280 281 buf_id = frame_cnt - 1; 282 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 283 284 return buf_id; 285 } 286 287 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) 288 { 289 u32 cfg; 290 291 DRM_DEBUG_KMS("enable[%d]\n", enable); 292 293 cfg = fimc_read(ctx, EXYNOS_CIOCTRL); 294 if (enable) 295 cfg |= EXYNOS_CIOCTRL_LASTENDEN; 296 else 297 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN; 298 299 fimc_write(ctx, cfg, EXYNOS_CIOCTRL); 300 } 301 302 static void fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) 303 { 304 u32 cfg; 305 306 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 307 308 /* RGB */ 309 cfg = fimc_read(ctx, EXYNOS_CISCCTRL); 310 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK; 311 312 switch (fmt) { 313 case DRM_FORMAT_RGB565: 314 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565; 315 fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 316 return; 317 case DRM_FORMAT_RGB888: 318 case DRM_FORMAT_XRGB8888: 319 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888; 320 fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 321 return; 322 default: 323 /* bypass */ 324 break; 325 } 326 327 /* YUV */ 328 cfg = fimc_read(ctx, EXYNOS_MSCTRL); 329 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK | 330 EXYNOS_MSCTRL_C_INT_IN_2PLANE | 331 EXYNOS_MSCTRL_ORDER422_YCBYCR); 332 333 switch (fmt) { 334 case DRM_FORMAT_YUYV: 335 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR; 336 break; 337 case DRM_FORMAT_YVYU: 338 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB; 339 break; 340 case DRM_FORMAT_UYVY: 341 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY; 342 break; 343 case DRM_FORMAT_VYUY: 344 case DRM_FORMAT_YUV444: 345 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY; 346 break; 347 case DRM_FORMAT_NV21: 348 case DRM_FORMAT_NV61: 349 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB | 350 EXYNOS_MSCTRL_C_INT_IN_2PLANE); 351 break; 352 case DRM_FORMAT_YUV422: 353 case DRM_FORMAT_YUV420: 354 case DRM_FORMAT_YVU420: 355 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE; 356 break; 357 case DRM_FORMAT_NV12: 358 case DRM_FORMAT_NV16: 359 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR | 360 EXYNOS_MSCTRL_C_INT_IN_2PLANE); 361 break; 362 } 363 364 fimc_write(ctx, cfg, EXYNOS_MSCTRL); 365 } 366 367 static void fimc_src_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) 368 { 369 u32 cfg; 370 371 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 372 373 cfg = fimc_read(ctx, EXYNOS_MSCTRL); 374 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB; 375 376 switch (fmt) { 377 case DRM_FORMAT_RGB565: 378 case DRM_FORMAT_RGB888: 379 case DRM_FORMAT_XRGB8888: 380 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB; 381 break; 382 case DRM_FORMAT_YUV444: 383 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 384 break; 385 case DRM_FORMAT_YUYV: 386 case DRM_FORMAT_YVYU: 387 case DRM_FORMAT_UYVY: 388 case DRM_FORMAT_VYUY: 389 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE; 390 break; 391 case DRM_FORMAT_NV16: 392 case DRM_FORMAT_NV61: 393 case DRM_FORMAT_YUV422: 394 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422; 395 break; 396 case DRM_FORMAT_YUV420: 397 case DRM_FORMAT_YVU420: 398 case DRM_FORMAT_NV12: 399 case DRM_FORMAT_NV21: 400 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 401 break; 402 } 403 404 fimc_write(ctx, cfg, EXYNOS_MSCTRL); 405 406 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM); 407 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK; 408 409 if (tiled) 410 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32; 411 else 412 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR; 413 414 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM); 415 416 fimc_src_set_fmt_order(ctx, fmt); 417 } 418 419 static void fimc_src_set_transf(struct fimc_context *ctx, unsigned int rotation) 420 { 421 unsigned int degree = rotation & DRM_MODE_ROTATE_MASK; 422 u32 cfg1, cfg2; 423 424 DRM_DEBUG_KMS("rotation[%x]\n", rotation); 425 426 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); 427 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | 428 EXYNOS_MSCTRL_FLIP_Y_MIRROR); 429 430 cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT); 431 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 432 433 switch (degree) { 434 case DRM_MODE_ROTATE_0: 435 if (rotation & DRM_MODE_REFLECT_X) 436 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 437 if (rotation & DRM_MODE_REFLECT_Y) 438 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 439 break; 440 case DRM_MODE_ROTATE_90: 441 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 442 if (rotation & DRM_MODE_REFLECT_X) 443 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 444 if (rotation & DRM_MODE_REFLECT_Y) 445 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 446 break; 447 case DRM_MODE_ROTATE_180: 448 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 449 EXYNOS_MSCTRL_FLIP_Y_MIRROR); 450 if (rotation & DRM_MODE_REFLECT_X) 451 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 452 if (rotation & DRM_MODE_REFLECT_Y) 453 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 454 break; 455 case DRM_MODE_ROTATE_270: 456 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 457 EXYNOS_MSCTRL_FLIP_Y_MIRROR); 458 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 459 if (rotation & DRM_MODE_REFLECT_X) 460 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 461 if (rotation & DRM_MODE_REFLECT_Y) 462 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 463 break; 464 } 465 466 fimc_write(ctx, cfg1, EXYNOS_MSCTRL); 467 fimc_write(ctx, cfg2, EXYNOS_CITRGFMT); 468 } 469 470 static void fimc_set_window(struct fimc_context *ctx, 471 struct exynos_drm_ipp_buffer *buf) 472 { 473 u32 cfg, h1, h2, v1, v2; 474 475 /* cropped image */ 476 h1 = buf->rect.x; 477 h2 = buf->buf.width - buf->rect.w - buf->rect.x; 478 v1 = buf->rect.y; 479 v2 = buf->buf.height - buf->rect.h - buf->rect.y; 480 481 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n", 482 buf->rect.x, buf->rect.y, buf->rect.w, buf->rect.h, 483 buf->buf.width, buf->buf.height); 484 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2); 485 486 /* 487 * set window offset 1, 2 size 488 * check figure 43-21 in user manual 489 */ 490 cfg = fimc_read(ctx, EXYNOS_CIWDOFST); 491 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK | 492 EXYNOS_CIWDOFST_WINVEROFST_MASK); 493 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) | 494 EXYNOS_CIWDOFST_WINVEROFST(v1)); 495 cfg |= EXYNOS_CIWDOFST_WINOFSEN; 496 fimc_write(ctx, cfg, EXYNOS_CIWDOFST); 497 498 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) | 499 EXYNOS_CIWDOFST2_WINVEROFST2(v2)); 500 fimc_write(ctx, cfg, EXYNOS_CIWDOFST2); 501 } 502 503 static void fimc_src_set_size(struct fimc_context *ctx, 504 struct exynos_drm_ipp_buffer *buf) 505 { 506 u32 cfg; 507 508 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", buf->buf.width, buf->buf.height); 509 510 /* original size */ 511 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(buf->buf.width) | 512 EXYNOS_ORGISIZE_VERTICAL(buf->buf.height)); 513 514 fimc_write(ctx, cfg, EXYNOS_ORGISIZE); 515 516 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", buf->rect.x, buf->rect.y, 517 buf->rect.w, buf->rect.h); 518 519 /* set input DMA image size */ 520 cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE); 521 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK | 522 EXYNOS_CIREAL_ISIZE_WIDTH_MASK); 523 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(buf->rect.w) | 524 EXYNOS_CIREAL_ISIZE_HEIGHT(buf->rect.h)); 525 fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE); 526 527 /* 528 * set input FIFO image size 529 * for now, we support only ITU601 8 bit mode 530 */ 531 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT | 532 EXYNOS_CISRCFMT_SOURCEHSIZE(buf->buf.width) | 533 EXYNOS_CISRCFMT_SOURCEVSIZE(buf->buf.height)); 534 fimc_write(ctx, cfg, EXYNOS_CISRCFMT); 535 536 /* offset Y(RGB), Cb, Cr */ 537 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(buf->rect.x) | 538 EXYNOS_CIIYOFF_VERTICAL(buf->rect.y)); 539 fimc_write(ctx, cfg, EXYNOS_CIIYOFF); 540 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(buf->rect.x) | 541 EXYNOS_CIICBOFF_VERTICAL(buf->rect.y)); 542 fimc_write(ctx, cfg, EXYNOS_CIICBOFF); 543 cfg = (EXYNOS_CIICROFF_HORIZONTAL(buf->rect.x) | 544 EXYNOS_CIICROFF_VERTICAL(buf->rect.y)); 545 fimc_write(ctx, cfg, EXYNOS_CIICROFF); 546 547 fimc_set_window(ctx, buf); 548 } 549 550 static void fimc_src_set_addr(struct fimc_context *ctx, 551 struct exynos_drm_ipp_buffer *buf) 552 { 553 fimc_write(ctx, buf->dma_addr[0], EXYNOS_CIIYSA(0)); 554 fimc_write(ctx, buf->dma_addr[1], EXYNOS_CIICBSA(0)); 555 fimc_write(ctx, buf->dma_addr[2], EXYNOS_CIICRSA(0)); 556 } 557 558 static void fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) 559 { 560 u32 cfg; 561 562 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 563 564 /* RGB */ 565 cfg = fimc_read(ctx, EXYNOS_CISCCTRL); 566 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK; 567 568 switch (fmt) { 569 case DRM_FORMAT_RGB565: 570 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565; 571 fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 572 return; 573 case DRM_FORMAT_RGB888: 574 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888; 575 fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 576 return; 577 case DRM_FORMAT_XRGB8888: 578 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 | 579 EXYNOS_CISCCTRL_EXTRGB_EXTENSION); 580 fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 581 break; 582 default: 583 /* bypass */ 584 break; 585 } 586 587 /* YUV */ 588 cfg = fimc_read(ctx, EXYNOS_CIOCTRL); 589 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK | 590 EXYNOS_CIOCTRL_ORDER422_MASK | 591 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK); 592 593 switch (fmt) { 594 case DRM_FORMAT_XRGB8888: 595 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT; 596 break; 597 case DRM_FORMAT_YUYV: 598 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR; 599 break; 600 case DRM_FORMAT_YVYU: 601 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB; 602 break; 603 case DRM_FORMAT_UYVY: 604 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY; 605 break; 606 case DRM_FORMAT_VYUY: 607 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY; 608 break; 609 case DRM_FORMAT_NV21: 610 case DRM_FORMAT_NV61: 611 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB; 612 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 613 break; 614 case DRM_FORMAT_YUV422: 615 case DRM_FORMAT_YUV420: 616 case DRM_FORMAT_YVU420: 617 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE; 618 break; 619 case DRM_FORMAT_NV12: 620 case DRM_FORMAT_NV16: 621 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR; 622 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 623 break; 624 } 625 626 fimc_write(ctx, cfg, EXYNOS_CIOCTRL); 627 } 628 629 static void fimc_dst_set_fmt(struct fimc_context *ctx, u32 fmt, bool tiled) 630 { 631 u32 cfg; 632 633 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 634 635 cfg = fimc_read(ctx, EXYNOS_CIEXTEN); 636 637 if (fmt == DRM_FORMAT_AYUV) { 638 cfg |= EXYNOS_CIEXTEN_YUV444_OUT; 639 fimc_write(ctx, cfg, EXYNOS_CIEXTEN); 640 } else { 641 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT; 642 fimc_write(ctx, cfg, EXYNOS_CIEXTEN); 643 644 cfg = fimc_read(ctx, EXYNOS_CITRGFMT); 645 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK; 646 647 switch (fmt) { 648 case DRM_FORMAT_RGB565: 649 case DRM_FORMAT_RGB888: 650 case DRM_FORMAT_XRGB8888: 651 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB; 652 break; 653 case DRM_FORMAT_YUYV: 654 case DRM_FORMAT_YVYU: 655 case DRM_FORMAT_UYVY: 656 case DRM_FORMAT_VYUY: 657 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; 658 break; 659 case DRM_FORMAT_NV16: 660 case DRM_FORMAT_NV61: 661 case DRM_FORMAT_YUV422: 662 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422; 663 break; 664 case DRM_FORMAT_YUV420: 665 case DRM_FORMAT_YVU420: 666 case DRM_FORMAT_NV12: 667 case DRM_FORMAT_NV21: 668 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; 669 break; 670 } 671 672 fimc_write(ctx, cfg, EXYNOS_CITRGFMT); 673 } 674 675 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM); 676 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK; 677 678 if (tiled) 679 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32; 680 else 681 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR; 682 683 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM); 684 685 fimc_dst_set_fmt_order(ctx, fmt); 686 } 687 688 static void fimc_dst_set_transf(struct fimc_context *ctx, unsigned int rotation) 689 { 690 unsigned int degree = rotation & DRM_MODE_ROTATE_MASK; 691 u32 cfg; 692 693 DRM_DEBUG_KMS("rotation[0x%x]\n", rotation); 694 695 cfg = fimc_read(ctx, EXYNOS_CITRGFMT); 696 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK; 697 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 698 699 switch (degree) { 700 case DRM_MODE_ROTATE_0: 701 if (rotation & DRM_MODE_REFLECT_X) 702 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 703 if (rotation & DRM_MODE_REFLECT_Y) 704 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 705 break; 706 case DRM_MODE_ROTATE_90: 707 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 708 if (rotation & DRM_MODE_REFLECT_X) 709 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 710 if (rotation & DRM_MODE_REFLECT_Y) 711 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 712 break; 713 case DRM_MODE_ROTATE_180: 714 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR | 715 EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 716 if (rotation & DRM_MODE_REFLECT_X) 717 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 718 if (rotation & DRM_MODE_REFLECT_Y) 719 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 720 break; 721 case DRM_MODE_ROTATE_270: 722 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE | 723 EXYNOS_CITRGFMT_FLIP_X_MIRROR | 724 EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 725 if (rotation & DRM_MODE_REFLECT_X) 726 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 727 if (rotation & DRM_MODE_REFLECT_Y) 728 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 729 break; 730 } 731 732 fimc_write(ctx, cfg, EXYNOS_CITRGFMT); 733 } 734 735 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, 736 struct drm_exynos_ipp_task_rect *src, 737 struct drm_exynos_ipp_task_rect *dst) 738 { 739 u32 cfg, cfg_ext, shfactor; 740 u32 pre_dst_width, pre_dst_height; 741 u32 hfactor, vfactor; 742 int ret = 0; 743 u32 src_w, src_h, dst_w, dst_h; 744 745 cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT); 746 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) { 747 src_w = src->h; 748 src_h = src->w; 749 } else { 750 src_w = src->w; 751 src_h = src->h; 752 } 753 754 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) { 755 dst_w = dst->h; 756 dst_h = dst->w; 757 } else { 758 dst_w = dst->w; 759 dst_h = dst->h; 760 } 761 762 /* fimc_ippdrv_check_property assures that dividers are not null */ 763 hfactor = fls(src_w / dst_w / 2); 764 if (hfactor > FIMC_SHFACTOR / 2) { 765 dev_err(ctx->dev, "failed to get ratio horizontal.\n"); 766 return -EINVAL; 767 } 768 769 vfactor = fls(src_h / dst_h / 2); 770 if (vfactor > FIMC_SHFACTOR / 2) { 771 dev_err(ctx->dev, "failed to get ratio vertical.\n"); 772 return -EINVAL; 773 } 774 775 pre_dst_width = src_w >> hfactor; 776 pre_dst_height = src_h >> vfactor; 777 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n", 778 pre_dst_width, pre_dst_height); 779 DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor); 780 781 sc->hratio = (src_w << 14) / (dst_w << hfactor); 782 sc->vratio = (src_h << 14) / (dst_h << vfactor); 783 sc->up_h = (dst_w >= src_w) ? true : false; 784 sc->up_v = (dst_h >= src_h) ? true : false; 785 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n", 786 sc->hratio, sc->vratio, sc->up_h, sc->up_v); 787 788 shfactor = FIMC_SHFACTOR - (hfactor + vfactor); 789 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor); 790 791 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) | 792 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) | 793 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor)); 794 fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO); 795 796 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) | 797 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height)); 798 fimc_write(ctx, cfg, EXYNOS_CISCPREDST); 799 800 return ret; 801 } 802 803 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) 804 { 805 u32 cfg, cfg_ext; 806 807 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n", 808 sc->range, sc->bypass, sc->up_h, sc->up_v); 809 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n", 810 sc->hratio, sc->vratio); 811 812 cfg = fimc_read(ctx, EXYNOS_CISCCTRL); 813 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS | 814 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V | 815 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK | 816 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK | 817 EXYNOS_CISCCTRL_CSCR2Y_WIDE | 818 EXYNOS_CISCCTRL_CSCY2R_WIDE); 819 820 if (sc->range) 821 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | 822 EXYNOS_CISCCTRL_CSCY2R_WIDE); 823 if (sc->bypass) 824 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; 825 if (sc->up_h) 826 cfg |= EXYNOS_CISCCTRL_SCALEUP_H; 827 if (sc->up_v) 828 cfg |= EXYNOS_CISCCTRL_SCALEUP_V; 829 830 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) | 831 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6))); 832 fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 833 834 cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN); 835 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK; 836 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK; 837 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) | 838 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio)); 839 fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN); 840 } 841 842 static void fimc_dst_set_size(struct fimc_context *ctx, 843 struct exynos_drm_ipp_buffer *buf) 844 { 845 u32 cfg, cfg_ext; 846 847 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", buf->buf.width, buf->buf.height); 848 849 /* original size */ 850 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(buf->buf.width) | 851 EXYNOS_ORGOSIZE_VERTICAL(buf->buf.height)); 852 853 fimc_write(ctx, cfg, EXYNOS_ORGOSIZE); 854 855 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", buf->rect.x, buf->rect.y, 856 buf->rect.w, buf->rect.h); 857 858 /* CSC ITU */ 859 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 860 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK; 861 862 if (buf->buf.width >= FIMC_WIDTH_ITU_709) 863 cfg |= EXYNOS_CIGCTRL_CSC_ITU709; 864 else 865 cfg |= EXYNOS_CIGCTRL_CSC_ITU601; 866 867 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 868 869 cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT); 870 871 /* target image size */ 872 cfg = fimc_read(ctx, EXYNOS_CITRGFMT); 873 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK | 874 EXYNOS_CITRGFMT_TARGETV_MASK); 875 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) 876 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(buf->rect.h) | 877 EXYNOS_CITRGFMT_TARGETVSIZE(buf->rect.w)); 878 else 879 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(buf->rect.w) | 880 EXYNOS_CITRGFMT_TARGETVSIZE(buf->rect.h)); 881 fimc_write(ctx, cfg, EXYNOS_CITRGFMT); 882 883 /* target area */ 884 cfg = EXYNOS_CITAREA_TARGET_AREA(buf->rect.w * buf->rect.h); 885 fimc_write(ctx, cfg, EXYNOS_CITAREA); 886 887 /* offset Y(RGB), Cb, Cr */ 888 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(buf->rect.x) | 889 EXYNOS_CIOYOFF_VERTICAL(buf->rect.y)); 890 fimc_write(ctx, cfg, EXYNOS_CIOYOFF); 891 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(buf->rect.x) | 892 EXYNOS_CIOCBOFF_VERTICAL(buf->rect.y)); 893 fimc_write(ctx, cfg, EXYNOS_CIOCBOFF); 894 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(buf->rect.x) | 895 EXYNOS_CIOCROFF_VERTICAL(buf->rect.y)); 896 fimc_write(ctx, cfg, EXYNOS_CIOCROFF); 897 } 898 899 static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, 900 bool enqueue) 901 { 902 unsigned long flags; 903 u32 buf_num; 904 u32 cfg; 905 906 DRM_DEBUG_KMS("buf_id[%d]enqueu[%d]\n", buf_id, enqueue); 907 908 spin_lock_irqsave(&ctx->lock, flags); 909 910 cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ); 911 912 if (enqueue) 913 cfg |= (1 << buf_id); 914 else 915 cfg &= ~(1 << buf_id); 916 917 fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ); 918 919 buf_num = hweight32(cfg); 920 921 if (enqueue && buf_num >= FIMC_BUF_START) 922 fimc_mask_irq(ctx, true); 923 else if (!enqueue && buf_num <= FIMC_BUF_STOP) 924 fimc_mask_irq(ctx, false); 925 926 spin_unlock_irqrestore(&ctx->lock, flags); 927 } 928 929 static void fimc_dst_set_addr(struct fimc_context *ctx, 930 struct exynos_drm_ipp_buffer *buf) 931 { 932 fimc_write(ctx, buf->dma_addr[0], EXYNOS_CIOYSA(0)); 933 fimc_write(ctx, buf->dma_addr[1], EXYNOS_CIOCBSA(0)); 934 fimc_write(ctx, buf->dma_addr[2], EXYNOS_CIOCRSA(0)); 935 936 fimc_dst_set_buf_seq(ctx, 0, true); 937 } 938 939 static void fimc_stop(struct fimc_context *ctx); 940 941 static irqreturn_t fimc_irq_handler(int irq, void *dev_id) 942 { 943 struct fimc_context *ctx = dev_id; 944 int buf_id; 945 946 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id); 947 948 fimc_clear_irq(ctx); 949 if (fimc_check_ovf(ctx)) 950 return IRQ_NONE; 951 952 if (!fimc_check_frame_end(ctx)) 953 return IRQ_NONE; 954 955 buf_id = fimc_get_buf_id(ctx); 956 if (buf_id < 0) 957 return IRQ_HANDLED; 958 959 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 960 961 if (ctx->task) { 962 struct exynos_drm_ipp_task *task = ctx->task; 963 964 ctx->task = NULL; 965 pm_runtime_mark_last_busy(ctx->dev); 966 pm_runtime_put_autosuspend(ctx->dev); 967 exynos_drm_ipp_task_done(task, 0); 968 } 969 970 fimc_dst_set_buf_seq(ctx, buf_id, false); 971 fimc_stop(ctx); 972 973 return IRQ_HANDLED; 974 } 975 976 static void fimc_clear_addr(struct fimc_context *ctx) 977 { 978 int i; 979 980 for (i = 0; i < FIMC_MAX_SRC; i++) { 981 fimc_write(ctx, 0, EXYNOS_CIIYSA(i)); 982 fimc_write(ctx, 0, EXYNOS_CIICBSA(i)); 983 fimc_write(ctx, 0, EXYNOS_CIICRSA(i)); 984 } 985 986 for (i = 0; i < FIMC_MAX_DST; i++) { 987 fimc_write(ctx, 0, EXYNOS_CIOYSA(i)); 988 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i)); 989 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i)); 990 } 991 } 992 993 static void fimc_reset(struct fimc_context *ctx) 994 { 995 /* reset h/w block */ 996 fimc_sw_reset(ctx); 997 998 /* reset scaler capability */ 999 memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 1000 1001 fimc_clear_addr(ctx); 1002 } 1003 1004 static void fimc_start(struct fimc_context *ctx) 1005 { 1006 u32 cfg0, cfg1; 1007 1008 fimc_mask_irq(ctx, true); 1009 1010 /* If set true, we can save jpeg about screen */ 1011 fimc_handle_jpeg(ctx, false); 1012 fimc_set_scaler(ctx, &ctx->sc); 1013 1014 fimc_set_type_ctrl(ctx); 1015 fimc_handle_lastend(ctx, false); 1016 1017 /* setup dma */ 1018 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); 1019 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; 1020 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; 1021 fimc_write(ctx, cfg0, EXYNOS_MSCTRL); 1022 1023 /* Reset status */ 1024 fimc_write(ctx, 0x0, EXYNOS_CISTATUS); 1025 1026 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); 1027 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; 1028 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; 1029 1030 /* Scaler */ 1031 cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL); 1032 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; 1033 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | 1034 EXYNOS_CISCCTRL_SCALERSTART); 1035 1036 fimc_write(ctx, cfg1, EXYNOS_CISCCTRL); 1037 1038 /* Enable image capture*/ 1039 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; 1040 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); 1041 1042 /* Disable frame end irq */ 1043 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE); 1044 1045 fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK); 1046 1047 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); 1048 } 1049 1050 static void fimc_stop(struct fimc_context *ctx) 1051 { 1052 u32 cfg; 1053 1054 /* Source clear */ 1055 cfg = fimc_read(ctx, EXYNOS_MSCTRL); 1056 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK; 1057 cfg &= ~EXYNOS_MSCTRL_ENVID; 1058 fimc_write(ctx, cfg, EXYNOS_MSCTRL); 1059 1060 fimc_mask_irq(ctx, false); 1061 1062 /* reset sequence */ 1063 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ); 1064 1065 /* Scaler disable */ 1066 fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART); 1067 1068 /* Disable image capture */ 1069 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT, 1070 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 1071 1072 /* Enable frame end irq */ 1073 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE); 1074 } 1075 1076 static int fimc_commit(struct exynos_drm_ipp *ipp, 1077 struct exynos_drm_ipp_task *task) 1078 { 1079 struct fimc_context *ctx = 1080 container_of(ipp, struct fimc_context, ipp); 1081 1082 pm_runtime_get_sync(ctx->dev); 1083 ctx->task = task; 1084 1085 fimc_src_set_fmt(ctx, task->src.buf.fourcc, task->src.buf.modifier); 1086 fimc_src_set_size(ctx, &task->src); 1087 fimc_src_set_transf(ctx, DRM_MODE_ROTATE_0); 1088 fimc_src_set_addr(ctx, &task->src); 1089 fimc_dst_set_fmt(ctx, task->dst.buf.fourcc, task->dst.buf.modifier); 1090 fimc_dst_set_transf(ctx, task->transform.rotation); 1091 fimc_dst_set_size(ctx, &task->dst); 1092 fimc_dst_set_addr(ctx, &task->dst); 1093 fimc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect); 1094 fimc_start(ctx); 1095 1096 return 0; 1097 } 1098 1099 static void fimc_abort(struct exynos_drm_ipp *ipp, 1100 struct exynos_drm_ipp_task *task) 1101 { 1102 struct fimc_context *ctx = 1103 container_of(ipp, struct fimc_context, ipp); 1104 1105 fimc_reset(ctx); 1106 1107 if (ctx->task) { 1108 struct exynos_drm_ipp_task *task = ctx->task; 1109 1110 ctx->task = NULL; 1111 pm_runtime_mark_last_busy(ctx->dev); 1112 pm_runtime_put_autosuspend(ctx->dev); 1113 exynos_drm_ipp_task_done(task, -EIO); 1114 } 1115 } 1116 1117 static struct exynos_drm_ipp_funcs ipp_funcs = { 1118 .commit = fimc_commit, 1119 .abort = fimc_abort, 1120 }; 1121 1122 static int fimc_bind(struct device *dev, struct device *master, void *data) 1123 { 1124 struct fimc_context *ctx = dev_get_drvdata(dev); 1125 struct drm_device *drm_dev = data; 1126 struct exynos_drm_ipp *ipp = &ctx->ipp; 1127 1128 ctx->drm_dev = drm_dev; 1129 drm_iommu_attach_device(drm_dev, dev); 1130 1131 exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs, 1132 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE | 1133 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT, 1134 ctx->formats, ctx->num_formats, "fimc"); 1135 1136 dev_info(dev, "The exynos fimc has been probed successfully\n"); 1137 1138 return 0; 1139 } 1140 1141 static void fimc_unbind(struct device *dev, struct device *master, 1142 void *data) 1143 { 1144 struct fimc_context *ctx = dev_get_drvdata(dev); 1145 struct drm_device *drm_dev = data; 1146 struct exynos_drm_ipp *ipp = &ctx->ipp; 1147 1148 exynos_drm_ipp_unregister(drm_dev, ipp); 1149 drm_iommu_detach_device(drm_dev, dev); 1150 } 1151 1152 static const struct component_ops fimc_component_ops = { 1153 .bind = fimc_bind, 1154 .unbind = fimc_unbind, 1155 }; 1156 1157 static void fimc_put_clocks(struct fimc_context *ctx) 1158 { 1159 int i; 1160 1161 for (i = 0; i < FIMC_CLKS_MAX; i++) { 1162 if (IS_ERR(ctx->clocks[i])) 1163 continue; 1164 clk_put(ctx->clocks[i]); 1165 ctx->clocks[i] = ERR_PTR(-EINVAL); 1166 } 1167 } 1168 1169 static int fimc_setup_clocks(struct fimc_context *ctx) 1170 { 1171 struct device *fimc_dev = ctx->dev; 1172 struct device *dev; 1173 int ret, i; 1174 1175 for (i = 0; i < FIMC_CLKS_MAX; i++) 1176 ctx->clocks[i] = ERR_PTR(-EINVAL); 1177 1178 for (i = 0; i < FIMC_CLKS_MAX; i++) { 1179 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B) 1180 dev = fimc_dev->parent; 1181 else 1182 dev = fimc_dev; 1183 1184 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); 1185 if (IS_ERR(ctx->clocks[i])) { 1186 ret = PTR_ERR(ctx->clocks[i]); 1187 dev_err(fimc_dev, "failed to get clock: %s\n", 1188 fimc_clock_names[i]); 1189 goto e_clk_free; 1190 } 1191 } 1192 1193 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); 1194 if (!ret) 1195 return ret; 1196 e_clk_free: 1197 fimc_put_clocks(ctx); 1198 return ret; 1199 } 1200 1201 int exynos_drm_check_fimc_device(struct device *dev) 1202 { 1203 int id = of_alias_get_id(dev->of_node, "fimc"); 1204 1205 if (id >= 0 && (BIT(id) & fimc_mask)) 1206 return 0; 1207 return -ENODEV; 1208 } 1209 1210 static const unsigned int fimc_formats[] = { 1211 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, 1212 DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61, 1213 DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, 1214 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422, 1215 DRM_FORMAT_YUV444, 1216 }; 1217 1218 static const unsigned int fimc_tiled_formats[] = { 1219 DRM_FORMAT_NV12, DRM_FORMAT_NV21, 1220 }; 1221 1222 static const struct drm_exynos_ipp_limit fimc_4210_limits_v1[] = { 1223 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) }, 1224 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4224, 2 }, .v = { 16, 0, 2 }) }, 1225 { IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1920 }, .v = { 128, 0 }) }, 1226 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, 1227 .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, 1228 }; 1229 1230 static const struct drm_exynos_ipp_limit fimc_4210_limits_v2[] = { 1231 { IPP_SIZE_LIMIT(BUFFER, .h = { 16, 8192, 8 }, .v = { 16, 8192, 2 }) }, 1232 { IPP_SIZE_LIMIT(AREA, .h = { 16, 1920, 2 }, .v = { 16, 0, 2 }) }, 1233 { IPP_SIZE_LIMIT(ROTATED, .h = { 128, 1366 }, .v = { 128, 0 }) }, 1234 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, 1235 .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, 1236 }; 1237 1238 static const struct drm_exynos_ipp_limit fimc_4210_limits_tiled_v1[] = { 1239 { IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) }, 1240 { IPP_SIZE_LIMIT(AREA, .h = { 128, 1920, 2 }, .v = { 128, 0, 2 }) }, 1241 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, 1242 .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, 1243 }; 1244 1245 static const struct drm_exynos_ipp_limit fimc_4210_limits_tiled_v2[] = { 1246 { IPP_SIZE_LIMIT(BUFFER, .h = { 128, 1920, 128 }, .v = { 32, 1920, 32 }) }, 1247 { IPP_SIZE_LIMIT(AREA, .h = { 128, 1366, 2 }, .v = { 128, 0, 2 }) }, 1248 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 64, (1 << 16) * 64 }, 1249 .v = { (1 << 16) / 64, (1 << 16) * 64 }) }, 1250 }; 1251 1252 static int fimc_probe(struct platform_device *pdev) 1253 { 1254 const struct drm_exynos_ipp_limit *limits; 1255 struct exynos_drm_ipp_formats *formats; 1256 struct device *dev = &pdev->dev; 1257 struct fimc_context *ctx; 1258 struct resource *res; 1259 int ret; 1260 int i, j, num_limits, num_formats; 1261 1262 if (exynos_drm_check_fimc_device(dev) != 0) 1263 return -ENODEV; 1264 1265 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1266 if (!ctx) 1267 return -ENOMEM; 1268 1269 ctx->dev = dev; 1270 ctx->id = of_alias_get_id(dev->of_node, "fimc"); 1271 1272 /* construct formats/limits array */ 1273 num_formats = ARRAY_SIZE(fimc_formats) + ARRAY_SIZE(fimc_tiled_formats); 1274 formats = devm_kzalloc(dev, sizeof(*formats) * num_formats, GFP_KERNEL); 1275 if (!formats) 1276 return -ENOMEM; 1277 1278 /* linear formats */ 1279 if (ctx->id < 3) { 1280 limits = fimc_4210_limits_v1; 1281 num_limits = ARRAY_SIZE(fimc_4210_limits_v1); 1282 } else { 1283 limits = fimc_4210_limits_v2; 1284 num_limits = ARRAY_SIZE(fimc_4210_limits_v2); 1285 } 1286 for (i = 0; i < ARRAY_SIZE(fimc_formats); i++) { 1287 formats[i].fourcc = fimc_formats[i]; 1288 formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE | 1289 DRM_EXYNOS_IPP_FORMAT_DESTINATION; 1290 formats[i].limits = limits; 1291 formats[i].num_limits = num_limits; 1292 } 1293 1294 /* tiled formats */ 1295 if (ctx->id < 3) { 1296 limits = fimc_4210_limits_tiled_v1; 1297 num_limits = ARRAY_SIZE(fimc_4210_limits_tiled_v1); 1298 } else { 1299 limits = fimc_4210_limits_tiled_v2; 1300 num_limits = ARRAY_SIZE(fimc_4210_limits_tiled_v2); 1301 } 1302 for (j = i, i = 0; i < ARRAY_SIZE(fimc_tiled_formats); j++, i++) { 1303 formats[j].fourcc = fimc_tiled_formats[i]; 1304 formats[j].modifier = DRM_FORMAT_MOD_SAMSUNG_64_32_TILE; 1305 formats[j].type = DRM_EXYNOS_IPP_FORMAT_SOURCE | 1306 DRM_EXYNOS_IPP_FORMAT_DESTINATION; 1307 formats[j].limits = limits; 1308 formats[j].num_limits = num_limits; 1309 } 1310 1311 ctx->formats = formats; 1312 ctx->num_formats = num_formats; 1313 1314 /* resource memory */ 1315 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1316 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1317 if (IS_ERR(ctx->regs)) 1318 return PTR_ERR(ctx->regs); 1319 1320 /* resource irq */ 1321 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1322 if (!res) { 1323 dev_err(dev, "failed to request irq resource.\n"); 1324 return -ENOENT; 1325 } 1326 1327 ret = devm_request_irq(dev, res->start, fimc_irq_handler, 1328 0, dev_name(dev), ctx); 1329 if (ret < 0) { 1330 dev_err(dev, "failed to request irq.\n"); 1331 return ret; 1332 } 1333 1334 ret = fimc_setup_clocks(ctx); 1335 if (ret < 0) 1336 return ret; 1337 1338 spin_lock_init(&ctx->lock); 1339 platform_set_drvdata(pdev, ctx); 1340 1341 pm_runtime_use_autosuspend(dev); 1342 pm_runtime_set_autosuspend_delay(dev, FIMC_AUTOSUSPEND_DELAY); 1343 pm_runtime_enable(dev); 1344 1345 ret = component_add(dev, &fimc_component_ops); 1346 if (ret) 1347 goto err_pm_dis; 1348 1349 dev_info(dev, "drm fimc registered successfully.\n"); 1350 1351 return 0; 1352 1353 err_pm_dis: 1354 pm_runtime_dont_use_autosuspend(dev); 1355 pm_runtime_disable(dev); 1356 fimc_put_clocks(ctx); 1357 1358 return ret; 1359 } 1360 1361 static int fimc_remove(struct platform_device *pdev) 1362 { 1363 struct device *dev = &pdev->dev; 1364 struct fimc_context *ctx = get_fimc_context(dev); 1365 1366 component_del(dev, &fimc_component_ops); 1367 pm_runtime_dont_use_autosuspend(dev); 1368 pm_runtime_disable(dev); 1369 1370 fimc_put_clocks(ctx); 1371 1372 return 0; 1373 } 1374 1375 #ifdef CONFIG_PM 1376 static int fimc_runtime_suspend(struct device *dev) 1377 { 1378 struct fimc_context *ctx = get_fimc_context(dev); 1379 1380 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1381 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); 1382 return 0; 1383 } 1384 1385 static int fimc_runtime_resume(struct device *dev) 1386 { 1387 struct fimc_context *ctx = get_fimc_context(dev); 1388 1389 DRM_DEBUG_KMS("id[%d]\n", ctx->id); 1390 return clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); 1391 } 1392 #endif 1393 1394 static const struct dev_pm_ops fimc_pm_ops = { 1395 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1396 pm_runtime_force_resume) 1397 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) 1398 }; 1399 1400 static const struct of_device_id fimc_of_match[] = { 1401 { .compatible = "samsung,exynos4210-fimc" }, 1402 { .compatible = "samsung,exynos4212-fimc" }, 1403 { }, 1404 }; 1405 MODULE_DEVICE_TABLE(of, fimc_of_match); 1406 1407 struct platform_driver fimc_driver = { 1408 .probe = fimc_probe, 1409 .remove = fimc_remove, 1410 .driver = { 1411 .of_match_table = fimc_of_match, 1412 .name = "exynos-drm-fimc", 1413 .owner = THIS_MODULE, 1414 .pm = &fimc_pm_ops, 1415 }, 1416 }; 1417