116102edbSEunchul Kim /* 216102edbSEunchul Kim * Copyright (C) 2012 Samsung Electronics Co.Ltd 316102edbSEunchul Kim * Authors: 416102edbSEunchul Kim * Eunchul Kim <chulspro.kim@samsung.com> 516102edbSEunchul Kim * Jinyoung Jeon <jy0.jeon@samsung.com> 616102edbSEunchul Kim * Sangmin Lee <lsmin.lee@samsung.com> 716102edbSEunchul Kim * 816102edbSEunchul Kim * This program is free software; you can redistribute it and/or modify it 916102edbSEunchul Kim * under the terms of the GNU General Public License as published by the 1016102edbSEunchul Kim * Free Software Foundation; either version 2 of the License, or (at your 1116102edbSEunchul Kim * option) any later version. 1216102edbSEunchul Kim * 1316102edbSEunchul Kim */ 1416102edbSEunchul Kim #include <linux/kernel.h> 1516102edbSEunchul Kim #include <linux/platform_device.h> 16a3ad6976SSeung-Woo Kim #include <linux/mfd/syscon.h> 175186fc5eSSylwester Nawrocki #include <linux/regmap.h> 1816102edbSEunchul Kim #include <linux/clk.h> 1916102edbSEunchul Kim #include <linux/pm_runtime.h> 2016102edbSEunchul Kim 2116102edbSEunchul Kim #include <drm/drmP.h> 2216102edbSEunchul Kim #include <drm/exynos_drm.h> 2316102edbSEunchul Kim #include "regs-fimc.h" 24e30655d0SMark Brown #include "exynos_drm_drv.h" 2516102edbSEunchul Kim #include "exynos_drm_ipp.h" 2616102edbSEunchul Kim #include "exynos_drm_fimc.h" 2716102edbSEunchul Kim 2816102edbSEunchul Kim /* 296fe891f6SEunchul Kim * FIMC stands for Fully Interactive Mobile Camera and 3016102edbSEunchul Kim * supports image scaler/rotator and input/output DMA operations. 3116102edbSEunchul Kim * input DMA reads image data from the memory. 3216102edbSEunchul Kim * output DMA writes image data to memory. 3316102edbSEunchul Kim * FIMC supports image rotation and image effect functions. 3416102edbSEunchul Kim * 3516102edbSEunchul Kim * M2M operation : supports crop/scale/rotation/csc so on. 3616102edbSEunchul Kim * Memory ----> FIMC H/W ----> Memory. 3716102edbSEunchul Kim * Writeback operation : supports cloned screen with FIMD. 3816102edbSEunchul Kim * FIMD ----> FIMC H/W ----> Memory. 3916102edbSEunchul Kim * Output operation : supports direct display using local path. 4016102edbSEunchul Kim * Memory ----> FIMC H/W ----> FIMD. 4116102edbSEunchul Kim */ 4216102edbSEunchul Kim 4316102edbSEunchul Kim /* 4416102edbSEunchul Kim * TODO 4516102edbSEunchul Kim * 1. check suspend/resume api if needed. 4616102edbSEunchul Kim * 2. need to check use case platform_device_id. 4716102edbSEunchul Kim * 3. check src/dst size with, height. 4816102edbSEunchul Kim * 4. added check_prepare api for right register. 4916102edbSEunchul Kim * 5. need to add supported list in prop_list. 5016102edbSEunchul Kim * 6. check prescaler/scaler optimization. 5116102edbSEunchul Kim */ 5216102edbSEunchul Kim 5316102edbSEunchul Kim #define FIMC_MAX_DEVS 4 5416102edbSEunchul Kim #define FIMC_MAX_SRC 2 5516102edbSEunchul Kim #define FIMC_MAX_DST 32 5616102edbSEunchul Kim #define FIMC_SHFACTOR 10 5716102edbSEunchul Kim #define FIMC_BUF_STOP 1 5816102edbSEunchul Kim #define FIMC_BUF_START 2 5916102edbSEunchul Kim #define FIMC_REG_SZ 32 6016102edbSEunchul Kim #define FIMC_WIDTH_ITU_709 1280 6116102edbSEunchul Kim #define FIMC_REFRESH_MAX 60 6216102edbSEunchul Kim #define FIMC_REFRESH_MIN 12 6316102edbSEunchul Kim #define FIMC_CROP_MAX 8192 6416102edbSEunchul Kim #define FIMC_CROP_MIN 32 6516102edbSEunchul Kim #define FIMC_SCALE_MAX 4224 6616102edbSEunchul Kim #define FIMC_SCALE_MIN 32 6716102edbSEunchul Kim 6816102edbSEunchul Kim #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) 6916102edbSEunchul Kim #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ 7016102edbSEunchul Kim struct fimc_context, ippdrv); 7116102edbSEunchul Kim #define fimc_read(offset) readl(ctx->regs + (offset)) 7216102edbSEunchul Kim #define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) 7316102edbSEunchul Kim 7416102edbSEunchul Kim enum fimc_wb { 7516102edbSEunchul Kim FIMC_WB_NONE, 7616102edbSEunchul Kim FIMC_WB_A, 7716102edbSEunchul Kim FIMC_WB_B, 7816102edbSEunchul Kim }; 7916102edbSEunchul Kim 80e5f86839SSylwester Nawrocki enum { 81e5f86839SSylwester Nawrocki FIMC_CLK_LCLK, 82e5f86839SSylwester Nawrocki FIMC_CLK_GATE, 83e5f86839SSylwester Nawrocki FIMC_CLK_WB_A, 84e5f86839SSylwester Nawrocki FIMC_CLK_WB_B, 85e5f86839SSylwester Nawrocki FIMC_CLK_MUX, 86e5f86839SSylwester Nawrocki FIMC_CLK_PARENT, 87e5f86839SSylwester Nawrocki FIMC_CLKS_MAX 88e5f86839SSylwester Nawrocki }; 89e5f86839SSylwester Nawrocki 90e5f86839SSylwester Nawrocki static const char * const fimc_clock_names[] = { 91e5f86839SSylwester Nawrocki [FIMC_CLK_LCLK] = "sclk_fimc", 92e5f86839SSylwester Nawrocki [FIMC_CLK_GATE] = "fimc", 93e5f86839SSylwester Nawrocki [FIMC_CLK_WB_A] = "pxl_async0", 94e5f86839SSylwester Nawrocki [FIMC_CLK_WB_B] = "pxl_async1", 95e5f86839SSylwester Nawrocki [FIMC_CLK_MUX] = "mux", 96e5f86839SSylwester Nawrocki [FIMC_CLK_PARENT] = "parent", 97e5f86839SSylwester Nawrocki }; 98e5f86839SSylwester Nawrocki 99e5f86839SSylwester Nawrocki #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL 100e5f86839SSylwester Nawrocki 10116102edbSEunchul Kim /* 10216102edbSEunchul Kim * A structure of scaler. 10316102edbSEunchul Kim * 10416102edbSEunchul Kim * @range: narrow, wide. 10516102edbSEunchul Kim * @bypass: unused scaler path. 10616102edbSEunchul Kim * @up_h: horizontal scale up. 10716102edbSEunchul Kim * @up_v: vertical scale up. 10816102edbSEunchul Kim * @hratio: horizontal ratio. 10916102edbSEunchul Kim * @vratio: vertical ratio. 11016102edbSEunchul Kim */ 11116102edbSEunchul Kim struct fimc_scaler { 11216102edbSEunchul Kim bool range; 11316102edbSEunchul Kim bool bypass; 11416102edbSEunchul Kim bool up_h; 11516102edbSEunchul Kim bool up_v; 11616102edbSEunchul Kim u32 hratio; 11716102edbSEunchul Kim u32 vratio; 11816102edbSEunchul Kim }; 11916102edbSEunchul Kim 12016102edbSEunchul Kim /* 12116102edbSEunchul Kim * A structure of scaler capability. 12216102edbSEunchul Kim * 12316102edbSEunchul Kim * find user manual table 43-1. 12416102edbSEunchul Kim * @in_hori: scaler input horizontal size. 12516102edbSEunchul Kim * @bypass: scaler bypass mode. 12616102edbSEunchul Kim * @dst_h_wo_rot: target horizontal size without output rotation. 12716102edbSEunchul Kim * @dst_h_rot: target horizontal size with output rotation. 12816102edbSEunchul Kim * @rl_w_wo_rot: real width without input rotation. 12916102edbSEunchul Kim * @rl_h_rot: real height without output rotation. 13016102edbSEunchul Kim */ 13116102edbSEunchul Kim struct fimc_capability { 13216102edbSEunchul Kim /* scaler */ 13316102edbSEunchul Kim u32 in_hori; 13416102edbSEunchul Kim u32 bypass; 13516102edbSEunchul Kim /* output rotator */ 13616102edbSEunchul Kim u32 dst_h_wo_rot; 13716102edbSEunchul Kim u32 dst_h_rot; 13816102edbSEunchul Kim /* input rotator */ 13916102edbSEunchul Kim u32 rl_w_wo_rot; 14016102edbSEunchul Kim u32 rl_h_rot; 14116102edbSEunchul Kim }; 14216102edbSEunchul Kim 14316102edbSEunchul Kim /* 14416102edbSEunchul Kim * A structure of fimc context. 14516102edbSEunchul Kim * 14616102edbSEunchul Kim * @ippdrv: prepare initialization using ippdrv. 14716102edbSEunchul Kim * @regs_res: register resources. 14816102edbSEunchul Kim * @regs: memory mapped io registers. 14916102edbSEunchul Kim * @lock: locking of operations. 150e5f86839SSylwester Nawrocki * @clocks: fimc clocks. 151e5f86839SSylwester Nawrocki * @clk_frequency: LCLK clock frequency. 1525186fc5eSSylwester Nawrocki * @sysreg: handle to SYSREG block regmap. 15316102edbSEunchul Kim * @sc: scaler infomations. 15416102edbSEunchul Kim * @pol: porarity of writeback. 15516102edbSEunchul Kim * @id: fimc id. 15616102edbSEunchul Kim * @irq: irq number. 15716102edbSEunchul Kim * @suspended: qos operations. 15816102edbSEunchul Kim */ 15916102edbSEunchul Kim struct fimc_context { 16016102edbSEunchul Kim struct exynos_drm_ippdrv ippdrv; 16116102edbSEunchul Kim struct resource *regs_res; 16216102edbSEunchul Kim void __iomem *regs; 16316102edbSEunchul Kim struct mutex lock; 164e5f86839SSylwester Nawrocki struct clk *clocks[FIMC_CLKS_MAX]; 165e5f86839SSylwester Nawrocki u32 clk_frequency; 1665186fc5eSSylwester Nawrocki struct regmap *sysreg; 16716102edbSEunchul Kim struct fimc_scaler sc; 16816102edbSEunchul Kim struct exynos_drm_ipp_pol pol; 16916102edbSEunchul Kim int id; 17016102edbSEunchul Kim int irq; 17116102edbSEunchul Kim bool suspended; 17216102edbSEunchul Kim }; 17316102edbSEunchul Kim 174b5c0b552SJoongMock Shin static void fimc_sw_reset(struct fimc_context *ctx) 17516102edbSEunchul Kim { 17616102edbSEunchul Kim u32 cfg; 17716102edbSEunchul Kim 178e39d5ce1SJinyoung Jeon /* stop dma operation */ 179e39d5ce1SJinyoung Jeon cfg = fimc_read(EXYNOS_CISTATUS); 180e39d5ce1SJinyoung Jeon if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) { 181e39d5ce1SJinyoung Jeon cfg = fimc_read(EXYNOS_MSCTRL); 182e39d5ce1SJinyoung Jeon cfg &= ~EXYNOS_MSCTRL_ENVID; 183e39d5ce1SJinyoung Jeon fimc_write(cfg, EXYNOS_MSCTRL); 184e39d5ce1SJinyoung Jeon } 18516102edbSEunchul Kim 18616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISRCFMT); 18716102edbSEunchul Kim cfg |= EXYNOS_CISRCFMT_ITU601_8BIT; 18816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISRCFMT); 18916102edbSEunchul Kim 190e39d5ce1SJinyoung Jeon /* disable image capture */ 191e39d5ce1SJinyoung Jeon cfg = fimc_read(EXYNOS_CIIMGCPT); 192e39d5ce1SJinyoung Jeon cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 193e39d5ce1SJinyoung Jeon fimc_write(cfg, EXYNOS_CIIMGCPT); 194e39d5ce1SJinyoung Jeon 19516102edbSEunchul Kim /* s/w reset */ 19616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 19716102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SWRST); 19816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 19916102edbSEunchul Kim 20016102edbSEunchul Kim /* s/w reset complete */ 20116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 20216102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_SWRST; 20316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 20416102edbSEunchul Kim 20516102edbSEunchul Kim /* reset sequence */ 20616102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIFCNTSEQ); 20716102edbSEunchul Kim } 20816102edbSEunchul Kim 2095186fc5eSSylwester Nawrocki static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx) 21016102edbSEunchul Kim { 2115186fc5eSSylwester Nawrocki return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK, 2125186fc5eSSylwester Nawrocki SYSREG_FIMD0WB_DEST_MASK, 2135186fc5eSSylwester Nawrocki ctx->id << SYSREG_FIMD0WB_DEST_SHIFT); 21416102edbSEunchul Kim } 21516102edbSEunchul Kim 21616102edbSEunchul Kim static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb) 21716102edbSEunchul Kim { 21816102edbSEunchul Kim u32 cfg; 21916102edbSEunchul Kim 220cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("wb[%d]\n", wb); 22116102edbSEunchul Kim 22216102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 22316102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | 22416102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_ITU_MASK | 22516102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_MIPI_MASK | 22616102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_FIMC_MASK | 22716102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_MASK | 22816102edbSEunchul Kim EXYNOS_CIGCTRL_SELWRITEBACK_MASK); 22916102edbSEunchul Kim 23016102edbSEunchul Kim switch (wb) { 23116102edbSEunchul Kim case FIMC_WB_A: 23216102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A | 23316102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 23416102edbSEunchul Kim break; 23516102edbSEunchul Kim case FIMC_WB_B: 23616102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B | 23716102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 23816102edbSEunchul Kim break; 23916102edbSEunchul Kim case FIMC_WB_NONE: 24016102edbSEunchul Kim default: 24116102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | 24216102edbSEunchul Kim EXYNOS_CIGCTRL_SELWRITEBACK_A | 24316102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_MIPI_A | 24416102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_FIMC_ITU); 24516102edbSEunchul Kim break; 24616102edbSEunchul Kim } 24716102edbSEunchul Kim 24816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 24916102edbSEunchul Kim } 25016102edbSEunchul Kim 25116102edbSEunchul Kim static void fimc_set_polarity(struct fimc_context *ctx, 25216102edbSEunchul Kim struct exynos_drm_ipp_pol *pol) 25316102edbSEunchul Kim { 25416102edbSEunchul Kim u32 cfg; 25516102edbSEunchul Kim 256cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n", 257cbc4c33dSYoungJun Cho pol->inv_pclk, pol->inv_vsync); 258cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n", 259cbc4c33dSYoungJun Cho pol->inv_href, pol->inv_hsync); 26016102edbSEunchul Kim 26116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 26216102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC | 26316102edbSEunchul Kim EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC); 26416102edbSEunchul Kim 26516102edbSEunchul Kim if (pol->inv_pclk) 26616102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLPCLK; 26716102edbSEunchul Kim if (pol->inv_vsync) 26816102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC; 26916102edbSEunchul Kim if (pol->inv_href) 27016102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLHREF; 27116102edbSEunchul Kim if (pol->inv_hsync) 27216102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC; 27316102edbSEunchul Kim 27416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 27516102edbSEunchul Kim } 27616102edbSEunchul Kim 27716102edbSEunchul Kim static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) 27816102edbSEunchul Kim { 27916102edbSEunchul Kim u32 cfg; 28016102edbSEunchul Kim 281cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]\n", enable); 28216102edbSEunchul Kim 28316102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 28416102edbSEunchul Kim if (enable) 28516102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CAM_JPEG; 28616102edbSEunchul Kim else 28716102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG; 28816102edbSEunchul Kim 28916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 29016102edbSEunchul Kim } 29116102edbSEunchul Kim 29216102edbSEunchul Kim static void fimc_handle_irq(struct fimc_context *ctx, bool enable, 29316102edbSEunchul Kim bool overflow, bool level) 29416102edbSEunchul Kim { 29516102edbSEunchul Kim u32 cfg; 29616102edbSEunchul Kim 297cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", 29816102edbSEunchul Kim enable, overflow, level); 29916102edbSEunchul Kim 30016102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 30116102edbSEunchul Kim if (enable) { 30216102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL); 30316102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE; 30416102edbSEunchul Kim if (overflow) 30516102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN; 30616102edbSEunchul Kim if (level) 30716102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL; 30816102edbSEunchul Kim } else 30916102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE); 31016102edbSEunchul Kim 31116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 31216102edbSEunchul Kim } 31316102edbSEunchul Kim 31416102edbSEunchul Kim static void fimc_clear_irq(struct fimc_context *ctx) 31516102edbSEunchul Kim { 31616102edbSEunchul Kim u32 cfg; 31716102edbSEunchul Kim 31816102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 31916102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_CLR; 32016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 32116102edbSEunchul Kim } 32216102edbSEunchul Kim 32316102edbSEunchul Kim static bool fimc_check_ovf(struct fimc_context *ctx) 32416102edbSEunchul Kim { 32516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 32616102edbSEunchul Kim u32 cfg, status, flag; 32716102edbSEunchul Kim 32816102edbSEunchul Kim status = fimc_read(EXYNOS_CISTATUS); 32916102edbSEunchul Kim flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB | 33016102edbSEunchul Kim EXYNOS_CISTATUS_OVFICR; 33116102edbSEunchul Kim 332cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("flag[0x%x]\n", flag); 33316102edbSEunchul Kim 33416102edbSEunchul Kim if (status & flag) { 33516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIWDOFST); 33616102edbSEunchul Kim cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 33716102edbSEunchul Kim EXYNOS_CIWDOFST_CLROVFICR); 33816102edbSEunchul Kim 33916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST); 34016102edbSEunchul Kim 34116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIWDOFST); 34216102edbSEunchul Kim cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 34316102edbSEunchul Kim EXYNOS_CIWDOFST_CLROVFICR); 34416102edbSEunchul Kim 34516102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST); 34616102edbSEunchul Kim 34716102edbSEunchul Kim dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n", 34816102edbSEunchul Kim ctx->id, status); 34916102edbSEunchul Kim return true; 35016102edbSEunchul Kim } 35116102edbSEunchul Kim 35216102edbSEunchul Kim return false; 35316102edbSEunchul Kim } 35416102edbSEunchul Kim 35516102edbSEunchul Kim static bool fimc_check_frame_end(struct fimc_context *ctx) 35616102edbSEunchul Kim { 35716102edbSEunchul Kim u32 cfg; 35816102edbSEunchul Kim 35916102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISTATUS); 36016102edbSEunchul Kim 361cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("cfg[0x%x]\n", cfg); 36216102edbSEunchul Kim 36316102edbSEunchul Kim if (!(cfg & EXYNOS_CISTATUS_FRAMEEND)) 36416102edbSEunchul Kim return false; 36516102edbSEunchul Kim 36616102edbSEunchul Kim cfg &= ~(EXYNOS_CISTATUS_FRAMEEND); 36716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISTATUS); 36816102edbSEunchul Kim 36916102edbSEunchul Kim return true; 37016102edbSEunchul Kim } 37116102edbSEunchul Kim 37216102edbSEunchul Kim static int fimc_get_buf_id(struct fimc_context *ctx) 37316102edbSEunchul Kim { 37416102edbSEunchul Kim u32 cfg; 37516102edbSEunchul Kim int frame_cnt, buf_id; 37616102edbSEunchul Kim 37716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISTATUS2); 37816102edbSEunchul Kim frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg); 37916102edbSEunchul Kim 38016102edbSEunchul Kim if (frame_cnt == 0) 38116102edbSEunchul Kim frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg); 38216102edbSEunchul Kim 383cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("present[%d]before[%d]\n", 38416102edbSEunchul Kim EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg), 38516102edbSEunchul Kim EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg)); 38616102edbSEunchul Kim 38716102edbSEunchul Kim if (frame_cnt == 0) { 38816102edbSEunchul Kim DRM_ERROR("failed to get frame count.\n"); 38916102edbSEunchul Kim return -EIO; 39016102edbSEunchul Kim } 39116102edbSEunchul Kim 39216102edbSEunchul Kim buf_id = frame_cnt - 1; 393cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 39416102edbSEunchul Kim 39516102edbSEunchul Kim return buf_id; 39616102edbSEunchul Kim } 39716102edbSEunchul Kim 39816102edbSEunchul Kim static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) 39916102edbSEunchul Kim { 40016102edbSEunchul Kim u32 cfg; 40116102edbSEunchul Kim 402cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]\n", enable); 40316102edbSEunchul Kim 40416102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIOCTRL); 40516102edbSEunchul Kim if (enable) 40616102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_LASTENDEN; 40716102edbSEunchul Kim else 40816102edbSEunchul Kim cfg &= ~EXYNOS_CIOCTRL_LASTENDEN; 40916102edbSEunchul Kim 41016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCTRL); 41116102edbSEunchul Kim } 41216102edbSEunchul Kim 41316102edbSEunchul Kim 41416102edbSEunchul Kim static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) 41516102edbSEunchul Kim { 41616102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 41716102edbSEunchul Kim u32 cfg; 41816102edbSEunchul Kim 419cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 42016102edbSEunchul Kim 42116102edbSEunchul Kim /* RGB */ 42216102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 42316102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK; 42416102edbSEunchul Kim 42516102edbSEunchul Kim switch (fmt) { 42616102edbSEunchul Kim case DRM_FORMAT_RGB565: 42716102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565; 42816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 42916102edbSEunchul Kim return 0; 43016102edbSEunchul Kim case DRM_FORMAT_RGB888: 43116102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 43216102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888; 43316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 43416102edbSEunchul Kim return 0; 43516102edbSEunchul Kim default: 43616102edbSEunchul Kim /* bypass */ 43716102edbSEunchul Kim break; 43816102edbSEunchul Kim } 43916102edbSEunchul Kim 44016102edbSEunchul Kim /* YUV */ 44116102edbSEunchul Kim cfg = fimc_read(EXYNOS_MSCTRL); 44216102edbSEunchul Kim cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK | 44316102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE | 44416102edbSEunchul Kim EXYNOS_MSCTRL_ORDER422_YCBYCR); 44516102edbSEunchul Kim 44616102edbSEunchul Kim switch (fmt) { 44716102edbSEunchul Kim case DRM_FORMAT_YUYV: 44816102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR; 44916102edbSEunchul Kim break; 45016102edbSEunchul Kim case DRM_FORMAT_YVYU: 45116102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB; 45216102edbSEunchul Kim break; 45316102edbSEunchul Kim case DRM_FORMAT_UYVY: 45416102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY; 45516102edbSEunchul Kim break; 45616102edbSEunchul Kim case DRM_FORMAT_VYUY: 45716102edbSEunchul Kim case DRM_FORMAT_YUV444: 45816102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY; 45916102edbSEunchul Kim break; 46016102edbSEunchul Kim case DRM_FORMAT_NV21: 46116102edbSEunchul Kim case DRM_FORMAT_NV61: 46216102edbSEunchul Kim cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB | 46316102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE); 46416102edbSEunchul Kim break; 46516102edbSEunchul Kim case DRM_FORMAT_YUV422: 46616102edbSEunchul Kim case DRM_FORMAT_YUV420: 46716102edbSEunchul Kim case DRM_FORMAT_YVU420: 46816102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE; 46916102edbSEunchul Kim break; 47016102edbSEunchul Kim case DRM_FORMAT_NV12: 47116102edbSEunchul Kim case DRM_FORMAT_NV12MT: 47216102edbSEunchul Kim case DRM_FORMAT_NV16: 47316102edbSEunchul Kim cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR | 47416102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE); 47516102edbSEunchul Kim break; 47616102edbSEunchul Kim default: 47716102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt); 47816102edbSEunchul Kim return -EINVAL; 47916102edbSEunchul Kim } 48016102edbSEunchul Kim 48116102edbSEunchul Kim fimc_write(cfg, EXYNOS_MSCTRL); 48216102edbSEunchul Kim 48316102edbSEunchul Kim return 0; 48416102edbSEunchul Kim } 48516102edbSEunchul Kim 48616102edbSEunchul Kim static int fimc_src_set_fmt(struct device *dev, u32 fmt) 48716102edbSEunchul Kim { 48816102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 48916102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 49016102edbSEunchul Kim u32 cfg; 49116102edbSEunchul Kim 492cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 49316102edbSEunchul Kim 49416102edbSEunchul Kim cfg = fimc_read(EXYNOS_MSCTRL); 49516102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB; 49616102edbSEunchul Kim 49716102edbSEunchul Kim switch (fmt) { 49816102edbSEunchul Kim case DRM_FORMAT_RGB565: 49916102edbSEunchul Kim case DRM_FORMAT_RGB888: 50016102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 50116102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_RGB; 50216102edbSEunchul Kim break; 50316102edbSEunchul Kim case DRM_FORMAT_YUV444: 50416102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 50516102edbSEunchul Kim break; 50616102edbSEunchul Kim case DRM_FORMAT_YUYV: 50716102edbSEunchul Kim case DRM_FORMAT_YVYU: 50816102edbSEunchul Kim case DRM_FORMAT_UYVY: 50916102edbSEunchul Kim case DRM_FORMAT_VYUY: 51016102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE; 51116102edbSEunchul Kim break; 51216102edbSEunchul Kim case DRM_FORMAT_NV16: 51316102edbSEunchul Kim case DRM_FORMAT_NV61: 51416102edbSEunchul Kim case DRM_FORMAT_YUV422: 51516102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422; 51616102edbSEunchul Kim break; 51716102edbSEunchul Kim case DRM_FORMAT_YUV420: 51816102edbSEunchul Kim case DRM_FORMAT_YVU420: 51916102edbSEunchul Kim case DRM_FORMAT_NV12: 52016102edbSEunchul Kim case DRM_FORMAT_NV21: 52116102edbSEunchul Kim case DRM_FORMAT_NV12MT: 52216102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 52316102edbSEunchul Kim break; 52416102edbSEunchul Kim default: 52516102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt); 52616102edbSEunchul Kim return -EINVAL; 52716102edbSEunchul Kim } 52816102edbSEunchul Kim 52916102edbSEunchul Kim fimc_write(cfg, EXYNOS_MSCTRL); 53016102edbSEunchul Kim 53116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIDMAPARAM); 53216102edbSEunchul Kim cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK; 53316102edbSEunchul Kim 53416102edbSEunchul Kim if (fmt == DRM_FORMAT_NV12MT) 53516102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32; 53616102edbSEunchul Kim else 53716102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR; 53816102edbSEunchul Kim 53916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIDMAPARAM); 54016102edbSEunchul Kim 54116102edbSEunchul Kim return fimc_src_set_fmt_order(ctx, fmt); 54216102edbSEunchul Kim } 54316102edbSEunchul Kim 54416102edbSEunchul Kim static int fimc_src_set_transf(struct device *dev, 54516102edbSEunchul Kim enum drm_exynos_degree degree, 54616102edbSEunchul Kim enum drm_exynos_flip flip, bool *swap) 54716102edbSEunchul Kim { 54816102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 54916102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 55016102edbSEunchul Kim u32 cfg1, cfg2; 55116102edbSEunchul Kim 552cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 55316102edbSEunchul Kim 55416102edbSEunchul Kim cfg1 = fimc_read(EXYNOS_MSCTRL); 55516102edbSEunchul Kim cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | 55616102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 55716102edbSEunchul Kim 55816102edbSEunchul Kim cfg2 = fimc_read(EXYNOS_CITRGFMT); 55916102edbSEunchul Kim cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 56016102edbSEunchul Kim 56116102edbSEunchul Kim switch (degree) { 56216102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 56316102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 56416102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 56516102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 56616102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 56716102edbSEunchul Kim break; 56816102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 56916102edbSEunchul Kim cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 57016102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 57116102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 57216102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 57316102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 57416102edbSEunchul Kim break; 57516102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 57616102edbSEunchul Kim cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 57716102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 57816102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 57916102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 58016102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 58116102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 58216102edbSEunchul Kim break; 58316102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 58416102edbSEunchul Kim cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 58516102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 58616102edbSEunchul Kim cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 58716102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 58816102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 58916102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 59016102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 59116102edbSEunchul Kim break; 59216102edbSEunchul Kim default: 59316102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 59416102edbSEunchul Kim return -EINVAL; 59516102edbSEunchul Kim } 59616102edbSEunchul Kim 59716102edbSEunchul Kim fimc_write(cfg1, EXYNOS_MSCTRL); 59816102edbSEunchul Kim fimc_write(cfg2, EXYNOS_CITRGFMT); 59916102edbSEunchul Kim *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0; 60016102edbSEunchul Kim 60116102edbSEunchul Kim return 0; 60216102edbSEunchul Kim } 60316102edbSEunchul Kim 60416102edbSEunchul Kim static int fimc_set_window(struct fimc_context *ctx, 60516102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 60616102edbSEunchul Kim { 60716102edbSEunchul Kim u32 cfg, h1, h2, v1, v2; 60816102edbSEunchul Kim 60916102edbSEunchul Kim /* cropped image */ 61016102edbSEunchul Kim h1 = pos->x; 61116102edbSEunchul Kim h2 = sz->hsize - pos->w - pos->x; 61216102edbSEunchul Kim v1 = pos->y; 61316102edbSEunchul Kim v2 = sz->vsize - pos->h - pos->y; 61416102edbSEunchul Kim 615cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n", 616cbc4c33dSYoungJun Cho pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize); 617cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2); 61816102edbSEunchul Kim 61916102edbSEunchul Kim /* 62016102edbSEunchul Kim * set window offset 1, 2 size 62116102edbSEunchul Kim * check figure 43-21 in user manual 62216102edbSEunchul Kim */ 62316102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIWDOFST); 62416102edbSEunchul Kim cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK | 62516102edbSEunchul Kim EXYNOS_CIWDOFST_WINVEROFST_MASK); 62616102edbSEunchul Kim cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) | 62716102edbSEunchul Kim EXYNOS_CIWDOFST_WINVEROFST(v1)); 62816102edbSEunchul Kim cfg |= EXYNOS_CIWDOFST_WINOFSEN; 62916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST); 63016102edbSEunchul Kim 63116102edbSEunchul Kim cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) | 63216102edbSEunchul Kim EXYNOS_CIWDOFST2_WINVEROFST2(v2)); 63316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST2); 63416102edbSEunchul Kim 63516102edbSEunchul Kim return 0; 63616102edbSEunchul Kim } 63716102edbSEunchul Kim 63816102edbSEunchul Kim static int fimc_src_set_size(struct device *dev, int swap, 63916102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 64016102edbSEunchul Kim { 64116102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 64216102edbSEunchul Kim struct drm_exynos_pos img_pos = *pos; 64316102edbSEunchul Kim struct drm_exynos_sz img_sz = *sz; 64416102edbSEunchul Kim u32 cfg; 64516102edbSEunchul Kim 646cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n", 647cbc4c33dSYoungJun Cho swap, sz->hsize, sz->vsize); 64816102edbSEunchul Kim 64916102edbSEunchul Kim /* original size */ 65016102edbSEunchul Kim cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) | 65116102edbSEunchul Kim EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize)); 65216102edbSEunchul Kim 65316102edbSEunchul Kim fimc_write(cfg, EXYNOS_ORGISIZE); 65416102edbSEunchul Kim 655cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h); 65616102edbSEunchul Kim 65716102edbSEunchul Kim if (swap) { 65816102edbSEunchul Kim img_pos.w = pos->h; 65916102edbSEunchul Kim img_pos.h = pos->w; 66016102edbSEunchul Kim img_sz.hsize = sz->vsize; 66116102edbSEunchul Kim img_sz.vsize = sz->hsize; 66216102edbSEunchul Kim } 66316102edbSEunchul Kim 66416102edbSEunchul Kim /* set input DMA image size */ 66516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIREAL_ISIZE); 66616102edbSEunchul Kim cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK | 66716102edbSEunchul Kim EXYNOS_CIREAL_ISIZE_WIDTH_MASK); 66816102edbSEunchul Kim cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) | 66916102edbSEunchul Kim EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h)); 67016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIREAL_ISIZE); 67116102edbSEunchul Kim 67216102edbSEunchul Kim /* 67316102edbSEunchul Kim * set input FIFO image size 67416102edbSEunchul Kim * for now, we support only ITU601 8 bit mode 67516102edbSEunchul Kim */ 67616102edbSEunchul Kim cfg = (EXYNOS_CISRCFMT_ITU601_8BIT | 67716102edbSEunchul Kim EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) | 67816102edbSEunchul Kim EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize)); 67916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISRCFMT); 68016102edbSEunchul Kim 68116102edbSEunchul Kim /* offset Y(RGB), Cb, Cr */ 68216102edbSEunchul Kim cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) | 68316102edbSEunchul Kim EXYNOS_CIIYOFF_VERTICAL(img_pos.y)); 68416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIIYOFF); 68516102edbSEunchul Kim cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) | 68616102edbSEunchul Kim EXYNOS_CIICBOFF_VERTICAL(img_pos.y)); 68716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIICBOFF); 68816102edbSEunchul Kim cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) | 68916102edbSEunchul Kim EXYNOS_CIICROFF_VERTICAL(img_pos.y)); 69016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIICROFF); 69116102edbSEunchul Kim 69216102edbSEunchul Kim return fimc_set_window(ctx, &img_pos, &img_sz); 69316102edbSEunchul Kim } 69416102edbSEunchul Kim 69516102edbSEunchul Kim static int fimc_src_set_addr(struct device *dev, 69616102edbSEunchul Kim struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 69716102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 69816102edbSEunchul Kim { 69916102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 70016102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 7017259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 70216102edbSEunchul Kim struct drm_exynos_ipp_property *property; 70316102edbSEunchul Kim struct drm_exynos_ipp_config *config; 70416102edbSEunchul Kim 70516102edbSEunchul Kim if (!c_node) { 70616102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 70716102edbSEunchul Kim return -EINVAL; 70816102edbSEunchul Kim } 70916102edbSEunchul Kim 71016102edbSEunchul Kim property = &c_node->property; 71116102edbSEunchul Kim 712cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 71316102edbSEunchul Kim property->prop_id, buf_id, buf_type); 71416102edbSEunchul Kim 71516102edbSEunchul Kim if (buf_id > FIMC_MAX_SRC) { 71616102edbSEunchul Kim dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 71716102edbSEunchul Kim return -ENOMEM; 71816102edbSEunchul Kim } 71916102edbSEunchul Kim 72016102edbSEunchul Kim /* address register set */ 72116102edbSEunchul Kim switch (buf_type) { 72216102edbSEunchul Kim case IPP_BUF_ENQUEUE: 72316102edbSEunchul Kim config = &property->config[EXYNOS_DRM_OPS_SRC]; 72416102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 72516102edbSEunchul Kim EXYNOS_CIIYSA(buf_id)); 72616102edbSEunchul Kim 72716102edbSEunchul Kim if (config->fmt == DRM_FORMAT_YVU420) { 72816102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 72916102edbSEunchul Kim EXYNOS_CIICBSA(buf_id)); 73016102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 73116102edbSEunchul Kim EXYNOS_CIICRSA(buf_id)); 73216102edbSEunchul Kim } else { 73316102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 73416102edbSEunchul Kim EXYNOS_CIICBSA(buf_id)); 73516102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 73616102edbSEunchul Kim EXYNOS_CIICRSA(buf_id)); 73716102edbSEunchul Kim } 73816102edbSEunchul Kim break; 73916102edbSEunchul Kim case IPP_BUF_DEQUEUE: 74016102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIIYSA(buf_id)); 74116102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIICBSA(buf_id)); 74216102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIICRSA(buf_id)); 74316102edbSEunchul Kim break; 74416102edbSEunchul Kim default: 74516102edbSEunchul Kim /* bypass */ 74616102edbSEunchul Kim break; 74716102edbSEunchul Kim } 74816102edbSEunchul Kim 74916102edbSEunchul Kim return 0; 75016102edbSEunchul Kim } 75116102edbSEunchul Kim 75216102edbSEunchul Kim static struct exynos_drm_ipp_ops fimc_src_ops = { 75316102edbSEunchul Kim .set_fmt = fimc_src_set_fmt, 75416102edbSEunchul Kim .set_transf = fimc_src_set_transf, 75516102edbSEunchul Kim .set_size = fimc_src_set_size, 75616102edbSEunchul Kim .set_addr = fimc_src_set_addr, 75716102edbSEunchul Kim }; 75816102edbSEunchul Kim 75916102edbSEunchul Kim static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) 76016102edbSEunchul Kim { 76116102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 76216102edbSEunchul Kim u32 cfg; 76316102edbSEunchul Kim 764cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 76516102edbSEunchul Kim 76616102edbSEunchul Kim /* RGB */ 76716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 76816102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK; 76916102edbSEunchul Kim 77016102edbSEunchul Kim switch (fmt) { 77116102edbSEunchul Kim case DRM_FORMAT_RGB565: 77216102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565; 77316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 77416102edbSEunchul Kim return 0; 77516102edbSEunchul Kim case DRM_FORMAT_RGB888: 77616102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888; 77716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 77816102edbSEunchul Kim return 0; 77916102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 78016102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 | 78116102edbSEunchul Kim EXYNOS_CISCCTRL_EXTRGB_EXTENSION); 78216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 78316102edbSEunchul Kim break; 78416102edbSEunchul Kim default: 78516102edbSEunchul Kim /* bypass */ 78616102edbSEunchul Kim break; 78716102edbSEunchul Kim } 78816102edbSEunchul Kim 78916102edbSEunchul Kim /* YUV */ 79016102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIOCTRL); 79116102edbSEunchul Kim cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK | 79216102edbSEunchul Kim EXYNOS_CIOCTRL_ORDER422_MASK | 79316102edbSEunchul Kim EXYNOS_CIOCTRL_YCBCR_PLANE_MASK); 79416102edbSEunchul Kim 79516102edbSEunchul Kim switch (fmt) { 79616102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 79716102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ALPHA_OUT; 79816102edbSEunchul Kim break; 79916102edbSEunchul Kim case DRM_FORMAT_YUYV: 80016102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR; 80116102edbSEunchul Kim break; 80216102edbSEunchul Kim case DRM_FORMAT_YVYU: 80316102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB; 80416102edbSEunchul Kim break; 80516102edbSEunchul Kim case DRM_FORMAT_UYVY: 80616102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY; 80716102edbSEunchul Kim break; 80816102edbSEunchul Kim case DRM_FORMAT_VYUY: 80916102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY; 81016102edbSEunchul Kim break; 81116102edbSEunchul Kim case DRM_FORMAT_NV21: 81216102edbSEunchul Kim case DRM_FORMAT_NV61: 81316102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB; 81416102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 81516102edbSEunchul Kim break; 81616102edbSEunchul Kim case DRM_FORMAT_YUV422: 81716102edbSEunchul Kim case DRM_FORMAT_YUV420: 81816102edbSEunchul Kim case DRM_FORMAT_YVU420: 81916102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE; 82016102edbSEunchul Kim break; 82116102edbSEunchul Kim case DRM_FORMAT_NV12: 82216102edbSEunchul Kim case DRM_FORMAT_NV12MT: 82316102edbSEunchul Kim case DRM_FORMAT_NV16: 82416102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR; 82516102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 82616102edbSEunchul Kim break; 82716102edbSEunchul Kim default: 82816102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); 82916102edbSEunchul Kim return -EINVAL; 83016102edbSEunchul Kim } 83116102edbSEunchul Kim 83216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCTRL); 83316102edbSEunchul Kim 83416102edbSEunchul Kim return 0; 83516102edbSEunchul Kim } 83616102edbSEunchul Kim 83716102edbSEunchul Kim static int fimc_dst_set_fmt(struct device *dev, u32 fmt) 83816102edbSEunchul Kim { 83916102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 84016102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 84116102edbSEunchul Kim u32 cfg; 84216102edbSEunchul Kim 843cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 84416102edbSEunchul Kim 84516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIEXTEN); 84616102edbSEunchul Kim 84716102edbSEunchul Kim if (fmt == DRM_FORMAT_AYUV) { 84816102edbSEunchul Kim cfg |= EXYNOS_CIEXTEN_YUV444_OUT; 84916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIEXTEN); 85016102edbSEunchul Kim } else { 85116102edbSEunchul Kim cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT; 85216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIEXTEN); 85316102edbSEunchul Kim 85416102edbSEunchul Kim cfg = fimc_read(EXYNOS_CITRGFMT); 85516102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK; 85616102edbSEunchul Kim 85716102edbSEunchul Kim switch (fmt) { 85816102edbSEunchul Kim case DRM_FORMAT_RGB565: 85916102edbSEunchul Kim case DRM_FORMAT_RGB888: 86016102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 86116102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB; 86216102edbSEunchul Kim break; 86316102edbSEunchul Kim case DRM_FORMAT_YUYV: 86416102edbSEunchul Kim case DRM_FORMAT_YVYU: 86516102edbSEunchul Kim case DRM_FORMAT_UYVY: 86616102edbSEunchul Kim case DRM_FORMAT_VYUY: 86716102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; 86816102edbSEunchul Kim break; 86916102edbSEunchul Kim case DRM_FORMAT_NV16: 87016102edbSEunchul Kim case DRM_FORMAT_NV61: 87116102edbSEunchul Kim case DRM_FORMAT_YUV422: 87216102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422; 87316102edbSEunchul Kim break; 87416102edbSEunchul Kim case DRM_FORMAT_YUV420: 87516102edbSEunchul Kim case DRM_FORMAT_YVU420: 87616102edbSEunchul Kim case DRM_FORMAT_NV12: 87716102edbSEunchul Kim case DRM_FORMAT_NV12MT: 87816102edbSEunchul Kim case DRM_FORMAT_NV21: 87916102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; 88016102edbSEunchul Kim break; 88116102edbSEunchul Kim default: 88216102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid target format 0x%x.\n", 88316102edbSEunchul Kim fmt); 88416102edbSEunchul Kim return -EINVAL; 88516102edbSEunchul Kim } 88616102edbSEunchul Kim 88716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITRGFMT); 88816102edbSEunchul Kim } 88916102edbSEunchul Kim 89016102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIDMAPARAM); 89116102edbSEunchul Kim cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK; 89216102edbSEunchul Kim 89316102edbSEunchul Kim if (fmt == DRM_FORMAT_NV12MT) 89416102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32; 89516102edbSEunchul Kim else 89616102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR; 89716102edbSEunchul Kim 89816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIDMAPARAM); 89916102edbSEunchul Kim 90016102edbSEunchul Kim return fimc_dst_set_fmt_order(ctx, fmt); 90116102edbSEunchul Kim } 90216102edbSEunchul Kim 90316102edbSEunchul Kim static int fimc_dst_set_transf(struct device *dev, 90416102edbSEunchul Kim enum drm_exynos_degree degree, 90516102edbSEunchul Kim enum drm_exynos_flip flip, bool *swap) 90616102edbSEunchul Kim { 90716102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 90816102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 90916102edbSEunchul Kim u32 cfg; 91016102edbSEunchul Kim 911cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 91216102edbSEunchul Kim 91316102edbSEunchul Kim cfg = fimc_read(EXYNOS_CITRGFMT); 91416102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK; 91516102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 91616102edbSEunchul Kim 91716102edbSEunchul Kim switch (degree) { 91816102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 91916102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 92016102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 92116102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 92216102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 92316102edbSEunchul Kim break; 92416102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 92516102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 92616102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 92716102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 92816102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 92916102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 93016102edbSEunchul Kim break; 93116102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 93216102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR | 93316102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 93416102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 93516102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 93616102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 93716102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 93816102edbSEunchul Kim break; 93916102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 94016102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE | 94116102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_X_MIRROR | 94216102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 94316102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 94416102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 94516102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 94616102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 94716102edbSEunchul Kim break; 94816102edbSEunchul Kim default: 94916102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 95016102edbSEunchul Kim return -EINVAL; 95116102edbSEunchul Kim } 95216102edbSEunchul Kim 95316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITRGFMT); 95416102edbSEunchul Kim *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0; 95516102edbSEunchul Kim 95616102edbSEunchul Kim return 0; 95716102edbSEunchul Kim } 95816102edbSEunchul Kim 95916102edbSEunchul Kim static int fimc_get_ratio_shift(u32 src, u32 dst, u32 *ratio, u32 *shift) 96016102edbSEunchul Kim { 961cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst); 96216102edbSEunchul Kim 96316102edbSEunchul Kim if (src >= dst * 64) { 96416102edbSEunchul Kim DRM_ERROR("failed to make ratio and shift.\n"); 96516102edbSEunchul Kim return -EINVAL; 96616102edbSEunchul Kim } else if (src >= dst * 32) { 96716102edbSEunchul Kim *ratio = 32; 96816102edbSEunchul Kim *shift = 5; 96916102edbSEunchul Kim } else if (src >= dst * 16) { 97016102edbSEunchul Kim *ratio = 16; 97116102edbSEunchul Kim *shift = 4; 97216102edbSEunchul Kim } else if (src >= dst * 8) { 97316102edbSEunchul Kim *ratio = 8; 97416102edbSEunchul Kim *shift = 3; 97516102edbSEunchul Kim } else if (src >= dst * 4) { 97616102edbSEunchul Kim *ratio = 4; 97716102edbSEunchul Kim *shift = 2; 97816102edbSEunchul Kim } else if (src >= dst * 2) { 97916102edbSEunchul Kim *ratio = 2; 98016102edbSEunchul Kim *shift = 1; 98116102edbSEunchul Kim } else { 98216102edbSEunchul Kim *ratio = 1; 98316102edbSEunchul Kim *shift = 0; 98416102edbSEunchul Kim } 98516102edbSEunchul Kim 98616102edbSEunchul Kim return 0; 98716102edbSEunchul Kim } 98816102edbSEunchul Kim 98916102edbSEunchul Kim static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, 99016102edbSEunchul Kim struct drm_exynos_pos *src, struct drm_exynos_pos *dst) 99116102edbSEunchul Kim { 99216102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 99316102edbSEunchul Kim u32 cfg, cfg_ext, shfactor; 99416102edbSEunchul Kim u32 pre_dst_width, pre_dst_height; 99516102edbSEunchul Kim u32 pre_hratio, hfactor, pre_vratio, vfactor; 99616102edbSEunchul Kim int ret = 0; 99716102edbSEunchul Kim u32 src_w, src_h, dst_w, dst_h; 99816102edbSEunchul Kim 99916102edbSEunchul Kim cfg_ext = fimc_read(EXYNOS_CITRGFMT); 100016102edbSEunchul Kim if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) { 100116102edbSEunchul Kim src_w = src->h; 100216102edbSEunchul Kim src_h = src->w; 100316102edbSEunchul Kim } else { 100416102edbSEunchul Kim src_w = src->w; 100516102edbSEunchul Kim src_h = src->h; 100616102edbSEunchul Kim } 100716102edbSEunchul Kim 100816102edbSEunchul Kim if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) { 100916102edbSEunchul Kim dst_w = dst->h; 101016102edbSEunchul Kim dst_h = dst->w; 101116102edbSEunchul Kim } else { 101216102edbSEunchul Kim dst_w = dst->w; 101316102edbSEunchul Kim dst_h = dst->h; 101416102edbSEunchul Kim } 101516102edbSEunchul Kim 101616102edbSEunchul Kim ret = fimc_get_ratio_shift(src_w, dst_w, &pre_hratio, &hfactor); 101716102edbSEunchul Kim if (ret) { 101816102edbSEunchul Kim dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); 101916102edbSEunchul Kim return ret; 102016102edbSEunchul Kim } 102116102edbSEunchul Kim 102216102edbSEunchul Kim ret = fimc_get_ratio_shift(src_h, dst_h, &pre_vratio, &vfactor); 102316102edbSEunchul Kim if (ret) { 102416102edbSEunchul Kim dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); 102516102edbSEunchul Kim return ret; 102616102edbSEunchul Kim } 102716102edbSEunchul Kim 102816102edbSEunchul Kim pre_dst_width = src_w / pre_hratio; 102916102edbSEunchul Kim pre_dst_height = src_h / pre_vratio; 1030cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n", 103116102edbSEunchul Kim pre_dst_width, pre_dst_height); 1032cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("pre_hratio[%d]hfactor[%d]pre_vratio[%d]vfactor[%d]\n", 1033cbc4c33dSYoungJun Cho pre_hratio, hfactor, pre_vratio, vfactor); 103416102edbSEunchul Kim 103516102edbSEunchul Kim sc->hratio = (src_w << 14) / (dst_w << hfactor); 103616102edbSEunchul Kim sc->vratio = (src_h << 14) / (dst_h << vfactor); 103716102edbSEunchul Kim sc->up_h = (dst_w >= src_w) ? true : false; 103816102edbSEunchul Kim sc->up_v = (dst_h >= src_h) ? true : false; 1039cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n", 1040cbc4c33dSYoungJun Cho sc->hratio, sc->vratio, sc->up_h, sc->up_v); 104116102edbSEunchul Kim 104216102edbSEunchul Kim shfactor = FIMC_SHFACTOR - (hfactor + vfactor); 1043cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("shfactor[%d]\n", shfactor); 104416102edbSEunchul Kim 104516102edbSEunchul Kim cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) | 104616102edbSEunchul Kim EXYNOS_CISCPRERATIO_PREHORRATIO(pre_hratio) | 104716102edbSEunchul Kim EXYNOS_CISCPRERATIO_PREVERRATIO(pre_vratio)); 104816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCPRERATIO); 104916102edbSEunchul Kim 105016102edbSEunchul Kim cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) | 105116102edbSEunchul Kim EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height)); 105216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCPREDST); 105316102edbSEunchul Kim 105416102edbSEunchul Kim return ret; 105516102edbSEunchul Kim } 105616102edbSEunchul Kim 105716102edbSEunchul Kim static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) 105816102edbSEunchul Kim { 105916102edbSEunchul Kim u32 cfg, cfg_ext; 106016102edbSEunchul Kim 1061cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n", 1062cbc4c33dSYoungJun Cho sc->range, sc->bypass, sc->up_h, sc->up_v); 1063cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n", 1064cbc4c33dSYoungJun Cho sc->hratio, sc->vratio); 106516102edbSEunchul Kim 106616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 106716102edbSEunchul Kim cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS | 106816102edbSEunchul Kim EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V | 106916102edbSEunchul Kim EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK | 107016102edbSEunchul Kim EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK | 107116102edbSEunchul Kim EXYNOS_CISCCTRL_CSCR2Y_WIDE | 107216102edbSEunchul Kim EXYNOS_CISCCTRL_CSCY2R_WIDE); 107316102edbSEunchul Kim 107416102edbSEunchul Kim if (sc->range) 107516102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | 107616102edbSEunchul Kim EXYNOS_CISCCTRL_CSCY2R_WIDE); 107716102edbSEunchul Kim if (sc->bypass) 107816102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; 107916102edbSEunchul Kim if (sc->up_h) 108016102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALEUP_H; 108116102edbSEunchul Kim if (sc->up_v) 108216102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALEUP_V; 108316102edbSEunchul Kim 108416102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) | 108516102edbSEunchul Kim EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6))); 108616102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 108716102edbSEunchul Kim 108816102edbSEunchul Kim cfg_ext = fimc_read(EXYNOS_CIEXTEN); 108916102edbSEunchul Kim cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK; 109016102edbSEunchul Kim cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK; 109116102edbSEunchul Kim cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) | 109216102edbSEunchul Kim EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio)); 109316102edbSEunchul Kim fimc_write(cfg_ext, EXYNOS_CIEXTEN); 109416102edbSEunchul Kim } 109516102edbSEunchul Kim 109616102edbSEunchul Kim static int fimc_dst_set_size(struct device *dev, int swap, 109716102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 109816102edbSEunchul Kim { 109916102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 110016102edbSEunchul Kim struct drm_exynos_pos img_pos = *pos; 110116102edbSEunchul Kim struct drm_exynos_sz img_sz = *sz; 110216102edbSEunchul Kim u32 cfg; 110316102edbSEunchul Kim 1104cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n", 1105cbc4c33dSYoungJun Cho swap, sz->hsize, sz->vsize); 110616102edbSEunchul Kim 110716102edbSEunchul Kim /* original size */ 110816102edbSEunchul Kim cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) | 110916102edbSEunchul Kim EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize)); 111016102edbSEunchul Kim 111116102edbSEunchul Kim fimc_write(cfg, EXYNOS_ORGOSIZE); 111216102edbSEunchul Kim 1113cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h); 111416102edbSEunchul Kim 111516102edbSEunchul Kim /* CSC ITU */ 111616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 111716102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_CSC_MASK; 111816102edbSEunchul Kim 111916102edbSEunchul Kim if (sz->hsize >= FIMC_WIDTH_ITU_709) 112016102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CSC_ITU709; 112116102edbSEunchul Kim else 112216102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CSC_ITU601; 112316102edbSEunchul Kim 112416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 112516102edbSEunchul Kim 112616102edbSEunchul Kim if (swap) { 112716102edbSEunchul Kim img_pos.w = pos->h; 112816102edbSEunchul Kim img_pos.h = pos->w; 112916102edbSEunchul Kim img_sz.hsize = sz->vsize; 113016102edbSEunchul Kim img_sz.vsize = sz->hsize; 113116102edbSEunchul Kim } 113216102edbSEunchul Kim 113316102edbSEunchul Kim /* target image size */ 113416102edbSEunchul Kim cfg = fimc_read(EXYNOS_CITRGFMT); 113516102edbSEunchul Kim cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK | 113616102edbSEunchul Kim EXYNOS_CITRGFMT_TARGETV_MASK); 113716102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) | 113816102edbSEunchul Kim EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h)); 113916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITRGFMT); 114016102edbSEunchul Kim 114116102edbSEunchul Kim /* target area */ 114216102edbSEunchul Kim cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h); 114316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITAREA); 114416102edbSEunchul Kim 114516102edbSEunchul Kim /* offset Y(RGB), Cb, Cr */ 114616102edbSEunchul Kim cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) | 114716102edbSEunchul Kim EXYNOS_CIOYOFF_VERTICAL(img_pos.y)); 114816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOYOFF); 114916102edbSEunchul Kim cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) | 115016102edbSEunchul Kim EXYNOS_CIOCBOFF_VERTICAL(img_pos.y)); 115116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCBOFF); 115216102edbSEunchul Kim cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) | 115316102edbSEunchul Kim EXYNOS_CIOCROFF_VERTICAL(img_pos.y)); 115416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCROFF); 115516102edbSEunchul Kim 115616102edbSEunchul Kim return 0; 115716102edbSEunchul Kim } 115816102edbSEunchul Kim 115916102edbSEunchul Kim static int fimc_dst_get_buf_seq(struct fimc_context *ctx) 116016102edbSEunchul Kim { 116116102edbSEunchul Kim u32 cfg, i, buf_num = 0; 116216102edbSEunchul Kim u32 mask = 0x00000001; 116316102edbSEunchul Kim 116416102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIFCNTSEQ); 116516102edbSEunchul Kim 116616102edbSEunchul Kim for (i = 0; i < FIMC_REG_SZ; i++) 116716102edbSEunchul Kim if (cfg & (mask << i)) 116816102edbSEunchul Kim buf_num++; 116916102edbSEunchul Kim 1170cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); 117116102edbSEunchul Kim 117216102edbSEunchul Kim return buf_num; 117316102edbSEunchul Kim } 117416102edbSEunchul Kim 117516102edbSEunchul Kim static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, 117616102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 117716102edbSEunchul Kim { 117816102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 117916102edbSEunchul Kim bool enable; 118016102edbSEunchul Kim u32 cfg; 118116102edbSEunchul Kim u32 mask = 0x00000001 << buf_id; 118216102edbSEunchul Kim int ret = 0; 118316102edbSEunchul Kim 1184cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); 118516102edbSEunchul Kim 118616102edbSEunchul Kim mutex_lock(&ctx->lock); 118716102edbSEunchul Kim 118816102edbSEunchul Kim /* mask register set */ 118916102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIFCNTSEQ); 119016102edbSEunchul Kim 119116102edbSEunchul Kim switch (buf_type) { 119216102edbSEunchul Kim case IPP_BUF_ENQUEUE: 119316102edbSEunchul Kim enable = true; 119416102edbSEunchul Kim break; 119516102edbSEunchul Kim case IPP_BUF_DEQUEUE: 119616102edbSEunchul Kim enable = false; 119716102edbSEunchul Kim break; 119816102edbSEunchul Kim default: 119916102edbSEunchul Kim dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); 120016102edbSEunchul Kim ret = -EINVAL; 120116102edbSEunchul Kim goto err_unlock; 120216102edbSEunchul Kim } 120316102edbSEunchul Kim 120416102edbSEunchul Kim /* sequence id */ 120513a32eb0SEunchul Kim cfg &= ~mask; 120616102edbSEunchul Kim cfg |= (enable << buf_id); 120716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIFCNTSEQ); 120816102edbSEunchul Kim 120916102edbSEunchul Kim /* interrupt enable */ 121016102edbSEunchul Kim if (buf_type == IPP_BUF_ENQUEUE && 121116102edbSEunchul Kim fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START) 121216102edbSEunchul Kim fimc_handle_irq(ctx, true, false, true); 121316102edbSEunchul Kim 121416102edbSEunchul Kim /* interrupt disable */ 121516102edbSEunchul Kim if (buf_type == IPP_BUF_DEQUEUE && 121616102edbSEunchul Kim fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP) 121716102edbSEunchul Kim fimc_handle_irq(ctx, false, false, true); 121816102edbSEunchul Kim 121916102edbSEunchul Kim err_unlock: 122016102edbSEunchul Kim mutex_unlock(&ctx->lock); 122116102edbSEunchul Kim return ret; 122216102edbSEunchul Kim } 122316102edbSEunchul Kim 122416102edbSEunchul Kim static int fimc_dst_set_addr(struct device *dev, 122516102edbSEunchul Kim struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 122616102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 122716102edbSEunchul Kim { 122816102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 122916102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 12307259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 123116102edbSEunchul Kim struct drm_exynos_ipp_property *property; 123216102edbSEunchul Kim struct drm_exynos_ipp_config *config; 123316102edbSEunchul Kim 123416102edbSEunchul Kim if (!c_node) { 123516102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 123616102edbSEunchul Kim return -EINVAL; 123716102edbSEunchul Kim } 123816102edbSEunchul Kim 123916102edbSEunchul Kim property = &c_node->property; 124016102edbSEunchul Kim 1241cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 124216102edbSEunchul Kim property->prop_id, buf_id, buf_type); 124316102edbSEunchul Kim 124416102edbSEunchul Kim if (buf_id > FIMC_MAX_DST) { 124516102edbSEunchul Kim dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 124616102edbSEunchul Kim return -ENOMEM; 124716102edbSEunchul Kim } 124816102edbSEunchul Kim 124916102edbSEunchul Kim /* address register set */ 125016102edbSEunchul Kim switch (buf_type) { 125116102edbSEunchul Kim case IPP_BUF_ENQUEUE: 125216102edbSEunchul Kim config = &property->config[EXYNOS_DRM_OPS_DST]; 125316102edbSEunchul Kim 125416102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 125516102edbSEunchul Kim EXYNOS_CIOYSA(buf_id)); 125616102edbSEunchul Kim 125716102edbSEunchul Kim if (config->fmt == DRM_FORMAT_YVU420) { 125816102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 125916102edbSEunchul Kim EXYNOS_CIOCBSA(buf_id)); 126016102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 126116102edbSEunchul Kim EXYNOS_CIOCRSA(buf_id)); 126216102edbSEunchul Kim } else { 126316102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 126416102edbSEunchul Kim EXYNOS_CIOCBSA(buf_id)); 126516102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 126616102edbSEunchul Kim EXYNOS_CIOCRSA(buf_id)); 126716102edbSEunchul Kim } 126816102edbSEunchul Kim break; 126916102edbSEunchul Kim case IPP_BUF_DEQUEUE: 127016102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIOYSA(buf_id)); 127116102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIOCBSA(buf_id)); 127216102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIOCRSA(buf_id)); 127316102edbSEunchul Kim break; 127416102edbSEunchul Kim default: 127516102edbSEunchul Kim /* bypass */ 127616102edbSEunchul Kim break; 127716102edbSEunchul Kim } 127816102edbSEunchul Kim 127916102edbSEunchul Kim return fimc_dst_set_buf_seq(ctx, buf_id, buf_type); 128016102edbSEunchul Kim } 128116102edbSEunchul Kim 128216102edbSEunchul Kim static struct exynos_drm_ipp_ops fimc_dst_ops = { 128316102edbSEunchul Kim .set_fmt = fimc_dst_set_fmt, 128416102edbSEunchul Kim .set_transf = fimc_dst_set_transf, 128516102edbSEunchul Kim .set_size = fimc_dst_set_size, 128616102edbSEunchul Kim .set_addr = fimc_dst_set_addr, 128716102edbSEunchul Kim }; 128816102edbSEunchul Kim 128916102edbSEunchul Kim static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable) 129016102edbSEunchul Kim { 1291cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]\n", enable); 129216102edbSEunchul Kim 129316102edbSEunchul Kim if (enable) { 1294e5f86839SSylwester Nawrocki clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); 1295e5f86839SSylwester Nawrocki clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); 129616102edbSEunchul Kim ctx->suspended = false; 129716102edbSEunchul Kim } else { 1298e5f86839SSylwester Nawrocki clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); 1299e5f86839SSylwester Nawrocki clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); 130016102edbSEunchul Kim ctx->suspended = true; 130116102edbSEunchul Kim } 130216102edbSEunchul Kim 130316102edbSEunchul Kim return 0; 130416102edbSEunchul Kim } 130516102edbSEunchul Kim 130616102edbSEunchul Kim static irqreturn_t fimc_irq_handler(int irq, void *dev_id) 130716102edbSEunchul Kim { 130816102edbSEunchul Kim struct fimc_context *ctx = dev_id; 130916102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 13107259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 131116102edbSEunchul Kim struct drm_exynos_ipp_event_work *event_work = 131216102edbSEunchul Kim c_node->event_work; 131316102edbSEunchul Kim int buf_id; 131416102edbSEunchul Kim 1315cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id); 131616102edbSEunchul Kim 131716102edbSEunchul Kim fimc_clear_irq(ctx); 131816102edbSEunchul Kim if (fimc_check_ovf(ctx)) 131916102edbSEunchul Kim return IRQ_NONE; 132016102edbSEunchul Kim 132116102edbSEunchul Kim if (!fimc_check_frame_end(ctx)) 132216102edbSEunchul Kim return IRQ_NONE; 132316102edbSEunchul Kim 132416102edbSEunchul Kim buf_id = fimc_get_buf_id(ctx); 132516102edbSEunchul Kim if (buf_id < 0) 132616102edbSEunchul Kim return IRQ_HANDLED; 132716102edbSEunchul Kim 1328cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 132916102edbSEunchul Kim 133016102edbSEunchul Kim if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) { 133116102edbSEunchul Kim DRM_ERROR("failed to dequeue.\n"); 133216102edbSEunchul Kim return IRQ_HANDLED; 133316102edbSEunchul Kim } 133416102edbSEunchul Kim 133516102edbSEunchul Kim event_work->ippdrv = ippdrv; 133616102edbSEunchul Kim event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id; 133716102edbSEunchul Kim queue_work(ippdrv->event_workq, (struct work_struct *)event_work); 133816102edbSEunchul Kim 133916102edbSEunchul Kim return IRQ_HANDLED; 134016102edbSEunchul Kim } 134116102edbSEunchul Kim 134216102edbSEunchul Kim static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) 134316102edbSEunchul Kim { 134416102edbSEunchul Kim struct drm_exynos_ipp_prop_list *prop_list; 134516102edbSEunchul Kim 134616102edbSEunchul Kim prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL); 134716102edbSEunchul Kim if (!prop_list) { 134816102edbSEunchul Kim DRM_ERROR("failed to alloc property list.\n"); 134916102edbSEunchul Kim return -ENOMEM; 135016102edbSEunchul Kim } 135116102edbSEunchul Kim 135216102edbSEunchul Kim prop_list->version = 1; 135316102edbSEunchul Kim prop_list->writeback = 1; 135416102edbSEunchul Kim prop_list->refresh_min = FIMC_REFRESH_MIN; 135516102edbSEunchul Kim prop_list->refresh_max = FIMC_REFRESH_MAX; 135616102edbSEunchul Kim prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) | 135716102edbSEunchul Kim (1 << EXYNOS_DRM_FLIP_VERTICAL) | 135816102edbSEunchul Kim (1 << EXYNOS_DRM_FLIP_HORIZONTAL); 135916102edbSEunchul Kim prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | 136016102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_90) | 136116102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_180) | 136216102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_270); 136316102edbSEunchul Kim prop_list->csc = 1; 136416102edbSEunchul Kim prop_list->crop = 1; 136516102edbSEunchul Kim prop_list->crop_max.hsize = FIMC_CROP_MAX; 136616102edbSEunchul Kim prop_list->crop_max.vsize = FIMC_CROP_MAX; 136716102edbSEunchul Kim prop_list->crop_min.hsize = FIMC_CROP_MIN; 136816102edbSEunchul Kim prop_list->crop_min.vsize = FIMC_CROP_MIN; 136916102edbSEunchul Kim prop_list->scale = 1; 137016102edbSEunchul Kim prop_list->scale_max.hsize = FIMC_SCALE_MAX; 137116102edbSEunchul Kim prop_list->scale_max.vsize = FIMC_SCALE_MAX; 137216102edbSEunchul Kim prop_list->scale_min.hsize = FIMC_SCALE_MIN; 137316102edbSEunchul Kim prop_list->scale_min.vsize = FIMC_SCALE_MIN; 137416102edbSEunchul Kim 137516102edbSEunchul Kim ippdrv->prop_list = prop_list; 137616102edbSEunchul Kim 137716102edbSEunchul Kim return 0; 137816102edbSEunchul Kim } 137916102edbSEunchul Kim 138016102edbSEunchul Kim static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip) 138116102edbSEunchul Kim { 138216102edbSEunchul Kim switch (flip) { 138316102edbSEunchul Kim case EXYNOS_DRM_FLIP_NONE: 138416102edbSEunchul Kim case EXYNOS_DRM_FLIP_VERTICAL: 138516102edbSEunchul Kim case EXYNOS_DRM_FLIP_HORIZONTAL: 13864f21877cSEunchul Kim case EXYNOS_DRM_FLIP_BOTH: 138716102edbSEunchul Kim return true; 138816102edbSEunchul Kim default: 1389cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("invalid flip\n"); 139016102edbSEunchul Kim return false; 139116102edbSEunchul Kim } 139216102edbSEunchul Kim } 139316102edbSEunchul Kim 139416102edbSEunchul Kim static int fimc_ippdrv_check_property(struct device *dev, 139516102edbSEunchul Kim struct drm_exynos_ipp_property *property) 139616102edbSEunchul Kim { 139716102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 139816102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 139916102edbSEunchul Kim struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list; 140016102edbSEunchul Kim struct drm_exynos_ipp_config *config; 140116102edbSEunchul Kim struct drm_exynos_pos *pos; 140216102edbSEunchul Kim struct drm_exynos_sz *sz; 140316102edbSEunchul Kim bool swap; 140416102edbSEunchul Kim int i; 140516102edbSEunchul Kim 140616102edbSEunchul Kim for_each_ipp_ops(i) { 140716102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && 140816102edbSEunchul Kim (property->cmd == IPP_CMD_WB)) 140916102edbSEunchul Kim continue; 141016102edbSEunchul Kim 141116102edbSEunchul Kim config = &property->config[i]; 141216102edbSEunchul Kim pos = &config->pos; 141316102edbSEunchul Kim sz = &config->sz; 141416102edbSEunchul Kim 141516102edbSEunchul Kim /* check for flip */ 141616102edbSEunchul Kim if (!fimc_check_drm_flip(config->flip)) { 141716102edbSEunchul Kim DRM_ERROR("invalid flip.\n"); 141816102edbSEunchul Kim goto err_property; 141916102edbSEunchul Kim } 142016102edbSEunchul Kim 142116102edbSEunchul Kim /* check for degree */ 142216102edbSEunchul Kim switch (config->degree) { 142316102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 142416102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 142516102edbSEunchul Kim swap = true; 142616102edbSEunchul Kim break; 142716102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 142816102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 142916102edbSEunchul Kim swap = false; 143016102edbSEunchul Kim break; 143116102edbSEunchul Kim default: 143216102edbSEunchul Kim DRM_ERROR("invalid degree.\n"); 143316102edbSEunchul Kim goto err_property; 143416102edbSEunchul Kim } 143516102edbSEunchul Kim 143616102edbSEunchul Kim /* check for buffer bound */ 143716102edbSEunchul Kim if ((pos->x + pos->w > sz->hsize) || 143816102edbSEunchul Kim (pos->y + pos->h > sz->vsize)) { 143916102edbSEunchul Kim DRM_ERROR("out of buf bound.\n"); 144016102edbSEunchul Kim goto err_property; 144116102edbSEunchul Kim } 144216102edbSEunchul Kim 144316102edbSEunchul Kim /* check for crop */ 144416102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { 144516102edbSEunchul Kim if (swap) { 144616102edbSEunchul Kim if ((pos->h < pp->crop_min.hsize) || 144716102edbSEunchul Kim (sz->vsize > pp->crop_max.hsize) || 144816102edbSEunchul Kim (pos->w < pp->crop_min.vsize) || 144916102edbSEunchul Kim (sz->hsize > pp->crop_max.vsize)) { 145016102edbSEunchul Kim DRM_ERROR("out of crop size.\n"); 145116102edbSEunchul Kim goto err_property; 145216102edbSEunchul Kim } 145316102edbSEunchul Kim } else { 145416102edbSEunchul Kim if ((pos->w < pp->crop_min.hsize) || 145516102edbSEunchul Kim (sz->hsize > pp->crop_max.hsize) || 145616102edbSEunchul Kim (pos->h < pp->crop_min.vsize) || 145716102edbSEunchul Kim (sz->vsize > pp->crop_max.vsize)) { 145816102edbSEunchul Kim DRM_ERROR("out of crop size.\n"); 145916102edbSEunchul Kim goto err_property; 146016102edbSEunchul Kim } 146116102edbSEunchul Kim } 146216102edbSEunchul Kim } 146316102edbSEunchul Kim 146416102edbSEunchul Kim /* check for scale */ 146516102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { 146616102edbSEunchul Kim if (swap) { 146716102edbSEunchul Kim if ((pos->h < pp->scale_min.hsize) || 146816102edbSEunchul Kim (sz->vsize > pp->scale_max.hsize) || 146916102edbSEunchul Kim (pos->w < pp->scale_min.vsize) || 147016102edbSEunchul Kim (sz->hsize > pp->scale_max.vsize)) { 147116102edbSEunchul Kim DRM_ERROR("out of scale size.\n"); 147216102edbSEunchul Kim goto err_property; 147316102edbSEunchul Kim } 147416102edbSEunchul Kim } else { 147516102edbSEunchul Kim if ((pos->w < pp->scale_min.hsize) || 147616102edbSEunchul Kim (sz->hsize > pp->scale_max.hsize) || 147716102edbSEunchul Kim (pos->h < pp->scale_min.vsize) || 147816102edbSEunchul Kim (sz->vsize > pp->scale_max.vsize)) { 147916102edbSEunchul Kim DRM_ERROR("out of scale size.\n"); 148016102edbSEunchul Kim goto err_property; 148116102edbSEunchul Kim } 148216102edbSEunchul Kim } 148316102edbSEunchul Kim } 148416102edbSEunchul Kim } 148516102edbSEunchul Kim 148616102edbSEunchul Kim return 0; 148716102edbSEunchul Kim 148816102edbSEunchul Kim err_property: 148916102edbSEunchul Kim for_each_ipp_ops(i) { 149016102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && 149116102edbSEunchul Kim (property->cmd == IPP_CMD_WB)) 149216102edbSEunchul Kim continue; 149316102edbSEunchul Kim 149416102edbSEunchul Kim config = &property->config[i]; 149516102edbSEunchul Kim pos = &config->pos; 149616102edbSEunchul Kim sz = &config->sz; 149716102edbSEunchul Kim 149816102edbSEunchul Kim DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", 149916102edbSEunchul Kim i ? "dst" : "src", config->flip, config->degree, 150016102edbSEunchul Kim pos->x, pos->y, pos->w, pos->h, 150116102edbSEunchul Kim sz->hsize, sz->vsize); 150216102edbSEunchul Kim } 150316102edbSEunchul Kim 150416102edbSEunchul Kim return -EINVAL; 150516102edbSEunchul Kim } 150616102edbSEunchul Kim 150716102edbSEunchul Kim static void fimc_clear_addr(struct fimc_context *ctx) 150816102edbSEunchul Kim { 150916102edbSEunchul Kim int i; 151016102edbSEunchul Kim 151116102edbSEunchul Kim for (i = 0; i < FIMC_MAX_SRC; i++) { 151216102edbSEunchul Kim fimc_write(0, EXYNOS_CIIYSA(i)); 151316102edbSEunchul Kim fimc_write(0, EXYNOS_CIICBSA(i)); 151416102edbSEunchul Kim fimc_write(0, EXYNOS_CIICRSA(i)); 151516102edbSEunchul Kim } 151616102edbSEunchul Kim 151716102edbSEunchul Kim for (i = 0; i < FIMC_MAX_DST; i++) { 151816102edbSEunchul Kim fimc_write(0, EXYNOS_CIOYSA(i)); 151916102edbSEunchul Kim fimc_write(0, EXYNOS_CIOCBSA(i)); 152016102edbSEunchul Kim fimc_write(0, EXYNOS_CIOCRSA(i)); 152116102edbSEunchul Kim } 152216102edbSEunchul Kim } 152316102edbSEunchul Kim 152416102edbSEunchul Kim static int fimc_ippdrv_reset(struct device *dev) 152516102edbSEunchul Kim { 152616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 152716102edbSEunchul Kim 152816102edbSEunchul Kim /* reset h/w block */ 1529b5c0b552SJoongMock Shin fimc_sw_reset(ctx); 153016102edbSEunchul Kim 153116102edbSEunchul Kim /* reset scaler capability */ 153216102edbSEunchul Kim memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 153316102edbSEunchul Kim 153416102edbSEunchul Kim fimc_clear_addr(ctx); 153516102edbSEunchul Kim 153616102edbSEunchul Kim return 0; 153716102edbSEunchul Kim } 153816102edbSEunchul Kim 153916102edbSEunchul Kim static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) 154016102edbSEunchul Kim { 154116102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 154216102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 15437259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 154416102edbSEunchul Kim struct drm_exynos_ipp_property *property; 154516102edbSEunchul Kim struct drm_exynos_ipp_config *config; 154616102edbSEunchul Kim struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; 154716102edbSEunchul Kim struct drm_exynos_ipp_set_wb set_wb; 154816102edbSEunchul Kim int ret, i; 154916102edbSEunchul Kim u32 cfg0, cfg1; 155016102edbSEunchul Kim 1551cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("cmd[%d]\n", cmd); 155216102edbSEunchul Kim 155316102edbSEunchul Kim if (!c_node) { 155416102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 155516102edbSEunchul Kim return -EINVAL; 155616102edbSEunchul Kim } 155716102edbSEunchul Kim 155816102edbSEunchul Kim property = &c_node->property; 155916102edbSEunchul Kim 156016102edbSEunchul Kim fimc_handle_irq(ctx, true, false, true); 156116102edbSEunchul Kim 156216102edbSEunchul Kim for_each_ipp_ops(i) { 156316102edbSEunchul Kim config = &property->config[i]; 156416102edbSEunchul Kim img_pos[i] = config->pos; 156516102edbSEunchul Kim } 156616102edbSEunchul Kim 156716102edbSEunchul Kim ret = fimc_set_prescaler(ctx, &ctx->sc, 156816102edbSEunchul Kim &img_pos[EXYNOS_DRM_OPS_SRC], 156916102edbSEunchul Kim &img_pos[EXYNOS_DRM_OPS_DST]); 157016102edbSEunchul Kim if (ret) { 157116102edbSEunchul Kim dev_err(dev, "failed to set precalser.\n"); 157216102edbSEunchul Kim return ret; 157316102edbSEunchul Kim } 157416102edbSEunchul Kim 157516102edbSEunchul Kim /* If set ture, we can save jpeg about screen */ 157616102edbSEunchul Kim fimc_handle_jpeg(ctx, false); 157716102edbSEunchul Kim fimc_set_scaler(ctx, &ctx->sc); 157816102edbSEunchul Kim fimc_set_polarity(ctx, &ctx->pol); 157916102edbSEunchul Kim 158016102edbSEunchul Kim switch (cmd) { 158116102edbSEunchul Kim case IPP_CMD_M2M: 158216102edbSEunchul Kim fimc_set_type_ctrl(ctx, FIMC_WB_NONE); 158316102edbSEunchul Kim fimc_handle_lastend(ctx, false); 158416102edbSEunchul Kim 158516102edbSEunchul Kim /* setup dma */ 158616102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_MSCTRL); 158716102edbSEunchul Kim cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; 158816102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; 158916102edbSEunchul Kim fimc_write(cfg0, EXYNOS_MSCTRL); 159016102edbSEunchul Kim break; 159116102edbSEunchul Kim case IPP_CMD_WB: 159216102edbSEunchul Kim fimc_set_type_ctrl(ctx, FIMC_WB_A); 159316102edbSEunchul Kim fimc_handle_lastend(ctx, true); 159416102edbSEunchul Kim 159516102edbSEunchul Kim /* setup FIMD */ 15965186fc5eSSylwester Nawrocki ret = fimc_set_camblk_fimd0_wb(ctx); 15975186fc5eSSylwester Nawrocki if (ret < 0) { 15985186fc5eSSylwester Nawrocki dev_err(dev, "camblk setup failed.\n"); 15995186fc5eSSylwester Nawrocki return ret; 16005186fc5eSSylwester Nawrocki } 160116102edbSEunchul Kim 160216102edbSEunchul Kim set_wb.enable = 1; 160316102edbSEunchul Kim set_wb.refresh = property->refresh_rate; 160416102edbSEunchul Kim exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 160516102edbSEunchul Kim break; 160616102edbSEunchul Kim case IPP_CMD_OUTPUT: 160716102edbSEunchul Kim default: 160816102edbSEunchul Kim ret = -EINVAL; 160916102edbSEunchul Kim dev_err(dev, "invalid operations.\n"); 161016102edbSEunchul Kim return ret; 161116102edbSEunchul Kim } 161216102edbSEunchul Kim 161316102edbSEunchul Kim /* Reset status */ 161416102edbSEunchul Kim fimc_write(0x0, EXYNOS_CISTATUS); 161516102edbSEunchul Kim 161616102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_CIIMGCPT); 161716102edbSEunchul Kim cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; 161816102edbSEunchul Kim cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; 161916102edbSEunchul Kim 162016102edbSEunchul Kim /* Scaler */ 162116102edbSEunchul Kim cfg1 = fimc_read(EXYNOS_CISCCTRL); 162216102edbSEunchul Kim cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; 162316102edbSEunchul Kim cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | 162416102edbSEunchul Kim EXYNOS_CISCCTRL_SCALERSTART); 162516102edbSEunchul Kim 162616102edbSEunchul Kim fimc_write(cfg1, EXYNOS_CISCCTRL); 162716102edbSEunchul Kim 162816102edbSEunchul Kim /* Enable image capture*/ 162916102edbSEunchul Kim cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; 163016102edbSEunchul Kim fimc_write(cfg0, EXYNOS_CIIMGCPT); 163116102edbSEunchul Kim 163216102edbSEunchul Kim /* Disable frame end irq */ 163316102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_CIGCTRL); 163416102edbSEunchul Kim cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE; 163516102edbSEunchul Kim fimc_write(cfg0, EXYNOS_CIGCTRL); 163616102edbSEunchul Kim 163716102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_CIOCTRL); 163816102edbSEunchul Kim cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK; 163916102edbSEunchul Kim fimc_write(cfg0, EXYNOS_CIOCTRL); 164016102edbSEunchul Kim 164116102edbSEunchul Kim if (cmd == IPP_CMD_M2M) { 164216102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_MSCTRL); 164316102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_ENVID; 164416102edbSEunchul Kim fimc_write(cfg0, EXYNOS_MSCTRL); 164516102edbSEunchul Kim 164616102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_MSCTRL); 164716102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_ENVID; 164816102edbSEunchul Kim fimc_write(cfg0, EXYNOS_MSCTRL); 164916102edbSEunchul Kim } 165016102edbSEunchul Kim 165116102edbSEunchul Kim return 0; 165216102edbSEunchul Kim } 165316102edbSEunchul Kim 165416102edbSEunchul Kim static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) 165516102edbSEunchul Kim { 165616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 165716102edbSEunchul Kim struct drm_exynos_ipp_set_wb set_wb = {0, 0}; 165816102edbSEunchul Kim u32 cfg; 165916102edbSEunchul Kim 1660cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("cmd[%d]\n", cmd); 166116102edbSEunchul Kim 166216102edbSEunchul Kim switch (cmd) { 166316102edbSEunchul Kim case IPP_CMD_M2M: 166416102edbSEunchul Kim /* Source clear */ 166516102edbSEunchul Kim cfg = fimc_read(EXYNOS_MSCTRL); 166616102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_INPUT_MASK; 166716102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_ENVID; 166816102edbSEunchul Kim fimc_write(cfg, EXYNOS_MSCTRL); 166916102edbSEunchul Kim break; 167016102edbSEunchul Kim case IPP_CMD_WB: 167116102edbSEunchul Kim exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 167216102edbSEunchul Kim break; 167316102edbSEunchul Kim case IPP_CMD_OUTPUT: 167416102edbSEunchul Kim default: 167516102edbSEunchul Kim dev_err(dev, "invalid operations.\n"); 167616102edbSEunchul Kim break; 167716102edbSEunchul Kim } 167816102edbSEunchul Kim 167916102edbSEunchul Kim fimc_handle_irq(ctx, false, false, true); 168016102edbSEunchul Kim 168116102edbSEunchul Kim /* reset sequence */ 168216102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIFCNTSEQ); 168316102edbSEunchul Kim 168416102edbSEunchul Kim /* Scaler disable */ 168516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 168616102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_SCALERSTART; 168716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 168816102edbSEunchul Kim 168916102edbSEunchul Kim /* Disable image capture */ 169016102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIIMGCPT); 169116102edbSEunchul Kim cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 169216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIIMGCPT); 169316102edbSEunchul Kim 169416102edbSEunchul Kim /* Enable frame end irq */ 169516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 169616102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE; 169716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 169816102edbSEunchul Kim } 169916102edbSEunchul Kim 1700e5f86839SSylwester Nawrocki static void fimc_put_clocks(struct fimc_context *ctx) 1701e5f86839SSylwester Nawrocki { 1702e5f86839SSylwester Nawrocki int i; 1703e5f86839SSylwester Nawrocki 1704e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) { 1705e5f86839SSylwester Nawrocki if (IS_ERR(ctx->clocks[i])) 1706e5f86839SSylwester Nawrocki continue; 1707e5f86839SSylwester Nawrocki clk_put(ctx->clocks[i]); 1708e5f86839SSylwester Nawrocki ctx->clocks[i] = ERR_PTR(-EINVAL); 1709e5f86839SSylwester Nawrocki } 1710e5f86839SSylwester Nawrocki } 1711e5f86839SSylwester Nawrocki 1712e5f86839SSylwester Nawrocki static int fimc_setup_clocks(struct fimc_context *ctx) 1713e5f86839SSylwester Nawrocki { 1714e5f86839SSylwester Nawrocki struct device *fimc_dev = ctx->ippdrv.dev; 1715e5f86839SSylwester Nawrocki struct device *dev; 1716e5f86839SSylwester Nawrocki int ret, i; 1717e5f86839SSylwester Nawrocki 1718e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) 1719e5f86839SSylwester Nawrocki ctx->clocks[i] = ERR_PTR(-EINVAL); 1720e5f86839SSylwester Nawrocki 1721e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) { 1722e5f86839SSylwester Nawrocki if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B) 1723e5f86839SSylwester Nawrocki dev = fimc_dev->parent; 1724e5f86839SSylwester Nawrocki else 1725e5f86839SSylwester Nawrocki dev = fimc_dev; 1726e5f86839SSylwester Nawrocki 1727e5f86839SSylwester Nawrocki ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); 1728e5f86839SSylwester Nawrocki if (IS_ERR(ctx->clocks[i])) { 1729e5f86839SSylwester Nawrocki if (i >= FIMC_CLK_MUX) 1730e5f86839SSylwester Nawrocki break; 1731e5f86839SSylwester Nawrocki ret = PTR_ERR(ctx->clocks[i]); 1732e5f86839SSylwester Nawrocki dev_err(fimc_dev, "failed to get clock: %s\n", 1733e5f86839SSylwester Nawrocki fimc_clock_names[i]); 1734e5f86839SSylwester Nawrocki goto e_clk_free; 1735e5f86839SSylwester Nawrocki } 1736e5f86839SSylwester Nawrocki } 1737e5f86839SSylwester Nawrocki 1738e5f86839SSylwester Nawrocki /* Optional FIMC LCLK parent clock setting */ 1739e5f86839SSylwester Nawrocki if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) { 1740e5f86839SSylwester Nawrocki ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX], 1741e5f86839SSylwester Nawrocki ctx->clocks[FIMC_CLK_PARENT]); 1742e5f86839SSylwester Nawrocki if (ret < 0) { 1743e5f86839SSylwester Nawrocki dev_err(fimc_dev, "failed to set parent.\n"); 1744e5f86839SSylwester Nawrocki goto e_clk_free; 1745e5f86839SSylwester Nawrocki } 1746e5f86839SSylwester Nawrocki } 1747e5f86839SSylwester Nawrocki 1748e5f86839SSylwester Nawrocki ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency); 1749e5f86839SSylwester Nawrocki if (ret < 0) 1750e5f86839SSylwester Nawrocki goto e_clk_free; 1751e5f86839SSylwester Nawrocki 1752e5f86839SSylwester Nawrocki ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); 1753e5f86839SSylwester Nawrocki if (!ret) 1754e5f86839SSylwester Nawrocki return ret; 1755e5f86839SSylwester Nawrocki e_clk_free: 1756e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 1757e5f86839SSylwester Nawrocki return ret; 1758e5f86839SSylwester Nawrocki } 1759e5f86839SSylwester Nawrocki 17605186fc5eSSylwester Nawrocki static int fimc_parse_dt(struct fimc_context *ctx) 17615186fc5eSSylwester Nawrocki { 17625186fc5eSSylwester Nawrocki struct device_node *node = ctx->ippdrv.dev->of_node; 17635186fc5eSSylwester Nawrocki 17645186fc5eSSylwester Nawrocki /* Handle only devices that support the LCD Writeback data path */ 17655186fc5eSSylwester Nawrocki if (!of_property_read_bool(node, "samsung,lcd-wb")) 17665186fc5eSSylwester Nawrocki return -ENODEV; 17675186fc5eSSylwester Nawrocki 17685186fc5eSSylwester Nawrocki if (of_property_read_u32(node, "clock-frequency", 17695186fc5eSSylwester Nawrocki &ctx->clk_frequency)) 17705186fc5eSSylwester Nawrocki ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY; 17715186fc5eSSylwester Nawrocki 17725186fc5eSSylwester Nawrocki ctx->id = of_alias_get_id(node, "fimc"); 17735186fc5eSSylwester Nawrocki 17745186fc5eSSylwester Nawrocki if (ctx->id < 0) { 17755186fc5eSSylwester Nawrocki dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n"); 17765186fc5eSSylwester Nawrocki return -EINVAL; 17775186fc5eSSylwester Nawrocki } 17785186fc5eSSylwester Nawrocki 17795186fc5eSSylwester Nawrocki return 0; 17805186fc5eSSylwester Nawrocki } 17815186fc5eSSylwester Nawrocki 178256550d94SGreg Kroah-Hartman static int fimc_probe(struct platform_device *pdev) 178316102edbSEunchul Kim { 178416102edbSEunchul Kim struct device *dev = &pdev->dev; 178516102edbSEunchul Kim struct fimc_context *ctx; 178616102edbSEunchul Kim struct resource *res; 178716102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv; 178816102edbSEunchul Kim int ret; 178916102edbSEunchul Kim 17905186fc5eSSylwester Nawrocki if (!dev->of_node) { 17915186fc5eSSylwester Nawrocki dev_err(dev, "device tree node not found.\n"); 17925186fc5eSSylwester Nawrocki return -ENODEV; 179316102edbSEunchul Kim } 179416102edbSEunchul Kim 179516102edbSEunchul Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 179616102edbSEunchul Kim if (!ctx) 179716102edbSEunchul Kim return -ENOMEM; 179816102edbSEunchul Kim 17995186fc5eSSylwester Nawrocki ctx->ippdrv.dev = dev; 18005186fc5eSSylwester Nawrocki 18015186fc5eSSylwester Nawrocki ret = fimc_parse_dt(ctx); 18025186fc5eSSylwester Nawrocki if (ret < 0) 18035186fc5eSSylwester Nawrocki return ret; 18045186fc5eSSylwester Nawrocki 18055186fc5eSSylwester Nawrocki ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 18065186fc5eSSylwester Nawrocki "samsung,sysreg"); 18075186fc5eSSylwester Nawrocki if (IS_ERR(ctx->sysreg)) { 18085186fc5eSSylwester Nawrocki dev_err(dev, "syscon regmap lookup failed.\n"); 18095186fc5eSSylwester Nawrocki return PTR_ERR(ctx->sysreg); 18105186fc5eSSylwester Nawrocki } 18115186fc5eSSylwester Nawrocki 181216102edbSEunchul Kim /* resource memory */ 181316102edbSEunchul Kim ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1814d4ed6025SThierry Reding ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1815d4ed6025SThierry Reding if (IS_ERR(ctx->regs)) 1816d4ed6025SThierry Reding return PTR_ERR(ctx->regs); 181716102edbSEunchul Kim 181816102edbSEunchul Kim /* resource irq */ 181916102edbSEunchul Kim res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 182016102edbSEunchul Kim if (!res) { 182116102edbSEunchul Kim dev_err(dev, "failed to request irq resource.\n"); 182215b3263eSSachin Kamat return -ENOENT; 182316102edbSEunchul Kim } 182416102edbSEunchul Kim 182516102edbSEunchul Kim ctx->irq = res->start; 1826dcb9a7c7SSeung-Woo Kim ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler, 182716102edbSEunchul Kim IRQF_ONESHOT, "drm_fimc", ctx); 182816102edbSEunchul Kim if (ret < 0) { 182916102edbSEunchul Kim dev_err(dev, "failed to request irq.\n"); 183015b3263eSSachin Kamat return ret; 183116102edbSEunchul Kim } 183216102edbSEunchul Kim 1833e5f86839SSylwester Nawrocki ret = fimc_setup_clocks(ctx); 1834e5f86839SSylwester Nawrocki if (ret < 0) 1835dcb9a7c7SSeung-Woo Kim return ret; 183616102edbSEunchul Kim 183716102edbSEunchul Kim ippdrv = &ctx->ippdrv; 183816102edbSEunchul Kim ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops; 183916102edbSEunchul Kim ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops; 184016102edbSEunchul Kim ippdrv->check_property = fimc_ippdrv_check_property; 184116102edbSEunchul Kim ippdrv->reset = fimc_ippdrv_reset; 184216102edbSEunchul Kim ippdrv->start = fimc_ippdrv_start; 184316102edbSEunchul Kim ippdrv->stop = fimc_ippdrv_stop; 184416102edbSEunchul Kim ret = fimc_init_prop_list(ippdrv); 184516102edbSEunchul Kim if (ret < 0) { 184616102edbSEunchul Kim dev_err(dev, "failed to init property list.\n"); 1847e5f86839SSylwester Nawrocki goto err_put_clk; 184816102edbSEunchul Kim } 184916102edbSEunchul Kim 1850cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv); 185116102edbSEunchul Kim 185216102edbSEunchul Kim mutex_init(&ctx->lock); 185316102edbSEunchul Kim platform_set_drvdata(pdev, ctx); 185416102edbSEunchul Kim 185516102edbSEunchul Kim pm_runtime_set_active(dev); 185616102edbSEunchul Kim pm_runtime_enable(dev); 185716102edbSEunchul Kim 185816102edbSEunchul Kim ret = exynos_drm_ippdrv_register(ippdrv); 185916102edbSEunchul Kim if (ret < 0) { 186016102edbSEunchul Kim dev_err(dev, "failed to register drm fimc device.\n"); 1861e5f86839SSylwester Nawrocki goto err_pm_dis; 186216102edbSEunchul Kim } 186316102edbSEunchul Kim 1864d873ab99SSeung-Woo Kim dev_info(dev, "drm fimc registered successfully.\n"); 186516102edbSEunchul Kim 186616102edbSEunchul Kim return 0; 186716102edbSEunchul Kim 1868e5f86839SSylwester Nawrocki err_pm_dis: 186916102edbSEunchul Kim pm_runtime_disable(dev); 1870e5f86839SSylwester Nawrocki err_put_clk: 1871e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 187287acdde5SSachin Kamat 187316102edbSEunchul Kim return ret; 187416102edbSEunchul Kim } 187516102edbSEunchul Kim 187656550d94SGreg Kroah-Hartman static int fimc_remove(struct platform_device *pdev) 187716102edbSEunchul Kim { 187816102edbSEunchul Kim struct device *dev = &pdev->dev; 187916102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 188016102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 188116102edbSEunchul Kim 188216102edbSEunchul Kim exynos_drm_ippdrv_unregister(ippdrv); 188316102edbSEunchul Kim mutex_destroy(&ctx->lock); 188416102edbSEunchul Kim 1885e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 188616102edbSEunchul Kim pm_runtime_set_suspended(dev); 188716102edbSEunchul Kim pm_runtime_disable(dev); 188816102edbSEunchul Kim 188916102edbSEunchul Kim return 0; 189016102edbSEunchul Kim } 189116102edbSEunchul Kim 189216102edbSEunchul Kim #ifdef CONFIG_PM_SLEEP 189316102edbSEunchul Kim static int fimc_suspend(struct device *dev) 189416102edbSEunchul Kim { 189516102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 189616102edbSEunchul Kim 1897cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 189816102edbSEunchul Kim 189916102edbSEunchul Kim if (pm_runtime_suspended(dev)) 190016102edbSEunchul Kim return 0; 190116102edbSEunchul Kim 190216102edbSEunchul Kim return fimc_clk_ctrl(ctx, false); 190316102edbSEunchul Kim } 190416102edbSEunchul Kim 190516102edbSEunchul Kim static int fimc_resume(struct device *dev) 190616102edbSEunchul Kim { 190716102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 190816102edbSEunchul Kim 1909cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 191016102edbSEunchul Kim 191116102edbSEunchul Kim if (!pm_runtime_suspended(dev)) 191216102edbSEunchul Kim return fimc_clk_ctrl(ctx, true); 191316102edbSEunchul Kim 191416102edbSEunchul Kim return 0; 191516102edbSEunchul Kim } 191616102edbSEunchul Kim #endif 191716102edbSEunchul Kim 191816102edbSEunchul Kim #ifdef CONFIG_PM_RUNTIME 191916102edbSEunchul Kim static int fimc_runtime_suspend(struct device *dev) 192016102edbSEunchul Kim { 192116102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 192216102edbSEunchul Kim 1923cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 192416102edbSEunchul Kim 192516102edbSEunchul Kim return fimc_clk_ctrl(ctx, false); 192616102edbSEunchul Kim } 192716102edbSEunchul Kim 192816102edbSEunchul Kim static int fimc_runtime_resume(struct device *dev) 192916102edbSEunchul Kim { 193016102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 193116102edbSEunchul Kim 1932cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 193316102edbSEunchul Kim 193416102edbSEunchul Kim return fimc_clk_ctrl(ctx, true); 193516102edbSEunchul Kim } 193616102edbSEunchul Kim #endif 193716102edbSEunchul Kim 193816102edbSEunchul Kim static const struct dev_pm_ops fimc_pm_ops = { 193916102edbSEunchul Kim SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) 194016102edbSEunchul Kim SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) 194116102edbSEunchul Kim }; 194216102edbSEunchul Kim 19435186fc5eSSylwester Nawrocki static const struct of_device_id fimc_of_match[] = { 19445186fc5eSSylwester Nawrocki { .compatible = "samsung,exynos4210-fimc" }, 19455186fc5eSSylwester Nawrocki { .compatible = "samsung,exynos4212-fimc" }, 19465186fc5eSSylwester Nawrocki { }, 19475186fc5eSSylwester Nawrocki }; 19485186fc5eSSylwester Nawrocki 194916102edbSEunchul Kim struct platform_driver fimc_driver = { 195016102edbSEunchul Kim .probe = fimc_probe, 195156550d94SGreg Kroah-Hartman .remove = fimc_remove, 195216102edbSEunchul Kim .driver = { 19535186fc5eSSylwester Nawrocki .of_match_table = fimc_of_match, 195416102edbSEunchul Kim .name = "exynos-drm-fimc", 195516102edbSEunchul Kim .owner = THIS_MODULE, 195616102edbSEunchul Kim .pm = &fimc_pm_ops, 195716102edbSEunchul Kim }, 195816102edbSEunchul Kim }; 195916102edbSEunchul Kim 1960