116102edbSEunchul Kim /* 216102edbSEunchul Kim * Copyright (C) 2012 Samsung Electronics Co.Ltd 316102edbSEunchul Kim * Authors: 416102edbSEunchul Kim * Eunchul Kim <chulspro.kim@samsung.com> 516102edbSEunchul Kim * Jinyoung Jeon <jy0.jeon@samsung.com> 616102edbSEunchul Kim * Sangmin Lee <lsmin.lee@samsung.com> 716102edbSEunchul Kim * 816102edbSEunchul Kim * This program is free software; you can redistribute it and/or modify it 916102edbSEunchul Kim * under the terms of the GNU General Public License as published by the 1016102edbSEunchul Kim * Free Software Foundation; either version 2 of the License, or (at your 1116102edbSEunchul Kim * option) any later version. 1216102edbSEunchul Kim * 1316102edbSEunchul Kim */ 1416102edbSEunchul Kim #include <linux/kernel.h> 1516102edbSEunchul Kim #include <linux/platform_device.h> 16a3ad6976SSeung-Woo Kim #include <linux/mfd/syscon.h> 175186fc5eSSylwester Nawrocki #include <linux/regmap.h> 1816102edbSEunchul Kim #include <linux/clk.h> 1916102edbSEunchul Kim #include <linux/pm_runtime.h> 203f1c781dSSachin Kamat #include <linux/of.h> 2116102edbSEunchul Kim 2216102edbSEunchul Kim #include <drm/drmP.h> 2316102edbSEunchul Kim #include <drm/exynos_drm.h> 2416102edbSEunchul Kim #include "regs-fimc.h" 25e30655d0SMark Brown #include "exynos_drm_drv.h" 2616102edbSEunchul Kim #include "exynos_drm_ipp.h" 2716102edbSEunchul Kim #include "exynos_drm_fimc.h" 2816102edbSEunchul Kim 2916102edbSEunchul Kim /* 306fe891f6SEunchul Kim * FIMC stands for Fully Interactive Mobile Camera and 3116102edbSEunchul Kim * supports image scaler/rotator and input/output DMA operations. 3216102edbSEunchul Kim * input DMA reads image data from the memory. 3316102edbSEunchul Kim * output DMA writes image data to memory. 3416102edbSEunchul Kim * FIMC supports image rotation and image effect functions. 3516102edbSEunchul Kim * 3616102edbSEunchul Kim * M2M operation : supports crop/scale/rotation/csc so on. 3716102edbSEunchul Kim * Memory ----> FIMC H/W ----> Memory. 3816102edbSEunchul Kim * Writeback operation : supports cloned screen with FIMD. 3916102edbSEunchul Kim * FIMD ----> FIMC H/W ----> Memory. 4016102edbSEunchul Kim * Output operation : supports direct display using local path. 4116102edbSEunchul Kim * Memory ----> FIMC H/W ----> FIMD. 4216102edbSEunchul Kim */ 4316102edbSEunchul Kim 4416102edbSEunchul Kim /* 4516102edbSEunchul Kim * TODO 4616102edbSEunchul Kim * 1. check suspend/resume api if needed. 4716102edbSEunchul Kim * 2. need to check use case platform_device_id. 4816102edbSEunchul Kim * 3. check src/dst size with, height. 4916102edbSEunchul Kim * 4. added check_prepare api for right register. 5016102edbSEunchul Kim * 5. need to add supported list in prop_list. 5116102edbSEunchul Kim * 6. check prescaler/scaler optimization. 5216102edbSEunchul Kim */ 5316102edbSEunchul Kim 5416102edbSEunchul Kim #define FIMC_MAX_DEVS 4 5516102edbSEunchul Kim #define FIMC_MAX_SRC 2 5616102edbSEunchul Kim #define FIMC_MAX_DST 32 5716102edbSEunchul Kim #define FIMC_SHFACTOR 10 5816102edbSEunchul Kim #define FIMC_BUF_STOP 1 5916102edbSEunchul Kim #define FIMC_BUF_START 2 6016102edbSEunchul Kim #define FIMC_REG_SZ 32 6116102edbSEunchul Kim #define FIMC_WIDTH_ITU_709 1280 6216102edbSEunchul Kim #define FIMC_REFRESH_MAX 60 6316102edbSEunchul Kim #define FIMC_REFRESH_MIN 12 6416102edbSEunchul Kim #define FIMC_CROP_MAX 8192 6516102edbSEunchul Kim #define FIMC_CROP_MIN 32 6616102edbSEunchul Kim #define FIMC_SCALE_MAX 4224 6716102edbSEunchul Kim #define FIMC_SCALE_MIN 32 6816102edbSEunchul Kim 6916102edbSEunchul Kim #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) 7016102edbSEunchul Kim #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ 7116102edbSEunchul Kim struct fimc_context, ippdrv); 7216102edbSEunchul Kim enum fimc_wb { 7316102edbSEunchul Kim FIMC_WB_NONE, 7416102edbSEunchul Kim FIMC_WB_A, 7516102edbSEunchul Kim FIMC_WB_B, 7616102edbSEunchul Kim }; 7716102edbSEunchul Kim 78e5f86839SSylwester Nawrocki enum { 79e5f86839SSylwester Nawrocki FIMC_CLK_LCLK, 80e5f86839SSylwester Nawrocki FIMC_CLK_GATE, 81e5f86839SSylwester Nawrocki FIMC_CLK_WB_A, 82e5f86839SSylwester Nawrocki FIMC_CLK_WB_B, 83e5f86839SSylwester Nawrocki FIMC_CLK_MUX, 84e5f86839SSylwester Nawrocki FIMC_CLK_PARENT, 85e5f86839SSylwester Nawrocki FIMC_CLKS_MAX 86e5f86839SSylwester Nawrocki }; 87e5f86839SSylwester Nawrocki 88e5f86839SSylwester Nawrocki static const char * const fimc_clock_names[] = { 89e5f86839SSylwester Nawrocki [FIMC_CLK_LCLK] = "sclk_fimc", 90e5f86839SSylwester Nawrocki [FIMC_CLK_GATE] = "fimc", 91e5f86839SSylwester Nawrocki [FIMC_CLK_WB_A] = "pxl_async0", 92e5f86839SSylwester Nawrocki [FIMC_CLK_WB_B] = "pxl_async1", 93e5f86839SSylwester Nawrocki [FIMC_CLK_MUX] = "mux", 94e5f86839SSylwester Nawrocki [FIMC_CLK_PARENT] = "parent", 95e5f86839SSylwester Nawrocki }; 96e5f86839SSylwester Nawrocki 97e5f86839SSylwester Nawrocki #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL 98e5f86839SSylwester Nawrocki 9916102edbSEunchul Kim /* 10016102edbSEunchul Kim * A structure of scaler. 10116102edbSEunchul Kim * 10216102edbSEunchul Kim * @range: narrow, wide. 10316102edbSEunchul Kim * @bypass: unused scaler path. 10416102edbSEunchul Kim * @up_h: horizontal scale up. 10516102edbSEunchul Kim * @up_v: vertical scale up. 10616102edbSEunchul Kim * @hratio: horizontal ratio. 10716102edbSEunchul Kim * @vratio: vertical ratio. 10816102edbSEunchul Kim */ 10916102edbSEunchul Kim struct fimc_scaler { 11016102edbSEunchul Kim bool range; 11116102edbSEunchul Kim bool bypass; 11216102edbSEunchul Kim bool up_h; 11316102edbSEunchul Kim bool up_v; 11416102edbSEunchul Kim u32 hratio; 11516102edbSEunchul Kim u32 vratio; 11616102edbSEunchul Kim }; 11716102edbSEunchul Kim 11816102edbSEunchul Kim /* 11916102edbSEunchul Kim * A structure of scaler capability. 12016102edbSEunchul Kim * 12116102edbSEunchul Kim * find user manual table 43-1. 12216102edbSEunchul Kim * @in_hori: scaler input horizontal size. 12316102edbSEunchul Kim * @bypass: scaler bypass mode. 12416102edbSEunchul Kim * @dst_h_wo_rot: target horizontal size without output rotation. 12516102edbSEunchul Kim * @dst_h_rot: target horizontal size with output rotation. 12616102edbSEunchul Kim * @rl_w_wo_rot: real width without input rotation. 12716102edbSEunchul Kim * @rl_h_rot: real height without output rotation. 12816102edbSEunchul Kim */ 12916102edbSEunchul Kim struct fimc_capability { 13016102edbSEunchul Kim /* scaler */ 13116102edbSEunchul Kim u32 in_hori; 13216102edbSEunchul Kim u32 bypass; 13316102edbSEunchul Kim /* output rotator */ 13416102edbSEunchul Kim u32 dst_h_wo_rot; 13516102edbSEunchul Kim u32 dst_h_rot; 13616102edbSEunchul Kim /* input rotator */ 13716102edbSEunchul Kim u32 rl_w_wo_rot; 13816102edbSEunchul Kim u32 rl_h_rot; 13916102edbSEunchul Kim }; 14016102edbSEunchul Kim 14116102edbSEunchul Kim /* 14216102edbSEunchul Kim * A structure of fimc context. 14316102edbSEunchul Kim * 14416102edbSEunchul Kim * @ippdrv: prepare initialization using ippdrv. 14516102edbSEunchul Kim * @regs_res: register resources. 14616102edbSEunchul Kim * @regs: memory mapped io registers. 14716102edbSEunchul Kim * @lock: locking of operations. 148e5f86839SSylwester Nawrocki * @clocks: fimc clocks. 149e5f86839SSylwester Nawrocki * @clk_frequency: LCLK clock frequency. 1505186fc5eSSylwester Nawrocki * @sysreg: handle to SYSREG block regmap. 15116102edbSEunchul Kim * @sc: scaler infomations. 15216102edbSEunchul Kim * @pol: porarity of writeback. 15316102edbSEunchul Kim * @id: fimc id. 15416102edbSEunchul Kim * @irq: irq number. 15516102edbSEunchul Kim * @suspended: qos operations. 15616102edbSEunchul Kim */ 15716102edbSEunchul Kim struct fimc_context { 15816102edbSEunchul Kim struct exynos_drm_ippdrv ippdrv; 15916102edbSEunchul Kim struct resource *regs_res; 16016102edbSEunchul Kim void __iomem *regs; 16116102edbSEunchul Kim struct mutex lock; 162e5f86839SSylwester Nawrocki struct clk *clocks[FIMC_CLKS_MAX]; 163e5f86839SSylwester Nawrocki u32 clk_frequency; 1645186fc5eSSylwester Nawrocki struct regmap *sysreg; 16516102edbSEunchul Kim struct fimc_scaler sc; 16616102edbSEunchul Kim struct exynos_drm_ipp_pol pol; 16716102edbSEunchul Kim int id; 16816102edbSEunchul Kim int irq; 16916102edbSEunchul Kim bool suspended; 17016102edbSEunchul Kim }; 17116102edbSEunchul Kim 172acd8afa8SAndrzej Hajda static u32 fimc_read(struct fimc_context *ctx, u32 reg) 173acd8afa8SAndrzej Hajda { 174acd8afa8SAndrzej Hajda return readl(ctx->regs + reg); 175acd8afa8SAndrzej Hajda } 176acd8afa8SAndrzej Hajda 177acd8afa8SAndrzej Hajda static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg) 178acd8afa8SAndrzej Hajda { 179acd8afa8SAndrzej Hajda writel(val, ctx->regs + reg); 180acd8afa8SAndrzej Hajda } 181acd8afa8SAndrzej Hajda 182acd8afa8SAndrzej Hajda static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits) 183acd8afa8SAndrzej Hajda { 184acd8afa8SAndrzej Hajda void __iomem *r = ctx->regs + reg; 185acd8afa8SAndrzej Hajda 186acd8afa8SAndrzej Hajda writel(readl(r) | bits, r); 187acd8afa8SAndrzej Hajda } 188acd8afa8SAndrzej Hajda 189acd8afa8SAndrzej Hajda static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits) 190acd8afa8SAndrzej Hajda { 191acd8afa8SAndrzej Hajda void __iomem *r = ctx->regs + reg; 192acd8afa8SAndrzej Hajda 193acd8afa8SAndrzej Hajda writel(readl(r) & ~bits, r); 194acd8afa8SAndrzej Hajda } 195acd8afa8SAndrzej Hajda 196b5c0b552SJoongMock Shin static void fimc_sw_reset(struct fimc_context *ctx) 19716102edbSEunchul Kim { 19816102edbSEunchul Kim u32 cfg; 19916102edbSEunchul Kim 200e39d5ce1SJinyoung Jeon /* stop dma operation */ 201acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CISTATUS); 202acd8afa8SAndrzej Hajda if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) 203acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); 20416102edbSEunchul Kim 205acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT); 20616102edbSEunchul Kim 207e39d5ce1SJinyoung Jeon /* disable image capture */ 208acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CIIMGCPT, 209acd8afa8SAndrzej Hajda EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 210e39d5ce1SJinyoung Jeon 21116102edbSEunchul Kim /* s/w reset */ 212acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST); 21316102edbSEunchul Kim 21416102edbSEunchul Kim /* s/w reset complete */ 215acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST); 21616102edbSEunchul Kim 21716102edbSEunchul Kim /* reset sequence */ 218acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ); 21916102edbSEunchul Kim } 22016102edbSEunchul Kim 2215186fc5eSSylwester Nawrocki static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx) 22216102edbSEunchul Kim { 2235186fc5eSSylwester Nawrocki return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK, 2245186fc5eSSylwester Nawrocki SYSREG_FIMD0WB_DEST_MASK, 2255186fc5eSSylwester Nawrocki ctx->id << SYSREG_FIMD0WB_DEST_SHIFT); 22616102edbSEunchul Kim } 22716102edbSEunchul Kim 22816102edbSEunchul Kim static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb) 22916102edbSEunchul Kim { 23016102edbSEunchul Kim u32 cfg; 23116102edbSEunchul Kim 232cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("wb[%d]\n", wb); 23316102edbSEunchul Kim 234acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 23516102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | 23616102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_ITU_MASK | 23716102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_MIPI_MASK | 23816102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_FIMC_MASK | 23916102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_MASK | 24016102edbSEunchul Kim EXYNOS_CIGCTRL_SELWRITEBACK_MASK); 24116102edbSEunchul Kim 24216102edbSEunchul Kim switch (wb) { 24316102edbSEunchul Kim case FIMC_WB_A: 24416102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A | 24516102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 24616102edbSEunchul Kim break; 24716102edbSEunchul Kim case FIMC_WB_B: 24816102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B | 24916102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 25016102edbSEunchul Kim break; 25116102edbSEunchul Kim case FIMC_WB_NONE: 25216102edbSEunchul Kim default: 25316102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | 25416102edbSEunchul Kim EXYNOS_CIGCTRL_SELWRITEBACK_A | 25516102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_MIPI_A | 25616102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_FIMC_ITU); 25716102edbSEunchul Kim break; 25816102edbSEunchul Kim } 25916102edbSEunchul Kim 260acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 26116102edbSEunchul Kim } 26216102edbSEunchul Kim 26316102edbSEunchul Kim static void fimc_set_polarity(struct fimc_context *ctx, 26416102edbSEunchul Kim struct exynos_drm_ipp_pol *pol) 26516102edbSEunchul Kim { 26616102edbSEunchul Kim u32 cfg; 26716102edbSEunchul Kim 268cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n", 269cbc4c33dSYoungJun Cho pol->inv_pclk, pol->inv_vsync); 270cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n", 271cbc4c33dSYoungJun Cho pol->inv_href, pol->inv_hsync); 27216102edbSEunchul Kim 273acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 27416102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC | 27516102edbSEunchul Kim EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC); 27616102edbSEunchul Kim 27716102edbSEunchul Kim if (pol->inv_pclk) 27816102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLPCLK; 27916102edbSEunchul Kim if (pol->inv_vsync) 28016102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC; 28116102edbSEunchul Kim if (pol->inv_href) 28216102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLHREF; 28316102edbSEunchul Kim if (pol->inv_hsync) 28416102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC; 28516102edbSEunchul Kim 286acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 28716102edbSEunchul Kim } 28816102edbSEunchul Kim 28916102edbSEunchul Kim static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) 29016102edbSEunchul Kim { 29116102edbSEunchul Kim u32 cfg; 29216102edbSEunchul Kim 293cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]\n", enable); 29416102edbSEunchul Kim 295acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 29616102edbSEunchul Kim if (enable) 29716102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CAM_JPEG; 29816102edbSEunchul Kim else 29916102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG; 30016102edbSEunchul Kim 301acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 30216102edbSEunchul Kim } 30316102edbSEunchul Kim 3048b4609cdSAndrzej Hajda static void fimc_mask_irq(struct fimc_context *ctx, bool enable) 30516102edbSEunchul Kim { 30616102edbSEunchul Kim u32 cfg; 30716102edbSEunchul Kim 3088b4609cdSAndrzej Hajda DRM_DEBUG_KMS("enable[%d]\n", enable); 30916102edbSEunchul Kim 310acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 31116102edbSEunchul Kim if (enable) { 3128b4609cdSAndrzej Hajda cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN; 3138b4609cdSAndrzej Hajda cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL; 31416102edbSEunchul Kim } else 3158b4609cdSAndrzej Hajda cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE; 316acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 31716102edbSEunchul Kim } 31816102edbSEunchul Kim 31916102edbSEunchul Kim static void fimc_clear_irq(struct fimc_context *ctx) 32016102edbSEunchul Kim { 321acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR); 32216102edbSEunchul Kim } 32316102edbSEunchul Kim 32416102edbSEunchul Kim static bool fimc_check_ovf(struct fimc_context *ctx) 32516102edbSEunchul Kim { 32616102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 327acd8afa8SAndrzej Hajda u32 status, flag; 32816102edbSEunchul Kim 329acd8afa8SAndrzej Hajda status = fimc_read(ctx, EXYNOS_CISTATUS); 33016102edbSEunchul Kim flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB | 33116102edbSEunchul Kim EXYNOS_CISTATUS_OVFICR; 33216102edbSEunchul Kim 333cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("flag[0x%x]\n", flag); 33416102edbSEunchul Kim 33516102edbSEunchul Kim if (status & flag) { 336acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_CIWDOFST, 337acd8afa8SAndrzej Hajda EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 33816102edbSEunchul Kim EXYNOS_CIWDOFST_CLROVFICR); 339acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CIWDOFST, 340acd8afa8SAndrzej Hajda EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 34116102edbSEunchul Kim EXYNOS_CIWDOFST_CLROVFICR); 34216102edbSEunchul Kim 34377d84ff8SMasanari Iida dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n", 34416102edbSEunchul Kim ctx->id, status); 34516102edbSEunchul Kim return true; 34616102edbSEunchul Kim } 34716102edbSEunchul Kim 34816102edbSEunchul Kim return false; 34916102edbSEunchul Kim } 35016102edbSEunchul Kim 35116102edbSEunchul Kim static bool fimc_check_frame_end(struct fimc_context *ctx) 35216102edbSEunchul Kim { 35316102edbSEunchul Kim u32 cfg; 35416102edbSEunchul Kim 355acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CISTATUS); 35616102edbSEunchul Kim 357cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("cfg[0x%x]\n", cfg); 35816102edbSEunchul Kim 35916102edbSEunchul Kim if (!(cfg & EXYNOS_CISTATUS_FRAMEEND)) 36016102edbSEunchul Kim return false; 36116102edbSEunchul Kim 36216102edbSEunchul Kim cfg &= ~(EXYNOS_CISTATUS_FRAMEEND); 363acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISTATUS); 36416102edbSEunchul Kim 36516102edbSEunchul Kim return true; 36616102edbSEunchul Kim } 36716102edbSEunchul Kim 36816102edbSEunchul Kim static int fimc_get_buf_id(struct fimc_context *ctx) 36916102edbSEunchul Kim { 37016102edbSEunchul Kim u32 cfg; 37116102edbSEunchul Kim int frame_cnt, buf_id; 37216102edbSEunchul Kim 373acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CISTATUS2); 37416102edbSEunchul Kim frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg); 37516102edbSEunchul Kim 37616102edbSEunchul Kim if (frame_cnt == 0) 37716102edbSEunchul Kim frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg); 37816102edbSEunchul Kim 379cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("present[%d]before[%d]\n", 38016102edbSEunchul Kim EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg), 38116102edbSEunchul Kim EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg)); 38216102edbSEunchul Kim 38316102edbSEunchul Kim if (frame_cnt == 0) { 38416102edbSEunchul Kim DRM_ERROR("failed to get frame count.\n"); 38516102edbSEunchul Kim return -EIO; 38616102edbSEunchul Kim } 38716102edbSEunchul Kim 38816102edbSEunchul Kim buf_id = frame_cnt - 1; 389cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 39016102edbSEunchul Kim 39116102edbSEunchul Kim return buf_id; 39216102edbSEunchul Kim } 39316102edbSEunchul Kim 39416102edbSEunchul Kim static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) 39516102edbSEunchul Kim { 39616102edbSEunchul Kim u32 cfg; 39716102edbSEunchul Kim 398cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]\n", enable); 39916102edbSEunchul Kim 400acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIOCTRL); 40116102edbSEunchul Kim if (enable) 40216102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_LASTENDEN; 40316102edbSEunchul Kim else 40416102edbSEunchul Kim cfg &= ~EXYNOS_CIOCTRL_LASTENDEN; 40516102edbSEunchul Kim 406acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIOCTRL); 40716102edbSEunchul Kim } 40816102edbSEunchul Kim 40916102edbSEunchul Kim 41016102edbSEunchul Kim static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) 41116102edbSEunchul Kim { 41216102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 41316102edbSEunchul Kim u32 cfg; 41416102edbSEunchul Kim 415cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 41616102edbSEunchul Kim 41716102edbSEunchul Kim /* RGB */ 418acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CISCCTRL); 41916102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK; 42016102edbSEunchul Kim 42116102edbSEunchul Kim switch (fmt) { 42216102edbSEunchul Kim case DRM_FORMAT_RGB565: 42316102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565; 424acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 42516102edbSEunchul Kim return 0; 42616102edbSEunchul Kim case DRM_FORMAT_RGB888: 42716102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 42816102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888; 429acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 43016102edbSEunchul Kim return 0; 43116102edbSEunchul Kim default: 43216102edbSEunchul Kim /* bypass */ 43316102edbSEunchul Kim break; 43416102edbSEunchul Kim } 43516102edbSEunchul Kim 43616102edbSEunchul Kim /* YUV */ 437acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_MSCTRL); 43816102edbSEunchul Kim cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK | 43916102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE | 44016102edbSEunchul Kim EXYNOS_MSCTRL_ORDER422_YCBYCR); 44116102edbSEunchul Kim 44216102edbSEunchul Kim switch (fmt) { 44316102edbSEunchul Kim case DRM_FORMAT_YUYV: 44416102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR; 44516102edbSEunchul Kim break; 44616102edbSEunchul Kim case DRM_FORMAT_YVYU: 44716102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB; 44816102edbSEunchul Kim break; 44916102edbSEunchul Kim case DRM_FORMAT_UYVY: 45016102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY; 45116102edbSEunchul Kim break; 45216102edbSEunchul Kim case DRM_FORMAT_VYUY: 45316102edbSEunchul Kim case DRM_FORMAT_YUV444: 45416102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY; 45516102edbSEunchul Kim break; 45616102edbSEunchul Kim case DRM_FORMAT_NV21: 45716102edbSEunchul Kim case DRM_FORMAT_NV61: 45816102edbSEunchul Kim cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB | 45916102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE); 46016102edbSEunchul Kim break; 46116102edbSEunchul Kim case DRM_FORMAT_YUV422: 46216102edbSEunchul Kim case DRM_FORMAT_YUV420: 46316102edbSEunchul Kim case DRM_FORMAT_YVU420: 46416102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE; 46516102edbSEunchul Kim break; 46616102edbSEunchul Kim case DRM_FORMAT_NV12: 46716102edbSEunchul Kim case DRM_FORMAT_NV12MT: 46816102edbSEunchul Kim case DRM_FORMAT_NV16: 46916102edbSEunchul Kim cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR | 47016102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE); 47116102edbSEunchul Kim break; 47216102edbSEunchul Kim default: 47316102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt); 47416102edbSEunchul Kim return -EINVAL; 47516102edbSEunchul Kim } 47616102edbSEunchul Kim 477acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_MSCTRL); 47816102edbSEunchul Kim 47916102edbSEunchul Kim return 0; 48016102edbSEunchul Kim } 48116102edbSEunchul Kim 48216102edbSEunchul Kim static int fimc_src_set_fmt(struct device *dev, u32 fmt) 48316102edbSEunchul Kim { 48416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 48516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 48616102edbSEunchul Kim u32 cfg; 48716102edbSEunchul Kim 488cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 48916102edbSEunchul Kim 490acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_MSCTRL); 49116102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB; 49216102edbSEunchul Kim 49316102edbSEunchul Kim switch (fmt) { 49416102edbSEunchul Kim case DRM_FORMAT_RGB565: 49516102edbSEunchul Kim case DRM_FORMAT_RGB888: 49616102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 49716102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_RGB; 49816102edbSEunchul Kim break; 49916102edbSEunchul Kim case DRM_FORMAT_YUV444: 50016102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 50116102edbSEunchul Kim break; 50216102edbSEunchul Kim case DRM_FORMAT_YUYV: 50316102edbSEunchul Kim case DRM_FORMAT_YVYU: 50416102edbSEunchul Kim case DRM_FORMAT_UYVY: 50516102edbSEunchul Kim case DRM_FORMAT_VYUY: 50616102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE; 50716102edbSEunchul Kim break; 50816102edbSEunchul Kim case DRM_FORMAT_NV16: 50916102edbSEunchul Kim case DRM_FORMAT_NV61: 51016102edbSEunchul Kim case DRM_FORMAT_YUV422: 51116102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422; 51216102edbSEunchul Kim break; 51316102edbSEunchul Kim case DRM_FORMAT_YUV420: 51416102edbSEunchul Kim case DRM_FORMAT_YVU420: 51516102edbSEunchul Kim case DRM_FORMAT_NV12: 51616102edbSEunchul Kim case DRM_FORMAT_NV21: 51716102edbSEunchul Kim case DRM_FORMAT_NV12MT: 51816102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 51916102edbSEunchul Kim break; 52016102edbSEunchul Kim default: 52116102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt); 52216102edbSEunchul Kim return -EINVAL; 52316102edbSEunchul Kim } 52416102edbSEunchul Kim 525acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_MSCTRL); 52616102edbSEunchul Kim 527acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM); 52816102edbSEunchul Kim cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK; 52916102edbSEunchul Kim 53016102edbSEunchul Kim if (fmt == DRM_FORMAT_NV12MT) 53116102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32; 53216102edbSEunchul Kim else 53316102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR; 53416102edbSEunchul Kim 535acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM); 53616102edbSEunchul Kim 53716102edbSEunchul Kim return fimc_src_set_fmt_order(ctx, fmt); 53816102edbSEunchul Kim } 53916102edbSEunchul Kim 54016102edbSEunchul Kim static int fimc_src_set_transf(struct device *dev, 54116102edbSEunchul Kim enum drm_exynos_degree degree, 54216102edbSEunchul Kim enum drm_exynos_flip flip, bool *swap) 54316102edbSEunchul Kim { 54416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 54516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 54616102edbSEunchul Kim u32 cfg1, cfg2; 54716102edbSEunchul Kim 548cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 54916102edbSEunchul Kim 550acd8afa8SAndrzej Hajda cfg1 = fimc_read(ctx, EXYNOS_MSCTRL); 55116102edbSEunchul Kim cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | 55216102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 55316102edbSEunchul Kim 554acd8afa8SAndrzej Hajda cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT); 55516102edbSEunchul Kim cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 55616102edbSEunchul Kim 55716102edbSEunchul Kim switch (degree) { 55816102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 55916102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 56016102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 56116102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 56216102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 56316102edbSEunchul Kim break; 56416102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 56516102edbSEunchul Kim cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 56616102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 56716102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 56816102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 56916102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 57016102edbSEunchul Kim break; 57116102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 57216102edbSEunchul Kim cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 57316102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 57416102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 57516102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 57616102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 57716102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 57816102edbSEunchul Kim break; 57916102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 58016102edbSEunchul Kim cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 58116102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 58216102edbSEunchul Kim cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 58316102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 58416102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 58516102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 58616102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 58716102edbSEunchul Kim break; 58816102edbSEunchul Kim default: 58916102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 59016102edbSEunchul Kim return -EINVAL; 59116102edbSEunchul Kim } 59216102edbSEunchul Kim 593acd8afa8SAndrzej Hajda fimc_write(ctx, cfg1, EXYNOS_MSCTRL); 594acd8afa8SAndrzej Hajda fimc_write(ctx, cfg2, EXYNOS_CITRGFMT); 59516102edbSEunchul Kim *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0; 59616102edbSEunchul Kim 59716102edbSEunchul Kim return 0; 59816102edbSEunchul Kim } 59916102edbSEunchul Kim 60016102edbSEunchul Kim static int fimc_set_window(struct fimc_context *ctx, 60116102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 60216102edbSEunchul Kim { 60316102edbSEunchul Kim u32 cfg, h1, h2, v1, v2; 60416102edbSEunchul Kim 60516102edbSEunchul Kim /* cropped image */ 60616102edbSEunchul Kim h1 = pos->x; 60716102edbSEunchul Kim h2 = sz->hsize - pos->w - pos->x; 60816102edbSEunchul Kim v1 = pos->y; 60916102edbSEunchul Kim v2 = sz->vsize - pos->h - pos->y; 61016102edbSEunchul Kim 611cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n", 612cbc4c33dSYoungJun Cho pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize); 613cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2); 61416102edbSEunchul Kim 61516102edbSEunchul Kim /* 61616102edbSEunchul Kim * set window offset 1, 2 size 61716102edbSEunchul Kim * check figure 43-21 in user manual 61816102edbSEunchul Kim */ 619acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIWDOFST); 62016102edbSEunchul Kim cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK | 62116102edbSEunchul Kim EXYNOS_CIWDOFST_WINVEROFST_MASK); 62216102edbSEunchul Kim cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) | 62316102edbSEunchul Kim EXYNOS_CIWDOFST_WINVEROFST(v1)); 62416102edbSEunchul Kim cfg |= EXYNOS_CIWDOFST_WINOFSEN; 625acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIWDOFST); 62616102edbSEunchul Kim 62716102edbSEunchul Kim cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) | 62816102edbSEunchul Kim EXYNOS_CIWDOFST2_WINVEROFST2(v2)); 629acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIWDOFST2); 63016102edbSEunchul Kim 63116102edbSEunchul Kim return 0; 63216102edbSEunchul Kim } 63316102edbSEunchul Kim 63416102edbSEunchul Kim static int fimc_src_set_size(struct device *dev, int swap, 63516102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 63616102edbSEunchul Kim { 63716102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 63816102edbSEunchul Kim struct drm_exynos_pos img_pos = *pos; 63916102edbSEunchul Kim struct drm_exynos_sz img_sz = *sz; 64016102edbSEunchul Kim u32 cfg; 64116102edbSEunchul Kim 642cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n", 643cbc4c33dSYoungJun Cho swap, sz->hsize, sz->vsize); 64416102edbSEunchul Kim 64516102edbSEunchul Kim /* original size */ 64616102edbSEunchul Kim cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) | 64716102edbSEunchul Kim EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize)); 64816102edbSEunchul Kim 649acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_ORGISIZE); 65016102edbSEunchul Kim 651cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h); 65216102edbSEunchul Kim 65316102edbSEunchul Kim if (swap) { 65416102edbSEunchul Kim img_pos.w = pos->h; 65516102edbSEunchul Kim img_pos.h = pos->w; 65616102edbSEunchul Kim img_sz.hsize = sz->vsize; 65716102edbSEunchul Kim img_sz.vsize = sz->hsize; 65816102edbSEunchul Kim } 65916102edbSEunchul Kim 66016102edbSEunchul Kim /* set input DMA image size */ 661acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE); 66216102edbSEunchul Kim cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK | 66316102edbSEunchul Kim EXYNOS_CIREAL_ISIZE_WIDTH_MASK); 66416102edbSEunchul Kim cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) | 66516102edbSEunchul Kim EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h)); 666acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE); 66716102edbSEunchul Kim 66816102edbSEunchul Kim /* 66916102edbSEunchul Kim * set input FIFO image size 67016102edbSEunchul Kim * for now, we support only ITU601 8 bit mode 67116102edbSEunchul Kim */ 67216102edbSEunchul Kim cfg = (EXYNOS_CISRCFMT_ITU601_8BIT | 67316102edbSEunchul Kim EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) | 67416102edbSEunchul Kim EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize)); 675acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISRCFMT); 67616102edbSEunchul Kim 67716102edbSEunchul Kim /* offset Y(RGB), Cb, Cr */ 67816102edbSEunchul Kim cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) | 67916102edbSEunchul Kim EXYNOS_CIIYOFF_VERTICAL(img_pos.y)); 680acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIIYOFF); 68116102edbSEunchul Kim cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) | 68216102edbSEunchul Kim EXYNOS_CIICBOFF_VERTICAL(img_pos.y)); 683acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIICBOFF); 68416102edbSEunchul Kim cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) | 68516102edbSEunchul Kim EXYNOS_CIICROFF_VERTICAL(img_pos.y)); 686acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIICROFF); 68716102edbSEunchul Kim 68816102edbSEunchul Kim return fimc_set_window(ctx, &img_pos, &img_sz); 68916102edbSEunchul Kim } 69016102edbSEunchul Kim 69116102edbSEunchul Kim static int fimc_src_set_addr(struct device *dev, 69216102edbSEunchul Kim struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 69316102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 69416102edbSEunchul Kim { 69516102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 69616102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 6977259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 69816102edbSEunchul Kim struct drm_exynos_ipp_property *property; 69916102edbSEunchul Kim struct drm_exynos_ipp_config *config; 70016102edbSEunchul Kim 70116102edbSEunchul Kim if (!c_node) { 70216102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 70316102edbSEunchul Kim return -EINVAL; 70416102edbSEunchul Kim } 70516102edbSEunchul Kim 70616102edbSEunchul Kim property = &c_node->property; 70716102edbSEunchul Kim 708cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 70916102edbSEunchul Kim property->prop_id, buf_id, buf_type); 71016102edbSEunchul Kim 71116102edbSEunchul Kim if (buf_id > FIMC_MAX_SRC) { 71216102edbSEunchul Kim dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 71316102edbSEunchul Kim return -ENOMEM; 71416102edbSEunchul Kim } 71516102edbSEunchul Kim 71616102edbSEunchul Kim /* address register set */ 71716102edbSEunchul Kim switch (buf_type) { 71816102edbSEunchul Kim case IPP_BUF_ENQUEUE: 71916102edbSEunchul Kim config = &property->config[EXYNOS_DRM_OPS_SRC]; 720acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y], 72116102edbSEunchul Kim EXYNOS_CIIYSA(buf_id)); 72216102edbSEunchul Kim 72316102edbSEunchul Kim if (config->fmt == DRM_FORMAT_YVU420) { 724acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR], 72516102edbSEunchul Kim EXYNOS_CIICBSA(buf_id)); 726acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB], 72716102edbSEunchul Kim EXYNOS_CIICRSA(buf_id)); 72816102edbSEunchul Kim } else { 729acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB], 73016102edbSEunchul Kim EXYNOS_CIICBSA(buf_id)); 731acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR], 73216102edbSEunchul Kim EXYNOS_CIICRSA(buf_id)); 73316102edbSEunchul Kim } 73416102edbSEunchul Kim break; 73516102edbSEunchul Kim case IPP_BUF_DEQUEUE: 736acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id)); 737acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id)); 738acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id)); 73916102edbSEunchul Kim break; 74016102edbSEunchul Kim default: 74116102edbSEunchul Kim /* bypass */ 74216102edbSEunchul Kim break; 74316102edbSEunchul Kim } 74416102edbSEunchul Kim 74516102edbSEunchul Kim return 0; 74616102edbSEunchul Kim } 74716102edbSEunchul Kim 74816102edbSEunchul Kim static struct exynos_drm_ipp_ops fimc_src_ops = { 74916102edbSEunchul Kim .set_fmt = fimc_src_set_fmt, 75016102edbSEunchul Kim .set_transf = fimc_src_set_transf, 75116102edbSEunchul Kim .set_size = fimc_src_set_size, 75216102edbSEunchul Kim .set_addr = fimc_src_set_addr, 75316102edbSEunchul Kim }; 75416102edbSEunchul Kim 75516102edbSEunchul Kim static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) 75616102edbSEunchul Kim { 75716102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 75816102edbSEunchul Kim u32 cfg; 75916102edbSEunchul Kim 760cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 76116102edbSEunchul Kim 76216102edbSEunchul Kim /* RGB */ 763acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CISCCTRL); 76416102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK; 76516102edbSEunchul Kim 76616102edbSEunchul Kim switch (fmt) { 76716102edbSEunchul Kim case DRM_FORMAT_RGB565: 76816102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565; 769acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 77016102edbSEunchul Kim return 0; 77116102edbSEunchul Kim case DRM_FORMAT_RGB888: 77216102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888; 773acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 77416102edbSEunchul Kim return 0; 77516102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 77616102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 | 77716102edbSEunchul Kim EXYNOS_CISCCTRL_EXTRGB_EXTENSION); 778acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 77916102edbSEunchul Kim break; 78016102edbSEunchul Kim default: 78116102edbSEunchul Kim /* bypass */ 78216102edbSEunchul Kim break; 78316102edbSEunchul Kim } 78416102edbSEunchul Kim 78516102edbSEunchul Kim /* YUV */ 786acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIOCTRL); 78716102edbSEunchul Kim cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK | 78816102edbSEunchul Kim EXYNOS_CIOCTRL_ORDER422_MASK | 78916102edbSEunchul Kim EXYNOS_CIOCTRL_YCBCR_PLANE_MASK); 79016102edbSEunchul Kim 79116102edbSEunchul Kim switch (fmt) { 79216102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 79316102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ALPHA_OUT; 79416102edbSEunchul Kim break; 79516102edbSEunchul Kim case DRM_FORMAT_YUYV: 79616102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR; 79716102edbSEunchul Kim break; 79816102edbSEunchul Kim case DRM_FORMAT_YVYU: 79916102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB; 80016102edbSEunchul Kim break; 80116102edbSEunchul Kim case DRM_FORMAT_UYVY: 80216102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY; 80316102edbSEunchul Kim break; 80416102edbSEunchul Kim case DRM_FORMAT_VYUY: 80516102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY; 80616102edbSEunchul Kim break; 80716102edbSEunchul Kim case DRM_FORMAT_NV21: 80816102edbSEunchul Kim case DRM_FORMAT_NV61: 80916102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB; 81016102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 81116102edbSEunchul Kim break; 81216102edbSEunchul Kim case DRM_FORMAT_YUV422: 81316102edbSEunchul Kim case DRM_FORMAT_YUV420: 81416102edbSEunchul Kim case DRM_FORMAT_YVU420: 81516102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE; 81616102edbSEunchul Kim break; 81716102edbSEunchul Kim case DRM_FORMAT_NV12: 81816102edbSEunchul Kim case DRM_FORMAT_NV12MT: 81916102edbSEunchul Kim case DRM_FORMAT_NV16: 82016102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR; 82116102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 82216102edbSEunchul Kim break; 82316102edbSEunchul Kim default: 82416102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); 82516102edbSEunchul Kim return -EINVAL; 82616102edbSEunchul Kim } 82716102edbSEunchul Kim 828acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIOCTRL); 82916102edbSEunchul Kim 83016102edbSEunchul Kim return 0; 83116102edbSEunchul Kim } 83216102edbSEunchul Kim 83316102edbSEunchul Kim static int fimc_dst_set_fmt(struct device *dev, u32 fmt) 83416102edbSEunchul Kim { 83516102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 83616102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 83716102edbSEunchul Kim u32 cfg; 83816102edbSEunchul Kim 839cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); 84016102edbSEunchul Kim 841acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIEXTEN); 84216102edbSEunchul Kim 84316102edbSEunchul Kim if (fmt == DRM_FORMAT_AYUV) { 84416102edbSEunchul Kim cfg |= EXYNOS_CIEXTEN_YUV444_OUT; 845acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIEXTEN); 84616102edbSEunchul Kim } else { 84716102edbSEunchul Kim cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT; 848acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIEXTEN); 84916102edbSEunchul Kim 850acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CITRGFMT); 85116102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK; 85216102edbSEunchul Kim 85316102edbSEunchul Kim switch (fmt) { 85416102edbSEunchul Kim case DRM_FORMAT_RGB565: 85516102edbSEunchul Kim case DRM_FORMAT_RGB888: 85616102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 85716102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB; 85816102edbSEunchul Kim break; 85916102edbSEunchul Kim case DRM_FORMAT_YUYV: 86016102edbSEunchul Kim case DRM_FORMAT_YVYU: 86116102edbSEunchul Kim case DRM_FORMAT_UYVY: 86216102edbSEunchul Kim case DRM_FORMAT_VYUY: 86316102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; 86416102edbSEunchul Kim break; 86516102edbSEunchul Kim case DRM_FORMAT_NV16: 86616102edbSEunchul Kim case DRM_FORMAT_NV61: 86716102edbSEunchul Kim case DRM_FORMAT_YUV422: 86816102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422; 86916102edbSEunchul Kim break; 87016102edbSEunchul Kim case DRM_FORMAT_YUV420: 87116102edbSEunchul Kim case DRM_FORMAT_YVU420: 87216102edbSEunchul Kim case DRM_FORMAT_NV12: 87316102edbSEunchul Kim case DRM_FORMAT_NV12MT: 87416102edbSEunchul Kim case DRM_FORMAT_NV21: 87516102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; 87616102edbSEunchul Kim break; 87716102edbSEunchul Kim default: 87816102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid target format 0x%x.\n", 87916102edbSEunchul Kim fmt); 88016102edbSEunchul Kim return -EINVAL; 88116102edbSEunchul Kim } 88216102edbSEunchul Kim 883acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CITRGFMT); 88416102edbSEunchul Kim } 88516102edbSEunchul Kim 886acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM); 88716102edbSEunchul Kim cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK; 88816102edbSEunchul Kim 88916102edbSEunchul Kim if (fmt == DRM_FORMAT_NV12MT) 89016102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32; 89116102edbSEunchul Kim else 89216102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR; 89316102edbSEunchul Kim 894acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM); 89516102edbSEunchul Kim 89616102edbSEunchul Kim return fimc_dst_set_fmt_order(ctx, fmt); 89716102edbSEunchul Kim } 89816102edbSEunchul Kim 89916102edbSEunchul Kim static int fimc_dst_set_transf(struct device *dev, 90016102edbSEunchul Kim enum drm_exynos_degree degree, 90116102edbSEunchul Kim enum drm_exynos_flip flip, bool *swap) 90216102edbSEunchul Kim { 90316102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 90416102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 90516102edbSEunchul Kim u32 cfg; 90616102edbSEunchul Kim 907cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); 90816102edbSEunchul Kim 909acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CITRGFMT); 91016102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK; 91116102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 91216102edbSEunchul Kim 91316102edbSEunchul Kim switch (degree) { 91416102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 91516102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 91616102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 91716102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 91816102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 91916102edbSEunchul Kim break; 92016102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 92116102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 92216102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 92316102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 92416102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 92516102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 92616102edbSEunchul Kim break; 92716102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 92816102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR | 92916102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 93016102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 93116102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 93216102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 93316102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 93416102edbSEunchul Kim break; 93516102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 93616102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE | 93716102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_X_MIRROR | 93816102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 93916102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 94016102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 94116102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 94216102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 94316102edbSEunchul Kim break; 94416102edbSEunchul Kim default: 94516102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 94616102edbSEunchul Kim return -EINVAL; 94716102edbSEunchul Kim } 94816102edbSEunchul Kim 949acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CITRGFMT); 95016102edbSEunchul Kim *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0; 95116102edbSEunchul Kim 95216102edbSEunchul Kim return 0; 95316102edbSEunchul Kim } 95416102edbSEunchul Kim 95516102edbSEunchul Kim static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, 95616102edbSEunchul Kim struct drm_exynos_pos *src, struct drm_exynos_pos *dst) 95716102edbSEunchul Kim { 95816102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 95916102edbSEunchul Kim u32 cfg, cfg_ext, shfactor; 96016102edbSEunchul Kim u32 pre_dst_width, pre_dst_height; 961be6cdfd1SAndrzej Hajda u32 hfactor, vfactor; 96216102edbSEunchul Kim int ret = 0; 96316102edbSEunchul Kim u32 src_w, src_h, dst_w, dst_h; 96416102edbSEunchul Kim 965acd8afa8SAndrzej Hajda cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT); 96616102edbSEunchul Kim if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) { 96716102edbSEunchul Kim src_w = src->h; 96816102edbSEunchul Kim src_h = src->w; 96916102edbSEunchul Kim } else { 97016102edbSEunchul Kim src_w = src->w; 97116102edbSEunchul Kim src_h = src->h; 97216102edbSEunchul Kim } 97316102edbSEunchul Kim 97416102edbSEunchul Kim if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) { 97516102edbSEunchul Kim dst_w = dst->h; 97616102edbSEunchul Kim dst_h = dst->w; 97716102edbSEunchul Kim } else { 97816102edbSEunchul Kim dst_w = dst->w; 97916102edbSEunchul Kim dst_h = dst->h; 98016102edbSEunchul Kim } 98116102edbSEunchul Kim 982be6cdfd1SAndrzej Hajda /* fimc_ippdrv_check_property assures that dividers are not null */ 983be6cdfd1SAndrzej Hajda hfactor = fls(src_w / dst_w / 2); 984be6cdfd1SAndrzej Hajda if (hfactor > FIMC_SHFACTOR / 2) { 98516102edbSEunchul Kim dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); 986be6cdfd1SAndrzej Hajda return -EINVAL; 98716102edbSEunchul Kim } 98816102edbSEunchul Kim 989be6cdfd1SAndrzej Hajda vfactor = fls(src_h / dst_h / 2); 990be6cdfd1SAndrzej Hajda if (vfactor > FIMC_SHFACTOR / 2) { 99116102edbSEunchul Kim dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); 992be6cdfd1SAndrzej Hajda return -EINVAL; 99316102edbSEunchul Kim } 99416102edbSEunchul Kim 995be6cdfd1SAndrzej Hajda pre_dst_width = src_w >> hfactor; 996be6cdfd1SAndrzej Hajda pre_dst_height = src_h >> vfactor; 997cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n", 99816102edbSEunchul Kim pre_dst_width, pre_dst_height); 999be6cdfd1SAndrzej Hajda DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor); 100016102edbSEunchul Kim 100116102edbSEunchul Kim sc->hratio = (src_w << 14) / (dst_w << hfactor); 100216102edbSEunchul Kim sc->vratio = (src_h << 14) / (dst_h << vfactor); 100316102edbSEunchul Kim sc->up_h = (dst_w >= src_w) ? true : false; 100416102edbSEunchul Kim sc->up_v = (dst_h >= src_h) ? true : false; 1005cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n", 1006cbc4c33dSYoungJun Cho sc->hratio, sc->vratio, sc->up_h, sc->up_v); 100716102edbSEunchul Kim 100816102edbSEunchul Kim shfactor = FIMC_SHFACTOR - (hfactor + vfactor); 1009cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("shfactor[%d]\n", shfactor); 101016102edbSEunchul Kim 101116102edbSEunchul Kim cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) | 1012be6cdfd1SAndrzej Hajda EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) | 1013be6cdfd1SAndrzej Hajda EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor)); 1014acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO); 101516102edbSEunchul Kim 101616102edbSEunchul Kim cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) | 101716102edbSEunchul Kim EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height)); 1018acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCPREDST); 101916102edbSEunchul Kim 102016102edbSEunchul Kim return ret; 102116102edbSEunchul Kim } 102216102edbSEunchul Kim 102316102edbSEunchul Kim static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) 102416102edbSEunchul Kim { 102516102edbSEunchul Kim u32 cfg, cfg_ext; 102616102edbSEunchul Kim 1027cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n", 1028cbc4c33dSYoungJun Cho sc->range, sc->bypass, sc->up_h, sc->up_v); 1029cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n", 1030cbc4c33dSYoungJun Cho sc->hratio, sc->vratio); 103116102edbSEunchul Kim 1032acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CISCCTRL); 103316102edbSEunchul Kim cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS | 103416102edbSEunchul Kim EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V | 103516102edbSEunchul Kim EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK | 103616102edbSEunchul Kim EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK | 103716102edbSEunchul Kim EXYNOS_CISCCTRL_CSCR2Y_WIDE | 103816102edbSEunchul Kim EXYNOS_CISCCTRL_CSCY2R_WIDE); 103916102edbSEunchul Kim 104016102edbSEunchul Kim if (sc->range) 104116102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | 104216102edbSEunchul Kim EXYNOS_CISCCTRL_CSCY2R_WIDE); 104316102edbSEunchul Kim if (sc->bypass) 104416102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; 104516102edbSEunchul Kim if (sc->up_h) 104616102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALEUP_H; 104716102edbSEunchul Kim if (sc->up_v) 104816102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALEUP_V; 104916102edbSEunchul Kim 105016102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) | 105116102edbSEunchul Kim EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6))); 1052acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CISCCTRL); 105316102edbSEunchul Kim 1054acd8afa8SAndrzej Hajda cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN); 105516102edbSEunchul Kim cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK; 105616102edbSEunchul Kim cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK; 105716102edbSEunchul Kim cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) | 105816102edbSEunchul Kim EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio)); 1059acd8afa8SAndrzej Hajda fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN); 106016102edbSEunchul Kim } 106116102edbSEunchul Kim 106216102edbSEunchul Kim static int fimc_dst_set_size(struct device *dev, int swap, 106316102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 106416102edbSEunchul Kim { 106516102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 106616102edbSEunchul Kim struct drm_exynos_pos img_pos = *pos; 106716102edbSEunchul Kim struct drm_exynos_sz img_sz = *sz; 106816102edbSEunchul Kim u32 cfg; 106916102edbSEunchul Kim 1070cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n", 1071cbc4c33dSYoungJun Cho swap, sz->hsize, sz->vsize); 107216102edbSEunchul Kim 107316102edbSEunchul Kim /* original size */ 107416102edbSEunchul Kim cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) | 107516102edbSEunchul Kim EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize)); 107616102edbSEunchul Kim 1077acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_ORGOSIZE); 107816102edbSEunchul Kim 1079cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h); 108016102edbSEunchul Kim 108116102edbSEunchul Kim /* CSC ITU */ 1082acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIGCTRL); 108316102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_CSC_MASK; 108416102edbSEunchul Kim 108516102edbSEunchul Kim if (sz->hsize >= FIMC_WIDTH_ITU_709) 108616102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CSC_ITU709; 108716102edbSEunchul Kim else 108816102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CSC_ITU601; 108916102edbSEunchul Kim 1090acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIGCTRL); 109116102edbSEunchul Kim 109216102edbSEunchul Kim if (swap) { 109316102edbSEunchul Kim img_pos.w = pos->h; 109416102edbSEunchul Kim img_pos.h = pos->w; 109516102edbSEunchul Kim img_sz.hsize = sz->vsize; 109616102edbSEunchul Kim img_sz.vsize = sz->hsize; 109716102edbSEunchul Kim } 109816102edbSEunchul Kim 109916102edbSEunchul Kim /* target image size */ 1100acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CITRGFMT); 110116102edbSEunchul Kim cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK | 110216102edbSEunchul Kim EXYNOS_CITRGFMT_TARGETV_MASK); 110316102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) | 110416102edbSEunchul Kim EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h)); 1105acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CITRGFMT); 110616102edbSEunchul Kim 110716102edbSEunchul Kim /* target area */ 110816102edbSEunchul Kim cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h); 1109acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CITAREA); 111016102edbSEunchul Kim 111116102edbSEunchul Kim /* offset Y(RGB), Cb, Cr */ 111216102edbSEunchul Kim cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) | 111316102edbSEunchul Kim EXYNOS_CIOYOFF_VERTICAL(img_pos.y)); 1114acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIOYOFF); 111516102edbSEunchul Kim cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) | 111616102edbSEunchul Kim EXYNOS_CIOCBOFF_VERTICAL(img_pos.y)); 1117acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIOCBOFF); 111816102edbSEunchul Kim cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) | 111916102edbSEunchul Kim EXYNOS_CIOCROFF_VERTICAL(img_pos.y)); 1120acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIOCROFF); 112116102edbSEunchul Kim 112216102edbSEunchul Kim return 0; 112316102edbSEunchul Kim } 112416102edbSEunchul Kim 112516102edbSEunchul Kim static int fimc_dst_get_buf_seq(struct fimc_context *ctx) 112616102edbSEunchul Kim { 112716102edbSEunchul Kim u32 cfg, i, buf_num = 0; 112816102edbSEunchul Kim u32 mask = 0x00000001; 112916102edbSEunchul Kim 1130acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ); 113116102edbSEunchul Kim 113216102edbSEunchul Kim for (i = 0; i < FIMC_REG_SZ; i++) 113316102edbSEunchul Kim if (cfg & (mask << i)) 113416102edbSEunchul Kim buf_num++; 113516102edbSEunchul Kim 1136cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); 113716102edbSEunchul Kim 113816102edbSEunchul Kim return buf_num; 113916102edbSEunchul Kim } 114016102edbSEunchul Kim 114116102edbSEunchul Kim static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, 114216102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 114316102edbSEunchul Kim { 114416102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 114516102edbSEunchul Kim bool enable; 114616102edbSEunchul Kim u32 cfg; 114716102edbSEunchul Kim u32 mask = 0x00000001 << buf_id; 114816102edbSEunchul Kim int ret = 0; 114916102edbSEunchul Kim 1150cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); 115116102edbSEunchul Kim 115216102edbSEunchul Kim mutex_lock(&ctx->lock); 115316102edbSEunchul Kim 115416102edbSEunchul Kim /* mask register set */ 1155acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ); 115616102edbSEunchul Kim 115716102edbSEunchul Kim switch (buf_type) { 115816102edbSEunchul Kim case IPP_BUF_ENQUEUE: 115916102edbSEunchul Kim enable = true; 116016102edbSEunchul Kim break; 116116102edbSEunchul Kim case IPP_BUF_DEQUEUE: 116216102edbSEunchul Kim enable = false; 116316102edbSEunchul Kim break; 116416102edbSEunchul Kim default: 116516102edbSEunchul Kim dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); 116616102edbSEunchul Kim ret = -EINVAL; 116716102edbSEunchul Kim goto err_unlock; 116816102edbSEunchul Kim } 116916102edbSEunchul Kim 117016102edbSEunchul Kim /* sequence id */ 117113a32eb0SEunchul Kim cfg &= ~mask; 117216102edbSEunchul Kim cfg |= (enable << buf_id); 1173acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ); 117416102edbSEunchul Kim 117516102edbSEunchul Kim /* interrupt enable */ 117616102edbSEunchul Kim if (buf_type == IPP_BUF_ENQUEUE && 117716102edbSEunchul Kim fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START) 11788b4609cdSAndrzej Hajda fimc_mask_irq(ctx, true); 117916102edbSEunchul Kim 118016102edbSEunchul Kim /* interrupt disable */ 118116102edbSEunchul Kim if (buf_type == IPP_BUF_DEQUEUE && 118216102edbSEunchul Kim fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP) 11838b4609cdSAndrzej Hajda fimc_mask_irq(ctx, false); 118416102edbSEunchul Kim 118516102edbSEunchul Kim err_unlock: 118616102edbSEunchul Kim mutex_unlock(&ctx->lock); 118716102edbSEunchul Kim return ret; 118816102edbSEunchul Kim } 118916102edbSEunchul Kim 119016102edbSEunchul Kim static int fimc_dst_set_addr(struct device *dev, 119116102edbSEunchul Kim struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 119216102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 119316102edbSEunchul Kim { 119416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 119516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 11967259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 119716102edbSEunchul Kim struct drm_exynos_ipp_property *property; 119816102edbSEunchul Kim struct drm_exynos_ipp_config *config; 119916102edbSEunchul Kim 120016102edbSEunchul Kim if (!c_node) { 120116102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 120216102edbSEunchul Kim return -EINVAL; 120316102edbSEunchul Kim } 120416102edbSEunchul Kim 120516102edbSEunchul Kim property = &c_node->property; 120616102edbSEunchul Kim 1207cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", 120816102edbSEunchul Kim property->prop_id, buf_id, buf_type); 120916102edbSEunchul Kim 121016102edbSEunchul Kim if (buf_id > FIMC_MAX_DST) { 121116102edbSEunchul Kim dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 121216102edbSEunchul Kim return -ENOMEM; 121316102edbSEunchul Kim } 121416102edbSEunchul Kim 121516102edbSEunchul Kim /* address register set */ 121616102edbSEunchul Kim switch (buf_type) { 121716102edbSEunchul Kim case IPP_BUF_ENQUEUE: 121816102edbSEunchul Kim config = &property->config[EXYNOS_DRM_OPS_DST]; 121916102edbSEunchul Kim 1220acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y], 122116102edbSEunchul Kim EXYNOS_CIOYSA(buf_id)); 122216102edbSEunchul Kim 122316102edbSEunchul Kim if (config->fmt == DRM_FORMAT_YVU420) { 1224acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR], 122516102edbSEunchul Kim EXYNOS_CIOCBSA(buf_id)); 1226acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB], 122716102edbSEunchul Kim EXYNOS_CIOCRSA(buf_id)); 122816102edbSEunchul Kim } else { 1229acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB], 123016102edbSEunchul Kim EXYNOS_CIOCBSA(buf_id)); 1231acd8afa8SAndrzej Hajda fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR], 123216102edbSEunchul Kim EXYNOS_CIOCRSA(buf_id)); 123316102edbSEunchul Kim } 123416102edbSEunchul Kim break; 123516102edbSEunchul Kim case IPP_BUF_DEQUEUE: 1236acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id)); 1237acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id)); 1238acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id)); 123916102edbSEunchul Kim break; 124016102edbSEunchul Kim default: 124116102edbSEunchul Kim /* bypass */ 124216102edbSEunchul Kim break; 124316102edbSEunchul Kim } 124416102edbSEunchul Kim 124516102edbSEunchul Kim return fimc_dst_set_buf_seq(ctx, buf_id, buf_type); 124616102edbSEunchul Kim } 124716102edbSEunchul Kim 124816102edbSEunchul Kim static struct exynos_drm_ipp_ops fimc_dst_ops = { 124916102edbSEunchul Kim .set_fmt = fimc_dst_set_fmt, 125016102edbSEunchul Kim .set_transf = fimc_dst_set_transf, 125116102edbSEunchul Kim .set_size = fimc_dst_set_size, 125216102edbSEunchul Kim .set_addr = fimc_dst_set_addr, 125316102edbSEunchul Kim }; 125416102edbSEunchul Kim 125516102edbSEunchul Kim static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable) 125616102edbSEunchul Kim { 1257cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("enable[%d]\n", enable); 125816102edbSEunchul Kim 125916102edbSEunchul Kim if (enable) { 1260e5f86839SSylwester Nawrocki clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); 1261e5f86839SSylwester Nawrocki clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); 126216102edbSEunchul Kim ctx->suspended = false; 126316102edbSEunchul Kim } else { 1264e5f86839SSylwester Nawrocki clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); 1265e5f86839SSylwester Nawrocki clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); 126616102edbSEunchul Kim ctx->suspended = true; 126716102edbSEunchul Kim } 126816102edbSEunchul Kim 126916102edbSEunchul Kim return 0; 127016102edbSEunchul Kim } 127116102edbSEunchul Kim 127216102edbSEunchul Kim static irqreturn_t fimc_irq_handler(int irq, void *dev_id) 127316102edbSEunchul Kim { 127416102edbSEunchul Kim struct fimc_context *ctx = dev_id; 127516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 12767259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 127716102edbSEunchul Kim struct drm_exynos_ipp_event_work *event_work = 127816102edbSEunchul Kim c_node->event_work; 127916102edbSEunchul Kim int buf_id; 128016102edbSEunchul Kim 1281cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id); 128216102edbSEunchul Kim 128316102edbSEunchul Kim fimc_clear_irq(ctx); 128416102edbSEunchul Kim if (fimc_check_ovf(ctx)) 128516102edbSEunchul Kim return IRQ_NONE; 128616102edbSEunchul Kim 128716102edbSEunchul Kim if (!fimc_check_frame_end(ctx)) 128816102edbSEunchul Kim return IRQ_NONE; 128916102edbSEunchul Kim 129016102edbSEunchul Kim buf_id = fimc_get_buf_id(ctx); 129116102edbSEunchul Kim if (buf_id < 0) 129216102edbSEunchul Kim return IRQ_HANDLED; 129316102edbSEunchul Kim 1294cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("buf_id[%d]\n", buf_id); 129516102edbSEunchul Kim 129616102edbSEunchul Kim if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) { 129716102edbSEunchul Kim DRM_ERROR("failed to dequeue.\n"); 129816102edbSEunchul Kim return IRQ_HANDLED; 129916102edbSEunchul Kim } 130016102edbSEunchul Kim 130116102edbSEunchul Kim event_work->ippdrv = ippdrv; 130216102edbSEunchul Kim event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id; 130316102edbSEunchul Kim queue_work(ippdrv->event_workq, (struct work_struct *)event_work); 130416102edbSEunchul Kim 130516102edbSEunchul Kim return IRQ_HANDLED; 130616102edbSEunchul Kim } 130716102edbSEunchul Kim 130816102edbSEunchul Kim static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) 130916102edbSEunchul Kim { 131031646054SAndrzej Hajda struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list; 131116102edbSEunchul Kim 131216102edbSEunchul Kim prop_list->version = 1; 131316102edbSEunchul Kim prop_list->writeback = 1; 131416102edbSEunchul Kim prop_list->refresh_min = FIMC_REFRESH_MIN; 131516102edbSEunchul Kim prop_list->refresh_max = FIMC_REFRESH_MAX; 131616102edbSEunchul Kim prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) | 131716102edbSEunchul Kim (1 << EXYNOS_DRM_FLIP_VERTICAL) | 131816102edbSEunchul Kim (1 << EXYNOS_DRM_FLIP_HORIZONTAL); 131916102edbSEunchul Kim prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | 132016102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_90) | 132116102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_180) | 132216102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_270); 132316102edbSEunchul Kim prop_list->csc = 1; 132416102edbSEunchul Kim prop_list->crop = 1; 132516102edbSEunchul Kim prop_list->crop_max.hsize = FIMC_CROP_MAX; 132616102edbSEunchul Kim prop_list->crop_max.vsize = FIMC_CROP_MAX; 132716102edbSEunchul Kim prop_list->crop_min.hsize = FIMC_CROP_MIN; 132816102edbSEunchul Kim prop_list->crop_min.vsize = FIMC_CROP_MIN; 132916102edbSEunchul Kim prop_list->scale = 1; 133016102edbSEunchul Kim prop_list->scale_max.hsize = FIMC_SCALE_MAX; 133116102edbSEunchul Kim prop_list->scale_max.vsize = FIMC_SCALE_MAX; 133216102edbSEunchul Kim prop_list->scale_min.hsize = FIMC_SCALE_MIN; 133316102edbSEunchul Kim prop_list->scale_min.vsize = FIMC_SCALE_MIN; 133416102edbSEunchul Kim 133516102edbSEunchul Kim return 0; 133616102edbSEunchul Kim } 133716102edbSEunchul Kim 133816102edbSEunchul Kim static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip) 133916102edbSEunchul Kim { 134016102edbSEunchul Kim switch (flip) { 134116102edbSEunchul Kim case EXYNOS_DRM_FLIP_NONE: 134216102edbSEunchul Kim case EXYNOS_DRM_FLIP_VERTICAL: 134316102edbSEunchul Kim case EXYNOS_DRM_FLIP_HORIZONTAL: 13444f21877cSEunchul Kim case EXYNOS_DRM_FLIP_BOTH: 134516102edbSEunchul Kim return true; 134616102edbSEunchul Kim default: 1347cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("invalid flip\n"); 134816102edbSEunchul Kim return false; 134916102edbSEunchul Kim } 135016102edbSEunchul Kim } 135116102edbSEunchul Kim 135216102edbSEunchul Kim static int fimc_ippdrv_check_property(struct device *dev, 135316102edbSEunchul Kim struct drm_exynos_ipp_property *property) 135416102edbSEunchul Kim { 135516102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 135616102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 135731646054SAndrzej Hajda struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list; 135816102edbSEunchul Kim struct drm_exynos_ipp_config *config; 135916102edbSEunchul Kim struct drm_exynos_pos *pos; 136016102edbSEunchul Kim struct drm_exynos_sz *sz; 136116102edbSEunchul Kim bool swap; 136216102edbSEunchul Kim int i; 136316102edbSEunchul Kim 136416102edbSEunchul Kim for_each_ipp_ops(i) { 136516102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && 136616102edbSEunchul Kim (property->cmd == IPP_CMD_WB)) 136716102edbSEunchul Kim continue; 136816102edbSEunchul Kim 136916102edbSEunchul Kim config = &property->config[i]; 137016102edbSEunchul Kim pos = &config->pos; 137116102edbSEunchul Kim sz = &config->sz; 137216102edbSEunchul Kim 137316102edbSEunchul Kim /* check for flip */ 137416102edbSEunchul Kim if (!fimc_check_drm_flip(config->flip)) { 137516102edbSEunchul Kim DRM_ERROR("invalid flip.\n"); 137616102edbSEunchul Kim goto err_property; 137716102edbSEunchul Kim } 137816102edbSEunchul Kim 137916102edbSEunchul Kim /* check for degree */ 138016102edbSEunchul Kim switch (config->degree) { 138116102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 138216102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 138316102edbSEunchul Kim swap = true; 138416102edbSEunchul Kim break; 138516102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 138616102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 138716102edbSEunchul Kim swap = false; 138816102edbSEunchul Kim break; 138916102edbSEunchul Kim default: 139016102edbSEunchul Kim DRM_ERROR("invalid degree.\n"); 139116102edbSEunchul Kim goto err_property; 139216102edbSEunchul Kim } 139316102edbSEunchul Kim 139416102edbSEunchul Kim /* check for buffer bound */ 139516102edbSEunchul Kim if ((pos->x + pos->w > sz->hsize) || 139616102edbSEunchul Kim (pos->y + pos->h > sz->vsize)) { 139716102edbSEunchul Kim DRM_ERROR("out of buf bound.\n"); 139816102edbSEunchul Kim goto err_property; 139916102edbSEunchul Kim } 140016102edbSEunchul Kim 140116102edbSEunchul Kim /* check for crop */ 140216102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { 140316102edbSEunchul Kim if (swap) { 140416102edbSEunchul Kim if ((pos->h < pp->crop_min.hsize) || 140516102edbSEunchul Kim (sz->vsize > pp->crop_max.hsize) || 140616102edbSEunchul Kim (pos->w < pp->crop_min.vsize) || 140716102edbSEunchul Kim (sz->hsize > pp->crop_max.vsize)) { 140816102edbSEunchul Kim DRM_ERROR("out of crop size.\n"); 140916102edbSEunchul Kim goto err_property; 141016102edbSEunchul Kim } 141116102edbSEunchul Kim } else { 141216102edbSEunchul Kim if ((pos->w < pp->crop_min.hsize) || 141316102edbSEunchul Kim (sz->hsize > pp->crop_max.hsize) || 141416102edbSEunchul Kim (pos->h < pp->crop_min.vsize) || 141516102edbSEunchul Kim (sz->vsize > pp->crop_max.vsize)) { 141616102edbSEunchul Kim DRM_ERROR("out of crop size.\n"); 141716102edbSEunchul Kim goto err_property; 141816102edbSEunchul Kim } 141916102edbSEunchul Kim } 142016102edbSEunchul Kim } 142116102edbSEunchul Kim 142216102edbSEunchul Kim /* check for scale */ 142316102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { 142416102edbSEunchul Kim if (swap) { 142516102edbSEunchul Kim if ((pos->h < pp->scale_min.hsize) || 142616102edbSEunchul Kim (sz->vsize > pp->scale_max.hsize) || 142716102edbSEunchul Kim (pos->w < pp->scale_min.vsize) || 142816102edbSEunchul Kim (sz->hsize > pp->scale_max.vsize)) { 142916102edbSEunchul Kim DRM_ERROR("out of scale size.\n"); 143016102edbSEunchul Kim goto err_property; 143116102edbSEunchul Kim } 143216102edbSEunchul Kim } else { 143316102edbSEunchul Kim if ((pos->w < pp->scale_min.hsize) || 143416102edbSEunchul Kim (sz->hsize > pp->scale_max.hsize) || 143516102edbSEunchul Kim (pos->h < pp->scale_min.vsize) || 143616102edbSEunchul Kim (sz->vsize > pp->scale_max.vsize)) { 143716102edbSEunchul Kim DRM_ERROR("out of scale size.\n"); 143816102edbSEunchul Kim goto err_property; 143916102edbSEunchul Kim } 144016102edbSEunchul Kim } 144116102edbSEunchul Kim } 144216102edbSEunchul Kim } 144316102edbSEunchul Kim 144416102edbSEunchul Kim return 0; 144516102edbSEunchul Kim 144616102edbSEunchul Kim err_property: 144716102edbSEunchul Kim for_each_ipp_ops(i) { 144816102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && 144916102edbSEunchul Kim (property->cmd == IPP_CMD_WB)) 145016102edbSEunchul Kim continue; 145116102edbSEunchul Kim 145216102edbSEunchul Kim config = &property->config[i]; 145316102edbSEunchul Kim pos = &config->pos; 145416102edbSEunchul Kim sz = &config->sz; 145516102edbSEunchul Kim 145616102edbSEunchul Kim DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", 145716102edbSEunchul Kim i ? "dst" : "src", config->flip, config->degree, 145816102edbSEunchul Kim pos->x, pos->y, pos->w, pos->h, 145916102edbSEunchul Kim sz->hsize, sz->vsize); 146016102edbSEunchul Kim } 146116102edbSEunchul Kim 146216102edbSEunchul Kim return -EINVAL; 146316102edbSEunchul Kim } 146416102edbSEunchul Kim 146516102edbSEunchul Kim static void fimc_clear_addr(struct fimc_context *ctx) 146616102edbSEunchul Kim { 146716102edbSEunchul Kim int i; 146816102edbSEunchul Kim 146916102edbSEunchul Kim for (i = 0; i < FIMC_MAX_SRC; i++) { 1470acd8afa8SAndrzej Hajda fimc_write(ctx, 0, EXYNOS_CIIYSA(i)); 1471acd8afa8SAndrzej Hajda fimc_write(ctx, 0, EXYNOS_CIICBSA(i)); 1472acd8afa8SAndrzej Hajda fimc_write(ctx, 0, EXYNOS_CIICRSA(i)); 147316102edbSEunchul Kim } 147416102edbSEunchul Kim 147516102edbSEunchul Kim for (i = 0; i < FIMC_MAX_DST; i++) { 1476acd8afa8SAndrzej Hajda fimc_write(ctx, 0, EXYNOS_CIOYSA(i)); 1477acd8afa8SAndrzej Hajda fimc_write(ctx, 0, EXYNOS_CIOCBSA(i)); 1478acd8afa8SAndrzej Hajda fimc_write(ctx, 0, EXYNOS_CIOCRSA(i)); 147916102edbSEunchul Kim } 148016102edbSEunchul Kim } 148116102edbSEunchul Kim 148216102edbSEunchul Kim static int fimc_ippdrv_reset(struct device *dev) 148316102edbSEunchul Kim { 148416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 148516102edbSEunchul Kim 148616102edbSEunchul Kim /* reset h/w block */ 1487b5c0b552SJoongMock Shin fimc_sw_reset(ctx); 148816102edbSEunchul Kim 148916102edbSEunchul Kim /* reset scaler capability */ 149016102edbSEunchul Kim memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 149116102edbSEunchul Kim 149216102edbSEunchul Kim fimc_clear_addr(ctx); 149316102edbSEunchul Kim 149416102edbSEunchul Kim return 0; 149516102edbSEunchul Kim } 149616102edbSEunchul Kim 149716102edbSEunchul Kim static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) 149816102edbSEunchul Kim { 149916102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 150016102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 15017259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 150216102edbSEunchul Kim struct drm_exynos_ipp_property *property; 150316102edbSEunchul Kim struct drm_exynos_ipp_config *config; 150416102edbSEunchul Kim struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; 150516102edbSEunchul Kim struct drm_exynos_ipp_set_wb set_wb; 150616102edbSEunchul Kim int ret, i; 150716102edbSEunchul Kim u32 cfg0, cfg1; 150816102edbSEunchul Kim 1509cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("cmd[%d]\n", cmd); 151016102edbSEunchul Kim 151116102edbSEunchul Kim if (!c_node) { 151216102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 151316102edbSEunchul Kim return -EINVAL; 151416102edbSEunchul Kim } 151516102edbSEunchul Kim 151616102edbSEunchul Kim property = &c_node->property; 151716102edbSEunchul Kim 15188b4609cdSAndrzej Hajda fimc_mask_irq(ctx, true); 151916102edbSEunchul Kim 152016102edbSEunchul Kim for_each_ipp_ops(i) { 152116102edbSEunchul Kim config = &property->config[i]; 152216102edbSEunchul Kim img_pos[i] = config->pos; 152316102edbSEunchul Kim } 152416102edbSEunchul Kim 152516102edbSEunchul Kim ret = fimc_set_prescaler(ctx, &ctx->sc, 152616102edbSEunchul Kim &img_pos[EXYNOS_DRM_OPS_SRC], 152716102edbSEunchul Kim &img_pos[EXYNOS_DRM_OPS_DST]); 152816102edbSEunchul Kim if (ret) { 152916102edbSEunchul Kim dev_err(dev, "failed to set precalser.\n"); 153016102edbSEunchul Kim return ret; 153116102edbSEunchul Kim } 153216102edbSEunchul Kim 153316102edbSEunchul Kim /* If set ture, we can save jpeg about screen */ 153416102edbSEunchul Kim fimc_handle_jpeg(ctx, false); 153516102edbSEunchul Kim fimc_set_scaler(ctx, &ctx->sc); 153616102edbSEunchul Kim fimc_set_polarity(ctx, &ctx->pol); 153716102edbSEunchul Kim 153816102edbSEunchul Kim switch (cmd) { 153916102edbSEunchul Kim case IPP_CMD_M2M: 154016102edbSEunchul Kim fimc_set_type_ctrl(ctx, FIMC_WB_NONE); 154116102edbSEunchul Kim fimc_handle_lastend(ctx, false); 154216102edbSEunchul Kim 154316102edbSEunchul Kim /* setup dma */ 1544acd8afa8SAndrzej Hajda cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); 154516102edbSEunchul Kim cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; 154616102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; 1547acd8afa8SAndrzej Hajda fimc_write(ctx, cfg0, EXYNOS_MSCTRL); 154816102edbSEunchul Kim break; 154916102edbSEunchul Kim case IPP_CMD_WB: 155016102edbSEunchul Kim fimc_set_type_ctrl(ctx, FIMC_WB_A); 155116102edbSEunchul Kim fimc_handle_lastend(ctx, true); 155216102edbSEunchul Kim 155316102edbSEunchul Kim /* setup FIMD */ 15545186fc5eSSylwester Nawrocki ret = fimc_set_camblk_fimd0_wb(ctx); 15555186fc5eSSylwester Nawrocki if (ret < 0) { 15565186fc5eSSylwester Nawrocki dev_err(dev, "camblk setup failed.\n"); 15575186fc5eSSylwester Nawrocki return ret; 15585186fc5eSSylwester Nawrocki } 155916102edbSEunchul Kim 156016102edbSEunchul Kim set_wb.enable = 1; 156116102edbSEunchul Kim set_wb.refresh = property->refresh_rate; 156216102edbSEunchul Kim exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 156316102edbSEunchul Kim break; 156416102edbSEunchul Kim case IPP_CMD_OUTPUT: 156516102edbSEunchul Kim default: 156616102edbSEunchul Kim ret = -EINVAL; 156716102edbSEunchul Kim dev_err(dev, "invalid operations.\n"); 156816102edbSEunchul Kim return ret; 156916102edbSEunchul Kim } 157016102edbSEunchul Kim 157116102edbSEunchul Kim /* Reset status */ 1572acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CISTATUS); 157316102edbSEunchul Kim 1574acd8afa8SAndrzej Hajda cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); 157516102edbSEunchul Kim cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; 157616102edbSEunchul Kim cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; 157716102edbSEunchul Kim 157816102edbSEunchul Kim /* Scaler */ 1579acd8afa8SAndrzej Hajda cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL); 158016102edbSEunchul Kim cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; 158116102edbSEunchul Kim cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | 158216102edbSEunchul Kim EXYNOS_CISCCTRL_SCALERSTART); 158316102edbSEunchul Kim 1584acd8afa8SAndrzej Hajda fimc_write(ctx, cfg1, EXYNOS_CISCCTRL); 158516102edbSEunchul Kim 158616102edbSEunchul Kim /* Enable image capture*/ 158716102edbSEunchul Kim cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; 1588acd8afa8SAndrzej Hajda fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); 158916102edbSEunchul Kim 159016102edbSEunchul Kim /* Disable frame end irq */ 1591acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE); 159216102edbSEunchul Kim 1593acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK); 159416102edbSEunchul Kim 159516102edbSEunchul Kim if (cmd == IPP_CMD_M2M) { 1596acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); 159716102edbSEunchul Kim 1598acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID); 159916102edbSEunchul Kim } 160016102edbSEunchul Kim 160116102edbSEunchul Kim return 0; 160216102edbSEunchul Kim } 160316102edbSEunchul Kim 160416102edbSEunchul Kim static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) 160516102edbSEunchul Kim { 160616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 160716102edbSEunchul Kim struct drm_exynos_ipp_set_wb set_wb = {0, 0}; 160816102edbSEunchul Kim u32 cfg; 160916102edbSEunchul Kim 1610cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("cmd[%d]\n", cmd); 161116102edbSEunchul Kim 161216102edbSEunchul Kim switch (cmd) { 161316102edbSEunchul Kim case IPP_CMD_M2M: 161416102edbSEunchul Kim /* Source clear */ 1615acd8afa8SAndrzej Hajda cfg = fimc_read(ctx, EXYNOS_MSCTRL); 161616102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_INPUT_MASK; 161716102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_ENVID; 1618acd8afa8SAndrzej Hajda fimc_write(ctx, cfg, EXYNOS_MSCTRL); 161916102edbSEunchul Kim break; 162016102edbSEunchul Kim case IPP_CMD_WB: 162116102edbSEunchul Kim exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 162216102edbSEunchul Kim break; 162316102edbSEunchul Kim case IPP_CMD_OUTPUT: 162416102edbSEunchul Kim default: 162516102edbSEunchul Kim dev_err(dev, "invalid operations.\n"); 162616102edbSEunchul Kim break; 162716102edbSEunchul Kim } 162816102edbSEunchul Kim 16298b4609cdSAndrzej Hajda fimc_mask_irq(ctx, false); 163016102edbSEunchul Kim 163116102edbSEunchul Kim /* reset sequence */ 1632acd8afa8SAndrzej Hajda fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ); 163316102edbSEunchul Kim 163416102edbSEunchul Kim /* Scaler disable */ 1635acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART); 163616102edbSEunchul Kim 163716102edbSEunchul Kim /* Disable image capture */ 1638acd8afa8SAndrzej Hajda fimc_clear_bits(ctx, EXYNOS_CIIMGCPT, 1639acd8afa8SAndrzej Hajda EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 164016102edbSEunchul Kim 164116102edbSEunchul Kim /* Enable frame end irq */ 1642acd8afa8SAndrzej Hajda fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE); 164316102edbSEunchul Kim } 164416102edbSEunchul Kim 1645e5f86839SSylwester Nawrocki static void fimc_put_clocks(struct fimc_context *ctx) 1646e5f86839SSylwester Nawrocki { 1647e5f86839SSylwester Nawrocki int i; 1648e5f86839SSylwester Nawrocki 1649e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) { 1650e5f86839SSylwester Nawrocki if (IS_ERR(ctx->clocks[i])) 1651e5f86839SSylwester Nawrocki continue; 1652e5f86839SSylwester Nawrocki clk_put(ctx->clocks[i]); 1653e5f86839SSylwester Nawrocki ctx->clocks[i] = ERR_PTR(-EINVAL); 1654e5f86839SSylwester Nawrocki } 1655e5f86839SSylwester Nawrocki } 1656e5f86839SSylwester Nawrocki 1657e5f86839SSylwester Nawrocki static int fimc_setup_clocks(struct fimc_context *ctx) 1658e5f86839SSylwester Nawrocki { 1659e5f86839SSylwester Nawrocki struct device *fimc_dev = ctx->ippdrv.dev; 1660e5f86839SSylwester Nawrocki struct device *dev; 1661e5f86839SSylwester Nawrocki int ret, i; 1662e5f86839SSylwester Nawrocki 1663e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) 1664e5f86839SSylwester Nawrocki ctx->clocks[i] = ERR_PTR(-EINVAL); 1665e5f86839SSylwester Nawrocki 1666e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) { 1667e5f86839SSylwester Nawrocki if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B) 1668e5f86839SSylwester Nawrocki dev = fimc_dev->parent; 1669e5f86839SSylwester Nawrocki else 1670e5f86839SSylwester Nawrocki dev = fimc_dev; 1671e5f86839SSylwester Nawrocki 1672e5f86839SSylwester Nawrocki ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); 1673e5f86839SSylwester Nawrocki if (IS_ERR(ctx->clocks[i])) { 1674e5f86839SSylwester Nawrocki if (i >= FIMC_CLK_MUX) 1675e5f86839SSylwester Nawrocki break; 1676e5f86839SSylwester Nawrocki ret = PTR_ERR(ctx->clocks[i]); 1677e5f86839SSylwester Nawrocki dev_err(fimc_dev, "failed to get clock: %s\n", 1678e5f86839SSylwester Nawrocki fimc_clock_names[i]); 1679e5f86839SSylwester Nawrocki goto e_clk_free; 1680e5f86839SSylwester Nawrocki } 1681e5f86839SSylwester Nawrocki } 1682e5f86839SSylwester Nawrocki 1683e5f86839SSylwester Nawrocki /* Optional FIMC LCLK parent clock setting */ 1684e5f86839SSylwester Nawrocki if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) { 1685e5f86839SSylwester Nawrocki ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX], 1686e5f86839SSylwester Nawrocki ctx->clocks[FIMC_CLK_PARENT]); 1687e5f86839SSylwester Nawrocki if (ret < 0) { 1688e5f86839SSylwester Nawrocki dev_err(fimc_dev, "failed to set parent.\n"); 1689e5f86839SSylwester Nawrocki goto e_clk_free; 1690e5f86839SSylwester Nawrocki } 1691e5f86839SSylwester Nawrocki } 1692e5f86839SSylwester Nawrocki 1693e5f86839SSylwester Nawrocki ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency); 1694e5f86839SSylwester Nawrocki if (ret < 0) 1695e5f86839SSylwester Nawrocki goto e_clk_free; 1696e5f86839SSylwester Nawrocki 1697e5f86839SSylwester Nawrocki ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); 1698e5f86839SSylwester Nawrocki if (!ret) 1699e5f86839SSylwester Nawrocki return ret; 1700e5f86839SSylwester Nawrocki e_clk_free: 1701e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 1702e5f86839SSylwester Nawrocki return ret; 1703e5f86839SSylwester Nawrocki } 1704e5f86839SSylwester Nawrocki 17055186fc5eSSylwester Nawrocki static int fimc_parse_dt(struct fimc_context *ctx) 17065186fc5eSSylwester Nawrocki { 17075186fc5eSSylwester Nawrocki struct device_node *node = ctx->ippdrv.dev->of_node; 17085186fc5eSSylwester Nawrocki 17095186fc5eSSylwester Nawrocki /* Handle only devices that support the LCD Writeback data path */ 17105186fc5eSSylwester Nawrocki if (!of_property_read_bool(node, "samsung,lcd-wb")) 17115186fc5eSSylwester Nawrocki return -ENODEV; 17125186fc5eSSylwester Nawrocki 17135186fc5eSSylwester Nawrocki if (of_property_read_u32(node, "clock-frequency", 17145186fc5eSSylwester Nawrocki &ctx->clk_frequency)) 17155186fc5eSSylwester Nawrocki ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY; 17165186fc5eSSylwester Nawrocki 17175186fc5eSSylwester Nawrocki ctx->id = of_alias_get_id(node, "fimc"); 17185186fc5eSSylwester Nawrocki 17195186fc5eSSylwester Nawrocki if (ctx->id < 0) { 17205186fc5eSSylwester Nawrocki dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n"); 17215186fc5eSSylwester Nawrocki return -EINVAL; 17225186fc5eSSylwester Nawrocki } 17235186fc5eSSylwester Nawrocki 17245186fc5eSSylwester Nawrocki return 0; 17255186fc5eSSylwester Nawrocki } 17265186fc5eSSylwester Nawrocki 172756550d94SGreg Kroah-Hartman static int fimc_probe(struct platform_device *pdev) 172816102edbSEunchul Kim { 172916102edbSEunchul Kim struct device *dev = &pdev->dev; 173016102edbSEunchul Kim struct fimc_context *ctx; 173116102edbSEunchul Kim struct resource *res; 173216102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv; 173316102edbSEunchul Kim int ret; 173416102edbSEunchul Kim 17355186fc5eSSylwester Nawrocki if (!dev->of_node) { 17365186fc5eSSylwester Nawrocki dev_err(dev, "device tree node not found.\n"); 17375186fc5eSSylwester Nawrocki return -ENODEV; 173816102edbSEunchul Kim } 173916102edbSEunchul Kim 174016102edbSEunchul Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 174116102edbSEunchul Kim if (!ctx) 174216102edbSEunchul Kim return -ENOMEM; 174316102edbSEunchul Kim 17445186fc5eSSylwester Nawrocki ctx->ippdrv.dev = dev; 17455186fc5eSSylwester Nawrocki 17465186fc5eSSylwester Nawrocki ret = fimc_parse_dt(ctx); 17475186fc5eSSylwester Nawrocki if (ret < 0) 17485186fc5eSSylwester Nawrocki return ret; 17495186fc5eSSylwester Nawrocki 17505186fc5eSSylwester Nawrocki ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 17515186fc5eSSylwester Nawrocki "samsung,sysreg"); 17525186fc5eSSylwester Nawrocki if (IS_ERR(ctx->sysreg)) { 17535186fc5eSSylwester Nawrocki dev_err(dev, "syscon regmap lookup failed.\n"); 17545186fc5eSSylwester Nawrocki return PTR_ERR(ctx->sysreg); 17555186fc5eSSylwester Nawrocki } 17565186fc5eSSylwester Nawrocki 175716102edbSEunchul Kim /* resource memory */ 175816102edbSEunchul Kim ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1759d4ed6025SThierry Reding ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1760d4ed6025SThierry Reding if (IS_ERR(ctx->regs)) 1761d4ed6025SThierry Reding return PTR_ERR(ctx->regs); 176216102edbSEunchul Kim 176316102edbSEunchul Kim /* resource irq */ 176416102edbSEunchul Kim res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 176516102edbSEunchul Kim if (!res) { 176616102edbSEunchul Kim dev_err(dev, "failed to request irq resource.\n"); 176715b3263eSSachin Kamat return -ENOENT; 176816102edbSEunchul Kim } 176916102edbSEunchul Kim 177016102edbSEunchul Kim ctx->irq = res->start; 1771dcb9a7c7SSeung-Woo Kim ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler, 177216102edbSEunchul Kim IRQF_ONESHOT, "drm_fimc", ctx); 177316102edbSEunchul Kim if (ret < 0) { 177416102edbSEunchul Kim dev_err(dev, "failed to request irq.\n"); 177515b3263eSSachin Kamat return ret; 177616102edbSEunchul Kim } 177716102edbSEunchul Kim 1778e5f86839SSylwester Nawrocki ret = fimc_setup_clocks(ctx); 1779e5f86839SSylwester Nawrocki if (ret < 0) 1780dcb9a7c7SSeung-Woo Kim return ret; 178116102edbSEunchul Kim 178216102edbSEunchul Kim ippdrv = &ctx->ippdrv; 178316102edbSEunchul Kim ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops; 178416102edbSEunchul Kim ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops; 178516102edbSEunchul Kim ippdrv->check_property = fimc_ippdrv_check_property; 178616102edbSEunchul Kim ippdrv->reset = fimc_ippdrv_reset; 178716102edbSEunchul Kim ippdrv->start = fimc_ippdrv_start; 178816102edbSEunchul Kim ippdrv->stop = fimc_ippdrv_stop; 178916102edbSEunchul Kim ret = fimc_init_prop_list(ippdrv); 179016102edbSEunchul Kim if (ret < 0) { 179116102edbSEunchul Kim dev_err(dev, "failed to init property list.\n"); 1792e5f86839SSylwester Nawrocki goto err_put_clk; 179316102edbSEunchul Kim } 179416102edbSEunchul Kim 1795cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv); 179616102edbSEunchul Kim 179716102edbSEunchul Kim mutex_init(&ctx->lock); 179816102edbSEunchul Kim platform_set_drvdata(pdev, ctx); 179916102edbSEunchul Kim 180016102edbSEunchul Kim pm_runtime_set_active(dev); 180116102edbSEunchul Kim pm_runtime_enable(dev); 180216102edbSEunchul Kim 180316102edbSEunchul Kim ret = exynos_drm_ippdrv_register(ippdrv); 180416102edbSEunchul Kim if (ret < 0) { 180516102edbSEunchul Kim dev_err(dev, "failed to register drm fimc device.\n"); 1806e5f86839SSylwester Nawrocki goto err_pm_dis; 180716102edbSEunchul Kim } 180816102edbSEunchul Kim 1809d873ab99SSeung-Woo Kim dev_info(dev, "drm fimc registered successfully.\n"); 181016102edbSEunchul Kim 181116102edbSEunchul Kim return 0; 181216102edbSEunchul Kim 1813e5f86839SSylwester Nawrocki err_pm_dis: 181416102edbSEunchul Kim pm_runtime_disable(dev); 1815e5f86839SSylwester Nawrocki err_put_clk: 1816e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 181787acdde5SSachin Kamat 181816102edbSEunchul Kim return ret; 181916102edbSEunchul Kim } 182016102edbSEunchul Kim 182156550d94SGreg Kroah-Hartman static int fimc_remove(struct platform_device *pdev) 182216102edbSEunchul Kim { 182316102edbSEunchul Kim struct device *dev = &pdev->dev; 182416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 182516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 182616102edbSEunchul Kim 182716102edbSEunchul Kim exynos_drm_ippdrv_unregister(ippdrv); 182816102edbSEunchul Kim mutex_destroy(&ctx->lock); 182916102edbSEunchul Kim 1830e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 183116102edbSEunchul Kim pm_runtime_set_suspended(dev); 183216102edbSEunchul Kim pm_runtime_disable(dev); 183316102edbSEunchul Kim 183416102edbSEunchul Kim return 0; 183516102edbSEunchul Kim } 183616102edbSEunchul Kim 183716102edbSEunchul Kim #ifdef CONFIG_PM_SLEEP 183816102edbSEunchul Kim static int fimc_suspend(struct device *dev) 183916102edbSEunchul Kim { 184016102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 184116102edbSEunchul Kim 1842cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 184316102edbSEunchul Kim 184416102edbSEunchul Kim if (pm_runtime_suspended(dev)) 184516102edbSEunchul Kim return 0; 184616102edbSEunchul Kim 184716102edbSEunchul Kim return fimc_clk_ctrl(ctx, false); 184816102edbSEunchul Kim } 184916102edbSEunchul Kim 185016102edbSEunchul Kim static int fimc_resume(struct device *dev) 185116102edbSEunchul Kim { 185216102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 185316102edbSEunchul Kim 1854cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 185516102edbSEunchul Kim 185616102edbSEunchul Kim if (!pm_runtime_suspended(dev)) 185716102edbSEunchul Kim return fimc_clk_ctrl(ctx, true); 185816102edbSEunchul Kim 185916102edbSEunchul Kim return 0; 186016102edbSEunchul Kim } 186116102edbSEunchul Kim #endif 186216102edbSEunchul Kim 186316102edbSEunchul Kim #ifdef CONFIG_PM_RUNTIME 186416102edbSEunchul Kim static int fimc_runtime_suspend(struct device *dev) 186516102edbSEunchul Kim { 186616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 186716102edbSEunchul Kim 1868cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 186916102edbSEunchul Kim 187016102edbSEunchul Kim return fimc_clk_ctrl(ctx, false); 187116102edbSEunchul Kim } 187216102edbSEunchul Kim 187316102edbSEunchul Kim static int fimc_runtime_resume(struct device *dev) 187416102edbSEunchul Kim { 187516102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 187616102edbSEunchul Kim 1877cbc4c33dSYoungJun Cho DRM_DEBUG_KMS("id[%d]\n", ctx->id); 187816102edbSEunchul Kim 187916102edbSEunchul Kim return fimc_clk_ctrl(ctx, true); 188016102edbSEunchul Kim } 188116102edbSEunchul Kim #endif 188216102edbSEunchul Kim 188316102edbSEunchul Kim static const struct dev_pm_ops fimc_pm_ops = { 188416102edbSEunchul Kim SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) 188516102edbSEunchul Kim SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) 188616102edbSEunchul Kim }; 188716102edbSEunchul Kim 18885186fc5eSSylwester Nawrocki static const struct of_device_id fimc_of_match[] = { 18895186fc5eSSylwester Nawrocki { .compatible = "samsung,exynos4210-fimc" }, 18905186fc5eSSylwester Nawrocki { .compatible = "samsung,exynos4212-fimc" }, 18915186fc5eSSylwester Nawrocki { }, 18925186fc5eSSylwester Nawrocki }; 18935186fc5eSSylwester Nawrocki 189416102edbSEunchul Kim struct platform_driver fimc_driver = { 189516102edbSEunchul Kim .probe = fimc_probe, 189656550d94SGreg Kroah-Hartman .remove = fimc_remove, 189716102edbSEunchul Kim .driver = { 18985186fc5eSSylwester Nawrocki .of_match_table = fimc_of_match, 189916102edbSEunchul Kim .name = "exynos-drm-fimc", 190016102edbSEunchul Kim .owner = THIS_MODULE, 190116102edbSEunchul Kim .pm = &fimc_pm_ops, 190216102edbSEunchul Kim }, 190316102edbSEunchul Kim }; 190416102edbSEunchul Kim 1905