116102edbSEunchul Kim /* 216102edbSEunchul Kim * Copyright (C) 2012 Samsung Electronics Co.Ltd 316102edbSEunchul Kim * Authors: 416102edbSEunchul Kim * Eunchul Kim <chulspro.kim@samsung.com> 516102edbSEunchul Kim * Jinyoung Jeon <jy0.jeon@samsung.com> 616102edbSEunchul Kim * Sangmin Lee <lsmin.lee@samsung.com> 716102edbSEunchul Kim * 816102edbSEunchul Kim * This program is free software; you can redistribute it and/or modify it 916102edbSEunchul Kim * under the terms of the GNU General Public License as published by the 1016102edbSEunchul Kim * Free Software Foundation; either version 2 of the License, or (at your 1116102edbSEunchul Kim * option) any later version. 1216102edbSEunchul Kim * 1316102edbSEunchul Kim */ 1416102edbSEunchul Kim #include <linux/kernel.h> 1516102edbSEunchul Kim #include <linux/module.h> 1616102edbSEunchul Kim #include <linux/platform_device.h> 17a3ad6976SSeung-Woo Kim #include <linux/mfd/syscon.h> 185186fc5eSSylwester Nawrocki #include <linux/regmap.h> 1916102edbSEunchul Kim #include <linux/clk.h> 2016102edbSEunchul Kim #include <linux/pm_runtime.h> 2116102edbSEunchul Kim 2216102edbSEunchul Kim #include <drm/drmP.h> 2316102edbSEunchul Kim #include <drm/exynos_drm.h> 2416102edbSEunchul Kim #include "regs-fimc.h" 2516102edbSEunchul Kim #include "exynos_drm_ipp.h" 2616102edbSEunchul Kim #include "exynos_drm_fimc.h" 2716102edbSEunchul Kim 2816102edbSEunchul Kim /* 296fe891f6SEunchul Kim * FIMC stands for Fully Interactive Mobile Camera and 3016102edbSEunchul Kim * supports image scaler/rotator and input/output DMA operations. 3116102edbSEunchul Kim * input DMA reads image data from the memory. 3216102edbSEunchul Kim * output DMA writes image data to memory. 3316102edbSEunchul Kim * FIMC supports image rotation and image effect functions. 3416102edbSEunchul Kim * 3516102edbSEunchul Kim * M2M operation : supports crop/scale/rotation/csc so on. 3616102edbSEunchul Kim * Memory ----> FIMC H/W ----> Memory. 3716102edbSEunchul Kim * Writeback operation : supports cloned screen with FIMD. 3816102edbSEunchul Kim * FIMD ----> FIMC H/W ----> Memory. 3916102edbSEunchul Kim * Output operation : supports direct display using local path. 4016102edbSEunchul Kim * Memory ----> FIMC H/W ----> FIMD. 4116102edbSEunchul Kim */ 4216102edbSEunchul Kim 4316102edbSEunchul Kim /* 4416102edbSEunchul Kim * TODO 4516102edbSEunchul Kim * 1. check suspend/resume api if needed. 4616102edbSEunchul Kim * 2. need to check use case platform_device_id. 4716102edbSEunchul Kim * 3. check src/dst size with, height. 4816102edbSEunchul Kim * 4. added check_prepare api for right register. 4916102edbSEunchul Kim * 5. need to add supported list in prop_list. 5016102edbSEunchul Kim * 6. check prescaler/scaler optimization. 5116102edbSEunchul Kim */ 5216102edbSEunchul Kim 5316102edbSEunchul Kim #define FIMC_MAX_DEVS 4 5416102edbSEunchul Kim #define FIMC_MAX_SRC 2 5516102edbSEunchul Kim #define FIMC_MAX_DST 32 5616102edbSEunchul Kim #define FIMC_SHFACTOR 10 5716102edbSEunchul Kim #define FIMC_BUF_STOP 1 5816102edbSEunchul Kim #define FIMC_BUF_START 2 5916102edbSEunchul Kim #define FIMC_REG_SZ 32 6016102edbSEunchul Kim #define FIMC_WIDTH_ITU_709 1280 6116102edbSEunchul Kim #define FIMC_REFRESH_MAX 60 6216102edbSEunchul Kim #define FIMC_REFRESH_MIN 12 6316102edbSEunchul Kim #define FIMC_CROP_MAX 8192 6416102edbSEunchul Kim #define FIMC_CROP_MIN 32 6516102edbSEunchul Kim #define FIMC_SCALE_MAX 4224 6616102edbSEunchul Kim #define FIMC_SCALE_MIN 32 6716102edbSEunchul Kim 6816102edbSEunchul Kim #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev)) 6916102edbSEunchul Kim #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ 7016102edbSEunchul Kim struct fimc_context, ippdrv); 7116102edbSEunchul Kim #define fimc_read(offset) readl(ctx->regs + (offset)) 7216102edbSEunchul Kim #define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) 7316102edbSEunchul Kim 7416102edbSEunchul Kim enum fimc_wb { 7516102edbSEunchul Kim FIMC_WB_NONE, 7616102edbSEunchul Kim FIMC_WB_A, 7716102edbSEunchul Kim FIMC_WB_B, 7816102edbSEunchul Kim }; 7916102edbSEunchul Kim 80e5f86839SSylwester Nawrocki enum { 81e5f86839SSylwester Nawrocki FIMC_CLK_LCLK, 82e5f86839SSylwester Nawrocki FIMC_CLK_GATE, 83e5f86839SSylwester Nawrocki FIMC_CLK_WB_A, 84e5f86839SSylwester Nawrocki FIMC_CLK_WB_B, 85e5f86839SSylwester Nawrocki FIMC_CLK_MUX, 86e5f86839SSylwester Nawrocki FIMC_CLK_PARENT, 87e5f86839SSylwester Nawrocki FIMC_CLKS_MAX 88e5f86839SSylwester Nawrocki }; 89e5f86839SSylwester Nawrocki 90e5f86839SSylwester Nawrocki static const char * const fimc_clock_names[] = { 91e5f86839SSylwester Nawrocki [FIMC_CLK_LCLK] = "sclk_fimc", 92e5f86839SSylwester Nawrocki [FIMC_CLK_GATE] = "fimc", 93e5f86839SSylwester Nawrocki [FIMC_CLK_WB_A] = "pxl_async0", 94e5f86839SSylwester Nawrocki [FIMC_CLK_WB_B] = "pxl_async1", 95e5f86839SSylwester Nawrocki [FIMC_CLK_MUX] = "mux", 96e5f86839SSylwester Nawrocki [FIMC_CLK_PARENT] = "parent", 97e5f86839SSylwester Nawrocki }; 98e5f86839SSylwester Nawrocki 99e5f86839SSylwester Nawrocki #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL 100e5f86839SSylwester Nawrocki 10116102edbSEunchul Kim /* 10216102edbSEunchul Kim * A structure of scaler. 10316102edbSEunchul Kim * 10416102edbSEunchul Kim * @range: narrow, wide. 10516102edbSEunchul Kim * @bypass: unused scaler path. 10616102edbSEunchul Kim * @up_h: horizontal scale up. 10716102edbSEunchul Kim * @up_v: vertical scale up. 10816102edbSEunchul Kim * @hratio: horizontal ratio. 10916102edbSEunchul Kim * @vratio: vertical ratio. 11016102edbSEunchul Kim */ 11116102edbSEunchul Kim struct fimc_scaler { 11216102edbSEunchul Kim bool range; 11316102edbSEunchul Kim bool bypass; 11416102edbSEunchul Kim bool up_h; 11516102edbSEunchul Kim bool up_v; 11616102edbSEunchul Kim u32 hratio; 11716102edbSEunchul Kim u32 vratio; 11816102edbSEunchul Kim }; 11916102edbSEunchul Kim 12016102edbSEunchul Kim /* 12116102edbSEunchul Kim * A structure of scaler capability. 12216102edbSEunchul Kim * 12316102edbSEunchul Kim * find user manual table 43-1. 12416102edbSEunchul Kim * @in_hori: scaler input horizontal size. 12516102edbSEunchul Kim * @bypass: scaler bypass mode. 12616102edbSEunchul Kim * @dst_h_wo_rot: target horizontal size without output rotation. 12716102edbSEunchul Kim * @dst_h_rot: target horizontal size with output rotation. 12816102edbSEunchul Kim * @rl_w_wo_rot: real width without input rotation. 12916102edbSEunchul Kim * @rl_h_rot: real height without output rotation. 13016102edbSEunchul Kim */ 13116102edbSEunchul Kim struct fimc_capability { 13216102edbSEunchul Kim /* scaler */ 13316102edbSEunchul Kim u32 in_hori; 13416102edbSEunchul Kim u32 bypass; 13516102edbSEunchul Kim /* output rotator */ 13616102edbSEunchul Kim u32 dst_h_wo_rot; 13716102edbSEunchul Kim u32 dst_h_rot; 13816102edbSEunchul Kim /* input rotator */ 13916102edbSEunchul Kim u32 rl_w_wo_rot; 14016102edbSEunchul Kim u32 rl_h_rot; 14116102edbSEunchul Kim }; 14216102edbSEunchul Kim 14316102edbSEunchul Kim /* 14416102edbSEunchul Kim * A structure of fimc context. 14516102edbSEunchul Kim * 14616102edbSEunchul Kim * @ippdrv: prepare initialization using ippdrv. 14716102edbSEunchul Kim * @regs_res: register resources. 14816102edbSEunchul Kim * @regs: memory mapped io registers. 14916102edbSEunchul Kim * @lock: locking of operations. 150e5f86839SSylwester Nawrocki * @clocks: fimc clocks. 151e5f86839SSylwester Nawrocki * @clk_frequency: LCLK clock frequency. 1525186fc5eSSylwester Nawrocki * @sysreg: handle to SYSREG block regmap. 15316102edbSEunchul Kim * @sc: scaler infomations. 15416102edbSEunchul Kim * @pol: porarity of writeback. 15516102edbSEunchul Kim * @id: fimc id. 15616102edbSEunchul Kim * @irq: irq number. 15716102edbSEunchul Kim * @suspended: qos operations. 15816102edbSEunchul Kim */ 15916102edbSEunchul Kim struct fimc_context { 16016102edbSEunchul Kim struct exynos_drm_ippdrv ippdrv; 16116102edbSEunchul Kim struct resource *regs_res; 16216102edbSEunchul Kim void __iomem *regs; 16316102edbSEunchul Kim struct mutex lock; 164e5f86839SSylwester Nawrocki struct clk *clocks[FIMC_CLKS_MAX]; 165e5f86839SSylwester Nawrocki u32 clk_frequency; 1665186fc5eSSylwester Nawrocki struct regmap *sysreg; 16716102edbSEunchul Kim struct fimc_scaler sc; 16816102edbSEunchul Kim struct exynos_drm_ipp_pol pol; 16916102edbSEunchul Kim int id; 17016102edbSEunchul Kim int irq; 17116102edbSEunchul Kim bool suspended; 17216102edbSEunchul Kim }; 17316102edbSEunchul Kim 174b5c0b552SJoongMock Shin static void fimc_sw_reset(struct fimc_context *ctx) 17516102edbSEunchul Kim { 17616102edbSEunchul Kim u32 cfg; 17716102edbSEunchul Kim 178b5c0b552SJoongMock Shin DRM_DEBUG_KMS("%s\n", __func__); 17916102edbSEunchul Kim 180e39d5ce1SJinyoung Jeon /* stop dma operation */ 181e39d5ce1SJinyoung Jeon cfg = fimc_read(EXYNOS_CISTATUS); 182e39d5ce1SJinyoung Jeon if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) { 183e39d5ce1SJinyoung Jeon cfg = fimc_read(EXYNOS_MSCTRL); 184e39d5ce1SJinyoung Jeon cfg &= ~EXYNOS_MSCTRL_ENVID; 185e39d5ce1SJinyoung Jeon fimc_write(cfg, EXYNOS_MSCTRL); 186e39d5ce1SJinyoung Jeon } 18716102edbSEunchul Kim 18816102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISRCFMT); 18916102edbSEunchul Kim cfg |= EXYNOS_CISRCFMT_ITU601_8BIT; 19016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISRCFMT); 19116102edbSEunchul Kim 192e39d5ce1SJinyoung Jeon /* disable image capture */ 193e39d5ce1SJinyoung Jeon cfg = fimc_read(EXYNOS_CIIMGCPT); 194e39d5ce1SJinyoung Jeon cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 195e39d5ce1SJinyoung Jeon fimc_write(cfg, EXYNOS_CIIMGCPT); 196e39d5ce1SJinyoung Jeon 19716102edbSEunchul Kim /* s/w reset */ 19816102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 19916102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SWRST); 20016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 20116102edbSEunchul Kim 20216102edbSEunchul Kim /* s/w reset complete */ 20316102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 20416102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_SWRST; 20516102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 20616102edbSEunchul Kim 20716102edbSEunchul Kim /* reset sequence */ 20816102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIFCNTSEQ); 20916102edbSEunchul Kim } 21016102edbSEunchul Kim 2115186fc5eSSylwester Nawrocki static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx) 21216102edbSEunchul Kim { 21316102edbSEunchul Kim DRM_DEBUG_KMS("%s\n", __func__); 21416102edbSEunchul Kim 2155186fc5eSSylwester Nawrocki return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK, 2165186fc5eSSylwester Nawrocki SYSREG_FIMD0WB_DEST_MASK, 2175186fc5eSSylwester Nawrocki ctx->id << SYSREG_FIMD0WB_DEST_SHIFT); 21816102edbSEunchul Kim } 21916102edbSEunchul Kim 22016102edbSEunchul Kim static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb) 22116102edbSEunchul Kim { 22216102edbSEunchul Kim u32 cfg; 22316102edbSEunchul Kim 22416102edbSEunchul Kim DRM_DEBUG_KMS("%s:wb[%d]\n", __func__, wb); 22516102edbSEunchul Kim 22616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 22716102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | 22816102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_ITU_MASK | 22916102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_MIPI_MASK | 23016102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_FIMC_MASK | 23116102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_MASK | 23216102edbSEunchul Kim EXYNOS_CIGCTRL_SELWRITEBACK_MASK); 23316102edbSEunchul Kim 23416102edbSEunchul Kim switch (wb) { 23516102edbSEunchul Kim case FIMC_WB_A: 23616102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A | 23716102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 23816102edbSEunchul Kim break; 23916102edbSEunchul Kim case FIMC_WB_B: 24016102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B | 24116102edbSEunchul Kim EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK); 24216102edbSEunchul Kim break; 24316102edbSEunchul Kim case FIMC_WB_NONE: 24416102edbSEunchul Kim default: 24516102edbSEunchul Kim cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | 24616102edbSEunchul Kim EXYNOS_CIGCTRL_SELWRITEBACK_A | 24716102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_MIPI_A | 24816102edbSEunchul Kim EXYNOS_CIGCTRL_SELCAM_FIMC_ITU); 24916102edbSEunchul Kim break; 25016102edbSEunchul Kim } 25116102edbSEunchul Kim 25216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 25316102edbSEunchul Kim } 25416102edbSEunchul Kim 25516102edbSEunchul Kim static void fimc_set_polarity(struct fimc_context *ctx, 25616102edbSEunchul Kim struct exynos_drm_ipp_pol *pol) 25716102edbSEunchul Kim { 25816102edbSEunchul Kim u32 cfg; 25916102edbSEunchul Kim 26016102edbSEunchul Kim DRM_DEBUG_KMS("%s:inv_pclk[%d]inv_vsync[%d]\n", 26116102edbSEunchul Kim __func__, pol->inv_pclk, pol->inv_vsync); 26216102edbSEunchul Kim DRM_DEBUG_KMS("%s:inv_href[%d]inv_hsync[%d]\n", 26316102edbSEunchul Kim __func__, pol->inv_href, pol->inv_hsync); 26416102edbSEunchul Kim 26516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 26616102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC | 26716102edbSEunchul Kim EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC); 26816102edbSEunchul Kim 26916102edbSEunchul Kim if (pol->inv_pclk) 27016102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLPCLK; 27116102edbSEunchul Kim if (pol->inv_vsync) 27216102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC; 27316102edbSEunchul Kim if (pol->inv_href) 27416102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLHREF; 27516102edbSEunchul Kim if (pol->inv_hsync) 27616102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC; 27716102edbSEunchul Kim 27816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 27916102edbSEunchul Kim } 28016102edbSEunchul Kim 28116102edbSEunchul Kim static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable) 28216102edbSEunchul Kim { 28316102edbSEunchul Kim u32 cfg; 28416102edbSEunchul Kim 28516102edbSEunchul Kim DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable); 28616102edbSEunchul Kim 28716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 28816102edbSEunchul Kim if (enable) 28916102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CAM_JPEG; 29016102edbSEunchul Kim else 29116102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG; 29216102edbSEunchul Kim 29316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 29416102edbSEunchul Kim } 29516102edbSEunchul Kim 29616102edbSEunchul Kim static void fimc_handle_irq(struct fimc_context *ctx, bool enable, 29716102edbSEunchul Kim bool overflow, bool level) 29816102edbSEunchul Kim { 29916102edbSEunchul Kim u32 cfg; 30016102edbSEunchul Kim 30116102edbSEunchul Kim DRM_DEBUG_KMS("%s:enable[%d]overflow[%d]level[%d]\n", __func__, 30216102edbSEunchul Kim enable, overflow, level); 30316102edbSEunchul Kim 30416102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 30516102edbSEunchul Kim if (enable) { 30616102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL); 30716102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE; 30816102edbSEunchul Kim if (overflow) 30916102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN; 31016102edbSEunchul Kim if (level) 31116102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL; 31216102edbSEunchul Kim } else 31316102edbSEunchul Kim cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE); 31416102edbSEunchul Kim 31516102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 31616102edbSEunchul Kim } 31716102edbSEunchul Kim 31816102edbSEunchul Kim static void fimc_clear_irq(struct fimc_context *ctx) 31916102edbSEunchul Kim { 32016102edbSEunchul Kim u32 cfg; 32116102edbSEunchul Kim 32216102edbSEunchul Kim DRM_DEBUG_KMS("%s\n", __func__); 32316102edbSEunchul Kim 32416102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 32516102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_CLR; 32616102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 32716102edbSEunchul Kim } 32816102edbSEunchul Kim 32916102edbSEunchul Kim static bool fimc_check_ovf(struct fimc_context *ctx) 33016102edbSEunchul Kim { 33116102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 33216102edbSEunchul Kim u32 cfg, status, flag; 33316102edbSEunchul Kim 33416102edbSEunchul Kim status = fimc_read(EXYNOS_CISTATUS); 33516102edbSEunchul Kim flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB | 33616102edbSEunchul Kim EXYNOS_CISTATUS_OVFICR; 33716102edbSEunchul Kim 33816102edbSEunchul Kim DRM_DEBUG_KMS("%s:flag[0x%x]\n", __func__, flag); 33916102edbSEunchul Kim 34016102edbSEunchul Kim if (status & flag) { 34116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIWDOFST); 34216102edbSEunchul Kim cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 34316102edbSEunchul Kim EXYNOS_CIWDOFST_CLROVFICR); 34416102edbSEunchul Kim 34516102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST); 34616102edbSEunchul Kim 34716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIWDOFST); 34816102edbSEunchul Kim cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB | 34916102edbSEunchul Kim EXYNOS_CIWDOFST_CLROVFICR); 35016102edbSEunchul Kim 35116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST); 35216102edbSEunchul Kim 35316102edbSEunchul Kim dev_err(ippdrv->dev, "occured overflow at %d, status 0x%x.\n", 35416102edbSEunchul Kim ctx->id, status); 35516102edbSEunchul Kim return true; 35616102edbSEunchul Kim } 35716102edbSEunchul Kim 35816102edbSEunchul Kim return false; 35916102edbSEunchul Kim } 36016102edbSEunchul Kim 36116102edbSEunchul Kim static bool fimc_check_frame_end(struct fimc_context *ctx) 36216102edbSEunchul Kim { 36316102edbSEunchul Kim u32 cfg; 36416102edbSEunchul Kim 36516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISTATUS); 36616102edbSEunchul Kim 36716102edbSEunchul Kim DRM_DEBUG_KMS("%s:cfg[0x%x]\n", __func__, cfg); 36816102edbSEunchul Kim 36916102edbSEunchul Kim if (!(cfg & EXYNOS_CISTATUS_FRAMEEND)) 37016102edbSEunchul Kim return false; 37116102edbSEunchul Kim 37216102edbSEunchul Kim cfg &= ~(EXYNOS_CISTATUS_FRAMEEND); 37316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISTATUS); 37416102edbSEunchul Kim 37516102edbSEunchul Kim return true; 37616102edbSEunchul Kim } 37716102edbSEunchul Kim 37816102edbSEunchul Kim static int fimc_get_buf_id(struct fimc_context *ctx) 37916102edbSEunchul Kim { 38016102edbSEunchul Kim u32 cfg; 38116102edbSEunchul Kim int frame_cnt, buf_id; 38216102edbSEunchul Kim 38316102edbSEunchul Kim DRM_DEBUG_KMS("%s\n", __func__); 38416102edbSEunchul Kim 38516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISTATUS2); 38616102edbSEunchul Kim frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg); 38716102edbSEunchul Kim 38816102edbSEunchul Kim if (frame_cnt == 0) 38916102edbSEunchul Kim frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg); 39016102edbSEunchul Kim 39116102edbSEunchul Kim DRM_DEBUG_KMS("%s:present[%d]before[%d]\n", __func__, 39216102edbSEunchul Kim EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg), 39316102edbSEunchul Kim EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg)); 39416102edbSEunchul Kim 39516102edbSEunchul Kim if (frame_cnt == 0) { 39616102edbSEunchul Kim DRM_ERROR("failed to get frame count.\n"); 39716102edbSEunchul Kim return -EIO; 39816102edbSEunchul Kim } 39916102edbSEunchul Kim 40016102edbSEunchul Kim buf_id = frame_cnt - 1; 40116102edbSEunchul Kim DRM_DEBUG_KMS("%s:buf_id[%d]\n", __func__, buf_id); 40216102edbSEunchul Kim 40316102edbSEunchul Kim return buf_id; 40416102edbSEunchul Kim } 40516102edbSEunchul Kim 40616102edbSEunchul Kim static void fimc_handle_lastend(struct fimc_context *ctx, bool enable) 40716102edbSEunchul Kim { 40816102edbSEunchul Kim u32 cfg; 40916102edbSEunchul Kim 41016102edbSEunchul Kim DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable); 41116102edbSEunchul Kim 41216102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIOCTRL); 41316102edbSEunchul Kim if (enable) 41416102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_LASTENDEN; 41516102edbSEunchul Kim else 41616102edbSEunchul Kim cfg &= ~EXYNOS_CIOCTRL_LASTENDEN; 41716102edbSEunchul Kim 41816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCTRL); 41916102edbSEunchul Kim } 42016102edbSEunchul Kim 42116102edbSEunchul Kim 42216102edbSEunchul Kim static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) 42316102edbSEunchul Kim { 42416102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 42516102edbSEunchul Kim u32 cfg; 42616102edbSEunchul Kim 42716102edbSEunchul Kim DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt); 42816102edbSEunchul Kim 42916102edbSEunchul Kim /* RGB */ 43016102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 43116102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK; 43216102edbSEunchul Kim 43316102edbSEunchul Kim switch (fmt) { 43416102edbSEunchul Kim case DRM_FORMAT_RGB565: 43516102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565; 43616102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 43716102edbSEunchul Kim return 0; 43816102edbSEunchul Kim case DRM_FORMAT_RGB888: 43916102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 44016102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888; 44116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 44216102edbSEunchul Kim return 0; 44316102edbSEunchul Kim default: 44416102edbSEunchul Kim /* bypass */ 44516102edbSEunchul Kim break; 44616102edbSEunchul Kim } 44716102edbSEunchul Kim 44816102edbSEunchul Kim /* YUV */ 44916102edbSEunchul Kim cfg = fimc_read(EXYNOS_MSCTRL); 45016102edbSEunchul Kim cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK | 45116102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE | 45216102edbSEunchul Kim EXYNOS_MSCTRL_ORDER422_YCBYCR); 45316102edbSEunchul Kim 45416102edbSEunchul Kim switch (fmt) { 45516102edbSEunchul Kim case DRM_FORMAT_YUYV: 45616102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR; 45716102edbSEunchul Kim break; 45816102edbSEunchul Kim case DRM_FORMAT_YVYU: 45916102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB; 46016102edbSEunchul Kim break; 46116102edbSEunchul Kim case DRM_FORMAT_UYVY: 46216102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY; 46316102edbSEunchul Kim break; 46416102edbSEunchul Kim case DRM_FORMAT_VYUY: 46516102edbSEunchul Kim case DRM_FORMAT_YUV444: 46616102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY; 46716102edbSEunchul Kim break; 46816102edbSEunchul Kim case DRM_FORMAT_NV21: 46916102edbSEunchul Kim case DRM_FORMAT_NV61: 47016102edbSEunchul Kim cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB | 47116102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE); 47216102edbSEunchul Kim break; 47316102edbSEunchul Kim case DRM_FORMAT_YUV422: 47416102edbSEunchul Kim case DRM_FORMAT_YUV420: 47516102edbSEunchul Kim case DRM_FORMAT_YVU420: 47616102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE; 47716102edbSEunchul Kim break; 47816102edbSEunchul Kim case DRM_FORMAT_NV12: 47916102edbSEunchul Kim case DRM_FORMAT_NV12MT: 48016102edbSEunchul Kim case DRM_FORMAT_NV16: 48116102edbSEunchul Kim cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR | 48216102edbSEunchul Kim EXYNOS_MSCTRL_C_INT_IN_2PLANE); 48316102edbSEunchul Kim break; 48416102edbSEunchul Kim default: 48516102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt); 48616102edbSEunchul Kim return -EINVAL; 48716102edbSEunchul Kim } 48816102edbSEunchul Kim 48916102edbSEunchul Kim fimc_write(cfg, EXYNOS_MSCTRL); 49016102edbSEunchul Kim 49116102edbSEunchul Kim return 0; 49216102edbSEunchul Kim } 49316102edbSEunchul Kim 49416102edbSEunchul Kim static int fimc_src_set_fmt(struct device *dev, u32 fmt) 49516102edbSEunchul Kim { 49616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 49716102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 49816102edbSEunchul Kim u32 cfg; 49916102edbSEunchul Kim 50016102edbSEunchul Kim DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt); 50116102edbSEunchul Kim 50216102edbSEunchul Kim cfg = fimc_read(EXYNOS_MSCTRL); 50316102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB; 50416102edbSEunchul Kim 50516102edbSEunchul Kim switch (fmt) { 50616102edbSEunchul Kim case DRM_FORMAT_RGB565: 50716102edbSEunchul Kim case DRM_FORMAT_RGB888: 50816102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 50916102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_RGB; 51016102edbSEunchul Kim break; 51116102edbSEunchul Kim case DRM_FORMAT_YUV444: 51216102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 51316102edbSEunchul Kim break; 51416102edbSEunchul Kim case DRM_FORMAT_YUYV: 51516102edbSEunchul Kim case DRM_FORMAT_YVYU: 51616102edbSEunchul Kim case DRM_FORMAT_UYVY: 51716102edbSEunchul Kim case DRM_FORMAT_VYUY: 51816102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE; 51916102edbSEunchul Kim break; 52016102edbSEunchul Kim case DRM_FORMAT_NV16: 52116102edbSEunchul Kim case DRM_FORMAT_NV61: 52216102edbSEunchul Kim case DRM_FORMAT_YUV422: 52316102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422; 52416102edbSEunchul Kim break; 52516102edbSEunchul Kim case DRM_FORMAT_YUV420: 52616102edbSEunchul Kim case DRM_FORMAT_YVU420: 52716102edbSEunchul Kim case DRM_FORMAT_NV12: 52816102edbSEunchul Kim case DRM_FORMAT_NV21: 52916102edbSEunchul Kim case DRM_FORMAT_NV12MT: 53016102edbSEunchul Kim cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; 53116102edbSEunchul Kim break; 53216102edbSEunchul Kim default: 53316102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt); 53416102edbSEunchul Kim return -EINVAL; 53516102edbSEunchul Kim } 53616102edbSEunchul Kim 53716102edbSEunchul Kim fimc_write(cfg, EXYNOS_MSCTRL); 53816102edbSEunchul Kim 53916102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIDMAPARAM); 54016102edbSEunchul Kim cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK; 54116102edbSEunchul Kim 54216102edbSEunchul Kim if (fmt == DRM_FORMAT_NV12MT) 54316102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32; 54416102edbSEunchul Kim else 54516102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR; 54616102edbSEunchul Kim 54716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIDMAPARAM); 54816102edbSEunchul Kim 54916102edbSEunchul Kim return fimc_src_set_fmt_order(ctx, fmt); 55016102edbSEunchul Kim } 55116102edbSEunchul Kim 55216102edbSEunchul Kim static int fimc_src_set_transf(struct device *dev, 55316102edbSEunchul Kim enum drm_exynos_degree degree, 55416102edbSEunchul Kim enum drm_exynos_flip flip, bool *swap) 55516102edbSEunchul Kim { 55616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 55716102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 55816102edbSEunchul Kim u32 cfg1, cfg2; 55916102edbSEunchul Kim 56016102edbSEunchul Kim DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__, 56116102edbSEunchul Kim degree, flip); 56216102edbSEunchul Kim 56316102edbSEunchul Kim cfg1 = fimc_read(EXYNOS_MSCTRL); 56416102edbSEunchul Kim cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR | 56516102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 56616102edbSEunchul Kim 56716102edbSEunchul Kim cfg2 = fimc_read(EXYNOS_CITRGFMT); 56816102edbSEunchul Kim cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 56916102edbSEunchul Kim 57016102edbSEunchul Kim switch (degree) { 57116102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 57216102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 57316102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 57416102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 57516102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 57616102edbSEunchul Kim break; 57716102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 57816102edbSEunchul Kim cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 57916102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 58016102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR; 58116102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 58216102edbSEunchul Kim cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR; 58316102edbSEunchul Kim break; 58416102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 58516102edbSEunchul Kim cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 58616102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 58716102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 58816102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 58916102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 59016102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 59116102edbSEunchul Kim break; 59216102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 59316102edbSEunchul Kim cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR | 59416102edbSEunchul Kim EXYNOS_MSCTRL_FLIP_Y_MIRROR); 59516102edbSEunchul Kim cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE; 59616102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 59716102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR; 59816102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 59916102edbSEunchul Kim cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; 60016102edbSEunchul Kim break; 60116102edbSEunchul Kim default: 60216102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 60316102edbSEunchul Kim return -EINVAL; 60416102edbSEunchul Kim } 60516102edbSEunchul Kim 60616102edbSEunchul Kim fimc_write(cfg1, EXYNOS_MSCTRL); 60716102edbSEunchul Kim fimc_write(cfg2, EXYNOS_CITRGFMT); 60816102edbSEunchul Kim *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0; 60916102edbSEunchul Kim 61016102edbSEunchul Kim return 0; 61116102edbSEunchul Kim } 61216102edbSEunchul Kim 61316102edbSEunchul Kim static int fimc_set_window(struct fimc_context *ctx, 61416102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 61516102edbSEunchul Kim { 61616102edbSEunchul Kim u32 cfg, h1, h2, v1, v2; 61716102edbSEunchul Kim 61816102edbSEunchul Kim /* cropped image */ 61916102edbSEunchul Kim h1 = pos->x; 62016102edbSEunchul Kim h2 = sz->hsize - pos->w - pos->x; 62116102edbSEunchul Kim v1 = pos->y; 62216102edbSEunchul Kim v2 = sz->vsize - pos->h - pos->y; 62316102edbSEunchul Kim 62416102edbSEunchul Kim DRM_DEBUG_KMS("%s:x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n", 62516102edbSEunchul Kim __func__, pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize); 62616102edbSEunchul Kim DRM_DEBUG_KMS("%s:h1[%d]h2[%d]v1[%d]v2[%d]\n", __func__, 62716102edbSEunchul Kim h1, h2, v1, v2); 62816102edbSEunchul Kim 62916102edbSEunchul Kim /* 63016102edbSEunchul Kim * set window offset 1, 2 size 63116102edbSEunchul Kim * check figure 43-21 in user manual 63216102edbSEunchul Kim */ 63316102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIWDOFST); 63416102edbSEunchul Kim cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK | 63516102edbSEunchul Kim EXYNOS_CIWDOFST_WINVEROFST_MASK); 63616102edbSEunchul Kim cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) | 63716102edbSEunchul Kim EXYNOS_CIWDOFST_WINVEROFST(v1)); 63816102edbSEunchul Kim cfg |= EXYNOS_CIWDOFST_WINOFSEN; 63916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST); 64016102edbSEunchul Kim 64116102edbSEunchul Kim cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) | 64216102edbSEunchul Kim EXYNOS_CIWDOFST2_WINVEROFST2(v2)); 64316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIWDOFST2); 64416102edbSEunchul Kim 64516102edbSEunchul Kim return 0; 64616102edbSEunchul Kim } 64716102edbSEunchul Kim 64816102edbSEunchul Kim static int fimc_src_set_size(struct device *dev, int swap, 64916102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 65016102edbSEunchul Kim { 65116102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 65216102edbSEunchul Kim struct drm_exynos_pos img_pos = *pos; 65316102edbSEunchul Kim struct drm_exynos_sz img_sz = *sz; 65416102edbSEunchul Kim u32 cfg; 65516102edbSEunchul Kim 65616102edbSEunchul Kim DRM_DEBUG_KMS("%s:swap[%d]hsize[%d]vsize[%d]\n", 65716102edbSEunchul Kim __func__, swap, sz->hsize, sz->vsize); 65816102edbSEunchul Kim 65916102edbSEunchul Kim /* original size */ 66016102edbSEunchul Kim cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) | 66116102edbSEunchul Kim EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize)); 66216102edbSEunchul Kim 66316102edbSEunchul Kim fimc_write(cfg, EXYNOS_ORGISIZE); 66416102edbSEunchul Kim 66516102edbSEunchul Kim DRM_DEBUG_KMS("%s:x[%d]y[%d]w[%d]h[%d]\n", __func__, 66616102edbSEunchul Kim pos->x, pos->y, pos->w, pos->h); 66716102edbSEunchul Kim 66816102edbSEunchul Kim if (swap) { 66916102edbSEunchul Kim img_pos.w = pos->h; 67016102edbSEunchul Kim img_pos.h = pos->w; 67116102edbSEunchul Kim img_sz.hsize = sz->vsize; 67216102edbSEunchul Kim img_sz.vsize = sz->hsize; 67316102edbSEunchul Kim } 67416102edbSEunchul Kim 67516102edbSEunchul Kim /* set input DMA image size */ 67616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIREAL_ISIZE); 67716102edbSEunchul Kim cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK | 67816102edbSEunchul Kim EXYNOS_CIREAL_ISIZE_WIDTH_MASK); 67916102edbSEunchul Kim cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) | 68016102edbSEunchul Kim EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h)); 68116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIREAL_ISIZE); 68216102edbSEunchul Kim 68316102edbSEunchul Kim /* 68416102edbSEunchul Kim * set input FIFO image size 68516102edbSEunchul Kim * for now, we support only ITU601 8 bit mode 68616102edbSEunchul Kim */ 68716102edbSEunchul Kim cfg = (EXYNOS_CISRCFMT_ITU601_8BIT | 68816102edbSEunchul Kim EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) | 68916102edbSEunchul Kim EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize)); 69016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISRCFMT); 69116102edbSEunchul Kim 69216102edbSEunchul Kim /* offset Y(RGB), Cb, Cr */ 69316102edbSEunchul Kim cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) | 69416102edbSEunchul Kim EXYNOS_CIIYOFF_VERTICAL(img_pos.y)); 69516102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIIYOFF); 69616102edbSEunchul Kim cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) | 69716102edbSEunchul Kim EXYNOS_CIICBOFF_VERTICAL(img_pos.y)); 69816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIICBOFF); 69916102edbSEunchul Kim cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) | 70016102edbSEunchul Kim EXYNOS_CIICROFF_VERTICAL(img_pos.y)); 70116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIICROFF); 70216102edbSEunchul Kim 70316102edbSEunchul Kim return fimc_set_window(ctx, &img_pos, &img_sz); 70416102edbSEunchul Kim } 70516102edbSEunchul Kim 70616102edbSEunchul Kim static int fimc_src_set_addr(struct device *dev, 70716102edbSEunchul Kim struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 70816102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 70916102edbSEunchul Kim { 71016102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 71116102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 7127259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 71316102edbSEunchul Kim struct drm_exynos_ipp_property *property; 71416102edbSEunchul Kim struct drm_exynos_ipp_config *config; 71516102edbSEunchul Kim 71616102edbSEunchul Kim if (!c_node) { 71716102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 71816102edbSEunchul Kim return -EINVAL; 71916102edbSEunchul Kim } 72016102edbSEunchul Kim 72116102edbSEunchul Kim property = &c_node->property; 72216102edbSEunchul Kim 72316102edbSEunchul Kim DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__, 72416102edbSEunchul Kim property->prop_id, buf_id, buf_type); 72516102edbSEunchul Kim 72616102edbSEunchul Kim if (buf_id > FIMC_MAX_SRC) { 72716102edbSEunchul Kim dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 72816102edbSEunchul Kim return -ENOMEM; 72916102edbSEunchul Kim } 73016102edbSEunchul Kim 73116102edbSEunchul Kim /* address register set */ 73216102edbSEunchul Kim switch (buf_type) { 73316102edbSEunchul Kim case IPP_BUF_ENQUEUE: 73416102edbSEunchul Kim config = &property->config[EXYNOS_DRM_OPS_SRC]; 73516102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 73616102edbSEunchul Kim EXYNOS_CIIYSA(buf_id)); 73716102edbSEunchul Kim 73816102edbSEunchul Kim if (config->fmt == DRM_FORMAT_YVU420) { 73916102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 74016102edbSEunchul Kim EXYNOS_CIICBSA(buf_id)); 74116102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 74216102edbSEunchul Kim EXYNOS_CIICRSA(buf_id)); 74316102edbSEunchul Kim } else { 74416102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 74516102edbSEunchul Kim EXYNOS_CIICBSA(buf_id)); 74616102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 74716102edbSEunchul Kim EXYNOS_CIICRSA(buf_id)); 74816102edbSEunchul Kim } 74916102edbSEunchul Kim break; 75016102edbSEunchul Kim case IPP_BUF_DEQUEUE: 75116102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIIYSA(buf_id)); 75216102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIICBSA(buf_id)); 75316102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIICRSA(buf_id)); 75416102edbSEunchul Kim break; 75516102edbSEunchul Kim default: 75616102edbSEunchul Kim /* bypass */ 75716102edbSEunchul Kim break; 75816102edbSEunchul Kim } 75916102edbSEunchul Kim 76016102edbSEunchul Kim return 0; 76116102edbSEunchul Kim } 76216102edbSEunchul Kim 76316102edbSEunchul Kim static struct exynos_drm_ipp_ops fimc_src_ops = { 76416102edbSEunchul Kim .set_fmt = fimc_src_set_fmt, 76516102edbSEunchul Kim .set_transf = fimc_src_set_transf, 76616102edbSEunchul Kim .set_size = fimc_src_set_size, 76716102edbSEunchul Kim .set_addr = fimc_src_set_addr, 76816102edbSEunchul Kim }; 76916102edbSEunchul Kim 77016102edbSEunchul Kim static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) 77116102edbSEunchul Kim { 77216102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 77316102edbSEunchul Kim u32 cfg; 77416102edbSEunchul Kim 77516102edbSEunchul Kim DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt); 77616102edbSEunchul Kim 77716102edbSEunchul Kim /* RGB */ 77816102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 77916102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK; 78016102edbSEunchul Kim 78116102edbSEunchul Kim switch (fmt) { 78216102edbSEunchul Kim case DRM_FORMAT_RGB565: 78316102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565; 78416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 78516102edbSEunchul Kim return 0; 78616102edbSEunchul Kim case DRM_FORMAT_RGB888: 78716102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888; 78816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 78916102edbSEunchul Kim return 0; 79016102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 79116102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 | 79216102edbSEunchul Kim EXYNOS_CISCCTRL_EXTRGB_EXTENSION); 79316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 79416102edbSEunchul Kim break; 79516102edbSEunchul Kim default: 79616102edbSEunchul Kim /* bypass */ 79716102edbSEunchul Kim break; 79816102edbSEunchul Kim } 79916102edbSEunchul Kim 80016102edbSEunchul Kim /* YUV */ 80116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIOCTRL); 80216102edbSEunchul Kim cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK | 80316102edbSEunchul Kim EXYNOS_CIOCTRL_ORDER422_MASK | 80416102edbSEunchul Kim EXYNOS_CIOCTRL_YCBCR_PLANE_MASK); 80516102edbSEunchul Kim 80616102edbSEunchul Kim switch (fmt) { 80716102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 80816102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ALPHA_OUT; 80916102edbSEunchul Kim break; 81016102edbSEunchul Kim case DRM_FORMAT_YUYV: 81116102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR; 81216102edbSEunchul Kim break; 81316102edbSEunchul Kim case DRM_FORMAT_YVYU: 81416102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB; 81516102edbSEunchul Kim break; 81616102edbSEunchul Kim case DRM_FORMAT_UYVY: 81716102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY; 81816102edbSEunchul Kim break; 81916102edbSEunchul Kim case DRM_FORMAT_VYUY: 82016102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY; 82116102edbSEunchul Kim break; 82216102edbSEunchul Kim case DRM_FORMAT_NV21: 82316102edbSEunchul Kim case DRM_FORMAT_NV61: 82416102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB; 82516102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 82616102edbSEunchul Kim break; 82716102edbSEunchul Kim case DRM_FORMAT_YUV422: 82816102edbSEunchul Kim case DRM_FORMAT_YUV420: 82916102edbSEunchul Kim case DRM_FORMAT_YVU420: 83016102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE; 83116102edbSEunchul Kim break; 83216102edbSEunchul Kim case DRM_FORMAT_NV12: 83316102edbSEunchul Kim case DRM_FORMAT_NV12MT: 83416102edbSEunchul Kim case DRM_FORMAT_NV16: 83516102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR; 83616102edbSEunchul Kim cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; 83716102edbSEunchul Kim break; 83816102edbSEunchul Kim default: 83916102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); 84016102edbSEunchul Kim return -EINVAL; 84116102edbSEunchul Kim } 84216102edbSEunchul Kim 84316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCTRL); 84416102edbSEunchul Kim 84516102edbSEunchul Kim return 0; 84616102edbSEunchul Kim } 84716102edbSEunchul Kim 84816102edbSEunchul Kim static int fimc_dst_set_fmt(struct device *dev, u32 fmt) 84916102edbSEunchul Kim { 85016102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 85116102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 85216102edbSEunchul Kim u32 cfg; 85316102edbSEunchul Kim 85416102edbSEunchul Kim DRM_DEBUG_KMS("%s:fmt[0x%x]\n", __func__, fmt); 85516102edbSEunchul Kim 85616102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIEXTEN); 85716102edbSEunchul Kim 85816102edbSEunchul Kim if (fmt == DRM_FORMAT_AYUV) { 85916102edbSEunchul Kim cfg |= EXYNOS_CIEXTEN_YUV444_OUT; 86016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIEXTEN); 86116102edbSEunchul Kim } else { 86216102edbSEunchul Kim cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT; 86316102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIEXTEN); 86416102edbSEunchul Kim 86516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CITRGFMT); 86616102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK; 86716102edbSEunchul Kim 86816102edbSEunchul Kim switch (fmt) { 86916102edbSEunchul Kim case DRM_FORMAT_RGB565: 87016102edbSEunchul Kim case DRM_FORMAT_RGB888: 87116102edbSEunchul Kim case DRM_FORMAT_XRGB8888: 87216102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB; 87316102edbSEunchul Kim break; 87416102edbSEunchul Kim case DRM_FORMAT_YUYV: 87516102edbSEunchul Kim case DRM_FORMAT_YVYU: 87616102edbSEunchul Kim case DRM_FORMAT_UYVY: 87716102edbSEunchul Kim case DRM_FORMAT_VYUY: 87816102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE; 87916102edbSEunchul Kim break; 88016102edbSEunchul Kim case DRM_FORMAT_NV16: 88116102edbSEunchul Kim case DRM_FORMAT_NV61: 88216102edbSEunchul Kim case DRM_FORMAT_YUV422: 88316102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422; 88416102edbSEunchul Kim break; 88516102edbSEunchul Kim case DRM_FORMAT_YUV420: 88616102edbSEunchul Kim case DRM_FORMAT_YVU420: 88716102edbSEunchul Kim case DRM_FORMAT_NV12: 88816102edbSEunchul Kim case DRM_FORMAT_NV12MT: 88916102edbSEunchul Kim case DRM_FORMAT_NV21: 89016102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; 89116102edbSEunchul Kim break; 89216102edbSEunchul Kim default: 89316102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid target format 0x%x.\n", 89416102edbSEunchul Kim fmt); 89516102edbSEunchul Kim return -EINVAL; 89616102edbSEunchul Kim } 89716102edbSEunchul Kim 89816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITRGFMT); 89916102edbSEunchul Kim } 90016102edbSEunchul Kim 90116102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIDMAPARAM); 90216102edbSEunchul Kim cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK; 90316102edbSEunchul Kim 90416102edbSEunchul Kim if (fmt == DRM_FORMAT_NV12MT) 90516102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32; 90616102edbSEunchul Kim else 90716102edbSEunchul Kim cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR; 90816102edbSEunchul Kim 90916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIDMAPARAM); 91016102edbSEunchul Kim 91116102edbSEunchul Kim return fimc_dst_set_fmt_order(ctx, fmt); 91216102edbSEunchul Kim } 91316102edbSEunchul Kim 91416102edbSEunchul Kim static int fimc_dst_set_transf(struct device *dev, 91516102edbSEunchul Kim enum drm_exynos_degree degree, 91616102edbSEunchul Kim enum drm_exynos_flip flip, bool *swap) 91716102edbSEunchul Kim { 91816102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 91916102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 92016102edbSEunchul Kim u32 cfg; 92116102edbSEunchul Kim 92216102edbSEunchul Kim DRM_DEBUG_KMS("%s:degree[%d]flip[0x%x]\n", __func__, 92316102edbSEunchul Kim degree, flip); 92416102edbSEunchul Kim 92516102edbSEunchul Kim cfg = fimc_read(EXYNOS_CITRGFMT); 92616102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK; 92716102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 92816102edbSEunchul Kim 92916102edbSEunchul Kim switch (degree) { 93016102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 93116102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 93216102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 93316102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 93416102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 93516102edbSEunchul Kim break; 93616102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 93716102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE; 93816102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 93916102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR; 94016102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 94116102edbSEunchul Kim cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 94216102edbSEunchul Kim break; 94316102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 94416102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR | 94516102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 94616102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 94716102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 94816102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 94916102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 95016102edbSEunchul Kim break; 95116102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 95216102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE | 95316102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_X_MIRROR | 95416102edbSEunchul Kim EXYNOS_CITRGFMT_FLIP_Y_MIRROR); 95516102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_VERTICAL) 95616102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR; 95716102edbSEunchul Kim if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) 95816102edbSEunchul Kim cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; 95916102edbSEunchul Kim break; 96016102edbSEunchul Kim default: 96116102edbSEunchul Kim dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); 96216102edbSEunchul Kim return -EINVAL; 96316102edbSEunchul Kim } 96416102edbSEunchul Kim 96516102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITRGFMT); 96616102edbSEunchul Kim *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0; 96716102edbSEunchul Kim 96816102edbSEunchul Kim return 0; 96916102edbSEunchul Kim } 97016102edbSEunchul Kim 97116102edbSEunchul Kim static int fimc_get_ratio_shift(u32 src, u32 dst, u32 *ratio, u32 *shift) 97216102edbSEunchul Kim { 97316102edbSEunchul Kim DRM_DEBUG_KMS("%s:src[%d]dst[%d]\n", __func__, src, dst); 97416102edbSEunchul Kim 97516102edbSEunchul Kim if (src >= dst * 64) { 97616102edbSEunchul Kim DRM_ERROR("failed to make ratio and shift.\n"); 97716102edbSEunchul Kim return -EINVAL; 97816102edbSEunchul Kim } else if (src >= dst * 32) { 97916102edbSEunchul Kim *ratio = 32; 98016102edbSEunchul Kim *shift = 5; 98116102edbSEunchul Kim } else if (src >= dst * 16) { 98216102edbSEunchul Kim *ratio = 16; 98316102edbSEunchul Kim *shift = 4; 98416102edbSEunchul Kim } else if (src >= dst * 8) { 98516102edbSEunchul Kim *ratio = 8; 98616102edbSEunchul Kim *shift = 3; 98716102edbSEunchul Kim } else if (src >= dst * 4) { 98816102edbSEunchul Kim *ratio = 4; 98916102edbSEunchul Kim *shift = 2; 99016102edbSEunchul Kim } else if (src >= dst * 2) { 99116102edbSEunchul Kim *ratio = 2; 99216102edbSEunchul Kim *shift = 1; 99316102edbSEunchul Kim } else { 99416102edbSEunchul Kim *ratio = 1; 99516102edbSEunchul Kim *shift = 0; 99616102edbSEunchul Kim } 99716102edbSEunchul Kim 99816102edbSEunchul Kim return 0; 99916102edbSEunchul Kim } 100016102edbSEunchul Kim 100116102edbSEunchul Kim static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc, 100216102edbSEunchul Kim struct drm_exynos_pos *src, struct drm_exynos_pos *dst) 100316102edbSEunchul Kim { 100416102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 100516102edbSEunchul Kim u32 cfg, cfg_ext, shfactor; 100616102edbSEunchul Kim u32 pre_dst_width, pre_dst_height; 100716102edbSEunchul Kim u32 pre_hratio, hfactor, pre_vratio, vfactor; 100816102edbSEunchul Kim int ret = 0; 100916102edbSEunchul Kim u32 src_w, src_h, dst_w, dst_h; 101016102edbSEunchul Kim 101116102edbSEunchul Kim cfg_ext = fimc_read(EXYNOS_CITRGFMT); 101216102edbSEunchul Kim if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) { 101316102edbSEunchul Kim src_w = src->h; 101416102edbSEunchul Kim src_h = src->w; 101516102edbSEunchul Kim } else { 101616102edbSEunchul Kim src_w = src->w; 101716102edbSEunchul Kim src_h = src->h; 101816102edbSEunchul Kim } 101916102edbSEunchul Kim 102016102edbSEunchul Kim if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) { 102116102edbSEunchul Kim dst_w = dst->h; 102216102edbSEunchul Kim dst_h = dst->w; 102316102edbSEunchul Kim } else { 102416102edbSEunchul Kim dst_w = dst->w; 102516102edbSEunchul Kim dst_h = dst->h; 102616102edbSEunchul Kim } 102716102edbSEunchul Kim 102816102edbSEunchul Kim ret = fimc_get_ratio_shift(src_w, dst_w, &pre_hratio, &hfactor); 102916102edbSEunchul Kim if (ret) { 103016102edbSEunchul Kim dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); 103116102edbSEunchul Kim return ret; 103216102edbSEunchul Kim } 103316102edbSEunchul Kim 103416102edbSEunchul Kim ret = fimc_get_ratio_shift(src_h, dst_h, &pre_vratio, &vfactor); 103516102edbSEunchul Kim if (ret) { 103616102edbSEunchul Kim dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); 103716102edbSEunchul Kim return ret; 103816102edbSEunchul Kim } 103916102edbSEunchul Kim 104016102edbSEunchul Kim pre_dst_width = src_w / pre_hratio; 104116102edbSEunchul Kim pre_dst_height = src_h / pre_vratio; 104216102edbSEunchul Kim DRM_DEBUG_KMS("%s:pre_dst_width[%d]pre_dst_height[%d]\n", __func__, 104316102edbSEunchul Kim pre_dst_width, pre_dst_height); 104416102edbSEunchul Kim DRM_DEBUG_KMS("%s:pre_hratio[%d]hfactor[%d]pre_vratio[%d]vfactor[%d]\n", 104516102edbSEunchul Kim __func__, pre_hratio, hfactor, pre_vratio, vfactor); 104616102edbSEunchul Kim 104716102edbSEunchul Kim sc->hratio = (src_w << 14) / (dst_w << hfactor); 104816102edbSEunchul Kim sc->vratio = (src_h << 14) / (dst_h << vfactor); 104916102edbSEunchul Kim sc->up_h = (dst_w >= src_w) ? true : false; 105016102edbSEunchul Kim sc->up_v = (dst_h >= src_h) ? true : false; 105116102edbSEunchul Kim DRM_DEBUG_KMS("%s:hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n", 105216102edbSEunchul Kim __func__, sc->hratio, sc->vratio, sc->up_h, sc->up_v); 105316102edbSEunchul Kim 105416102edbSEunchul Kim shfactor = FIMC_SHFACTOR - (hfactor + vfactor); 105516102edbSEunchul Kim DRM_DEBUG_KMS("%s:shfactor[%d]\n", __func__, shfactor); 105616102edbSEunchul Kim 105716102edbSEunchul Kim cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) | 105816102edbSEunchul Kim EXYNOS_CISCPRERATIO_PREHORRATIO(pre_hratio) | 105916102edbSEunchul Kim EXYNOS_CISCPRERATIO_PREVERRATIO(pre_vratio)); 106016102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCPRERATIO); 106116102edbSEunchul Kim 106216102edbSEunchul Kim cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) | 106316102edbSEunchul Kim EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height)); 106416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCPREDST); 106516102edbSEunchul Kim 106616102edbSEunchul Kim return ret; 106716102edbSEunchul Kim } 106816102edbSEunchul Kim 106916102edbSEunchul Kim static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc) 107016102edbSEunchul Kim { 107116102edbSEunchul Kim u32 cfg, cfg_ext; 107216102edbSEunchul Kim 107316102edbSEunchul Kim DRM_DEBUG_KMS("%s:range[%d]bypass[%d]up_h[%d]up_v[%d]\n", 107416102edbSEunchul Kim __func__, sc->range, sc->bypass, sc->up_h, sc->up_v); 107516102edbSEunchul Kim DRM_DEBUG_KMS("%s:hratio[%d]vratio[%d]\n", 107616102edbSEunchul Kim __func__, sc->hratio, sc->vratio); 107716102edbSEunchul Kim 107816102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 107916102edbSEunchul Kim cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS | 108016102edbSEunchul Kim EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V | 108116102edbSEunchul Kim EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK | 108216102edbSEunchul Kim EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK | 108316102edbSEunchul Kim EXYNOS_CISCCTRL_CSCR2Y_WIDE | 108416102edbSEunchul Kim EXYNOS_CISCCTRL_CSCY2R_WIDE); 108516102edbSEunchul Kim 108616102edbSEunchul Kim if (sc->range) 108716102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE | 108816102edbSEunchul Kim EXYNOS_CISCCTRL_CSCY2R_WIDE); 108916102edbSEunchul Kim if (sc->bypass) 109016102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALERBYPASS; 109116102edbSEunchul Kim if (sc->up_h) 109216102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALEUP_H; 109316102edbSEunchul Kim if (sc->up_v) 109416102edbSEunchul Kim cfg |= EXYNOS_CISCCTRL_SCALEUP_V; 109516102edbSEunchul Kim 109616102edbSEunchul Kim cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) | 109716102edbSEunchul Kim EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6))); 109816102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 109916102edbSEunchul Kim 110016102edbSEunchul Kim cfg_ext = fimc_read(EXYNOS_CIEXTEN); 110116102edbSEunchul Kim cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK; 110216102edbSEunchul Kim cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK; 110316102edbSEunchul Kim cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) | 110416102edbSEunchul Kim EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio)); 110516102edbSEunchul Kim fimc_write(cfg_ext, EXYNOS_CIEXTEN); 110616102edbSEunchul Kim } 110716102edbSEunchul Kim 110816102edbSEunchul Kim static int fimc_dst_set_size(struct device *dev, int swap, 110916102edbSEunchul Kim struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) 111016102edbSEunchul Kim { 111116102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 111216102edbSEunchul Kim struct drm_exynos_pos img_pos = *pos; 111316102edbSEunchul Kim struct drm_exynos_sz img_sz = *sz; 111416102edbSEunchul Kim u32 cfg; 111516102edbSEunchul Kim 111616102edbSEunchul Kim DRM_DEBUG_KMS("%s:swap[%d]hsize[%d]vsize[%d]\n", 111716102edbSEunchul Kim __func__, swap, sz->hsize, sz->vsize); 111816102edbSEunchul Kim 111916102edbSEunchul Kim /* original size */ 112016102edbSEunchul Kim cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) | 112116102edbSEunchul Kim EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize)); 112216102edbSEunchul Kim 112316102edbSEunchul Kim fimc_write(cfg, EXYNOS_ORGOSIZE); 112416102edbSEunchul Kim 112516102edbSEunchul Kim DRM_DEBUG_KMS("%s:x[%d]y[%d]w[%d]h[%d]\n", 112616102edbSEunchul Kim __func__, pos->x, pos->y, pos->w, pos->h); 112716102edbSEunchul Kim 112816102edbSEunchul Kim /* CSC ITU */ 112916102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 113016102edbSEunchul Kim cfg &= ~EXYNOS_CIGCTRL_CSC_MASK; 113116102edbSEunchul Kim 113216102edbSEunchul Kim if (sz->hsize >= FIMC_WIDTH_ITU_709) 113316102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CSC_ITU709; 113416102edbSEunchul Kim else 113516102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_CSC_ITU601; 113616102edbSEunchul Kim 113716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 113816102edbSEunchul Kim 113916102edbSEunchul Kim if (swap) { 114016102edbSEunchul Kim img_pos.w = pos->h; 114116102edbSEunchul Kim img_pos.h = pos->w; 114216102edbSEunchul Kim img_sz.hsize = sz->vsize; 114316102edbSEunchul Kim img_sz.vsize = sz->hsize; 114416102edbSEunchul Kim } 114516102edbSEunchul Kim 114616102edbSEunchul Kim /* target image size */ 114716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CITRGFMT); 114816102edbSEunchul Kim cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK | 114916102edbSEunchul Kim EXYNOS_CITRGFMT_TARGETV_MASK); 115016102edbSEunchul Kim cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) | 115116102edbSEunchul Kim EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h)); 115216102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITRGFMT); 115316102edbSEunchul Kim 115416102edbSEunchul Kim /* target area */ 115516102edbSEunchul Kim cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h); 115616102edbSEunchul Kim fimc_write(cfg, EXYNOS_CITAREA); 115716102edbSEunchul Kim 115816102edbSEunchul Kim /* offset Y(RGB), Cb, Cr */ 115916102edbSEunchul Kim cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) | 116016102edbSEunchul Kim EXYNOS_CIOYOFF_VERTICAL(img_pos.y)); 116116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOYOFF); 116216102edbSEunchul Kim cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) | 116316102edbSEunchul Kim EXYNOS_CIOCBOFF_VERTICAL(img_pos.y)); 116416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCBOFF); 116516102edbSEunchul Kim cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) | 116616102edbSEunchul Kim EXYNOS_CIOCROFF_VERTICAL(img_pos.y)); 116716102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIOCROFF); 116816102edbSEunchul Kim 116916102edbSEunchul Kim return 0; 117016102edbSEunchul Kim } 117116102edbSEunchul Kim 117216102edbSEunchul Kim static int fimc_dst_get_buf_seq(struct fimc_context *ctx) 117316102edbSEunchul Kim { 117416102edbSEunchul Kim u32 cfg, i, buf_num = 0; 117516102edbSEunchul Kim u32 mask = 0x00000001; 117616102edbSEunchul Kim 117716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIFCNTSEQ); 117816102edbSEunchul Kim 117916102edbSEunchul Kim for (i = 0; i < FIMC_REG_SZ; i++) 118016102edbSEunchul Kim if (cfg & (mask << i)) 118116102edbSEunchul Kim buf_num++; 118216102edbSEunchul Kim 118316102edbSEunchul Kim DRM_DEBUG_KMS("%s:buf_num[%d]\n", __func__, buf_num); 118416102edbSEunchul Kim 118516102edbSEunchul Kim return buf_num; 118616102edbSEunchul Kim } 118716102edbSEunchul Kim 118816102edbSEunchul Kim static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id, 118916102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 119016102edbSEunchul Kim { 119116102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 119216102edbSEunchul Kim bool enable; 119316102edbSEunchul Kim u32 cfg; 119416102edbSEunchul Kim u32 mask = 0x00000001 << buf_id; 119516102edbSEunchul Kim int ret = 0; 119616102edbSEunchul Kim 119716102edbSEunchul Kim DRM_DEBUG_KMS("%s:buf_id[%d]buf_type[%d]\n", __func__, 119816102edbSEunchul Kim buf_id, buf_type); 119916102edbSEunchul Kim 120016102edbSEunchul Kim mutex_lock(&ctx->lock); 120116102edbSEunchul Kim 120216102edbSEunchul Kim /* mask register set */ 120316102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIFCNTSEQ); 120416102edbSEunchul Kim 120516102edbSEunchul Kim switch (buf_type) { 120616102edbSEunchul Kim case IPP_BUF_ENQUEUE: 120716102edbSEunchul Kim enable = true; 120816102edbSEunchul Kim break; 120916102edbSEunchul Kim case IPP_BUF_DEQUEUE: 121016102edbSEunchul Kim enable = false; 121116102edbSEunchul Kim break; 121216102edbSEunchul Kim default: 121316102edbSEunchul Kim dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); 121416102edbSEunchul Kim ret = -EINVAL; 121516102edbSEunchul Kim goto err_unlock; 121616102edbSEunchul Kim } 121716102edbSEunchul Kim 121816102edbSEunchul Kim /* sequence id */ 121913a32eb0SEunchul Kim cfg &= ~mask; 122016102edbSEunchul Kim cfg |= (enable << buf_id); 122116102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIFCNTSEQ); 122216102edbSEunchul Kim 122316102edbSEunchul Kim /* interrupt enable */ 122416102edbSEunchul Kim if (buf_type == IPP_BUF_ENQUEUE && 122516102edbSEunchul Kim fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START) 122616102edbSEunchul Kim fimc_handle_irq(ctx, true, false, true); 122716102edbSEunchul Kim 122816102edbSEunchul Kim /* interrupt disable */ 122916102edbSEunchul Kim if (buf_type == IPP_BUF_DEQUEUE && 123016102edbSEunchul Kim fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP) 123116102edbSEunchul Kim fimc_handle_irq(ctx, false, false, true); 123216102edbSEunchul Kim 123316102edbSEunchul Kim err_unlock: 123416102edbSEunchul Kim mutex_unlock(&ctx->lock); 123516102edbSEunchul Kim return ret; 123616102edbSEunchul Kim } 123716102edbSEunchul Kim 123816102edbSEunchul Kim static int fimc_dst_set_addr(struct device *dev, 123916102edbSEunchul Kim struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, 124016102edbSEunchul Kim enum drm_exynos_ipp_buf_type buf_type) 124116102edbSEunchul Kim { 124216102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 124316102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 12447259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 124516102edbSEunchul Kim struct drm_exynos_ipp_property *property; 124616102edbSEunchul Kim struct drm_exynos_ipp_config *config; 124716102edbSEunchul Kim 124816102edbSEunchul Kim if (!c_node) { 124916102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 125016102edbSEunchul Kim return -EINVAL; 125116102edbSEunchul Kim } 125216102edbSEunchul Kim 125316102edbSEunchul Kim property = &c_node->property; 125416102edbSEunchul Kim 125516102edbSEunchul Kim DRM_DEBUG_KMS("%s:prop_id[%d]buf_id[%d]buf_type[%d]\n", __func__, 125616102edbSEunchul Kim property->prop_id, buf_id, buf_type); 125716102edbSEunchul Kim 125816102edbSEunchul Kim if (buf_id > FIMC_MAX_DST) { 125916102edbSEunchul Kim dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); 126016102edbSEunchul Kim return -ENOMEM; 126116102edbSEunchul Kim } 126216102edbSEunchul Kim 126316102edbSEunchul Kim /* address register set */ 126416102edbSEunchul Kim switch (buf_type) { 126516102edbSEunchul Kim case IPP_BUF_ENQUEUE: 126616102edbSEunchul Kim config = &property->config[EXYNOS_DRM_OPS_DST]; 126716102edbSEunchul Kim 126816102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], 126916102edbSEunchul Kim EXYNOS_CIOYSA(buf_id)); 127016102edbSEunchul Kim 127116102edbSEunchul Kim if (config->fmt == DRM_FORMAT_YVU420) { 127216102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 127316102edbSEunchul Kim EXYNOS_CIOCBSA(buf_id)); 127416102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 127516102edbSEunchul Kim EXYNOS_CIOCRSA(buf_id)); 127616102edbSEunchul Kim } else { 127716102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], 127816102edbSEunchul Kim EXYNOS_CIOCBSA(buf_id)); 127916102edbSEunchul Kim fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], 128016102edbSEunchul Kim EXYNOS_CIOCRSA(buf_id)); 128116102edbSEunchul Kim } 128216102edbSEunchul Kim break; 128316102edbSEunchul Kim case IPP_BUF_DEQUEUE: 128416102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIOYSA(buf_id)); 128516102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIOCBSA(buf_id)); 128616102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIOCRSA(buf_id)); 128716102edbSEunchul Kim break; 128816102edbSEunchul Kim default: 128916102edbSEunchul Kim /* bypass */ 129016102edbSEunchul Kim break; 129116102edbSEunchul Kim } 129216102edbSEunchul Kim 129316102edbSEunchul Kim return fimc_dst_set_buf_seq(ctx, buf_id, buf_type); 129416102edbSEunchul Kim } 129516102edbSEunchul Kim 129616102edbSEunchul Kim static struct exynos_drm_ipp_ops fimc_dst_ops = { 129716102edbSEunchul Kim .set_fmt = fimc_dst_set_fmt, 129816102edbSEunchul Kim .set_transf = fimc_dst_set_transf, 129916102edbSEunchul Kim .set_size = fimc_dst_set_size, 130016102edbSEunchul Kim .set_addr = fimc_dst_set_addr, 130116102edbSEunchul Kim }; 130216102edbSEunchul Kim 130316102edbSEunchul Kim static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable) 130416102edbSEunchul Kim { 130516102edbSEunchul Kim DRM_DEBUG_KMS("%s:enable[%d]\n", __func__, enable); 130616102edbSEunchul Kim 130716102edbSEunchul Kim if (enable) { 1308e5f86839SSylwester Nawrocki clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); 1309e5f86839SSylwester Nawrocki clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); 131016102edbSEunchul Kim ctx->suspended = false; 131116102edbSEunchul Kim } else { 1312e5f86839SSylwester Nawrocki clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); 1313e5f86839SSylwester Nawrocki clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); 131416102edbSEunchul Kim ctx->suspended = true; 131516102edbSEunchul Kim } 131616102edbSEunchul Kim 131716102edbSEunchul Kim return 0; 131816102edbSEunchul Kim } 131916102edbSEunchul Kim 132016102edbSEunchul Kim static irqreturn_t fimc_irq_handler(int irq, void *dev_id) 132116102edbSEunchul Kim { 132216102edbSEunchul Kim struct fimc_context *ctx = dev_id; 132316102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 13247259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 132516102edbSEunchul Kim struct drm_exynos_ipp_event_work *event_work = 132616102edbSEunchul Kim c_node->event_work; 132716102edbSEunchul Kim int buf_id; 132816102edbSEunchul Kim 132916102edbSEunchul Kim DRM_DEBUG_KMS("%s:fimc id[%d]\n", __func__, ctx->id); 133016102edbSEunchul Kim 133116102edbSEunchul Kim fimc_clear_irq(ctx); 133216102edbSEunchul Kim if (fimc_check_ovf(ctx)) 133316102edbSEunchul Kim return IRQ_NONE; 133416102edbSEunchul Kim 133516102edbSEunchul Kim if (!fimc_check_frame_end(ctx)) 133616102edbSEunchul Kim return IRQ_NONE; 133716102edbSEunchul Kim 133816102edbSEunchul Kim buf_id = fimc_get_buf_id(ctx); 133916102edbSEunchul Kim if (buf_id < 0) 134016102edbSEunchul Kim return IRQ_HANDLED; 134116102edbSEunchul Kim 134216102edbSEunchul Kim DRM_DEBUG_KMS("%s:buf_id[%d]\n", __func__, buf_id); 134316102edbSEunchul Kim 134416102edbSEunchul Kim if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) { 134516102edbSEunchul Kim DRM_ERROR("failed to dequeue.\n"); 134616102edbSEunchul Kim return IRQ_HANDLED; 134716102edbSEunchul Kim } 134816102edbSEunchul Kim 134916102edbSEunchul Kim event_work->ippdrv = ippdrv; 135016102edbSEunchul Kim event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id; 135116102edbSEunchul Kim queue_work(ippdrv->event_workq, (struct work_struct *)event_work); 135216102edbSEunchul Kim 135316102edbSEunchul Kim return IRQ_HANDLED; 135416102edbSEunchul Kim } 135516102edbSEunchul Kim 135616102edbSEunchul Kim static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) 135716102edbSEunchul Kim { 135816102edbSEunchul Kim struct drm_exynos_ipp_prop_list *prop_list; 135916102edbSEunchul Kim 136016102edbSEunchul Kim DRM_DEBUG_KMS("%s\n", __func__); 136116102edbSEunchul Kim 136216102edbSEunchul Kim prop_list = devm_kzalloc(ippdrv->dev, sizeof(*prop_list), GFP_KERNEL); 136316102edbSEunchul Kim if (!prop_list) { 136416102edbSEunchul Kim DRM_ERROR("failed to alloc property list.\n"); 136516102edbSEunchul Kim return -ENOMEM; 136616102edbSEunchul Kim } 136716102edbSEunchul Kim 136816102edbSEunchul Kim prop_list->version = 1; 136916102edbSEunchul Kim prop_list->writeback = 1; 137016102edbSEunchul Kim prop_list->refresh_min = FIMC_REFRESH_MIN; 137116102edbSEunchul Kim prop_list->refresh_max = FIMC_REFRESH_MAX; 137216102edbSEunchul Kim prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) | 137316102edbSEunchul Kim (1 << EXYNOS_DRM_FLIP_VERTICAL) | 137416102edbSEunchul Kim (1 << EXYNOS_DRM_FLIP_HORIZONTAL); 137516102edbSEunchul Kim prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | 137616102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_90) | 137716102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_180) | 137816102edbSEunchul Kim (1 << EXYNOS_DRM_DEGREE_270); 137916102edbSEunchul Kim prop_list->csc = 1; 138016102edbSEunchul Kim prop_list->crop = 1; 138116102edbSEunchul Kim prop_list->crop_max.hsize = FIMC_CROP_MAX; 138216102edbSEunchul Kim prop_list->crop_max.vsize = FIMC_CROP_MAX; 138316102edbSEunchul Kim prop_list->crop_min.hsize = FIMC_CROP_MIN; 138416102edbSEunchul Kim prop_list->crop_min.vsize = FIMC_CROP_MIN; 138516102edbSEunchul Kim prop_list->scale = 1; 138616102edbSEunchul Kim prop_list->scale_max.hsize = FIMC_SCALE_MAX; 138716102edbSEunchul Kim prop_list->scale_max.vsize = FIMC_SCALE_MAX; 138816102edbSEunchul Kim prop_list->scale_min.hsize = FIMC_SCALE_MIN; 138916102edbSEunchul Kim prop_list->scale_min.vsize = FIMC_SCALE_MIN; 139016102edbSEunchul Kim 139116102edbSEunchul Kim ippdrv->prop_list = prop_list; 139216102edbSEunchul Kim 139316102edbSEunchul Kim return 0; 139416102edbSEunchul Kim } 139516102edbSEunchul Kim 139616102edbSEunchul Kim static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip) 139716102edbSEunchul Kim { 139816102edbSEunchul Kim switch (flip) { 139916102edbSEunchul Kim case EXYNOS_DRM_FLIP_NONE: 140016102edbSEunchul Kim case EXYNOS_DRM_FLIP_VERTICAL: 140116102edbSEunchul Kim case EXYNOS_DRM_FLIP_HORIZONTAL: 14024f21877cSEunchul Kim case EXYNOS_DRM_FLIP_BOTH: 140316102edbSEunchul Kim return true; 140416102edbSEunchul Kim default: 140516102edbSEunchul Kim DRM_DEBUG_KMS("%s:invalid flip\n", __func__); 140616102edbSEunchul Kim return false; 140716102edbSEunchul Kim } 140816102edbSEunchul Kim } 140916102edbSEunchul Kim 141016102edbSEunchul Kim static int fimc_ippdrv_check_property(struct device *dev, 141116102edbSEunchul Kim struct drm_exynos_ipp_property *property) 141216102edbSEunchul Kim { 141316102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 141416102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 141516102edbSEunchul Kim struct drm_exynos_ipp_prop_list *pp = ippdrv->prop_list; 141616102edbSEunchul Kim struct drm_exynos_ipp_config *config; 141716102edbSEunchul Kim struct drm_exynos_pos *pos; 141816102edbSEunchul Kim struct drm_exynos_sz *sz; 141916102edbSEunchul Kim bool swap; 142016102edbSEunchul Kim int i; 142116102edbSEunchul Kim 142216102edbSEunchul Kim DRM_DEBUG_KMS("%s\n", __func__); 142316102edbSEunchul Kim 142416102edbSEunchul Kim for_each_ipp_ops(i) { 142516102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && 142616102edbSEunchul Kim (property->cmd == IPP_CMD_WB)) 142716102edbSEunchul Kim continue; 142816102edbSEunchul Kim 142916102edbSEunchul Kim config = &property->config[i]; 143016102edbSEunchul Kim pos = &config->pos; 143116102edbSEunchul Kim sz = &config->sz; 143216102edbSEunchul Kim 143316102edbSEunchul Kim /* check for flip */ 143416102edbSEunchul Kim if (!fimc_check_drm_flip(config->flip)) { 143516102edbSEunchul Kim DRM_ERROR("invalid flip.\n"); 143616102edbSEunchul Kim goto err_property; 143716102edbSEunchul Kim } 143816102edbSEunchul Kim 143916102edbSEunchul Kim /* check for degree */ 144016102edbSEunchul Kim switch (config->degree) { 144116102edbSEunchul Kim case EXYNOS_DRM_DEGREE_90: 144216102edbSEunchul Kim case EXYNOS_DRM_DEGREE_270: 144316102edbSEunchul Kim swap = true; 144416102edbSEunchul Kim break; 144516102edbSEunchul Kim case EXYNOS_DRM_DEGREE_0: 144616102edbSEunchul Kim case EXYNOS_DRM_DEGREE_180: 144716102edbSEunchul Kim swap = false; 144816102edbSEunchul Kim break; 144916102edbSEunchul Kim default: 145016102edbSEunchul Kim DRM_ERROR("invalid degree.\n"); 145116102edbSEunchul Kim goto err_property; 145216102edbSEunchul Kim } 145316102edbSEunchul Kim 145416102edbSEunchul Kim /* check for buffer bound */ 145516102edbSEunchul Kim if ((pos->x + pos->w > sz->hsize) || 145616102edbSEunchul Kim (pos->y + pos->h > sz->vsize)) { 145716102edbSEunchul Kim DRM_ERROR("out of buf bound.\n"); 145816102edbSEunchul Kim goto err_property; 145916102edbSEunchul Kim } 146016102edbSEunchul Kim 146116102edbSEunchul Kim /* check for crop */ 146216102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { 146316102edbSEunchul Kim if (swap) { 146416102edbSEunchul Kim if ((pos->h < pp->crop_min.hsize) || 146516102edbSEunchul Kim (sz->vsize > pp->crop_max.hsize) || 146616102edbSEunchul Kim (pos->w < pp->crop_min.vsize) || 146716102edbSEunchul Kim (sz->hsize > pp->crop_max.vsize)) { 146816102edbSEunchul Kim DRM_ERROR("out of crop size.\n"); 146916102edbSEunchul Kim goto err_property; 147016102edbSEunchul Kim } 147116102edbSEunchul Kim } else { 147216102edbSEunchul Kim if ((pos->w < pp->crop_min.hsize) || 147316102edbSEunchul Kim (sz->hsize > pp->crop_max.hsize) || 147416102edbSEunchul Kim (pos->h < pp->crop_min.vsize) || 147516102edbSEunchul Kim (sz->vsize > pp->crop_max.vsize)) { 147616102edbSEunchul Kim DRM_ERROR("out of crop size.\n"); 147716102edbSEunchul Kim goto err_property; 147816102edbSEunchul Kim } 147916102edbSEunchul Kim } 148016102edbSEunchul Kim } 148116102edbSEunchul Kim 148216102edbSEunchul Kim /* check for scale */ 148316102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { 148416102edbSEunchul Kim if (swap) { 148516102edbSEunchul Kim if ((pos->h < pp->scale_min.hsize) || 148616102edbSEunchul Kim (sz->vsize > pp->scale_max.hsize) || 148716102edbSEunchul Kim (pos->w < pp->scale_min.vsize) || 148816102edbSEunchul Kim (sz->hsize > pp->scale_max.vsize)) { 148916102edbSEunchul Kim DRM_ERROR("out of scale size.\n"); 149016102edbSEunchul Kim goto err_property; 149116102edbSEunchul Kim } 149216102edbSEunchul Kim } else { 149316102edbSEunchul Kim if ((pos->w < pp->scale_min.hsize) || 149416102edbSEunchul Kim (sz->hsize > pp->scale_max.hsize) || 149516102edbSEunchul Kim (pos->h < pp->scale_min.vsize) || 149616102edbSEunchul Kim (sz->vsize > pp->scale_max.vsize)) { 149716102edbSEunchul Kim DRM_ERROR("out of scale size.\n"); 149816102edbSEunchul Kim goto err_property; 149916102edbSEunchul Kim } 150016102edbSEunchul Kim } 150116102edbSEunchul Kim } 150216102edbSEunchul Kim } 150316102edbSEunchul Kim 150416102edbSEunchul Kim return 0; 150516102edbSEunchul Kim 150616102edbSEunchul Kim err_property: 150716102edbSEunchul Kim for_each_ipp_ops(i) { 150816102edbSEunchul Kim if ((i == EXYNOS_DRM_OPS_SRC) && 150916102edbSEunchul Kim (property->cmd == IPP_CMD_WB)) 151016102edbSEunchul Kim continue; 151116102edbSEunchul Kim 151216102edbSEunchul Kim config = &property->config[i]; 151316102edbSEunchul Kim pos = &config->pos; 151416102edbSEunchul Kim sz = &config->sz; 151516102edbSEunchul Kim 151616102edbSEunchul Kim DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", 151716102edbSEunchul Kim i ? "dst" : "src", config->flip, config->degree, 151816102edbSEunchul Kim pos->x, pos->y, pos->w, pos->h, 151916102edbSEunchul Kim sz->hsize, sz->vsize); 152016102edbSEunchul Kim } 152116102edbSEunchul Kim 152216102edbSEunchul Kim return -EINVAL; 152316102edbSEunchul Kim } 152416102edbSEunchul Kim 152516102edbSEunchul Kim static void fimc_clear_addr(struct fimc_context *ctx) 152616102edbSEunchul Kim { 152716102edbSEunchul Kim int i; 152816102edbSEunchul Kim 152916102edbSEunchul Kim DRM_DEBUG_KMS("%s:\n", __func__); 153016102edbSEunchul Kim 153116102edbSEunchul Kim for (i = 0; i < FIMC_MAX_SRC; i++) { 153216102edbSEunchul Kim fimc_write(0, EXYNOS_CIIYSA(i)); 153316102edbSEunchul Kim fimc_write(0, EXYNOS_CIICBSA(i)); 153416102edbSEunchul Kim fimc_write(0, EXYNOS_CIICRSA(i)); 153516102edbSEunchul Kim } 153616102edbSEunchul Kim 153716102edbSEunchul Kim for (i = 0; i < FIMC_MAX_DST; i++) { 153816102edbSEunchul Kim fimc_write(0, EXYNOS_CIOYSA(i)); 153916102edbSEunchul Kim fimc_write(0, EXYNOS_CIOCBSA(i)); 154016102edbSEunchul Kim fimc_write(0, EXYNOS_CIOCRSA(i)); 154116102edbSEunchul Kim } 154216102edbSEunchul Kim } 154316102edbSEunchul Kim 154416102edbSEunchul Kim static int fimc_ippdrv_reset(struct device *dev) 154516102edbSEunchul Kim { 154616102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 154716102edbSEunchul Kim 154816102edbSEunchul Kim DRM_DEBUG_KMS("%s\n", __func__); 154916102edbSEunchul Kim 155016102edbSEunchul Kim /* reset h/w block */ 1551b5c0b552SJoongMock Shin fimc_sw_reset(ctx); 155216102edbSEunchul Kim 155316102edbSEunchul Kim /* reset scaler capability */ 155416102edbSEunchul Kim memset(&ctx->sc, 0x0, sizeof(ctx->sc)); 155516102edbSEunchul Kim 155616102edbSEunchul Kim fimc_clear_addr(ctx); 155716102edbSEunchul Kim 155816102edbSEunchul Kim return 0; 155916102edbSEunchul Kim } 156016102edbSEunchul Kim 156116102edbSEunchul Kim static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) 156216102edbSEunchul Kim { 156316102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 156416102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 15657259c3d6SEunchul Kim struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; 156616102edbSEunchul Kim struct drm_exynos_ipp_property *property; 156716102edbSEunchul Kim struct drm_exynos_ipp_config *config; 156816102edbSEunchul Kim struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; 156916102edbSEunchul Kim struct drm_exynos_ipp_set_wb set_wb; 157016102edbSEunchul Kim int ret, i; 157116102edbSEunchul Kim u32 cfg0, cfg1; 157216102edbSEunchul Kim 157316102edbSEunchul Kim DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd); 157416102edbSEunchul Kim 157516102edbSEunchul Kim if (!c_node) { 157616102edbSEunchul Kim DRM_ERROR("failed to get c_node.\n"); 157716102edbSEunchul Kim return -EINVAL; 157816102edbSEunchul Kim } 157916102edbSEunchul Kim 158016102edbSEunchul Kim property = &c_node->property; 158116102edbSEunchul Kim 158216102edbSEunchul Kim fimc_handle_irq(ctx, true, false, true); 158316102edbSEunchul Kim 158416102edbSEunchul Kim for_each_ipp_ops(i) { 158516102edbSEunchul Kim config = &property->config[i]; 158616102edbSEunchul Kim img_pos[i] = config->pos; 158716102edbSEunchul Kim } 158816102edbSEunchul Kim 158916102edbSEunchul Kim ret = fimc_set_prescaler(ctx, &ctx->sc, 159016102edbSEunchul Kim &img_pos[EXYNOS_DRM_OPS_SRC], 159116102edbSEunchul Kim &img_pos[EXYNOS_DRM_OPS_DST]); 159216102edbSEunchul Kim if (ret) { 159316102edbSEunchul Kim dev_err(dev, "failed to set precalser.\n"); 159416102edbSEunchul Kim return ret; 159516102edbSEunchul Kim } 159616102edbSEunchul Kim 159716102edbSEunchul Kim /* If set ture, we can save jpeg about screen */ 159816102edbSEunchul Kim fimc_handle_jpeg(ctx, false); 159916102edbSEunchul Kim fimc_set_scaler(ctx, &ctx->sc); 160016102edbSEunchul Kim fimc_set_polarity(ctx, &ctx->pol); 160116102edbSEunchul Kim 160216102edbSEunchul Kim switch (cmd) { 160316102edbSEunchul Kim case IPP_CMD_M2M: 160416102edbSEunchul Kim fimc_set_type_ctrl(ctx, FIMC_WB_NONE); 160516102edbSEunchul Kim fimc_handle_lastend(ctx, false); 160616102edbSEunchul Kim 160716102edbSEunchul Kim /* setup dma */ 160816102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_MSCTRL); 160916102edbSEunchul Kim cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; 161016102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; 161116102edbSEunchul Kim fimc_write(cfg0, EXYNOS_MSCTRL); 161216102edbSEunchul Kim break; 161316102edbSEunchul Kim case IPP_CMD_WB: 161416102edbSEunchul Kim fimc_set_type_ctrl(ctx, FIMC_WB_A); 161516102edbSEunchul Kim fimc_handle_lastend(ctx, true); 161616102edbSEunchul Kim 161716102edbSEunchul Kim /* setup FIMD */ 16185186fc5eSSylwester Nawrocki ret = fimc_set_camblk_fimd0_wb(ctx); 16195186fc5eSSylwester Nawrocki if (ret < 0) { 16205186fc5eSSylwester Nawrocki dev_err(dev, "camblk setup failed.\n"); 16215186fc5eSSylwester Nawrocki return ret; 16225186fc5eSSylwester Nawrocki } 162316102edbSEunchul Kim 162416102edbSEunchul Kim set_wb.enable = 1; 162516102edbSEunchul Kim set_wb.refresh = property->refresh_rate; 162616102edbSEunchul Kim exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 162716102edbSEunchul Kim break; 162816102edbSEunchul Kim case IPP_CMD_OUTPUT: 162916102edbSEunchul Kim default: 163016102edbSEunchul Kim ret = -EINVAL; 163116102edbSEunchul Kim dev_err(dev, "invalid operations.\n"); 163216102edbSEunchul Kim return ret; 163316102edbSEunchul Kim } 163416102edbSEunchul Kim 163516102edbSEunchul Kim /* Reset status */ 163616102edbSEunchul Kim fimc_write(0x0, EXYNOS_CISTATUS); 163716102edbSEunchul Kim 163816102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_CIIMGCPT); 163916102edbSEunchul Kim cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; 164016102edbSEunchul Kim cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; 164116102edbSEunchul Kim 164216102edbSEunchul Kim /* Scaler */ 164316102edbSEunchul Kim cfg1 = fimc_read(EXYNOS_CISCCTRL); 164416102edbSEunchul Kim cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK; 164516102edbSEunchul Kim cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE | 164616102edbSEunchul Kim EXYNOS_CISCCTRL_SCALERSTART); 164716102edbSEunchul Kim 164816102edbSEunchul Kim fimc_write(cfg1, EXYNOS_CISCCTRL); 164916102edbSEunchul Kim 165016102edbSEunchul Kim /* Enable image capture*/ 165116102edbSEunchul Kim cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; 165216102edbSEunchul Kim fimc_write(cfg0, EXYNOS_CIIMGCPT); 165316102edbSEunchul Kim 165416102edbSEunchul Kim /* Disable frame end irq */ 165516102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_CIGCTRL); 165616102edbSEunchul Kim cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE; 165716102edbSEunchul Kim fimc_write(cfg0, EXYNOS_CIGCTRL); 165816102edbSEunchul Kim 165916102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_CIOCTRL); 166016102edbSEunchul Kim cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK; 166116102edbSEunchul Kim fimc_write(cfg0, EXYNOS_CIOCTRL); 166216102edbSEunchul Kim 166316102edbSEunchul Kim if (cmd == IPP_CMD_M2M) { 166416102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_MSCTRL); 166516102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_ENVID; 166616102edbSEunchul Kim fimc_write(cfg0, EXYNOS_MSCTRL); 166716102edbSEunchul Kim 166816102edbSEunchul Kim cfg0 = fimc_read(EXYNOS_MSCTRL); 166916102edbSEunchul Kim cfg0 |= EXYNOS_MSCTRL_ENVID; 167016102edbSEunchul Kim fimc_write(cfg0, EXYNOS_MSCTRL); 167116102edbSEunchul Kim } 167216102edbSEunchul Kim 167316102edbSEunchul Kim return 0; 167416102edbSEunchul Kim } 167516102edbSEunchul Kim 167616102edbSEunchul Kim static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) 167716102edbSEunchul Kim { 167816102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 167916102edbSEunchul Kim struct drm_exynos_ipp_set_wb set_wb = {0, 0}; 168016102edbSEunchul Kim u32 cfg; 168116102edbSEunchul Kim 168216102edbSEunchul Kim DRM_DEBUG_KMS("%s:cmd[%d]\n", __func__, cmd); 168316102edbSEunchul Kim 168416102edbSEunchul Kim switch (cmd) { 168516102edbSEunchul Kim case IPP_CMD_M2M: 168616102edbSEunchul Kim /* Source clear */ 168716102edbSEunchul Kim cfg = fimc_read(EXYNOS_MSCTRL); 168816102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_INPUT_MASK; 168916102edbSEunchul Kim cfg &= ~EXYNOS_MSCTRL_ENVID; 169016102edbSEunchul Kim fimc_write(cfg, EXYNOS_MSCTRL); 169116102edbSEunchul Kim break; 169216102edbSEunchul Kim case IPP_CMD_WB: 169316102edbSEunchul Kim exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); 169416102edbSEunchul Kim break; 169516102edbSEunchul Kim case IPP_CMD_OUTPUT: 169616102edbSEunchul Kim default: 169716102edbSEunchul Kim dev_err(dev, "invalid operations.\n"); 169816102edbSEunchul Kim break; 169916102edbSEunchul Kim } 170016102edbSEunchul Kim 170116102edbSEunchul Kim fimc_handle_irq(ctx, false, false, true); 170216102edbSEunchul Kim 170316102edbSEunchul Kim /* reset sequence */ 170416102edbSEunchul Kim fimc_write(0x0, EXYNOS_CIFCNTSEQ); 170516102edbSEunchul Kim 170616102edbSEunchul Kim /* Scaler disable */ 170716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CISCCTRL); 170816102edbSEunchul Kim cfg &= ~EXYNOS_CISCCTRL_SCALERSTART; 170916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CISCCTRL); 171016102edbSEunchul Kim 171116102edbSEunchul Kim /* Disable image capture */ 171216102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIIMGCPT); 171316102edbSEunchul Kim cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN); 171416102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIIMGCPT); 171516102edbSEunchul Kim 171616102edbSEunchul Kim /* Enable frame end irq */ 171716102edbSEunchul Kim cfg = fimc_read(EXYNOS_CIGCTRL); 171816102edbSEunchul Kim cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE; 171916102edbSEunchul Kim fimc_write(cfg, EXYNOS_CIGCTRL); 172016102edbSEunchul Kim } 172116102edbSEunchul Kim 1722e5f86839SSylwester Nawrocki static void fimc_put_clocks(struct fimc_context *ctx) 1723e5f86839SSylwester Nawrocki { 1724e5f86839SSylwester Nawrocki int i; 1725e5f86839SSylwester Nawrocki 1726e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) { 1727e5f86839SSylwester Nawrocki if (IS_ERR(ctx->clocks[i])) 1728e5f86839SSylwester Nawrocki continue; 1729e5f86839SSylwester Nawrocki clk_put(ctx->clocks[i]); 1730e5f86839SSylwester Nawrocki ctx->clocks[i] = ERR_PTR(-EINVAL); 1731e5f86839SSylwester Nawrocki } 1732e5f86839SSylwester Nawrocki } 1733e5f86839SSylwester Nawrocki 1734e5f86839SSylwester Nawrocki static int fimc_setup_clocks(struct fimc_context *ctx) 1735e5f86839SSylwester Nawrocki { 1736e5f86839SSylwester Nawrocki struct device *fimc_dev = ctx->ippdrv.dev; 1737e5f86839SSylwester Nawrocki struct device *dev; 1738e5f86839SSylwester Nawrocki int ret, i; 1739e5f86839SSylwester Nawrocki 1740e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) 1741e5f86839SSylwester Nawrocki ctx->clocks[i] = ERR_PTR(-EINVAL); 1742e5f86839SSylwester Nawrocki 1743e5f86839SSylwester Nawrocki for (i = 0; i < FIMC_CLKS_MAX; i++) { 1744e5f86839SSylwester Nawrocki if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B) 1745e5f86839SSylwester Nawrocki dev = fimc_dev->parent; 1746e5f86839SSylwester Nawrocki else 1747e5f86839SSylwester Nawrocki dev = fimc_dev; 1748e5f86839SSylwester Nawrocki 1749e5f86839SSylwester Nawrocki ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]); 1750e5f86839SSylwester Nawrocki if (IS_ERR(ctx->clocks[i])) { 1751e5f86839SSylwester Nawrocki if (i >= FIMC_CLK_MUX) 1752e5f86839SSylwester Nawrocki break; 1753e5f86839SSylwester Nawrocki ret = PTR_ERR(ctx->clocks[i]); 1754e5f86839SSylwester Nawrocki dev_err(fimc_dev, "failed to get clock: %s\n", 1755e5f86839SSylwester Nawrocki fimc_clock_names[i]); 1756e5f86839SSylwester Nawrocki goto e_clk_free; 1757e5f86839SSylwester Nawrocki } 1758e5f86839SSylwester Nawrocki } 1759e5f86839SSylwester Nawrocki 1760e5f86839SSylwester Nawrocki /* Optional FIMC LCLK parent clock setting */ 1761e5f86839SSylwester Nawrocki if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) { 1762e5f86839SSylwester Nawrocki ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX], 1763e5f86839SSylwester Nawrocki ctx->clocks[FIMC_CLK_PARENT]); 1764e5f86839SSylwester Nawrocki if (ret < 0) { 1765e5f86839SSylwester Nawrocki dev_err(fimc_dev, "failed to set parent.\n"); 1766e5f86839SSylwester Nawrocki goto e_clk_free; 1767e5f86839SSylwester Nawrocki } 1768e5f86839SSylwester Nawrocki } 1769e5f86839SSylwester Nawrocki 1770e5f86839SSylwester Nawrocki ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency); 1771e5f86839SSylwester Nawrocki if (ret < 0) 1772e5f86839SSylwester Nawrocki goto e_clk_free; 1773e5f86839SSylwester Nawrocki 1774e5f86839SSylwester Nawrocki ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]); 1775e5f86839SSylwester Nawrocki if (!ret) 1776e5f86839SSylwester Nawrocki return ret; 1777e5f86839SSylwester Nawrocki e_clk_free: 1778e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 1779e5f86839SSylwester Nawrocki return ret; 1780e5f86839SSylwester Nawrocki } 1781e5f86839SSylwester Nawrocki 17825186fc5eSSylwester Nawrocki static int fimc_parse_dt(struct fimc_context *ctx) 17835186fc5eSSylwester Nawrocki { 17845186fc5eSSylwester Nawrocki struct device_node *node = ctx->ippdrv.dev->of_node; 17855186fc5eSSylwester Nawrocki 17865186fc5eSSylwester Nawrocki /* Handle only devices that support the LCD Writeback data path */ 17875186fc5eSSylwester Nawrocki if (!of_property_read_bool(node, "samsung,lcd-wb")) 17885186fc5eSSylwester Nawrocki return -ENODEV; 17895186fc5eSSylwester Nawrocki 17905186fc5eSSylwester Nawrocki if (of_property_read_u32(node, "clock-frequency", 17915186fc5eSSylwester Nawrocki &ctx->clk_frequency)) 17925186fc5eSSylwester Nawrocki ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY; 17935186fc5eSSylwester Nawrocki 17945186fc5eSSylwester Nawrocki ctx->id = of_alias_get_id(node, "fimc"); 17955186fc5eSSylwester Nawrocki 17965186fc5eSSylwester Nawrocki if (ctx->id < 0) { 17975186fc5eSSylwester Nawrocki dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n"); 17985186fc5eSSylwester Nawrocki return -EINVAL; 17995186fc5eSSylwester Nawrocki } 18005186fc5eSSylwester Nawrocki 18015186fc5eSSylwester Nawrocki return 0; 18025186fc5eSSylwester Nawrocki } 18035186fc5eSSylwester Nawrocki 180456550d94SGreg Kroah-Hartman static int fimc_probe(struct platform_device *pdev) 180516102edbSEunchul Kim { 180616102edbSEunchul Kim struct device *dev = &pdev->dev; 180716102edbSEunchul Kim struct fimc_context *ctx; 180816102edbSEunchul Kim struct resource *res; 180916102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv; 181016102edbSEunchul Kim int ret; 181116102edbSEunchul Kim 18125186fc5eSSylwester Nawrocki if (!dev->of_node) { 18135186fc5eSSylwester Nawrocki dev_err(dev, "device tree node not found.\n"); 18145186fc5eSSylwester Nawrocki return -ENODEV; 181516102edbSEunchul Kim } 181616102edbSEunchul Kim 181716102edbSEunchul Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 181816102edbSEunchul Kim if (!ctx) 181916102edbSEunchul Kim return -ENOMEM; 182016102edbSEunchul Kim 18215186fc5eSSylwester Nawrocki ctx->ippdrv.dev = dev; 18225186fc5eSSylwester Nawrocki 18235186fc5eSSylwester Nawrocki ret = fimc_parse_dt(ctx); 18245186fc5eSSylwester Nawrocki if (ret < 0) 18255186fc5eSSylwester Nawrocki return ret; 18265186fc5eSSylwester Nawrocki 18275186fc5eSSylwester Nawrocki ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 18285186fc5eSSylwester Nawrocki "samsung,sysreg"); 18295186fc5eSSylwester Nawrocki if (IS_ERR(ctx->sysreg)) { 18305186fc5eSSylwester Nawrocki dev_err(dev, "syscon regmap lookup failed.\n"); 18315186fc5eSSylwester Nawrocki return PTR_ERR(ctx->sysreg); 18325186fc5eSSylwester Nawrocki } 18335186fc5eSSylwester Nawrocki 183416102edbSEunchul Kim /* resource memory */ 183516102edbSEunchul Kim ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1836d4ed6025SThierry Reding ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); 1837d4ed6025SThierry Reding if (IS_ERR(ctx->regs)) 1838d4ed6025SThierry Reding return PTR_ERR(ctx->regs); 183916102edbSEunchul Kim 184016102edbSEunchul Kim /* resource irq */ 184116102edbSEunchul Kim res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 184216102edbSEunchul Kim if (!res) { 184316102edbSEunchul Kim dev_err(dev, "failed to request irq resource.\n"); 184415b3263eSSachin Kamat return -ENOENT; 184516102edbSEunchul Kim } 184616102edbSEunchul Kim 184716102edbSEunchul Kim ctx->irq = res->start; 184816102edbSEunchul Kim ret = request_threaded_irq(ctx->irq, NULL, fimc_irq_handler, 184916102edbSEunchul Kim IRQF_ONESHOT, "drm_fimc", ctx); 185016102edbSEunchul Kim if (ret < 0) { 185116102edbSEunchul Kim dev_err(dev, "failed to request irq.\n"); 185215b3263eSSachin Kamat return ret; 185316102edbSEunchul Kim } 185416102edbSEunchul Kim 1855e5f86839SSylwester Nawrocki ret = fimc_setup_clocks(ctx); 1856e5f86839SSylwester Nawrocki if (ret < 0) 1857e5f86839SSylwester Nawrocki goto err_free_irq; 185816102edbSEunchul Kim 185916102edbSEunchul Kim ippdrv = &ctx->ippdrv; 186016102edbSEunchul Kim ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops; 186116102edbSEunchul Kim ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops; 186216102edbSEunchul Kim ippdrv->check_property = fimc_ippdrv_check_property; 186316102edbSEunchul Kim ippdrv->reset = fimc_ippdrv_reset; 186416102edbSEunchul Kim ippdrv->start = fimc_ippdrv_start; 186516102edbSEunchul Kim ippdrv->stop = fimc_ippdrv_stop; 186616102edbSEunchul Kim ret = fimc_init_prop_list(ippdrv); 186716102edbSEunchul Kim if (ret < 0) { 186816102edbSEunchul Kim dev_err(dev, "failed to init property list.\n"); 1869e5f86839SSylwester Nawrocki goto err_put_clk; 187016102edbSEunchul Kim } 187116102edbSEunchul Kim 187216102edbSEunchul Kim DRM_DEBUG_KMS("%s:id[%d]ippdrv[0x%x]\n", __func__, ctx->id, 187316102edbSEunchul Kim (int)ippdrv); 187416102edbSEunchul Kim 187516102edbSEunchul Kim mutex_init(&ctx->lock); 187616102edbSEunchul Kim platform_set_drvdata(pdev, ctx); 187716102edbSEunchul Kim 187816102edbSEunchul Kim pm_runtime_set_active(dev); 187916102edbSEunchul Kim pm_runtime_enable(dev); 188016102edbSEunchul Kim 188116102edbSEunchul Kim ret = exynos_drm_ippdrv_register(ippdrv); 188216102edbSEunchul Kim if (ret < 0) { 188316102edbSEunchul Kim dev_err(dev, "failed to register drm fimc device.\n"); 1884e5f86839SSylwester Nawrocki goto err_pm_dis; 188516102edbSEunchul Kim } 188616102edbSEunchul Kim 1887d873ab99SSeung-Woo Kim dev_info(dev, "drm fimc registered successfully.\n"); 188816102edbSEunchul Kim 188916102edbSEunchul Kim return 0; 189016102edbSEunchul Kim 1891e5f86839SSylwester Nawrocki err_pm_dis: 189216102edbSEunchul Kim pm_runtime_disable(dev); 1893e5f86839SSylwester Nawrocki err_put_clk: 1894e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 1895e5f86839SSylwester Nawrocki err_free_irq: 189616102edbSEunchul Kim free_irq(ctx->irq, ctx); 189787acdde5SSachin Kamat 189816102edbSEunchul Kim return ret; 189916102edbSEunchul Kim } 190016102edbSEunchul Kim 190156550d94SGreg Kroah-Hartman static int fimc_remove(struct platform_device *pdev) 190216102edbSEunchul Kim { 190316102edbSEunchul Kim struct device *dev = &pdev->dev; 190416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 190516102edbSEunchul Kim struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; 190616102edbSEunchul Kim 190716102edbSEunchul Kim exynos_drm_ippdrv_unregister(ippdrv); 190816102edbSEunchul Kim mutex_destroy(&ctx->lock); 190916102edbSEunchul Kim 1910e5f86839SSylwester Nawrocki fimc_put_clocks(ctx); 191116102edbSEunchul Kim pm_runtime_set_suspended(dev); 191216102edbSEunchul Kim pm_runtime_disable(dev); 191316102edbSEunchul Kim 191416102edbSEunchul Kim free_irq(ctx->irq, ctx); 191516102edbSEunchul Kim 191616102edbSEunchul Kim return 0; 191716102edbSEunchul Kim } 191816102edbSEunchul Kim 191916102edbSEunchul Kim #ifdef CONFIG_PM_SLEEP 192016102edbSEunchul Kim static int fimc_suspend(struct device *dev) 192116102edbSEunchul Kim { 192216102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 192316102edbSEunchul Kim 192416102edbSEunchul Kim DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id); 192516102edbSEunchul Kim 192616102edbSEunchul Kim if (pm_runtime_suspended(dev)) 192716102edbSEunchul Kim return 0; 192816102edbSEunchul Kim 192916102edbSEunchul Kim return fimc_clk_ctrl(ctx, false); 193016102edbSEunchul Kim } 193116102edbSEunchul Kim 193216102edbSEunchul Kim static int fimc_resume(struct device *dev) 193316102edbSEunchul Kim { 193416102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 193516102edbSEunchul Kim 193616102edbSEunchul Kim DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id); 193716102edbSEunchul Kim 193816102edbSEunchul Kim if (!pm_runtime_suspended(dev)) 193916102edbSEunchul Kim return fimc_clk_ctrl(ctx, true); 194016102edbSEunchul Kim 194116102edbSEunchul Kim return 0; 194216102edbSEunchul Kim } 194316102edbSEunchul Kim #endif 194416102edbSEunchul Kim 194516102edbSEunchul Kim #ifdef CONFIG_PM_RUNTIME 194616102edbSEunchul Kim static int fimc_runtime_suspend(struct device *dev) 194716102edbSEunchul Kim { 194816102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 194916102edbSEunchul Kim 195016102edbSEunchul Kim DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id); 195116102edbSEunchul Kim 195216102edbSEunchul Kim return fimc_clk_ctrl(ctx, false); 195316102edbSEunchul Kim } 195416102edbSEunchul Kim 195516102edbSEunchul Kim static int fimc_runtime_resume(struct device *dev) 195616102edbSEunchul Kim { 195716102edbSEunchul Kim struct fimc_context *ctx = get_fimc_context(dev); 195816102edbSEunchul Kim 195916102edbSEunchul Kim DRM_DEBUG_KMS("%s:id[%d]\n", __func__, ctx->id); 196016102edbSEunchul Kim 196116102edbSEunchul Kim return fimc_clk_ctrl(ctx, true); 196216102edbSEunchul Kim } 196316102edbSEunchul Kim #endif 196416102edbSEunchul Kim 196516102edbSEunchul Kim static const struct dev_pm_ops fimc_pm_ops = { 196616102edbSEunchul Kim SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) 196716102edbSEunchul Kim SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) 196816102edbSEunchul Kim }; 196916102edbSEunchul Kim 19705186fc5eSSylwester Nawrocki static const struct of_device_id fimc_of_match[] = { 19715186fc5eSSylwester Nawrocki { .compatible = "samsung,exynos4210-fimc" }, 19725186fc5eSSylwester Nawrocki { .compatible = "samsung,exynos4212-fimc" }, 19735186fc5eSSylwester Nawrocki { }, 19745186fc5eSSylwester Nawrocki }; 19755186fc5eSSylwester Nawrocki 197616102edbSEunchul Kim struct platform_driver fimc_driver = { 197716102edbSEunchul Kim .probe = fimc_probe, 197856550d94SGreg Kroah-Hartman .remove = fimc_remove, 197916102edbSEunchul Kim .driver = { 19805186fc5eSSylwester Nawrocki .of_match_table = fimc_of_match, 198116102edbSEunchul Kim .name = "exynos-drm-fimc", 198216102edbSEunchul Kim .owner = THIS_MODULE, 198316102edbSEunchul Kim .pm = &fimc_pm_ops, 198416102edbSEunchul Kim }, 198516102edbSEunchul Kim }; 198616102edbSEunchul Kim 1987