1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Samsung SoC MIPI DSI Master driver.
4  *
5  * Copyright (c) 2014 Samsung Electronics Co., Ltd
6  *
7  * Contacts: Tomasz Figa <t.figa@samsung.com>
8 */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/component.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/irq.h>
15 #include <linux/of_device.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_graph.h>
18 #include <linux/phy/phy.h>
19 #include <linux/regulator/consumer.h>
20 
21 #include <asm/unaligned.h>
22 
23 #include <video/mipi_display.h>
24 #include <video/videomode.h>
25 
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_fb_helper.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include <drm/drm_panel.h>
31 #include <drm/drm_print.h>
32 #include <drm/drm_probe_helper.h>
33 #include <drm/drm_simple_kms_helper.h>
34 
35 #include "exynos_drm_crtc.h"
36 #include "exynos_drm_drv.h"
37 
38 /* returns true iff both arguments logically differs */
39 #define NEQV(a, b) (!(a) ^ !(b))
40 
41 /* DSIM_STATUS */
42 #define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
43 #define DSIM_STOP_STATE_CLK		(1 << 8)
44 #define DSIM_TX_READY_HS_CLK		(1 << 10)
45 #define DSIM_PLL_STABLE			(1 << 31)
46 
47 /* DSIM_SWRST */
48 #define DSIM_FUNCRST			(1 << 16)
49 #define DSIM_SWRST			(1 << 0)
50 
51 /* DSIM_TIMEOUT */
52 #define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
53 #define DSIM_BTA_TIMEOUT(x)		((x) << 16)
54 
55 /* DSIM_CLKCTRL */
56 #define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
57 #define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
58 #define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
59 #define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
60 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
61 #define DSIM_BYTE_CLKEN			(1 << 24)
62 #define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
63 #define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
64 #define DSIM_PLL_BYPASS			(1 << 27)
65 #define DSIM_ESC_CLKEN			(1 << 28)
66 #define DSIM_TX_REQUEST_HSCLK		(1 << 31)
67 
68 /* DSIM_CONFIG */
69 #define DSIM_LANE_EN_CLK		(1 << 0)
70 #define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
71 #define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
72 #define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
73 #define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
74 #define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
75 #define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
76 #define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
77 #define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
78 #define DSIM_SUB_VC			(((x) & 0x3) << 16)
79 #define DSIM_MAIN_VC			(((x) & 0x3) << 18)
80 #define DSIM_HSA_MODE			(1 << 20)
81 #define DSIM_HBP_MODE			(1 << 21)
82 #define DSIM_HFP_MODE			(1 << 22)
83 #define DSIM_HSE_MODE			(1 << 23)
84 #define DSIM_AUTO_MODE			(1 << 24)
85 #define DSIM_VIDEO_MODE			(1 << 25)
86 #define DSIM_BURST_MODE			(1 << 26)
87 #define DSIM_SYNC_INFORM		(1 << 27)
88 #define DSIM_EOT_DISABLE		(1 << 28)
89 #define DSIM_MFLUSH_VS			(1 << 29)
90 /* This flag is valid only for exynos3250/3472/5260/5430 */
91 #define DSIM_CLKLANE_STOP		(1 << 30)
92 
93 /* DSIM_ESCMODE */
94 #define DSIM_TX_TRIGGER_RST		(1 << 4)
95 #define DSIM_TX_LPDT_LP			(1 << 6)
96 #define DSIM_CMD_LPDT_LP		(1 << 7)
97 #define DSIM_FORCE_BTA			(1 << 16)
98 #define DSIM_FORCE_STOP_STATE		(1 << 20)
99 #define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
100 #define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
101 
102 /* DSIM_MDRESOL */
103 #define DSIM_MAIN_STAND_BY		(1 << 31)
104 #define DSIM_MAIN_VRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 16)
105 #define DSIM_MAIN_HRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 0)
106 
107 /* DSIM_MVPORCH */
108 #define DSIM_CMD_ALLOW(x)		((x) << 28)
109 #define DSIM_STABLE_VFP(x)		((x) << 16)
110 #define DSIM_MAIN_VBP(x)		((x) << 0)
111 #define DSIM_CMD_ALLOW_MASK		(0xf << 28)
112 #define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
113 #define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
114 
115 /* DSIM_MHPORCH */
116 #define DSIM_MAIN_HFP(x)		((x) << 16)
117 #define DSIM_MAIN_HBP(x)		((x) << 0)
118 #define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
119 #define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
120 
121 /* DSIM_MSYNC */
122 #define DSIM_MAIN_VSA(x)		((x) << 22)
123 #define DSIM_MAIN_HSA(x)		((x) << 0)
124 #define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
125 #define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
126 
127 /* DSIM_SDRESOL */
128 #define DSIM_SUB_STANDY(x)		((x) << 31)
129 #define DSIM_SUB_VRESOL(x)		((x) << 16)
130 #define DSIM_SUB_HRESOL(x)		((x) << 0)
131 #define DSIM_SUB_STANDY_MASK		((0x1) << 31)
132 #define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
133 #define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
134 
135 /* DSIM_INTSRC */
136 #define DSIM_INT_PLL_STABLE		(1 << 31)
137 #define DSIM_INT_SW_RST_RELEASE		(1 << 30)
138 #define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
139 #define DSIM_INT_SFR_HDR_FIFO_EMPTY	(1 << 28)
140 #define DSIM_INT_BTA			(1 << 25)
141 #define DSIM_INT_FRAME_DONE		(1 << 24)
142 #define DSIM_INT_RX_TIMEOUT		(1 << 21)
143 #define DSIM_INT_BTA_TIMEOUT		(1 << 20)
144 #define DSIM_INT_RX_DONE		(1 << 18)
145 #define DSIM_INT_RX_TE			(1 << 17)
146 #define DSIM_INT_RX_ACK			(1 << 16)
147 #define DSIM_INT_RX_ECC_ERR		(1 << 15)
148 #define DSIM_INT_RX_CRC_ERR		(1 << 14)
149 
150 /* DSIM_FIFOCTRL */
151 #define DSIM_RX_DATA_FULL		(1 << 25)
152 #define DSIM_RX_DATA_EMPTY		(1 << 24)
153 #define DSIM_SFR_HEADER_FULL		(1 << 23)
154 #define DSIM_SFR_HEADER_EMPTY		(1 << 22)
155 #define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
156 #define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
157 #define DSIM_I80_HEADER_FULL		(1 << 19)
158 #define DSIM_I80_HEADER_EMPTY		(1 << 18)
159 #define DSIM_I80_PAYLOAD_FULL		(1 << 17)
160 #define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
161 #define DSIM_SD_HEADER_FULL		(1 << 15)
162 #define DSIM_SD_HEADER_EMPTY		(1 << 14)
163 #define DSIM_SD_PAYLOAD_FULL		(1 << 13)
164 #define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
165 #define DSIM_MD_HEADER_FULL		(1 << 11)
166 #define DSIM_MD_HEADER_EMPTY		(1 << 10)
167 #define DSIM_MD_PAYLOAD_FULL		(1 << 9)
168 #define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
169 #define DSIM_RX_FIFO			(1 << 4)
170 #define DSIM_SFR_FIFO			(1 << 3)
171 #define DSIM_I80_FIFO			(1 << 2)
172 #define DSIM_SD_FIFO			(1 << 1)
173 #define DSIM_MD_FIFO			(1 << 0)
174 
175 /* DSIM_PHYACCHR */
176 #define DSIM_AFC_EN			(1 << 14)
177 #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
178 
179 /* DSIM_PLLCTRL */
180 #define DSIM_FREQ_BAND(x)		((x) << 24)
181 #define DSIM_PLL_EN			(1 << 23)
182 #define DSIM_PLL_P(x)			((x) << 13)
183 #define DSIM_PLL_M(x)			((x) << 4)
184 #define DSIM_PLL_S(x)			((x) << 1)
185 
186 /* DSIM_PHYCTRL */
187 #define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
188 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP	(1 << 30)
189 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP	(1 << 14)
190 
191 /* DSIM_PHYTIMING */
192 #define DSIM_PHYTIMING_LPX(x)		((x) << 8)
193 #define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
194 
195 /* DSIM_PHYTIMING1 */
196 #define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
197 #define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
198 #define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
199 #define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
200 
201 /* DSIM_PHYTIMING2 */
202 #define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
203 #define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
204 #define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
205 
206 #define DSI_MAX_BUS_WIDTH		4
207 #define DSI_NUM_VIRTUAL_CHANNELS	4
208 #define DSI_TX_FIFO_SIZE		2048
209 #define DSI_RX_FIFO_SIZE		256
210 #define DSI_XFER_TIMEOUT_MS		100
211 #define DSI_RX_FIFO_EMPTY		0x30800002
212 
213 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
214 
215 static const char *const clk_names[5] = { "bus_clk", "sclk_mipi",
216 	"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
217 	"sclk_rgb_vclk_to_dsim0" };
218 
219 enum exynos_dsi_transfer_type {
220 	EXYNOS_DSI_TX,
221 	EXYNOS_DSI_RX,
222 };
223 
224 struct exynos_dsi_transfer {
225 	struct list_head list;
226 	struct completion completed;
227 	int result;
228 	struct mipi_dsi_packet packet;
229 	u16 flags;
230 	u16 tx_done;
231 
232 	u8 *rx_payload;
233 	u16 rx_len;
234 	u16 rx_done;
235 };
236 
237 #define DSIM_STATE_ENABLED		BIT(0)
238 #define DSIM_STATE_INITIALIZED		BIT(1)
239 #define DSIM_STATE_CMD_LPM		BIT(2)
240 #define DSIM_STATE_VIDOUT_AVAILABLE	BIT(3)
241 
242 struct exynos_dsi_driver_data {
243 	const unsigned int *reg_ofs;
244 	unsigned int plltmr_reg;
245 	unsigned int has_freqband:1;
246 	unsigned int has_clklane_stop:1;
247 	unsigned int num_clks;
248 	unsigned int max_freq;
249 	unsigned int wait_for_reset;
250 	unsigned int num_bits_resol;
251 	const unsigned int *reg_values;
252 };
253 
254 struct exynos_dsi {
255 	struct drm_encoder encoder;
256 	struct mipi_dsi_host dsi_host;
257 	struct drm_connector connector;
258 	struct drm_panel *panel;
259 	struct list_head bridge_chain;
260 	struct drm_bridge *out_bridge;
261 	struct device *dev;
262 
263 	void __iomem *reg_base;
264 	struct phy *phy;
265 	struct clk **clks;
266 	struct regulator_bulk_data supplies[2];
267 	int irq;
268 	int te_gpio;
269 
270 	u32 pll_clk_rate;
271 	u32 burst_clk_rate;
272 	u32 esc_clk_rate;
273 	u32 lanes;
274 	u32 mode_flags;
275 	u32 format;
276 
277 	int state;
278 	struct drm_property *brightness;
279 	struct completion completed;
280 
281 	spinlock_t transfer_lock; /* protects transfer_list */
282 	struct list_head transfer_list;
283 
284 	const struct exynos_dsi_driver_data *driver_data;
285 };
286 
287 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
288 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
289 
290 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
291 {
292 	return container_of(e, struct exynos_dsi, encoder);
293 }
294 
295 enum reg_idx {
296 	DSIM_STATUS_REG,	/* Status register */
297 	DSIM_SWRST_REG,		/* Software reset register */
298 	DSIM_CLKCTRL_REG,	/* Clock control register */
299 	DSIM_TIMEOUT_REG,	/* Time out register */
300 	DSIM_CONFIG_REG,	/* Configuration register */
301 	DSIM_ESCMODE_REG,	/* Escape mode register */
302 	DSIM_MDRESOL_REG,
303 	DSIM_MVPORCH_REG,	/* Main display Vporch register */
304 	DSIM_MHPORCH_REG,	/* Main display Hporch register */
305 	DSIM_MSYNC_REG,		/* Main display sync area register */
306 	DSIM_INTSRC_REG,	/* Interrupt source register */
307 	DSIM_INTMSK_REG,	/* Interrupt mask register */
308 	DSIM_PKTHDR_REG,	/* Packet Header FIFO register */
309 	DSIM_PAYLOAD_REG,	/* Payload FIFO register */
310 	DSIM_RXFIFO_REG,	/* Read FIFO register */
311 	DSIM_FIFOCTRL_REG,	/* FIFO status and control register */
312 	DSIM_PLLCTRL_REG,	/* PLL control register */
313 	DSIM_PHYCTRL_REG,
314 	DSIM_PHYTIMING_REG,
315 	DSIM_PHYTIMING1_REG,
316 	DSIM_PHYTIMING2_REG,
317 	NUM_REGS
318 };
319 
320 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
321 				    u32 val)
322 {
323 
324 	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
325 }
326 
327 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
328 {
329 	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
330 }
331 
332 static const unsigned int exynos_reg_ofs[] = {
333 	[DSIM_STATUS_REG] =  0x00,
334 	[DSIM_SWRST_REG] =  0x04,
335 	[DSIM_CLKCTRL_REG] =  0x08,
336 	[DSIM_TIMEOUT_REG] =  0x0c,
337 	[DSIM_CONFIG_REG] =  0x10,
338 	[DSIM_ESCMODE_REG] =  0x14,
339 	[DSIM_MDRESOL_REG] =  0x18,
340 	[DSIM_MVPORCH_REG] =  0x1c,
341 	[DSIM_MHPORCH_REG] =  0x20,
342 	[DSIM_MSYNC_REG] =  0x24,
343 	[DSIM_INTSRC_REG] =  0x2c,
344 	[DSIM_INTMSK_REG] =  0x30,
345 	[DSIM_PKTHDR_REG] =  0x34,
346 	[DSIM_PAYLOAD_REG] =  0x38,
347 	[DSIM_RXFIFO_REG] =  0x3c,
348 	[DSIM_FIFOCTRL_REG] =  0x44,
349 	[DSIM_PLLCTRL_REG] =  0x4c,
350 	[DSIM_PHYCTRL_REG] =  0x5c,
351 	[DSIM_PHYTIMING_REG] =  0x64,
352 	[DSIM_PHYTIMING1_REG] =  0x68,
353 	[DSIM_PHYTIMING2_REG] =  0x6c,
354 };
355 
356 static const unsigned int exynos5433_reg_ofs[] = {
357 	[DSIM_STATUS_REG] = 0x04,
358 	[DSIM_SWRST_REG] = 0x0C,
359 	[DSIM_CLKCTRL_REG] = 0x10,
360 	[DSIM_TIMEOUT_REG] = 0x14,
361 	[DSIM_CONFIG_REG] = 0x18,
362 	[DSIM_ESCMODE_REG] = 0x1C,
363 	[DSIM_MDRESOL_REG] = 0x20,
364 	[DSIM_MVPORCH_REG] = 0x24,
365 	[DSIM_MHPORCH_REG] = 0x28,
366 	[DSIM_MSYNC_REG] = 0x2C,
367 	[DSIM_INTSRC_REG] = 0x34,
368 	[DSIM_INTMSK_REG] = 0x38,
369 	[DSIM_PKTHDR_REG] = 0x3C,
370 	[DSIM_PAYLOAD_REG] = 0x40,
371 	[DSIM_RXFIFO_REG] = 0x44,
372 	[DSIM_FIFOCTRL_REG] = 0x4C,
373 	[DSIM_PLLCTRL_REG] = 0x94,
374 	[DSIM_PHYCTRL_REG] = 0xA4,
375 	[DSIM_PHYTIMING_REG] = 0xB4,
376 	[DSIM_PHYTIMING1_REG] = 0xB8,
377 	[DSIM_PHYTIMING2_REG] = 0xBC,
378 };
379 
380 enum reg_value_idx {
381 	RESET_TYPE,
382 	PLL_TIMER,
383 	STOP_STATE_CNT,
384 	PHYCTRL_ULPS_EXIT,
385 	PHYCTRL_VREG_LP,
386 	PHYCTRL_SLEW_UP,
387 	PHYTIMING_LPX,
388 	PHYTIMING_HS_EXIT,
389 	PHYTIMING_CLK_PREPARE,
390 	PHYTIMING_CLK_ZERO,
391 	PHYTIMING_CLK_POST,
392 	PHYTIMING_CLK_TRAIL,
393 	PHYTIMING_HS_PREPARE,
394 	PHYTIMING_HS_ZERO,
395 	PHYTIMING_HS_TRAIL
396 };
397 
398 static const unsigned int reg_values[] = {
399 	[RESET_TYPE] = DSIM_SWRST,
400 	[PLL_TIMER] = 500,
401 	[STOP_STATE_CNT] = 0xf,
402 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
403 	[PHYCTRL_VREG_LP] = 0,
404 	[PHYCTRL_SLEW_UP] = 0,
405 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
406 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
407 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
408 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
409 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
410 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
411 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
412 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
413 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
414 };
415 
416 static const unsigned int exynos5422_reg_values[] = {
417 	[RESET_TYPE] = DSIM_SWRST,
418 	[PLL_TIMER] = 500,
419 	[STOP_STATE_CNT] = 0xf,
420 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
421 	[PHYCTRL_VREG_LP] = 0,
422 	[PHYCTRL_SLEW_UP] = 0,
423 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
424 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
425 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
426 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
427 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
428 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
429 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
430 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
431 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
432 };
433 
434 static const unsigned int exynos5433_reg_values[] = {
435 	[RESET_TYPE] = DSIM_FUNCRST,
436 	[PLL_TIMER] = 22200,
437 	[STOP_STATE_CNT] = 0xa,
438 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
439 	[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
440 	[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
441 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
442 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
443 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
444 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
445 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
446 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
447 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
448 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
449 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
450 };
451 
452 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
453 	.reg_ofs = exynos_reg_ofs,
454 	.plltmr_reg = 0x50,
455 	.has_freqband = 1,
456 	.has_clklane_stop = 1,
457 	.num_clks = 2,
458 	.max_freq = 1000,
459 	.wait_for_reset = 1,
460 	.num_bits_resol = 11,
461 	.reg_values = reg_values,
462 };
463 
464 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
465 	.reg_ofs = exynos_reg_ofs,
466 	.plltmr_reg = 0x50,
467 	.has_freqband = 1,
468 	.has_clklane_stop = 1,
469 	.num_clks = 2,
470 	.max_freq = 1000,
471 	.wait_for_reset = 1,
472 	.num_bits_resol = 11,
473 	.reg_values = reg_values,
474 };
475 
476 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
477 	.reg_ofs = exynos_reg_ofs,
478 	.plltmr_reg = 0x58,
479 	.num_clks = 2,
480 	.max_freq = 1000,
481 	.wait_for_reset = 1,
482 	.num_bits_resol = 11,
483 	.reg_values = reg_values,
484 };
485 
486 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
487 	.reg_ofs = exynos5433_reg_ofs,
488 	.plltmr_reg = 0xa0,
489 	.has_clklane_stop = 1,
490 	.num_clks = 5,
491 	.max_freq = 1500,
492 	.wait_for_reset = 0,
493 	.num_bits_resol = 12,
494 	.reg_values = exynos5433_reg_values,
495 };
496 
497 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
498 	.reg_ofs = exynos5433_reg_ofs,
499 	.plltmr_reg = 0xa0,
500 	.has_clklane_stop = 1,
501 	.num_clks = 2,
502 	.max_freq = 1500,
503 	.wait_for_reset = 1,
504 	.num_bits_resol = 12,
505 	.reg_values = exynos5422_reg_values,
506 };
507 
508 static const struct of_device_id exynos_dsi_of_match[] = {
509 	{ .compatible = "samsung,exynos3250-mipi-dsi",
510 	  .data = &exynos3_dsi_driver_data },
511 	{ .compatible = "samsung,exynos4210-mipi-dsi",
512 	  .data = &exynos4_dsi_driver_data },
513 	{ .compatible = "samsung,exynos5410-mipi-dsi",
514 	  .data = &exynos5_dsi_driver_data },
515 	{ .compatible = "samsung,exynos5422-mipi-dsi",
516 	  .data = &exynos5422_dsi_driver_data },
517 	{ .compatible = "samsung,exynos5433-mipi-dsi",
518 	  .data = &exynos5433_dsi_driver_data },
519 	{ }
520 };
521 
522 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
523 {
524 	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
525 		return;
526 
527 	dev_err(dsi->dev, "timeout waiting for reset\n");
528 }
529 
530 static void exynos_dsi_reset(struct exynos_dsi *dsi)
531 {
532 	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
533 
534 	reinit_completion(&dsi->completed);
535 	exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
536 }
537 
538 #ifndef MHZ
539 #define MHZ	(1000*1000)
540 #endif
541 
542 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
543 		unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
544 {
545 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
546 	unsigned long best_freq = 0;
547 	u32 min_delta = 0xffffffff;
548 	u8 p_min, p_max;
549 	u8 _p, best_p;
550 	u16 _m, best_m;
551 	u8 _s, best_s;
552 
553 	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
554 	p_max = fin / (6 * MHZ);
555 
556 	for (_p = p_min; _p <= p_max; ++_p) {
557 		for (_s = 0; _s <= 5; ++_s) {
558 			u64 tmp;
559 			u32 delta;
560 
561 			tmp = (u64)fout * (_p << _s);
562 			do_div(tmp, fin);
563 			_m = tmp;
564 			if (_m < 41 || _m > 125)
565 				continue;
566 
567 			tmp = (u64)_m * fin;
568 			do_div(tmp, _p);
569 			if (tmp < 500 * MHZ ||
570 					tmp > driver_data->max_freq * MHZ)
571 				continue;
572 
573 			tmp = (u64)_m * fin;
574 			do_div(tmp, _p << _s);
575 
576 			delta = abs(fout - tmp);
577 			if (delta < min_delta) {
578 				best_p = _p;
579 				best_m = _m;
580 				best_s = _s;
581 				min_delta = delta;
582 				best_freq = tmp;
583 			}
584 		}
585 	}
586 
587 	if (best_freq) {
588 		*p = best_p;
589 		*m = best_m;
590 		*s = best_s;
591 	}
592 
593 	return best_freq;
594 }
595 
596 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
597 					unsigned long freq)
598 {
599 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
600 	unsigned long fin, fout;
601 	int timeout;
602 	u8 p, s;
603 	u16 m;
604 	u32 reg;
605 
606 	fin = dsi->pll_clk_rate;
607 	fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
608 	if (!fout) {
609 		dev_err(dsi->dev,
610 			"failed to find PLL PMS for requested frequency\n");
611 		return 0;
612 	}
613 	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
614 
615 	writel(driver_data->reg_values[PLL_TIMER],
616 			dsi->reg_base + driver_data->plltmr_reg);
617 
618 	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
619 
620 	if (driver_data->has_freqband) {
621 		static const unsigned long freq_bands[] = {
622 			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
623 			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
624 			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
625 			770 * MHZ, 870 * MHZ, 950 * MHZ,
626 		};
627 		int band;
628 
629 		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
630 			if (fout < freq_bands[band])
631 				break;
632 
633 		dev_dbg(dsi->dev, "band %d\n", band);
634 
635 		reg |= DSIM_FREQ_BAND(band);
636 	}
637 
638 	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
639 
640 	timeout = 1000;
641 	do {
642 		if (timeout-- == 0) {
643 			dev_err(dsi->dev, "PLL failed to stabilize\n");
644 			return 0;
645 		}
646 		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
647 	} while ((reg & DSIM_PLL_STABLE) == 0);
648 
649 	return fout;
650 }
651 
652 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
653 {
654 	unsigned long hs_clk, byte_clk, esc_clk;
655 	unsigned long esc_div;
656 	u32 reg;
657 
658 	hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
659 	if (!hs_clk) {
660 		dev_err(dsi->dev, "failed to configure DSI PLL\n");
661 		return -EFAULT;
662 	}
663 
664 	byte_clk = hs_clk / 8;
665 	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
666 	esc_clk = byte_clk / esc_div;
667 
668 	if (esc_clk > 20 * MHZ) {
669 		++esc_div;
670 		esc_clk = byte_clk / esc_div;
671 	}
672 
673 	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
674 		hs_clk, byte_clk, esc_clk);
675 
676 	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
677 	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
678 			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
679 			| DSIM_BYTE_CLK_SRC_MASK);
680 	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
681 			| DSIM_ESC_PRESCALER(esc_div)
682 			| DSIM_LANE_ESC_CLK_EN_CLK
683 			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
684 			| DSIM_BYTE_CLK_SRC(0)
685 			| DSIM_TX_REQUEST_HSCLK;
686 	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
687 
688 	return 0;
689 }
690 
691 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
692 {
693 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
694 	const unsigned int *reg_values = driver_data->reg_values;
695 	u32 reg;
696 
697 	if (driver_data->has_freqband)
698 		return;
699 
700 	/* B D-PHY: D-PHY Master & Slave Analog Block control */
701 	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
702 		reg_values[PHYCTRL_SLEW_UP];
703 	exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
704 
705 	/*
706 	 * T LPX: Transmitted length of any Low-Power state period
707 	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
708 	 *	burst
709 	 */
710 	reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
711 	exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
712 
713 	/*
714 	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
715 	 *	Line state immediately before the HS-0 Line state starting the
716 	 *	HS transmission
717 	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
718 	 *	transmitting the Clock.
719 	 * T CLK_POST: Time that the transmitter continues to send HS clock
720 	 *	after the last associated Data Lane has transitioned to LP Mode
721 	 *	Interval is defined as the period from the end of T HS-TRAIL to
722 	 *	the beginning of T CLK-TRAIL
723 	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
724 	 *	the last payload clock bit of a HS transmission burst
725 	 */
726 	reg = reg_values[PHYTIMING_CLK_PREPARE] |
727 		reg_values[PHYTIMING_CLK_ZERO] |
728 		reg_values[PHYTIMING_CLK_POST] |
729 		reg_values[PHYTIMING_CLK_TRAIL];
730 
731 	exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
732 
733 	/*
734 	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
735 	 *	Line state immediately before the HS-0 Line state starting the
736 	 *	HS transmission
737 	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
738 	 *	transmitting the Sync sequence.
739 	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
740 	 *	state after last payload data bit of a HS transmission burst
741 	 */
742 	reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
743 		reg_values[PHYTIMING_HS_TRAIL];
744 	exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
745 }
746 
747 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
748 {
749 	u32 reg;
750 
751 	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
752 	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
753 			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
754 	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
755 
756 	reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
757 	reg &= ~DSIM_PLL_EN;
758 	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
759 }
760 
761 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
762 {
763 	u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
764 	reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
765 			DSIM_LANE_EN(lane));
766 	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
767 }
768 
769 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
770 {
771 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
772 	int timeout;
773 	u32 reg;
774 	u32 lanes_mask;
775 
776 	/* Initialize FIFO pointers */
777 	reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
778 	reg &= ~0x1f;
779 	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
780 
781 	usleep_range(9000, 11000);
782 
783 	reg |= 0x1f;
784 	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
785 	usleep_range(9000, 11000);
786 
787 	/* DSI configuration */
788 	reg = 0;
789 
790 	/*
791 	 * The first bit of mode_flags specifies display configuration.
792 	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
793 	 * mode, otherwise it will support command mode.
794 	 */
795 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
796 		reg |= DSIM_VIDEO_MODE;
797 
798 		/*
799 		 * The user manual describes that following bits are ignored in
800 		 * command mode.
801 		 */
802 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
803 			reg |= DSIM_MFLUSH_VS;
804 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
805 			reg |= DSIM_SYNC_INFORM;
806 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
807 			reg |= DSIM_BURST_MODE;
808 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
809 			reg |= DSIM_AUTO_MODE;
810 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
811 			reg |= DSIM_HSE_MODE;
812 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP))
813 			reg |= DSIM_HFP_MODE;
814 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP))
815 			reg |= DSIM_HBP_MODE;
816 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA))
817 			reg |= DSIM_HSA_MODE;
818 	}
819 
820 	if (!(dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
821 		reg |= DSIM_EOT_DISABLE;
822 
823 	switch (dsi->format) {
824 	case MIPI_DSI_FMT_RGB888:
825 		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
826 		break;
827 	case MIPI_DSI_FMT_RGB666:
828 		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
829 		break;
830 	case MIPI_DSI_FMT_RGB666_PACKED:
831 		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
832 		break;
833 	case MIPI_DSI_FMT_RGB565:
834 		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
835 		break;
836 	default:
837 		dev_err(dsi->dev, "invalid pixel format\n");
838 		return -EINVAL;
839 	}
840 
841 	/*
842 	 * Use non-continuous clock mode if the periparal wants and
843 	 * host controller supports
844 	 *
845 	 * In non-continous clock mode, host controller will turn off
846 	 * the HS clock between high-speed transmissions to reduce
847 	 * power consumption.
848 	 */
849 	if (driver_data->has_clklane_stop &&
850 			dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
851 		reg |= DSIM_CLKLANE_STOP;
852 	}
853 	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
854 
855 	lanes_mask = BIT(dsi->lanes) - 1;
856 	exynos_dsi_enable_lane(dsi, lanes_mask);
857 
858 	/* Check clock and data lane state are stop state */
859 	timeout = 100;
860 	do {
861 		if (timeout-- == 0) {
862 			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
863 			return -EFAULT;
864 		}
865 
866 		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
867 		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
868 		    != DSIM_STOP_STATE_DAT(lanes_mask))
869 			continue;
870 	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
871 
872 	reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
873 	reg &= ~DSIM_STOP_STATE_CNT_MASK;
874 	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
875 	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
876 
877 	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
878 	exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
879 
880 	return 0;
881 }
882 
883 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
884 {
885 	struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode;
886 	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
887 	u32 reg;
888 
889 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
890 		reg = DSIM_CMD_ALLOW(0xf)
891 			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
892 			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
893 		exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
894 
895 		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
896 			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
897 		exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
898 
899 		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
900 			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
901 		exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
902 	}
903 	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
904 		DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
905 
906 	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
907 
908 	dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
909 }
910 
911 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
912 {
913 	u32 reg;
914 
915 	reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
916 	if (enable)
917 		reg |= DSIM_MAIN_STAND_BY;
918 	else
919 		reg &= ~DSIM_MAIN_STAND_BY;
920 	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
921 }
922 
923 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
924 {
925 	int timeout = 2000;
926 
927 	do {
928 		u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
929 
930 		if (!(reg & DSIM_SFR_HEADER_FULL))
931 			return 0;
932 
933 		if (!cond_resched())
934 			usleep_range(950, 1050);
935 	} while (--timeout);
936 
937 	return -ETIMEDOUT;
938 }
939 
940 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
941 {
942 	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
943 
944 	if (lpm)
945 		v |= DSIM_CMD_LPDT_LP;
946 	else
947 		v &= ~DSIM_CMD_LPDT_LP;
948 
949 	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
950 }
951 
952 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
953 {
954 	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
955 	v |= DSIM_FORCE_BTA;
956 	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
957 }
958 
959 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
960 					struct exynos_dsi_transfer *xfer)
961 {
962 	struct device *dev = dsi->dev;
963 	struct mipi_dsi_packet *pkt = &xfer->packet;
964 	const u8 *payload = pkt->payload + xfer->tx_done;
965 	u16 length = pkt->payload_length - xfer->tx_done;
966 	bool first = !xfer->tx_done;
967 	u32 reg;
968 
969 	dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
970 		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
971 
972 	if (length > DSI_TX_FIFO_SIZE)
973 		length = DSI_TX_FIFO_SIZE;
974 
975 	xfer->tx_done += length;
976 
977 	/* Send payload */
978 	while (length >= 4) {
979 		reg = get_unaligned_le32(payload);
980 		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
981 		payload += 4;
982 		length -= 4;
983 	}
984 
985 	reg = 0;
986 	switch (length) {
987 	case 3:
988 		reg |= payload[2] << 16;
989 		fallthrough;
990 	case 2:
991 		reg |= payload[1] << 8;
992 		fallthrough;
993 	case 1:
994 		reg |= payload[0];
995 		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
996 		break;
997 	}
998 
999 	/* Send packet header */
1000 	if (!first)
1001 		return;
1002 
1003 	reg = get_unaligned_le32(pkt->header);
1004 	if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
1005 		dev_err(dev, "waiting for header FIFO timed out\n");
1006 		return;
1007 	}
1008 
1009 	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1010 		 dsi->state & DSIM_STATE_CMD_LPM)) {
1011 		exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1012 		dsi->state ^= DSIM_STATE_CMD_LPM;
1013 	}
1014 
1015 	exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
1016 
1017 	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1018 		exynos_dsi_force_bta(dsi);
1019 }
1020 
1021 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
1022 					struct exynos_dsi_transfer *xfer)
1023 {
1024 	u8 *payload = xfer->rx_payload + xfer->rx_done;
1025 	bool first = !xfer->rx_done;
1026 	struct device *dev = dsi->dev;
1027 	u16 length;
1028 	u32 reg;
1029 
1030 	if (first) {
1031 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1032 
1033 		switch (reg & 0x3f) {
1034 		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1035 		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1036 			if (xfer->rx_len >= 2) {
1037 				payload[1] = reg >> 16;
1038 				++xfer->rx_done;
1039 			}
1040 			fallthrough;
1041 		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1042 		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1043 			payload[0] = reg >> 8;
1044 			++xfer->rx_done;
1045 			xfer->rx_len = xfer->rx_done;
1046 			xfer->result = 0;
1047 			goto clear_fifo;
1048 		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1049 			dev_err(dev, "DSI Error Report: 0x%04x\n",
1050 				(reg >> 8) & 0xffff);
1051 			xfer->result = 0;
1052 			goto clear_fifo;
1053 		}
1054 
1055 		length = (reg >> 8) & 0xffff;
1056 		if (length > xfer->rx_len) {
1057 			dev_err(dev,
1058 				"response too long (%u > %u bytes), stripping\n",
1059 				xfer->rx_len, length);
1060 			length = xfer->rx_len;
1061 		} else if (length < xfer->rx_len)
1062 			xfer->rx_len = length;
1063 	}
1064 
1065 	length = xfer->rx_len - xfer->rx_done;
1066 	xfer->rx_done += length;
1067 
1068 	/* Receive payload */
1069 	while (length >= 4) {
1070 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1071 		payload[0] = (reg >>  0) & 0xff;
1072 		payload[1] = (reg >>  8) & 0xff;
1073 		payload[2] = (reg >> 16) & 0xff;
1074 		payload[3] = (reg >> 24) & 0xff;
1075 		payload += 4;
1076 		length -= 4;
1077 	}
1078 
1079 	if (length) {
1080 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1081 		switch (length) {
1082 		case 3:
1083 			payload[2] = (reg >> 16) & 0xff;
1084 			fallthrough;
1085 		case 2:
1086 			payload[1] = (reg >> 8) & 0xff;
1087 			fallthrough;
1088 		case 1:
1089 			payload[0] = reg & 0xff;
1090 		}
1091 	}
1092 
1093 	if (xfer->rx_done == xfer->rx_len)
1094 		xfer->result = 0;
1095 
1096 clear_fifo:
1097 	length = DSI_RX_FIFO_SIZE / 4;
1098 	do {
1099 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
1100 		if (reg == DSI_RX_FIFO_EMPTY)
1101 			break;
1102 	} while (--length);
1103 }
1104 
1105 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
1106 {
1107 	unsigned long flags;
1108 	struct exynos_dsi_transfer *xfer;
1109 	bool start = false;
1110 
1111 again:
1112 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1113 
1114 	if (list_empty(&dsi->transfer_list)) {
1115 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1116 		return;
1117 	}
1118 
1119 	xfer = list_first_entry(&dsi->transfer_list,
1120 					struct exynos_dsi_transfer, list);
1121 
1122 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1123 
1124 	if (xfer->packet.payload_length &&
1125 	    xfer->tx_done == xfer->packet.payload_length)
1126 		/* waiting for RX */
1127 		return;
1128 
1129 	exynos_dsi_send_to_fifo(dsi, xfer);
1130 
1131 	if (xfer->packet.payload_length || xfer->rx_len)
1132 		return;
1133 
1134 	xfer->result = 0;
1135 	complete(&xfer->completed);
1136 
1137 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1138 
1139 	list_del_init(&xfer->list);
1140 	start = !list_empty(&dsi->transfer_list);
1141 
1142 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1143 
1144 	if (start)
1145 		goto again;
1146 }
1147 
1148 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
1149 {
1150 	struct exynos_dsi_transfer *xfer;
1151 	unsigned long flags;
1152 	bool start = true;
1153 
1154 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1155 
1156 	if (list_empty(&dsi->transfer_list)) {
1157 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1158 		return false;
1159 	}
1160 
1161 	xfer = list_first_entry(&dsi->transfer_list,
1162 					struct exynos_dsi_transfer, list);
1163 
1164 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1165 
1166 	dev_dbg(dsi->dev,
1167 		"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1168 		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1169 		xfer->rx_done);
1170 
1171 	if (xfer->tx_done != xfer->packet.payload_length)
1172 		return true;
1173 
1174 	if (xfer->rx_done != xfer->rx_len)
1175 		exynos_dsi_read_from_fifo(dsi, xfer);
1176 
1177 	if (xfer->rx_done != xfer->rx_len)
1178 		return true;
1179 
1180 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1181 
1182 	list_del_init(&xfer->list);
1183 	start = !list_empty(&dsi->transfer_list);
1184 
1185 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1186 
1187 	if (!xfer->rx_len)
1188 		xfer->result = 0;
1189 	complete(&xfer->completed);
1190 
1191 	return start;
1192 }
1193 
1194 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1195 					struct exynos_dsi_transfer *xfer)
1196 {
1197 	unsigned long flags;
1198 	bool start;
1199 
1200 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1201 
1202 	if (!list_empty(&dsi->transfer_list) &&
1203 	    xfer == list_first_entry(&dsi->transfer_list,
1204 				     struct exynos_dsi_transfer, list)) {
1205 		list_del_init(&xfer->list);
1206 		start = !list_empty(&dsi->transfer_list);
1207 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1208 		if (start)
1209 			exynos_dsi_transfer_start(dsi);
1210 		return;
1211 	}
1212 
1213 	list_del_init(&xfer->list);
1214 
1215 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1216 }
1217 
1218 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1219 					struct exynos_dsi_transfer *xfer)
1220 {
1221 	unsigned long flags;
1222 	bool stopped;
1223 
1224 	xfer->tx_done = 0;
1225 	xfer->rx_done = 0;
1226 	xfer->result = -ETIMEDOUT;
1227 	init_completion(&xfer->completed);
1228 
1229 	spin_lock_irqsave(&dsi->transfer_lock, flags);
1230 
1231 	stopped = list_empty(&dsi->transfer_list);
1232 	list_add_tail(&xfer->list, &dsi->transfer_list);
1233 
1234 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1235 
1236 	if (stopped)
1237 		exynos_dsi_transfer_start(dsi);
1238 
1239 	wait_for_completion_timeout(&xfer->completed,
1240 				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1241 	if (xfer->result == -ETIMEDOUT) {
1242 		struct mipi_dsi_packet *pkt = &xfer->packet;
1243 		exynos_dsi_remove_transfer(dsi, xfer);
1244 		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1245 			(int)pkt->payload_length, pkt->payload);
1246 		return -ETIMEDOUT;
1247 	}
1248 
1249 	/* Also covers hardware timeout condition */
1250 	return xfer->result;
1251 }
1252 
1253 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1254 {
1255 	struct exynos_dsi *dsi = dev_id;
1256 	u32 status;
1257 
1258 	status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
1259 	if (!status) {
1260 		static unsigned long int j;
1261 		if (printk_timed_ratelimit(&j, 500))
1262 			dev_warn(dsi->dev, "spurious interrupt\n");
1263 		return IRQ_HANDLED;
1264 	}
1265 	exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
1266 
1267 	if (status & DSIM_INT_SW_RST_RELEASE) {
1268 		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1269 			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
1270 			DSIM_INT_SW_RST_RELEASE);
1271 		exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
1272 		complete(&dsi->completed);
1273 		return IRQ_HANDLED;
1274 	}
1275 
1276 	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1277 			DSIM_INT_PLL_STABLE)))
1278 		return IRQ_HANDLED;
1279 
1280 	if (exynos_dsi_transfer_finish(dsi))
1281 		exynos_dsi_transfer_start(dsi);
1282 
1283 	return IRQ_HANDLED;
1284 }
1285 
1286 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1287 {
1288 	struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1289 	struct drm_encoder *encoder = &dsi->encoder;
1290 
1291 	if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1292 		exynos_drm_crtc_te_handler(encoder->crtc);
1293 
1294 	return IRQ_HANDLED;
1295 }
1296 
1297 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1298 {
1299 	enable_irq(dsi->irq);
1300 
1301 	if (gpio_is_valid(dsi->te_gpio))
1302 		enable_irq(gpio_to_irq(dsi->te_gpio));
1303 }
1304 
1305 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1306 {
1307 	if (gpio_is_valid(dsi->te_gpio))
1308 		disable_irq(gpio_to_irq(dsi->te_gpio));
1309 
1310 	disable_irq(dsi->irq);
1311 }
1312 
1313 static int exynos_dsi_init(struct exynos_dsi *dsi)
1314 {
1315 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1316 
1317 	exynos_dsi_reset(dsi);
1318 	exynos_dsi_enable_irq(dsi);
1319 
1320 	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1321 		exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1322 
1323 	exynos_dsi_enable_clock(dsi);
1324 	if (driver_data->wait_for_reset)
1325 		exynos_dsi_wait_for_reset(dsi);
1326 	exynos_dsi_set_phy_ctrl(dsi);
1327 	exynos_dsi_init_link(dsi);
1328 
1329 	return 0;
1330 }
1331 
1332 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
1333 				      struct device *panel)
1334 {
1335 	int ret;
1336 	int te_gpio_irq;
1337 
1338 	dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
1339 	if (dsi->te_gpio == -ENOENT)
1340 		return 0;
1341 
1342 	if (!gpio_is_valid(dsi->te_gpio)) {
1343 		ret = dsi->te_gpio;
1344 		dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
1345 		goto out;
1346 	}
1347 
1348 	ret = gpio_request(dsi->te_gpio, "te_gpio");
1349 	if (ret) {
1350 		dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1351 		goto out;
1352 	}
1353 
1354 	te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1355 
1356 	ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1357 				   IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1358 	if (ret) {
1359 		dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1360 		gpio_free(dsi->te_gpio);
1361 		goto out;
1362 	}
1363 
1364 out:
1365 	return ret;
1366 }
1367 
1368 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1369 {
1370 	if (gpio_is_valid(dsi->te_gpio)) {
1371 		free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1372 		gpio_free(dsi->te_gpio);
1373 		dsi->te_gpio = -ENOENT;
1374 	}
1375 }
1376 
1377 static void exynos_dsi_enable(struct drm_encoder *encoder)
1378 {
1379 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1380 	struct drm_bridge *iter;
1381 	int ret;
1382 
1383 	if (dsi->state & DSIM_STATE_ENABLED)
1384 		return;
1385 
1386 	ret = pm_runtime_resume_and_get(dsi->dev);
1387 	if (ret < 0) {
1388 		dev_err(dsi->dev, "failed to enable DSI device.\n");
1389 		return;
1390 	}
1391 
1392 	dsi->state |= DSIM_STATE_ENABLED;
1393 
1394 	if (dsi->panel) {
1395 		ret = drm_panel_prepare(dsi->panel);
1396 		if (ret < 0)
1397 			goto err_put_sync;
1398 	} else {
1399 		list_for_each_entry_reverse(iter, &dsi->bridge_chain,
1400 					    chain_node) {
1401 			if (iter->funcs->pre_enable)
1402 				iter->funcs->pre_enable(iter);
1403 		}
1404 	}
1405 
1406 	exynos_dsi_set_display_mode(dsi);
1407 	exynos_dsi_set_display_enable(dsi, true);
1408 
1409 	if (dsi->panel) {
1410 		ret = drm_panel_enable(dsi->panel);
1411 		if (ret < 0)
1412 			goto err_display_disable;
1413 	} else {
1414 		list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1415 			if (iter->funcs->enable)
1416 				iter->funcs->enable(iter);
1417 		}
1418 	}
1419 
1420 	dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1421 	return;
1422 
1423 err_display_disable:
1424 	exynos_dsi_set_display_enable(dsi, false);
1425 	drm_panel_unprepare(dsi->panel);
1426 
1427 err_put_sync:
1428 	dsi->state &= ~DSIM_STATE_ENABLED;
1429 	pm_runtime_put(dsi->dev);
1430 }
1431 
1432 static void exynos_dsi_disable(struct drm_encoder *encoder)
1433 {
1434 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1435 	struct drm_bridge *iter;
1436 
1437 	if (!(dsi->state & DSIM_STATE_ENABLED))
1438 		return;
1439 
1440 	dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1441 
1442 	drm_panel_disable(dsi->panel);
1443 
1444 	list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) {
1445 		if (iter->funcs->disable)
1446 			iter->funcs->disable(iter);
1447 	}
1448 
1449 	exynos_dsi_set_display_enable(dsi, false);
1450 	drm_panel_unprepare(dsi->panel);
1451 
1452 	list_for_each_entry(iter, &dsi->bridge_chain, chain_node) {
1453 		if (iter->funcs->post_disable)
1454 			iter->funcs->post_disable(iter);
1455 	}
1456 
1457 	dsi->state &= ~DSIM_STATE_ENABLED;
1458 	pm_runtime_put_sync(dsi->dev);
1459 }
1460 
1461 static enum drm_connector_status
1462 exynos_dsi_detect(struct drm_connector *connector, bool force)
1463 {
1464 	return connector->status;
1465 }
1466 
1467 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1468 {
1469 	drm_connector_unregister(connector);
1470 	drm_connector_cleanup(connector);
1471 	connector->dev = NULL;
1472 }
1473 
1474 static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
1475 	.detect = exynos_dsi_detect,
1476 	.fill_modes = drm_helper_probe_single_connector_modes,
1477 	.destroy = exynos_dsi_connector_destroy,
1478 	.reset = drm_atomic_helper_connector_reset,
1479 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1480 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1481 };
1482 
1483 static int exynos_dsi_get_modes(struct drm_connector *connector)
1484 {
1485 	struct exynos_dsi *dsi = connector_to_dsi(connector);
1486 
1487 	if (dsi->panel)
1488 		return drm_panel_get_modes(dsi->panel, connector);
1489 
1490 	return 0;
1491 }
1492 
1493 static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1494 	.get_modes = exynos_dsi_get_modes,
1495 };
1496 
1497 static int exynos_dsi_create_connector(struct drm_encoder *encoder)
1498 {
1499 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1500 	struct drm_connector *connector = &dsi->connector;
1501 	struct drm_device *drm = encoder->dev;
1502 	int ret;
1503 
1504 	connector->polled = DRM_CONNECTOR_POLL_HPD;
1505 
1506 	ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
1507 				 DRM_MODE_CONNECTOR_DSI);
1508 	if (ret) {
1509 		DRM_DEV_ERROR(dsi->dev,
1510 			      "Failed to initialize connector with drm\n");
1511 		return ret;
1512 	}
1513 
1514 	connector->status = connector_status_disconnected;
1515 	drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1516 	drm_connector_attach_encoder(connector, encoder);
1517 	if (!drm->registered)
1518 		return 0;
1519 
1520 	connector->funcs->reset(connector);
1521 	drm_connector_register(connector);
1522 	return 0;
1523 }
1524 
1525 static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1526 	.enable = exynos_dsi_enable,
1527 	.disable = exynos_dsi_disable,
1528 };
1529 
1530 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1531 
1532 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1533 				  struct mipi_dsi_device *device)
1534 {
1535 	struct exynos_dsi *dsi = host_to_dsi(host);
1536 	struct drm_encoder *encoder = &dsi->encoder;
1537 	struct drm_device *drm = encoder->dev;
1538 	struct drm_bridge *out_bridge;
1539 
1540 	out_bridge  = of_drm_find_bridge(device->dev.of_node);
1541 	if (out_bridge) {
1542 		drm_bridge_attach(encoder, out_bridge, NULL, 0);
1543 		dsi->out_bridge = out_bridge;
1544 		list_splice_init(&encoder->bridge_chain, &dsi->bridge_chain);
1545 	} else {
1546 		int ret = exynos_dsi_create_connector(encoder);
1547 
1548 		if (ret) {
1549 			DRM_DEV_ERROR(dsi->dev,
1550 				      "failed to create connector ret = %d\n",
1551 				      ret);
1552 			drm_encoder_cleanup(encoder);
1553 			return ret;
1554 		}
1555 
1556 		dsi->panel = of_drm_find_panel(device->dev.of_node);
1557 		if (IS_ERR(dsi->panel))
1558 			dsi->panel = NULL;
1559 		else
1560 			dsi->connector.status = connector_status_connected;
1561 	}
1562 
1563 	/*
1564 	 * This is a temporary solution and should be made by more generic way.
1565 	 *
1566 	 * If attached panel device is for command mode one, dsi should register
1567 	 * TE interrupt handler.
1568 	 */
1569 	if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1570 		int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
1571 		if (ret)
1572 			return ret;
1573 	}
1574 
1575 	mutex_lock(&drm->mode_config.mutex);
1576 
1577 	dsi->lanes = device->lanes;
1578 	dsi->format = device->format;
1579 	dsi->mode_flags = device->mode_flags;
1580 	exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
1581 			!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
1582 
1583 	mutex_unlock(&drm->mode_config.mutex);
1584 
1585 	if (drm->mode_config.poll_enabled)
1586 		drm_kms_helper_hotplug_event(drm);
1587 
1588 	return 0;
1589 }
1590 
1591 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1592 				  struct mipi_dsi_device *device)
1593 {
1594 	struct exynos_dsi *dsi = host_to_dsi(host);
1595 	struct drm_device *drm = dsi->encoder.dev;
1596 
1597 	if (dsi->panel) {
1598 		mutex_lock(&drm->mode_config.mutex);
1599 		exynos_dsi_disable(&dsi->encoder);
1600 		dsi->panel = NULL;
1601 		dsi->connector.status = connector_status_disconnected;
1602 		mutex_unlock(&drm->mode_config.mutex);
1603 	} else {
1604 		if (dsi->out_bridge->funcs->detach)
1605 			dsi->out_bridge->funcs->detach(dsi->out_bridge);
1606 		dsi->out_bridge = NULL;
1607 		INIT_LIST_HEAD(&dsi->bridge_chain);
1608 	}
1609 
1610 	if (drm->mode_config.poll_enabled)
1611 		drm_kms_helper_hotplug_event(drm);
1612 
1613 	exynos_dsi_unregister_te_irq(dsi);
1614 
1615 	return 0;
1616 }
1617 
1618 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1619 					 const struct mipi_dsi_msg *msg)
1620 {
1621 	struct exynos_dsi *dsi = host_to_dsi(host);
1622 	struct exynos_dsi_transfer xfer;
1623 	int ret;
1624 
1625 	if (!(dsi->state & DSIM_STATE_ENABLED))
1626 		return -EINVAL;
1627 
1628 	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1629 		ret = exynos_dsi_init(dsi);
1630 		if (ret)
1631 			return ret;
1632 		dsi->state |= DSIM_STATE_INITIALIZED;
1633 	}
1634 
1635 	ret = mipi_dsi_create_packet(&xfer.packet, msg);
1636 	if (ret < 0)
1637 		return ret;
1638 
1639 	xfer.rx_len = msg->rx_len;
1640 	xfer.rx_payload = msg->rx_buf;
1641 	xfer.flags = msg->flags;
1642 
1643 	ret = exynos_dsi_transfer(dsi, &xfer);
1644 	return (ret < 0) ? ret : xfer.rx_done;
1645 }
1646 
1647 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1648 	.attach = exynos_dsi_host_attach,
1649 	.detach = exynos_dsi_host_detach,
1650 	.transfer = exynos_dsi_host_transfer,
1651 };
1652 
1653 static int exynos_dsi_of_read_u32(const struct device_node *np,
1654 				  const char *propname, u32 *out_value)
1655 {
1656 	int ret = of_property_read_u32(np, propname, out_value);
1657 
1658 	if (ret < 0)
1659 		pr_err("%pOF: failed to get '%s' property\n", np, propname);
1660 
1661 	return ret;
1662 }
1663 
1664 enum {
1665 	DSI_PORT_IN,
1666 	DSI_PORT_OUT
1667 };
1668 
1669 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1670 {
1671 	struct device *dev = dsi->dev;
1672 	struct device_node *node = dev->of_node;
1673 	int ret;
1674 
1675 	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1676 				     &dsi->pll_clk_rate);
1677 	if (ret < 0)
1678 		return ret;
1679 
1680 	ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
1681 				     &dsi->burst_clk_rate);
1682 	if (ret < 0)
1683 		return ret;
1684 
1685 	ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
1686 				     &dsi->esc_clk_rate);
1687 	if (ret < 0)
1688 		return ret;
1689 
1690 	return 0;
1691 }
1692 
1693 static int exynos_dsi_bind(struct device *dev, struct device *master,
1694 				void *data)
1695 {
1696 	struct exynos_dsi *dsi = dev_get_drvdata(dev);
1697 	struct drm_encoder *encoder = &dsi->encoder;
1698 	struct drm_device *drm_dev = data;
1699 	struct device_node *in_bridge_node;
1700 	struct drm_bridge *in_bridge;
1701 	int ret;
1702 
1703 	drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS);
1704 
1705 	drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
1706 
1707 	ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
1708 	if (ret < 0)
1709 		return ret;
1710 
1711 	in_bridge_node = of_graph_get_remote_node(dev->of_node, DSI_PORT_IN, 0);
1712 	if (in_bridge_node) {
1713 		in_bridge = of_drm_find_bridge(in_bridge_node);
1714 		if (in_bridge)
1715 			drm_bridge_attach(encoder, in_bridge, NULL, 0);
1716 		of_node_put(in_bridge_node);
1717 	}
1718 
1719 	return mipi_dsi_host_register(&dsi->dsi_host);
1720 }
1721 
1722 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1723 				void *data)
1724 {
1725 	struct exynos_dsi *dsi = dev_get_drvdata(dev);
1726 	struct drm_encoder *encoder = &dsi->encoder;
1727 
1728 	exynos_dsi_disable(encoder);
1729 
1730 	mipi_dsi_host_unregister(&dsi->dsi_host);
1731 }
1732 
1733 static const struct component_ops exynos_dsi_component_ops = {
1734 	.bind	= exynos_dsi_bind,
1735 	.unbind	= exynos_dsi_unbind,
1736 };
1737 
1738 static int exynos_dsi_probe(struct platform_device *pdev)
1739 {
1740 	struct device *dev = &pdev->dev;
1741 	struct exynos_dsi *dsi;
1742 	int ret, i;
1743 
1744 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1745 	if (!dsi)
1746 		return -ENOMEM;
1747 
1748 	/* To be checked as invalid one */
1749 	dsi->te_gpio = -ENOENT;
1750 
1751 	init_completion(&dsi->completed);
1752 	spin_lock_init(&dsi->transfer_lock);
1753 	INIT_LIST_HEAD(&dsi->transfer_list);
1754 	INIT_LIST_HEAD(&dsi->bridge_chain);
1755 
1756 	dsi->dsi_host.ops = &exynos_dsi_ops;
1757 	dsi->dsi_host.dev = dev;
1758 
1759 	dsi->dev = dev;
1760 	dsi->driver_data = of_device_get_match_data(dev);
1761 
1762 	dsi->supplies[0].supply = "vddcore";
1763 	dsi->supplies[1].supply = "vddio";
1764 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1765 				      dsi->supplies);
1766 	if (ret)
1767 		return dev_err_probe(dev, ret, "failed to get regulators\n");
1768 
1769 	dsi->clks = devm_kcalloc(dev,
1770 			dsi->driver_data->num_clks, sizeof(*dsi->clks),
1771 			GFP_KERNEL);
1772 	if (!dsi->clks)
1773 		return -ENOMEM;
1774 
1775 	for (i = 0; i < dsi->driver_data->num_clks; i++) {
1776 		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1777 		if (IS_ERR(dsi->clks[i])) {
1778 			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1779 				dsi->clks[i] = devm_clk_get(dev,
1780 							OLD_SCLK_MIPI_CLK_NAME);
1781 				if (!IS_ERR(dsi->clks[i]))
1782 					continue;
1783 			}
1784 
1785 			dev_info(dev, "failed to get the clock: %s\n",
1786 					clk_names[i]);
1787 			return PTR_ERR(dsi->clks[i]);
1788 		}
1789 	}
1790 
1791 	dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1792 	if (IS_ERR(dsi->reg_base))
1793 		return PTR_ERR(dsi->reg_base);
1794 
1795 	dsi->phy = devm_phy_get(dev, "dsim");
1796 	if (IS_ERR(dsi->phy)) {
1797 		dev_info(dev, "failed to get dsim phy\n");
1798 		return PTR_ERR(dsi->phy);
1799 	}
1800 
1801 	dsi->irq = platform_get_irq(pdev, 0);
1802 	if (dsi->irq < 0)
1803 		return dsi->irq;
1804 
1805 	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1806 					exynos_dsi_irq,
1807 					IRQF_ONESHOT | IRQF_NO_AUTOEN,
1808 					dev_name(dev), dsi);
1809 	if (ret) {
1810 		dev_err(dev, "failed to request dsi irq\n");
1811 		return ret;
1812 	}
1813 
1814 	ret = exynos_dsi_parse_dt(dsi);
1815 	if (ret)
1816 		return ret;
1817 
1818 	platform_set_drvdata(pdev, dsi);
1819 
1820 	pm_runtime_enable(dev);
1821 
1822 	ret = component_add(dev, &exynos_dsi_component_ops);
1823 	if (ret)
1824 		goto err_disable_runtime;
1825 
1826 	return 0;
1827 
1828 err_disable_runtime:
1829 	pm_runtime_disable(dev);
1830 
1831 	return ret;
1832 }
1833 
1834 static int exynos_dsi_remove(struct platform_device *pdev)
1835 {
1836 	pm_runtime_disable(&pdev->dev);
1837 
1838 	component_del(&pdev->dev, &exynos_dsi_component_ops);
1839 
1840 	return 0;
1841 }
1842 
1843 static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1844 {
1845 	struct exynos_dsi *dsi = dev_get_drvdata(dev);
1846 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1847 	int ret, i;
1848 
1849 	usleep_range(10000, 20000);
1850 
1851 	if (dsi->state & DSIM_STATE_INITIALIZED) {
1852 		dsi->state &= ~DSIM_STATE_INITIALIZED;
1853 
1854 		exynos_dsi_disable_clock(dsi);
1855 
1856 		exynos_dsi_disable_irq(dsi);
1857 	}
1858 
1859 	dsi->state &= ~DSIM_STATE_CMD_LPM;
1860 
1861 	phy_power_off(dsi->phy);
1862 
1863 	for (i = driver_data->num_clks - 1; i > -1; i--)
1864 		clk_disable_unprepare(dsi->clks[i]);
1865 
1866 	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1867 	if (ret < 0)
1868 		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1869 
1870 	return 0;
1871 }
1872 
1873 static int __maybe_unused exynos_dsi_resume(struct device *dev)
1874 {
1875 	struct exynos_dsi *dsi = dev_get_drvdata(dev);
1876 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1877 	int ret, i;
1878 
1879 	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1880 	if (ret < 0) {
1881 		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1882 		return ret;
1883 	}
1884 
1885 	for (i = 0; i < driver_data->num_clks; i++) {
1886 		ret = clk_prepare_enable(dsi->clks[i]);
1887 		if (ret < 0)
1888 			goto err_clk;
1889 	}
1890 
1891 	ret = phy_power_on(dsi->phy);
1892 	if (ret < 0) {
1893 		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1894 		goto err_clk;
1895 	}
1896 
1897 	return 0;
1898 
1899 err_clk:
1900 	while (--i > -1)
1901 		clk_disable_unprepare(dsi->clks[i]);
1902 	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1903 
1904 	return ret;
1905 }
1906 
1907 static const struct dev_pm_ops exynos_dsi_pm_ops = {
1908 	SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
1909 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1910 				pm_runtime_force_resume)
1911 };
1912 
1913 struct platform_driver dsi_driver = {
1914 	.probe = exynos_dsi_probe,
1915 	.remove = exynos_dsi_remove,
1916 	.driver = {
1917 		   .name = "exynos-dsi",
1918 		   .owner = THIS_MODULE,
1919 		   .pm = &exynos_dsi_pm_ops,
1920 		   .of_match_table = exynos_dsi_of_match,
1921 	},
1922 };
1923 
1924 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1925 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1926 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1927 MODULE_LICENSE("GPL v2");
1928