1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Samsung SoC MIPI DSI Master driver. 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd 6 * 7 * Contacts: Tomasz Figa <t.figa@samsung.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/component.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/irq.h> 15 #include <linux/of_device.h> 16 #include <linux/of_gpio.h> 17 #include <linux/of_graph.h> 18 #include <linux/phy/phy.h> 19 #include <linux/regulator/consumer.h> 20 21 #include <asm/unaligned.h> 22 23 #include <video/mipi_display.h> 24 #include <video/videomode.h> 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_bridge.h> 28 #include <drm/drm_fb_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 #include <drm/drm_panel.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 34 #include "exynos_drm_crtc.h" 35 #include "exynos_drm_drv.h" 36 37 /* returns true iff both arguments logically differs */ 38 #define NEQV(a, b) (!(a) ^ !(b)) 39 40 /* DSIM_STATUS */ 41 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 42 #define DSIM_STOP_STATE_CLK (1 << 8) 43 #define DSIM_TX_READY_HS_CLK (1 << 10) 44 #define DSIM_PLL_STABLE (1 << 31) 45 46 /* DSIM_SWRST */ 47 #define DSIM_FUNCRST (1 << 16) 48 #define DSIM_SWRST (1 << 0) 49 50 /* DSIM_TIMEOUT */ 51 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 52 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 53 54 /* DSIM_CLKCTRL */ 55 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 56 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 57 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 58 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 59 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 60 #define DSIM_BYTE_CLKEN (1 << 24) 61 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 62 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 63 #define DSIM_PLL_BYPASS (1 << 27) 64 #define DSIM_ESC_CLKEN (1 << 28) 65 #define DSIM_TX_REQUEST_HSCLK (1 << 31) 66 67 /* DSIM_CONFIG */ 68 #define DSIM_LANE_EN_CLK (1 << 0) 69 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 70 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 71 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 72 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 73 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 74 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 75 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 76 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 77 #define DSIM_SUB_VC (((x) & 0x3) << 16) 78 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 79 #define DSIM_HSA_MODE (1 << 20) 80 #define DSIM_HBP_MODE (1 << 21) 81 #define DSIM_HFP_MODE (1 << 22) 82 #define DSIM_HSE_MODE (1 << 23) 83 #define DSIM_AUTO_MODE (1 << 24) 84 #define DSIM_VIDEO_MODE (1 << 25) 85 #define DSIM_BURST_MODE (1 << 26) 86 #define DSIM_SYNC_INFORM (1 << 27) 87 #define DSIM_EOT_DISABLE (1 << 28) 88 #define DSIM_MFLUSH_VS (1 << 29) 89 /* This flag is valid only for exynos3250/3472/5260/5430 */ 90 #define DSIM_CLKLANE_STOP (1 << 30) 91 92 /* DSIM_ESCMODE */ 93 #define DSIM_TX_TRIGGER_RST (1 << 4) 94 #define DSIM_TX_LPDT_LP (1 << 6) 95 #define DSIM_CMD_LPDT_LP (1 << 7) 96 #define DSIM_FORCE_BTA (1 << 16) 97 #define DSIM_FORCE_STOP_STATE (1 << 20) 98 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 99 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 100 101 /* DSIM_MDRESOL */ 102 #define DSIM_MAIN_STAND_BY (1 << 31) 103 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 104 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 105 106 /* DSIM_MVPORCH */ 107 #define DSIM_CMD_ALLOW(x) ((x) << 28) 108 #define DSIM_STABLE_VFP(x) ((x) << 16) 109 #define DSIM_MAIN_VBP(x) ((x) << 0) 110 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 111 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 112 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 113 114 /* DSIM_MHPORCH */ 115 #define DSIM_MAIN_HFP(x) ((x) << 16) 116 #define DSIM_MAIN_HBP(x) ((x) << 0) 117 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 118 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 119 120 /* DSIM_MSYNC */ 121 #define DSIM_MAIN_VSA(x) ((x) << 22) 122 #define DSIM_MAIN_HSA(x) ((x) << 0) 123 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 124 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 125 126 /* DSIM_SDRESOL */ 127 #define DSIM_SUB_STANDY(x) ((x) << 31) 128 #define DSIM_SUB_VRESOL(x) ((x) << 16) 129 #define DSIM_SUB_HRESOL(x) ((x) << 0) 130 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 131 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 132 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 133 134 /* DSIM_INTSRC */ 135 #define DSIM_INT_PLL_STABLE (1 << 31) 136 #define DSIM_INT_SW_RST_RELEASE (1 << 30) 137 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 138 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 139 #define DSIM_INT_BTA (1 << 25) 140 #define DSIM_INT_FRAME_DONE (1 << 24) 141 #define DSIM_INT_RX_TIMEOUT (1 << 21) 142 #define DSIM_INT_BTA_TIMEOUT (1 << 20) 143 #define DSIM_INT_RX_DONE (1 << 18) 144 #define DSIM_INT_RX_TE (1 << 17) 145 #define DSIM_INT_RX_ACK (1 << 16) 146 #define DSIM_INT_RX_ECC_ERR (1 << 15) 147 #define DSIM_INT_RX_CRC_ERR (1 << 14) 148 149 /* DSIM_FIFOCTRL */ 150 #define DSIM_RX_DATA_FULL (1 << 25) 151 #define DSIM_RX_DATA_EMPTY (1 << 24) 152 #define DSIM_SFR_HEADER_FULL (1 << 23) 153 #define DSIM_SFR_HEADER_EMPTY (1 << 22) 154 #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 155 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 156 #define DSIM_I80_HEADER_FULL (1 << 19) 157 #define DSIM_I80_HEADER_EMPTY (1 << 18) 158 #define DSIM_I80_PAYLOAD_FULL (1 << 17) 159 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 160 #define DSIM_SD_HEADER_FULL (1 << 15) 161 #define DSIM_SD_HEADER_EMPTY (1 << 14) 162 #define DSIM_SD_PAYLOAD_FULL (1 << 13) 163 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 164 #define DSIM_MD_HEADER_FULL (1 << 11) 165 #define DSIM_MD_HEADER_EMPTY (1 << 10) 166 #define DSIM_MD_PAYLOAD_FULL (1 << 9) 167 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 168 #define DSIM_RX_FIFO (1 << 4) 169 #define DSIM_SFR_FIFO (1 << 3) 170 #define DSIM_I80_FIFO (1 << 2) 171 #define DSIM_SD_FIFO (1 << 1) 172 #define DSIM_MD_FIFO (1 << 0) 173 174 /* DSIM_PHYACCHR */ 175 #define DSIM_AFC_EN (1 << 14) 176 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 177 178 /* DSIM_PLLCTRL */ 179 #define DSIM_FREQ_BAND(x) ((x) << 24) 180 #define DSIM_PLL_EN (1 << 23) 181 #define DSIM_PLL_P(x) ((x) << 13) 182 #define DSIM_PLL_M(x) ((x) << 4) 183 #define DSIM_PLL_S(x) ((x) << 1) 184 185 /* DSIM_PHYCTRL */ 186 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 187 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 188 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 189 190 /* DSIM_PHYTIMING */ 191 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 192 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 193 194 /* DSIM_PHYTIMING1 */ 195 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 196 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 197 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 198 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 199 200 /* DSIM_PHYTIMING2 */ 201 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 202 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 203 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 204 205 #define DSI_MAX_BUS_WIDTH 4 206 #define DSI_NUM_VIRTUAL_CHANNELS 4 207 #define DSI_TX_FIFO_SIZE 2048 208 #define DSI_RX_FIFO_SIZE 256 209 #define DSI_XFER_TIMEOUT_MS 100 210 #define DSI_RX_FIFO_EMPTY 0x30800002 211 212 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 213 214 static char *clk_names[5] = { "bus_clk", "sclk_mipi", 215 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 216 "sclk_rgb_vclk_to_dsim0" }; 217 218 enum exynos_dsi_transfer_type { 219 EXYNOS_DSI_TX, 220 EXYNOS_DSI_RX, 221 }; 222 223 struct exynos_dsi_transfer { 224 struct list_head list; 225 struct completion completed; 226 int result; 227 struct mipi_dsi_packet packet; 228 u16 flags; 229 u16 tx_done; 230 231 u8 *rx_payload; 232 u16 rx_len; 233 u16 rx_done; 234 }; 235 236 #define DSIM_STATE_ENABLED BIT(0) 237 #define DSIM_STATE_INITIALIZED BIT(1) 238 #define DSIM_STATE_CMD_LPM BIT(2) 239 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 240 241 struct exynos_dsi_driver_data { 242 const unsigned int *reg_ofs; 243 unsigned int plltmr_reg; 244 unsigned int has_freqband:1; 245 unsigned int has_clklane_stop:1; 246 unsigned int num_clks; 247 unsigned int max_freq; 248 unsigned int wait_for_reset; 249 unsigned int num_bits_resol; 250 const unsigned int *reg_values; 251 }; 252 253 struct exynos_dsi { 254 struct drm_encoder encoder; 255 struct mipi_dsi_host dsi_host; 256 struct drm_connector connector; 257 struct drm_panel *panel; 258 struct drm_bridge *out_bridge; 259 struct device *dev; 260 261 void __iomem *reg_base; 262 struct phy *phy; 263 struct clk **clks; 264 struct regulator_bulk_data supplies[2]; 265 int irq; 266 int te_gpio; 267 268 u32 pll_clk_rate; 269 u32 burst_clk_rate; 270 u32 esc_clk_rate; 271 u32 lanes; 272 u32 mode_flags; 273 u32 format; 274 275 int state; 276 struct drm_property *brightness; 277 struct completion completed; 278 279 spinlock_t transfer_lock; /* protects transfer_list */ 280 struct list_head transfer_list; 281 282 const struct exynos_dsi_driver_data *driver_data; 283 struct device_node *in_bridge_node; 284 }; 285 286 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 287 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 288 289 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) 290 { 291 return container_of(e, struct exynos_dsi, encoder); 292 } 293 294 enum reg_idx { 295 DSIM_STATUS_REG, /* Status register */ 296 DSIM_SWRST_REG, /* Software reset register */ 297 DSIM_CLKCTRL_REG, /* Clock control register */ 298 DSIM_TIMEOUT_REG, /* Time out register */ 299 DSIM_CONFIG_REG, /* Configuration register */ 300 DSIM_ESCMODE_REG, /* Escape mode register */ 301 DSIM_MDRESOL_REG, 302 DSIM_MVPORCH_REG, /* Main display Vporch register */ 303 DSIM_MHPORCH_REG, /* Main display Hporch register */ 304 DSIM_MSYNC_REG, /* Main display sync area register */ 305 DSIM_INTSRC_REG, /* Interrupt source register */ 306 DSIM_INTMSK_REG, /* Interrupt mask register */ 307 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 308 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 309 DSIM_RXFIFO_REG, /* Read FIFO register */ 310 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 311 DSIM_PLLCTRL_REG, /* PLL control register */ 312 DSIM_PHYCTRL_REG, 313 DSIM_PHYTIMING_REG, 314 DSIM_PHYTIMING1_REG, 315 DSIM_PHYTIMING2_REG, 316 NUM_REGS 317 }; 318 319 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 320 u32 val) 321 { 322 323 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 324 } 325 326 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 327 { 328 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 329 } 330 331 static const unsigned int exynos_reg_ofs[] = { 332 [DSIM_STATUS_REG] = 0x00, 333 [DSIM_SWRST_REG] = 0x04, 334 [DSIM_CLKCTRL_REG] = 0x08, 335 [DSIM_TIMEOUT_REG] = 0x0c, 336 [DSIM_CONFIG_REG] = 0x10, 337 [DSIM_ESCMODE_REG] = 0x14, 338 [DSIM_MDRESOL_REG] = 0x18, 339 [DSIM_MVPORCH_REG] = 0x1c, 340 [DSIM_MHPORCH_REG] = 0x20, 341 [DSIM_MSYNC_REG] = 0x24, 342 [DSIM_INTSRC_REG] = 0x2c, 343 [DSIM_INTMSK_REG] = 0x30, 344 [DSIM_PKTHDR_REG] = 0x34, 345 [DSIM_PAYLOAD_REG] = 0x38, 346 [DSIM_RXFIFO_REG] = 0x3c, 347 [DSIM_FIFOCTRL_REG] = 0x44, 348 [DSIM_PLLCTRL_REG] = 0x4c, 349 [DSIM_PHYCTRL_REG] = 0x5c, 350 [DSIM_PHYTIMING_REG] = 0x64, 351 [DSIM_PHYTIMING1_REG] = 0x68, 352 [DSIM_PHYTIMING2_REG] = 0x6c, 353 }; 354 355 static const unsigned int exynos5433_reg_ofs[] = { 356 [DSIM_STATUS_REG] = 0x04, 357 [DSIM_SWRST_REG] = 0x0C, 358 [DSIM_CLKCTRL_REG] = 0x10, 359 [DSIM_TIMEOUT_REG] = 0x14, 360 [DSIM_CONFIG_REG] = 0x18, 361 [DSIM_ESCMODE_REG] = 0x1C, 362 [DSIM_MDRESOL_REG] = 0x20, 363 [DSIM_MVPORCH_REG] = 0x24, 364 [DSIM_MHPORCH_REG] = 0x28, 365 [DSIM_MSYNC_REG] = 0x2C, 366 [DSIM_INTSRC_REG] = 0x34, 367 [DSIM_INTMSK_REG] = 0x38, 368 [DSIM_PKTHDR_REG] = 0x3C, 369 [DSIM_PAYLOAD_REG] = 0x40, 370 [DSIM_RXFIFO_REG] = 0x44, 371 [DSIM_FIFOCTRL_REG] = 0x4C, 372 [DSIM_PLLCTRL_REG] = 0x94, 373 [DSIM_PHYCTRL_REG] = 0xA4, 374 [DSIM_PHYTIMING_REG] = 0xB4, 375 [DSIM_PHYTIMING1_REG] = 0xB8, 376 [DSIM_PHYTIMING2_REG] = 0xBC, 377 }; 378 379 enum reg_value_idx { 380 RESET_TYPE, 381 PLL_TIMER, 382 STOP_STATE_CNT, 383 PHYCTRL_ULPS_EXIT, 384 PHYCTRL_VREG_LP, 385 PHYCTRL_SLEW_UP, 386 PHYTIMING_LPX, 387 PHYTIMING_HS_EXIT, 388 PHYTIMING_CLK_PREPARE, 389 PHYTIMING_CLK_ZERO, 390 PHYTIMING_CLK_POST, 391 PHYTIMING_CLK_TRAIL, 392 PHYTIMING_HS_PREPARE, 393 PHYTIMING_HS_ZERO, 394 PHYTIMING_HS_TRAIL 395 }; 396 397 static const unsigned int reg_values[] = { 398 [RESET_TYPE] = DSIM_SWRST, 399 [PLL_TIMER] = 500, 400 [STOP_STATE_CNT] = 0xf, 401 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 402 [PHYCTRL_VREG_LP] = 0, 403 [PHYCTRL_SLEW_UP] = 0, 404 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 405 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 406 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 407 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 408 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 409 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 410 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 411 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 412 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 413 }; 414 415 static const unsigned int exynos5422_reg_values[] = { 416 [RESET_TYPE] = DSIM_SWRST, 417 [PLL_TIMER] = 500, 418 [STOP_STATE_CNT] = 0xf, 419 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 420 [PHYCTRL_VREG_LP] = 0, 421 [PHYCTRL_SLEW_UP] = 0, 422 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 423 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 424 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 425 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 426 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 427 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 428 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 429 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 430 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 431 }; 432 433 static const unsigned int exynos5433_reg_values[] = { 434 [RESET_TYPE] = DSIM_FUNCRST, 435 [PLL_TIMER] = 22200, 436 [STOP_STATE_CNT] = 0xa, 437 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 438 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 439 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 440 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 441 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 442 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 443 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 444 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 445 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 446 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 447 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 448 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 449 }; 450 451 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 452 .reg_ofs = exynos_reg_ofs, 453 .plltmr_reg = 0x50, 454 .has_freqband = 1, 455 .has_clklane_stop = 1, 456 .num_clks = 2, 457 .max_freq = 1000, 458 .wait_for_reset = 1, 459 .num_bits_resol = 11, 460 .reg_values = reg_values, 461 }; 462 463 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 464 .reg_ofs = exynos_reg_ofs, 465 .plltmr_reg = 0x50, 466 .has_freqband = 1, 467 .has_clklane_stop = 1, 468 .num_clks = 2, 469 .max_freq = 1000, 470 .wait_for_reset = 1, 471 .num_bits_resol = 11, 472 .reg_values = reg_values, 473 }; 474 475 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 476 .reg_ofs = exynos_reg_ofs, 477 .plltmr_reg = 0x58, 478 .num_clks = 2, 479 .max_freq = 1000, 480 .wait_for_reset = 1, 481 .num_bits_resol = 11, 482 .reg_values = reg_values, 483 }; 484 485 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 486 .reg_ofs = exynos5433_reg_ofs, 487 .plltmr_reg = 0xa0, 488 .has_clklane_stop = 1, 489 .num_clks = 5, 490 .max_freq = 1500, 491 .wait_for_reset = 0, 492 .num_bits_resol = 12, 493 .reg_values = exynos5433_reg_values, 494 }; 495 496 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 497 .reg_ofs = exynos5433_reg_ofs, 498 .plltmr_reg = 0xa0, 499 .has_clklane_stop = 1, 500 .num_clks = 2, 501 .max_freq = 1500, 502 .wait_for_reset = 1, 503 .num_bits_resol = 12, 504 .reg_values = exynos5422_reg_values, 505 }; 506 507 static const struct of_device_id exynos_dsi_of_match[] = { 508 { .compatible = "samsung,exynos3250-mipi-dsi", 509 .data = &exynos3_dsi_driver_data }, 510 { .compatible = "samsung,exynos4210-mipi-dsi", 511 .data = &exynos4_dsi_driver_data }, 512 { .compatible = "samsung,exynos5410-mipi-dsi", 513 .data = &exynos5_dsi_driver_data }, 514 { .compatible = "samsung,exynos5422-mipi-dsi", 515 .data = &exynos5422_dsi_driver_data }, 516 { .compatible = "samsung,exynos5433-mipi-dsi", 517 .data = &exynos5433_dsi_driver_data }, 518 { } 519 }; 520 521 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 522 { 523 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 524 return; 525 526 dev_err(dsi->dev, "timeout waiting for reset\n"); 527 } 528 529 static void exynos_dsi_reset(struct exynos_dsi *dsi) 530 { 531 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 532 533 reinit_completion(&dsi->completed); 534 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 535 } 536 537 #ifndef MHZ 538 #define MHZ (1000*1000) 539 #endif 540 541 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 542 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 543 { 544 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 545 unsigned long best_freq = 0; 546 u32 min_delta = 0xffffffff; 547 u8 p_min, p_max; 548 u8 _p, uninitialized_var(best_p); 549 u16 _m, uninitialized_var(best_m); 550 u8 _s, uninitialized_var(best_s); 551 552 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 553 p_max = fin / (6 * MHZ); 554 555 for (_p = p_min; _p <= p_max; ++_p) { 556 for (_s = 0; _s <= 5; ++_s) { 557 u64 tmp; 558 u32 delta; 559 560 tmp = (u64)fout * (_p << _s); 561 do_div(tmp, fin); 562 _m = tmp; 563 if (_m < 41 || _m > 125) 564 continue; 565 566 tmp = (u64)_m * fin; 567 do_div(tmp, _p); 568 if (tmp < 500 * MHZ || 569 tmp > driver_data->max_freq * MHZ) 570 continue; 571 572 tmp = (u64)_m * fin; 573 do_div(tmp, _p << _s); 574 575 delta = abs(fout - tmp); 576 if (delta < min_delta) { 577 best_p = _p; 578 best_m = _m; 579 best_s = _s; 580 min_delta = delta; 581 best_freq = tmp; 582 } 583 } 584 } 585 586 if (best_freq) { 587 *p = best_p; 588 *m = best_m; 589 *s = best_s; 590 } 591 592 return best_freq; 593 } 594 595 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 596 unsigned long freq) 597 { 598 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 599 unsigned long fin, fout; 600 int timeout; 601 u8 p, s; 602 u16 m; 603 u32 reg; 604 605 fin = dsi->pll_clk_rate; 606 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 607 if (!fout) { 608 dev_err(dsi->dev, 609 "failed to find PLL PMS for requested frequency\n"); 610 return 0; 611 } 612 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 613 614 writel(driver_data->reg_values[PLL_TIMER], 615 dsi->reg_base + driver_data->plltmr_reg); 616 617 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 618 619 if (driver_data->has_freqband) { 620 static const unsigned long freq_bands[] = { 621 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 622 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 623 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 624 770 * MHZ, 870 * MHZ, 950 * MHZ, 625 }; 626 int band; 627 628 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 629 if (fout < freq_bands[band]) 630 break; 631 632 dev_dbg(dsi->dev, "band %d\n", band); 633 634 reg |= DSIM_FREQ_BAND(band); 635 } 636 637 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 638 639 timeout = 1000; 640 do { 641 if (timeout-- == 0) { 642 dev_err(dsi->dev, "PLL failed to stabilize\n"); 643 return 0; 644 } 645 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 646 } while ((reg & DSIM_PLL_STABLE) == 0); 647 648 return fout; 649 } 650 651 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 652 { 653 unsigned long hs_clk, byte_clk, esc_clk; 654 unsigned long esc_div; 655 u32 reg; 656 657 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 658 if (!hs_clk) { 659 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 660 return -EFAULT; 661 } 662 663 byte_clk = hs_clk / 8; 664 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 665 esc_clk = byte_clk / esc_div; 666 667 if (esc_clk > 20 * MHZ) { 668 ++esc_div; 669 esc_clk = byte_clk / esc_div; 670 } 671 672 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 673 hs_clk, byte_clk, esc_clk); 674 675 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 676 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 677 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 678 | DSIM_BYTE_CLK_SRC_MASK); 679 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 680 | DSIM_ESC_PRESCALER(esc_div) 681 | DSIM_LANE_ESC_CLK_EN_CLK 682 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 683 | DSIM_BYTE_CLK_SRC(0) 684 | DSIM_TX_REQUEST_HSCLK; 685 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 686 687 return 0; 688 } 689 690 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 691 { 692 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 693 const unsigned int *reg_values = driver_data->reg_values; 694 u32 reg; 695 696 if (driver_data->has_freqband) 697 return; 698 699 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 700 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 701 reg_values[PHYCTRL_SLEW_UP]; 702 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 703 704 /* 705 * T LPX: Transmitted length of any Low-Power state period 706 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 707 * burst 708 */ 709 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 710 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 711 712 /* 713 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 714 * Line state immediately before the HS-0 Line state starting the 715 * HS transmission 716 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 717 * transmitting the Clock. 718 * T CLK_POST: Time that the transmitter continues to send HS clock 719 * after the last associated Data Lane has transitioned to LP Mode 720 * Interval is defined as the period from the end of T HS-TRAIL to 721 * the beginning of T CLK-TRAIL 722 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 723 * the last payload clock bit of a HS transmission burst 724 */ 725 reg = reg_values[PHYTIMING_CLK_PREPARE] | 726 reg_values[PHYTIMING_CLK_ZERO] | 727 reg_values[PHYTIMING_CLK_POST] | 728 reg_values[PHYTIMING_CLK_TRAIL]; 729 730 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 731 732 /* 733 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 734 * Line state immediately before the HS-0 Line state starting the 735 * HS transmission 736 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 737 * transmitting the Sync sequence. 738 * T HS-TRAIL: Time that the transmitter drives the flipped differential 739 * state after last payload data bit of a HS transmission burst 740 */ 741 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 742 reg_values[PHYTIMING_HS_TRAIL]; 743 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 744 } 745 746 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 747 { 748 u32 reg; 749 750 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 751 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 752 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 753 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 754 755 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 756 reg &= ~DSIM_PLL_EN; 757 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 758 } 759 760 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 761 { 762 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 763 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 764 DSIM_LANE_EN(lane)); 765 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 766 } 767 768 static int exynos_dsi_init_link(struct exynos_dsi *dsi) 769 { 770 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 771 int timeout; 772 u32 reg; 773 u32 lanes_mask; 774 775 /* Initialize FIFO pointers */ 776 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 777 reg &= ~0x1f; 778 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 779 780 usleep_range(9000, 11000); 781 782 reg |= 0x1f; 783 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 784 usleep_range(9000, 11000); 785 786 /* DSI configuration */ 787 reg = 0; 788 789 /* 790 * The first bit of mode_flags specifies display configuration. 791 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 792 * mode, otherwise it will support command mode. 793 */ 794 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 795 reg |= DSIM_VIDEO_MODE; 796 797 /* 798 * The user manual describes that following bits are ignored in 799 * command mode. 800 */ 801 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 802 reg |= DSIM_MFLUSH_VS; 803 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 804 reg |= DSIM_SYNC_INFORM; 805 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 806 reg |= DSIM_BURST_MODE; 807 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 808 reg |= DSIM_AUTO_MODE; 809 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 810 reg |= DSIM_HSE_MODE; 811 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 812 reg |= DSIM_HFP_MODE; 813 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 814 reg |= DSIM_HBP_MODE; 815 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 816 reg |= DSIM_HSA_MODE; 817 } 818 819 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 820 reg |= DSIM_EOT_DISABLE; 821 822 switch (dsi->format) { 823 case MIPI_DSI_FMT_RGB888: 824 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 825 break; 826 case MIPI_DSI_FMT_RGB666: 827 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 828 break; 829 case MIPI_DSI_FMT_RGB666_PACKED: 830 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 831 break; 832 case MIPI_DSI_FMT_RGB565: 833 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 834 break; 835 default: 836 dev_err(dsi->dev, "invalid pixel format\n"); 837 return -EINVAL; 838 } 839 840 /* 841 * Use non-continuous clock mode if the periparal wants and 842 * host controller supports 843 * 844 * In non-continous clock mode, host controller will turn off 845 * the HS clock between high-speed transmissions to reduce 846 * power consumption. 847 */ 848 if (driver_data->has_clklane_stop && 849 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 850 reg |= DSIM_CLKLANE_STOP; 851 } 852 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 853 854 lanes_mask = BIT(dsi->lanes) - 1; 855 exynos_dsi_enable_lane(dsi, lanes_mask); 856 857 /* Check clock and data lane state are stop state */ 858 timeout = 100; 859 do { 860 if (timeout-- == 0) { 861 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 862 return -EFAULT; 863 } 864 865 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 866 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 867 != DSIM_STOP_STATE_DAT(lanes_mask)) 868 continue; 869 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 870 871 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 872 reg &= ~DSIM_STOP_STATE_CNT_MASK; 873 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 874 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 875 876 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 877 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 878 879 return 0; 880 } 881 882 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 883 { 884 struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode; 885 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 886 u32 reg; 887 888 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 889 reg = DSIM_CMD_ALLOW(0xf) 890 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 891 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 892 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 893 894 reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) 895 | DSIM_MAIN_HBP(m->htotal - m->hsync_end); 896 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 897 898 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 899 | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); 900 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 901 } 902 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 903 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 904 905 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 906 907 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 908 } 909 910 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 911 { 912 u32 reg; 913 914 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 915 if (enable) 916 reg |= DSIM_MAIN_STAND_BY; 917 else 918 reg &= ~DSIM_MAIN_STAND_BY; 919 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 920 } 921 922 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 923 { 924 int timeout = 2000; 925 926 do { 927 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 928 929 if (!(reg & DSIM_SFR_HEADER_FULL)) 930 return 0; 931 932 if (!cond_resched()) 933 usleep_range(950, 1050); 934 } while (--timeout); 935 936 return -ETIMEDOUT; 937 } 938 939 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 940 { 941 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 942 943 if (lpm) 944 v |= DSIM_CMD_LPDT_LP; 945 else 946 v &= ~DSIM_CMD_LPDT_LP; 947 948 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 949 } 950 951 static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 952 { 953 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 954 v |= DSIM_FORCE_BTA; 955 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 956 } 957 958 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 959 struct exynos_dsi_transfer *xfer) 960 { 961 struct device *dev = dsi->dev; 962 struct mipi_dsi_packet *pkt = &xfer->packet; 963 const u8 *payload = pkt->payload + xfer->tx_done; 964 u16 length = pkt->payload_length - xfer->tx_done; 965 bool first = !xfer->tx_done; 966 u32 reg; 967 968 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 969 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 970 971 if (length > DSI_TX_FIFO_SIZE) 972 length = DSI_TX_FIFO_SIZE; 973 974 xfer->tx_done += length; 975 976 /* Send payload */ 977 while (length >= 4) { 978 reg = get_unaligned_le32(payload); 979 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 980 payload += 4; 981 length -= 4; 982 } 983 984 reg = 0; 985 switch (length) { 986 case 3: 987 reg |= payload[2] << 16; 988 /* Fall through */ 989 case 2: 990 reg |= payload[1] << 8; 991 /* Fall through */ 992 case 1: 993 reg |= payload[0]; 994 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 995 break; 996 } 997 998 /* Send packet header */ 999 if (!first) 1000 return; 1001 1002 reg = get_unaligned_le32(pkt->header); 1003 if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 1004 dev_err(dev, "waiting for header FIFO timed out\n"); 1005 return; 1006 } 1007 1008 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1009 dsi->state & DSIM_STATE_CMD_LPM)) { 1010 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1011 dsi->state ^= DSIM_STATE_CMD_LPM; 1012 } 1013 1014 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 1015 1016 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1017 exynos_dsi_force_bta(dsi); 1018 } 1019 1020 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 1021 struct exynos_dsi_transfer *xfer) 1022 { 1023 u8 *payload = xfer->rx_payload + xfer->rx_done; 1024 bool first = !xfer->rx_done; 1025 struct device *dev = dsi->dev; 1026 u16 length; 1027 u32 reg; 1028 1029 if (first) { 1030 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1031 1032 switch (reg & 0x3f) { 1033 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1034 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1035 if (xfer->rx_len >= 2) { 1036 payload[1] = reg >> 16; 1037 ++xfer->rx_done; 1038 } 1039 /* Fall through */ 1040 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1041 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1042 payload[0] = reg >> 8; 1043 ++xfer->rx_done; 1044 xfer->rx_len = xfer->rx_done; 1045 xfer->result = 0; 1046 goto clear_fifo; 1047 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1048 dev_err(dev, "DSI Error Report: 0x%04x\n", 1049 (reg >> 8) & 0xffff); 1050 xfer->result = 0; 1051 goto clear_fifo; 1052 } 1053 1054 length = (reg >> 8) & 0xffff; 1055 if (length > xfer->rx_len) { 1056 dev_err(dev, 1057 "response too long (%u > %u bytes), stripping\n", 1058 xfer->rx_len, length); 1059 length = xfer->rx_len; 1060 } else if (length < xfer->rx_len) 1061 xfer->rx_len = length; 1062 } 1063 1064 length = xfer->rx_len - xfer->rx_done; 1065 xfer->rx_done += length; 1066 1067 /* Receive payload */ 1068 while (length >= 4) { 1069 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1070 payload[0] = (reg >> 0) & 0xff; 1071 payload[1] = (reg >> 8) & 0xff; 1072 payload[2] = (reg >> 16) & 0xff; 1073 payload[3] = (reg >> 24) & 0xff; 1074 payload += 4; 1075 length -= 4; 1076 } 1077 1078 if (length) { 1079 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1080 switch (length) { 1081 case 3: 1082 payload[2] = (reg >> 16) & 0xff; 1083 /* Fall through */ 1084 case 2: 1085 payload[1] = (reg >> 8) & 0xff; 1086 /* Fall through */ 1087 case 1: 1088 payload[0] = reg & 0xff; 1089 } 1090 } 1091 1092 if (xfer->rx_done == xfer->rx_len) 1093 xfer->result = 0; 1094 1095 clear_fifo: 1096 length = DSI_RX_FIFO_SIZE / 4; 1097 do { 1098 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1099 if (reg == DSI_RX_FIFO_EMPTY) 1100 break; 1101 } while (--length); 1102 } 1103 1104 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 1105 { 1106 unsigned long flags; 1107 struct exynos_dsi_transfer *xfer; 1108 bool start = false; 1109 1110 again: 1111 spin_lock_irqsave(&dsi->transfer_lock, flags); 1112 1113 if (list_empty(&dsi->transfer_list)) { 1114 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1115 return; 1116 } 1117 1118 xfer = list_first_entry(&dsi->transfer_list, 1119 struct exynos_dsi_transfer, list); 1120 1121 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1122 1123 if (xfer->packet.payload_length && 1124 xfer->tx_done == xfer->packet.payload_length) 1125 /* waiting for RX */ 1126 return; 1127 1128 exynos_dsi_send_to_fifo(dsi, xfer); 1129 1130 if (xfer->packet.payload_length || xfer->rx_len) 1131 return; 1132 1133 xfer->result = 0; 1134 complete(&xfer->completed); 1135 1136 spin_lock_irqsave(&dsi->transfer_lock, flags); 1137 1138 list_del_init(&xfer->list); 1139 start = !list_empty(&dsi->transfer_list); 1140 1141 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1142 1143 if (start) 1144 goto again; 1145 } 1146 1147 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 1148 { 1149 struct exynos_dsi_transfer *xfer; 1150 unsigned long flags; 1151 bool start = true; 1152 1153 spin_lock_irqsave(&dsi->transfer_lock, flags); 1154 1155 if (list_empty(&dsi->transfer_list)) { 1156 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1157 return false; 1158 } 1159 1160 xfer = list_first_entry(&dsi->transfer_list, 1161 struct exynos_dsi_transfer, list); 1162 1163 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1164 1165 dev_dbg(dsi->dev, 1166 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1167 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1168 xfer->rx_done); 1169 1170 if (xfer->tx_done != xfer->packet.payload_length) 1171 return true; 1172 1173 if (xfer->rx_done != xfer->rx_len) 1174 exynos_dsi_read_from_fifo(dsi, xfer); 1175 1176 if (xfer->rx_done != xfer->rx_len) 1177 return true; 1178 1179 spin_lock_irqsave(&dsi->transfer_lock, flags); 1180 1181 list_del_init(&xfer->list); 1182 start = !list_empty(&dsi->transfer_list); 1183 1184 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1185 1186 if (!xfer->rx_len) 1187 xfer->result = 0; 1188 complete(&xfer->completed); 1189 1190 return start; 1191 } 1192 1193 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 1194 struct exynos_dsi_transfer *xfer) 1195 { 1196 unsigned long flags; 1197 bool start; 1198 1199 spin_lock_irqsave(&dsi->transfer_lock, flags); 1200 1201 if (!list_empty(&dsi->transfer_list) && 1202 xfer == list_first_entry(&dsi->transfer_list, 1203 struct exynos_dsi_transfer, list)) { 1204 list_del_init(&xfer->list); 1205 start = !list_empty(&dsi->transfer_list); 1206 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1207 if (start) 1208 exynos_dsi_transfer_start(dsi); 1209 return; 1210 } 1211 1212 list_del_init(&xfer->list); 1213 1214 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1215 } 1216 1217 static int exynos_dsi_transfer(struct exynos_dsi *dsi, 1218 struct exynos_dsi_transfer *xfer) 1219 { 1220 unsigned long flags; 1221 bool stopped; 1222 1223 xfer->tx_done = 0; 1224 xfer->rx_done = 0; 1225 xfer->result = -ETIMEDOUT; 1226 init_completion(&xfer->completed); 1227 1228 spin_lock_irqsave(&dsi->transfer_lock, flags); 1229 1230 stopped = list_empty(&dsi->transfer_list); 1231 list_add_tail(&xfer->list, &dsi->transfer_list); 1232 1233 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1234 1235 if (stopped) 1236 exynos_dsi_transfer_start(dsi); 1237 1238 wait_for_completion_timeout(&xfer->completed, 1239 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1240 if (xfer->result == -ETIMEDOUT) { 1241 struct mipi_dsi_packet *pkt = &xfer->packet; 1242 exynos_dsi_remove_transfer(dsi, xfer); 1243 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1244 (int)pkt->payload_length, pkt->payload); 1245 return -ETIMEDOUT; 1246 } 1247 1248 /* Also covers hardware timeout condition */ 1249 return xfer->result; 1250 } 1251 1252 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 1253 { 1254 struct exynos_dsi *dsi = dev_id; 1255 u32 status; 1256 1257 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 1258 if (!status) { 1259 static unsigned long int j; 1260 if (printk_timed_ratelimit(&j, 500)) 1261 dev_warn(dsi->dev, "spurious interrupt\n"); 1262 return IRQ_HANDLED; 1263 } 1264 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 1265 1266 if (status & DSIM_INT_SW_RST_RELEASE) { 1267 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1268 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | 1269 DSIM_INT_SW_RST_RELEASE); 1270 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 1271 complete(&dsi->completed); 1272 return IRQ_HANDLED; 1273 } 1274 1275 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1276 DSIM_INT_PLL_STABLE))) 1277 return IRQ_HANDLED; 1278 1279 if (exynos_dsi_transfer_finish(dsi)) 1280 exynos_dsi_transfer_start(dsi); 1281 1282 return IRQ_HANDLED; 1283 } 1284 1285 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1286 { 1287 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 1288 struct drm_encoder *encoder = &dsi->encoder; 1289 1290 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1291 exynos_drm_crtc_te_handler(encoder->crtc); 1292 1293 return IRQ_HANDLED; 1294 } 1295 1296 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1297 { 1298 enable_irq(dsi->irq); 1299 1300 if (gpio_is_valid(dsi->te_gpio)) 1301 enable_irq(gpio_to_irq(dsi->te_gpio)); 1302 } 1303 1304 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1305 { 1306 if (gpio_is_valid(dsi->te_gpio)) 1307 disable_irq(gpio_to_irq(dsi->te_gpio)); 1308 1309 disable_irq(dsi->irq); 1310 } 1311 1312 static int exynos_dsi_init(struct exynos_dsi *dsi) 1313 { 1314 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1315 1316 exynos_dsi_reset(dsi); 1317 exynos_dsi_enable_irq(dsi); 1318 1319 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1320 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1321 1322 exynos_dsi_enable_clock(dsi); 1323 if (driver_data->wait_for_reset) 1324 exynos_dsi_wait_for_reset(dsi); 1325 exynos_dsi_set_phy_ctrl(dsi); 1326 exynos_dsi_init_link(dsi); 1327 1328 return 0; 1329 } 1330 1331 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, 1332 struct device *panel) 1333 { 1334 int ret; 1335 int te_gpio_irq; 1336 1337 dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0); 1338 if (dsi->te_gpio == -ENOENT) 1339 return 0; 1340 1341 if (!gpio_is_valid(dsi->te_gpio)) { 1342 ret = dsi->te_gpio; 1343 dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret); 1344 goto out; 1345 } 1346 1347 ret = gpio_request(dsi->te_gpio, "te_gpio"); 1348 if (ret) { 1349 dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1350 goto out; 1351 } 1352 1353 te_gpio_irq = gpio_to_irq(dsi->te_gpio); 1354 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 1355 1356 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1357 IRQF_TRIGGER_RISING, "TE", dsi); 1358 if (ret) { 1359 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1360 gpio_free(dsi->te_gpio); 1361 goto out; 1362 } 1363 1364 out: 1365 return ret; 1366 } 1367 1368 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1369 { 1370 if (gpio_is_valid(dsi->te_gpio)) { 1371 free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1372 gpio_free(dsi->te_gpio); 1373 dsi->te_gpio = -ENOENT; 1374 } 1375 } 1376 1377 static void exynos_dsi_enable(struct drm_encoder *encoder) 1378 { 1379 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1380 int ret; 1381 1382 if (dsi->state & DSIM_STATE_ENABLED) 1383 return; 1384 1385 pm_runtime_get_sync(dsi->dev); 1386 dsi->state |= DSIM_STATE_ENABLED; 1387 1388 if (dsi->panel) { 1389 ret = drm_panel_prepare(dsi->panel); 1390 if (ret < 0) 1391 goto err_put_sync; 1392 } else { 1393 drm_bridge_pre_enable(dsi->out_bridge); 1394 } 1395 1396 exynos_dsi_set_display_mode(dsi); 1397 exynos_dsi_set_display_enable(dsi, true); 1398 1399 if (dsi->panel) { 1400 ret = drm_panel_enable(dsi->panel); 1401 if (ret < 0) 1402 goto err_display_disable; 1403 } else { 1404 drm_bridge_enable(dsi->out_bridge); 1405 } 1406 1407 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1408 return; 1409 1410 err_display_disable: 1411 exynos_dsi_set_display_enable(dsi, false); 1412 drm_panel_unprepare(dsi->panel); 1413 1414 err_put_sync: 1415 dsi->state &= ~DSIM_STATE_ENABLED; 1416 pm_runtime_put(dsi->dev); 1417 } 1418 1419 static void exynos_dsi_disable(struct drm_encoder *encoder) 1420 { 1421 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1422 1423 if (!(dsi->state & DSIM_STATE_ENABLED)) 1424 return; 1425 1426 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1427 1428 drm_panel_disable(dsi->panel); 1429 drm_bridge_disable(dsi->out_bridge); 1430 exynos_dsi_set_display_enable(dsi, false); 1431 drm_panel_unprepare(dsi->panel); 1432 drm_bridge_post_disable(dsi->out_bridge); 1433 dsi->state &= ~DSIM_STATE_ENABLED; 1434 pm_runtime_put_sync(dsi->dev); 1435 } 1436 1437 static enum drm_connector_status 1438 exynos_dsi_detect(struct drm_connector *connector, bool force) 1439 { 1440 return connector->status; 1441 } 1442 1443 static void exynos_dsi_connector_destroy(struct drm_connector *connector) 1444 { 1445 drm_connector_unregister(connector); 1446 drm_connector_cleanup(connector); 1447 connector->dev = NULL; 1448 } 1449 1450 static const struct drm_connector_funcs exynos_dsi_connector_funcs = { 1451 .detect = exynos_dsi_detect, 1452 .fill_modes = drm_helper_probe_single_connector_modes, 1453 .destroy = exynos_dsi_connector_destroy, 1454 .reset = drm_atomic_helper_connector_reset, 1455 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1456 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1457 }; 1458 1459 static int exynos_dsi_get_modes(struct drm_connector *connector) 1460 { 1461 struct exynos_dsi *dsi = connector_to_dsi(connector); 1462 1463 if (dsi->panel) 1464 return dsi->panel->funcs->get_modes(dsi->panel); 1465 1466 return 0; 1467 } 1468 1469 static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 1470 .get_modes = exynos_dsi_get_modes, 1471 }; 1472 1473 static int exynos_dsi_create_connector(struct drm_encoder *encoder) 1474 { 1475 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1476 struct drm_connector *connector = &dsi->connector; 1477 struct drm_device *drm = encoder->dev; 1478 int ret; 1479 1480 connector->polled = DRM_CONNECTOR_POLL_HPD; 1481 1482 ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs, 1483 DRM_MODE_CONNECTOR_DSI); 1484 if (ret) { 1485 DRM_DEV_ERROR(dsi->dev, 1486 "Failed to initialize connector with drm\n"); 1487 return ret; 1488 } 1489 1490 connector->status = connector_status_disconnected; 1491 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 1492 drm_connector_attach_encoder(connector, encoder); 1493 if (!drm->registered) 1494 return 0; 1495 1496 connector->funcs->reset(connector); 1497 drm_fb_helper_add_one_connector(drm->fb_helper, connector); 1498 drm_connector_register(connector); 1499 return 0; 1500 } 1501 1502 static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { 1503 .enable = exynos_dsi_enable, 1504 .disable = exynos_dsi_disable, 1505 }; 1506 1507 static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { 1508 .destroy = drm_encoder_cleanup, 1509 }; 1510 1511 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 1512 1513 static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1514 struct mipi_dsi_device *device) 1515 { 1516 struct exynos_dsi *dsi = host_to_dsi(host); 1517 struct drm_encoder *encoder = &dsi->encoder; 1518 struct drm_device *drm = encoder->dev; 1519 struct drm_bridge *out_bridge; 1520 1521 out_bridge = of_drm_find_bridge(device->dev.of_node); 1522 if (out_bridge) { 1523 drm_bridge_attach(encoder, out_bridge, NULL); 1524 dsi->out_bridge = out_bridge; 1525 encoder->bridge = NULL; 1526 } else { 1527 int ret = exynos_dsi_create_connector(encoder); 1528 1529 if (ret) { 1530 DRM_DEV_ERROR(dsi->dev, 1531 "failed to create connector ret = %d\n", 1532 ret); 1533 drm_encoder_cleanup(encoder); 1534 return ret; 1535 } 1536 1537 dsi->panel = of_drm_find_panel(device->dev.of_node); 1538 if (IS_ERR(dsi->panel)) { 1539 dsi->panel = NULL; 1540 } else { 1541 drm_panel_attach(dsi->panel, &dsi->connector); 1542 dsi->connector.status = connector_status_connected; 1543 } 1544 } 1545 1546 /* 1547 * This is a temporary solution and should be made by more generic way. 1548 * 1549 * If attached panel device is for command mode one, dsi should register 1550 * TE interrupt handler. 1551 */ 1552 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1553 int ret = exynos_dsi_register_te_irq(dsi, &device->dev); 1554 if (ret) 1555 return ret; 1556 } 1557 1558 mutex_lock(&drm->mode_config.mutex); 1559 1560 dsi->lanes = device->lanes; 1561 dsi->format = device->format; 1562 dsi->mode_flags = device->mode_flags; 1563 exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = 1564 !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); 1565 1566 mutex_unlock(&drm->mode_config.mutex); 1567 1568 if (drm->mode_config.poll_enabled) 1569 drm_kms_helper_hotplug_event(drm); 1570 1571 return 0; 1572 } 1573 1574 static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1575 struct mipi_dsi_device *device) 1576 { 1577 struct exynos_dsi *dsi = host_to_dsi(host); 1578 struct drm_device *drm = dsi->encoder.dev; 1579 1580 if (dsi->panel) { 1581 mutex_lock(&drm->mode_config.mutex); 1582 exynos_dsi_disable(&dsi->encoder); 1583 drm_panel_detach(dsi->panel); 1584 dsi->panel = NULL; 1585 dsi->connector.status = connector_status_disconnected; 1586 mutex_unlock(&drm->mode_config.mutex); 1587 } else { 1588 if (dsi->out_bridge->funcs->detach) 1589 dsi->out_bridge->funcs->detach(dsi->out_bridge); 1590 dsi->out_bridge = NULL; 1591 } 1592 1593 if (drm->mode_config.poll_enabled) 1594 drm_kms_helper_hotplug_event(drm); 1595 1596 exynos_dsi_unregister_te_irq(dsi); 1597 1598 return 0; 1599 } 1600 1601 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1602 const struct mipi_dsi_msg *msg) 1603 { 1604 struct exynos_dsi *dsi = host_to_dsi(host); 1605 struct exynos_dsi_transfer xfer; 1606 int ret; 1607 1608 if (!(dsi->state & DSIM_STATE_ENABLED)) 1609 return -EINVAL; 1610 1611 if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1612 ret = exynos_dsi_init(dsi); 1613 if (ret) 1614 return ret; 1615 dsi->state |= DSIM_STATE_INITIALIZED; 1616 } 1617 1618 ret = mipi_dsi_create_packet(&xfer.packet, msg); 1619 if (ret < 0) 1620 return ret; 1621 1622 xfer.rx_len = msg->rx_len; 1623 xfer.rx_payload = msg->rx_buf; 1624 xfer.flags = msg->flags; 1625 1626 ret = exynos_dsi_transfer(dsi, &xfer); 1627 return (ret < 0) ? ret : xfer.rx_done; 1628 } 1629 1630 static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1631 .attach = exynos_dsi_host_attach, 1632 .detach = exynos_dsi_host_detach, 1633 .transfer = exynos_dsi_host_transfer, 1634 }; 1635 1636 static int exynos_dsi_of_read_u32(const struct device_node *np, 1637 const char *propname, u32 *out_value) 1638 { 1639 int ret = of_property_read_u32(np, propname, out_value); 1640 1641 if (ret < 0) 1642 pr_err("%pOF: failed to get '%s' property\n", np, propname); 1643 1644 return ret; 1645 } 1646 1647 enum { 1648 DSI_PORT_IN, 1649 DSI_PORT_OUT 1650 }; 1651 1652 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 1653 { 1654 struct device *dev = dsi->dev; 1655 struct device_node *node = dev->of_node; 1656 int ret; 1657 1658 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 1659 &dsi->pll_clk_rate); 1660 if (ret < 0) 1661 return ret; 1662 1663 ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 1664 &dsi->burst_clk_rate); 1665 if (ret < 0) 1666 return ret; 1667 1668 ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 1669 &dsi->esc_clk_rate); 1670 if (ret < 0) 1671 return ret; 1672 1673 dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0); 1674 1675 return 0; 1676 } 1677 1678 static int exynos_dsi_bind(struct device *dev, struct device *master, 1679 void *data) 1680 { 1681 struct drm_encoder *encoder = dev_get_drvdata(dev); 1682 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1683 struct drm_device *drm_dev = data; 1684 struct drm_bridge *in_bridge; 1685 int ret; 1686 1687 drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, 1688 DRM_MODE_ENCODER_TMDS, NULL); 1689 1690 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); 1691 1692 ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); 1693 if (ret < 0) 1694 return ret; 1695 1696 if (dsi->in_bridge_node) { 1697 in_bridge = of_drm_find_bridge(dsi->in_bridge_node); 1698 if (in_bridge) 1699 drm_bridge_attach(encoder, in_bridge, NULL); 1700 } 1701 1702 return mipi_dsi_host_register(&dsi->dsi_host); 1703 } 1704 1705 static void exynos_dsi_unbind(struct device *dev, struct device *master, 1706 void *data) 1707 { 1708 struct drm_encoder *encoder = dev_get_drvdata(dev); 1709 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1710 1711 exynos_dsi_disable(encoder); 1712 1713 mipi_dsi_host_unregister(&dsi->dsi_host); 1714 } 1715 1716 static const struct component_ops exynos_dsi_component_ops = { 1717 .bind = exynos_dsi_bind, 1718 .unbind = exynos_dsi_unbind, 1719 }; 1720 1721 static int exynos_dsi_probe(struct platform_device *pdev) 1722 { 1723 struct device *dev = &pdev->dev; 1724 struct resource *res; 1725 struct exynos_dsi *dsi; 1726 int ret, i; 1727 1728 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1729 if (!dsi) 1730 return -ENOMEM; 1731 1732 /* To be checked as invalid one */ 1733 dsi->te_gpio = -ENOENT; 1734 1735 init_completion(&dsi->completed); 1736 spin_lock_init(&dsi->transfer_lock); 1737 INIT_LIST_HEAD(&dsi->transfer_list); 1738 1739 dsi->dsi_host.ops = &exynos_dsi_ops; 1740 dsi->dsi_host.dev = dev; 1741 1742 dsi->dev = dev; 1743 dsi->driver_data = of_device_get_match_data(dev); 1744 1745 ret = exynos_dsi_parse_dt(dsi); 1746 if (ret) 1747 return ret; 1748 1749 dsi->supplies[0].supply = "vddcore"; 1750 dsi->supplies[1].supply = "vddio"; 1751 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1752 dsi->supplies); 1753 if (ret) { 1754 dev_info(dev, "failed to get regulators: %d\n", ret); 1755 return -EPROBE_DEFER; 1756 } 1757 1758 dsi->clks = devm_kcalloc(dev, 1759 dsi->driver_data->num_clks, sizeof(*dsi->clks), 1760 GFP_KERNEL); 1761 if (!dsi->clks) 1762 return -ENOMEM; 1763 1764 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1765 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1766 if (IS_ERR(dsi->clks[i])) { 1767 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1768 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 1769 i--; 1770 continue; 1771 } 1772 1773 dev_info(dev, "failed to get the clock: %s\n", 1774 clk_names[i]); 1775 return PTR_ERR(dsi->clks[i]); 1776 } 1777 } 1778 1779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1780 dsi->reg_base = devm_ioremap_resource(dev, res); 1781 if (IS_ERR(dsi->reg_base)) { 1782 dev_err(dev, "failed to remap io region\n"); 1783 return PTR_ERR(dsi->reg_base); 1784 } 1785 1786 dsi->phy = devm_phy_get(dev, "dsim"); 1787 if (IS_ERR(dsi->phy)) { 1788 dev_info(dev, "failed to get dsim phy\n"); 1789 return PTR_ERR(dsi->phy); 1790 } 1791 1792 dsi->irq = platform_get_irq(pdev, 0); 1793 if (dsi->irq < 0) { 1794 dev_err(dev, "failed to request dsi irq resource\n"); 1795 return dsi->irq; 1796 } 1797 1798 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1799 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1800 exynos_dsi_irq, IRQF_ONESHOT, 1801 dev_name(dev), dsi); 1802 if (ret) { 1803 dev_err(dev, "failed to request dsi irq\n"); 1804 return ret; 1805 } 1806 1807 platform_set_drvdata(pdev, &dsi->encoder); 1808 1809 pm_runtime_enable(dev); 1810 1811 return component_add(dev, &exynos_dsi_component_ops); 1812 } 1813 1814 static int exynos_dsi_remove(struct platform_device *pdev) 1815 { 1816 struct exynos_dsi *dsi = platform_get_drvdata(pdev); 1817 1818 of_node_put(dsi->in_bridge_node); 1819 1820 pm_runtime_disable(&pdev->dev); 1821 1822 component_del(&pdev->dev, &exynos_dsi_component_ops); 1823 1824 return 0; 1825 } 1826 1827 static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1828 { 1829 struct drm_encoder *encoder = dev_get_drvdata(dev); 1830 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1831 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1832 int ret, i; 1833 1834 usleep_range(10000, 20000); 1835 1836 if (dsi->state & DSIM_STATE_INITIALIZED) { 1837 dsi->state &= ~DSIM_STATE_INITIALIZED; 1838 1839 exynos_dsi_disable_clock(dsi); 1840 1841 exynos_dsi_disable_irq(dsi); 1842 } 1843 1844 dsi->state &= ~DSIM_STATE_CMD_LPM; 1845 1846 phy_power_off(dsi->phy); 1847 1848 for (i = driver_data->num_clks - 1; i > -1; i--) 1849 clk_disable_unprepare(dsi->clks[i]); 1850 1851 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1852 if (ret < 0) 1853 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1854 1855 return 0; 1856 } 1857 1858 static int __maybe_unused exynos_dsi_resume(struct device *dev) 1859 { 1860 struct drm_encoder *encoder = dev_get_drvdata(dev); 1861 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1862 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1863 int ret, i; 1864 1865 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1866 if (ret < 0) { 1867 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1868 return ret; 1869 } 1870 1871 for (i = 0; i < driver_data->num_clks; i++) { 1872 ret = clk_prepare_enable(dsi->clks[i]); 1873 if (ret < 0) 1874 goto err_clk; 1875 } 1876 1877 ret = phy_power_on(dsi->phy); 1878 if (ret < 0) { 1879 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1880 goto err_clk; 1881 } 1882 1883 return 0; 1884 1885 err_clk: 1886 while (--i > -1) 1887 clk_disable_unprepare(dsi->clks[i]); 1888 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1889 1890 return ret; 1891 } 1892 1893 static const struct dev_pm_ops exynos_dsi_pm_ops = { 1894 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 1895 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1896 pm_runtime_force_resume) 1897 }; 1898 1899 struct platform_driver dsi_driver = { 1900 .probe = exynos_dsi_probe, 1901 .remove = exynos_dsi_remove, 1902 .driver = { 1903 .name = "exynos-dsi", 1904 .owner = THIS_MODULE, 1905 .pm = &exynos_dsi_pm_ops, 1906 .of_match_table = exynos_dsi_of_match, 1907 }, 1908 }; 1909 1910 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 1911 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 1912 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 1913 MODULE_LICENSE("GPL v2"); 1914