1 /* 2 * Samsung SoC MIPI DSI Master driver. 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd 5 * 6 * Contacts: Tomasz Figa <t.figa@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <asm/unaligned.h> 14 15 #include <drm/drmP.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_mipi_dsi.h> 18 #include <drm/drm_panel.h> 19 #include <drm/drm_atomic_helper.h> 20 21 #include <linux/clk.h> 22 #include <linux/gpio/consumer.h> 23 #include <linux/irq.h> 24 #include <linux/of_device.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_graph.h> 27 #include <linux/phy/phy.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/component.h> 30 31 #include <video/mipi_display.h> 32 #include <video/videomode.h> 33 34 #include "exynos_drm_crtc.h" 35 #include "exynos_drm_drv.h" 36 37 /* returns true iff both arguments logically differs */ 38 #define NEQV(a, b) (!(a) ^ !(b)) 39 40 /* DSIM_STATUS */ 41 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 42 #define DSIM_STOP_STATE_CLK (1 << 8) 43 #define DSIM_TX_READY_HS_CLK (1 << 10) 44 #define DSIM_PLL_STABLE (1 << 31) 45 46 /* DSIM_SWRST */ 47 #define DSIM_FUNCRST (1 << 16) 48 #define DSIM_SWRST (1 << 0) 49 50 /* DSIM_TIMEOUT */ 51 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 52 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 53 54 /* DSIM_CLKCTRL */ 55 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 56 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 57 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 58 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 59 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 60 #define DSIM_BYTE_CLKEN (1 << 24) 61 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 62 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 63 #define DSIM_PLL_BYPASS (1 << 27) 64 #define DSIM_ESC_CLKEN (1 << 28) 65 #define DSIM_TX_REQUEST_HSCLK (1 << 31) 66 67 /* DSIM_CONFIG */ 68 #define DSIM_LANE_EN_CLK (1 << 0) 69 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 70 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 71 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 72 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 73 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 74 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 75 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 76 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 77 #define DSIM_SUB_VC (((x) & 0x3) << 16) 78 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 79 #define DSIM_HSA_MODE (1 << 20) 80 #define DSIM_HBP_MODE (1 << 21) 81 #define DSIM_HFP_MODE (1 << 22) 82 #define DSIM_HSE_MODE (1 << 23) 83 #define DSIM_AUTO_MODE (1 << 24) 84 #define DSIM_VIDEO_MODE (1 << 25) 85 #define DSIM_BURST_MODE (1 << 26) 86 #define DSIM_SYNC_INFORM (1 << 27) 87 #define DSIM_EOT_DISABLE (1 << 28) 88 #define DSIM_MFLUSH_VS (1 << 29) 89 /* This flag is valid only for exynos3250/3472/5260/5430 */ 90 #define DSIM_CLKLANE_STOP (1 << 30) 91 92 /* DSIM_ESCMODE */ 93 #define DSIM_TX_TRIGGER_RST (1 << 4) 94 #define DSIM_TX_LPDT_LP (1 << 6) 95 #define DSIM_CMD_LPDT_LP (1 << 7) 96 #define DSIM_FORCE_BTA (1 << 16) 97 #define DSIM_FORCE_STOP_STATE (1 << 20) 98 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 99 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 100 101 /* DSIM_MDRESOL */ 102 #define DSIM_MAIN_STAND_BY (1 << 31) 103 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 104 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 105 106 /* DSIM_MVPORCH */ 107 #define DSIM_CMD_ALLOW(x) ((x) << 28) 108 #define DSIM_STABLE_VFP(x) ((x) << 16) 109 #define DSIM_MAIN_VBP(x) ((x) << 0) 110 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 111 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 112 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 113 114 /* DSIM_MHPORCH */ 115 #define DSIM_MAIN_HFP(x) ((x) << 16) 116 #define DSIM_MAIN_HBP(x) ((x) << 0) 117 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 118 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 119 120 /* DSIM_MSYNC */ 121 #define DSIM_MAIN_VSA(x) ((x) << 22) 122 #define DSIM_MAIN_HSA(x) ((x) << 0) 123 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 124 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 125 126 /* DSIM_SDRESOL */ 127 #define DSIM_SUB_STANDY(x) ((x) << 31) 128 #define DSIM_SUB_VRESOL(x) ((x) << 16) 129 #define DSIM_SUB_HRESOL(x) ((x) << 0) 130 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 131 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 132 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 133 134 /* DSIM_INTSRC */ 135 #define DSIM_INT_PLL_STABLE (1 << 31) 136 #define DSIM_INT_SW_RST_RELEASE (1 << 30) 137 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 138 #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 139 #define DSIM_INT_BTA (1 << 25) 140 #define DSIM_INT_FRAME_DONE (1 << 24) 141 #define DSIM_INT_RX_TIMEOUT (1 << 21) 142 #define DSIM_INT_BTA_TIMEOUT (1 << 20) 143 #define DSIM_INT_RX_DONE (1 << 18) 144 #define DSIM_INT_RX_TE (1 << 17) 145 #define DSIM_INT_RX_ACK (1 << 16) 146 #define DSIM_INT_RX_ECC_ERR (1 << 15) 147 #define DSIM_INT_RX_CRC_ERR (1 << 14) 148 149 /* DSIM_FIFOCTRL */ 150 #define DSIM_RX_DATA_FULL (1 << 25) 151 #define DSIM_RX_DATA_EMPTY (1 << 24) 152 #define DSIM_SFR_HEADER_FULL (1 << 23) 153 #define DSIM_SFR_HEADER_EMPTY (1 << 22) 154 #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 155 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 156 #define DSIM_I80_HEADER_FULL (1 << 19) 157 #define DSIM_I80_HEADER_EMPTY (1 << 18) 158 #define DSIM_I80_PAYLOAD_FULL (1 << 17) 159 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 160 #define DSIM_SD_HEADER_FULL (1 << 15) 161 #define DSIM_SD_HEADER_EMPTY (1 << 14) 162 #define DSIM_SD_PAYLOAD_FULL (1 << 13) 163 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 164 #define DSIM_MD_HEADER_FULL (1 << 11) 165 #define DSIM_MD_HEADER_EMPTY (1 << 10) 166 #define DSIM_MD_PAYLOAD_FULL (1 << 9) 167 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 168 #define DSIM_RX_FIFO (1 << 4) 169 #define DSIM_SFR_FIFO (1 << 3) 170 #define DSIM_I80_FIFO (1 << 2) 171 #define DSIM_SD_FIFO (1 << 1) 172 #define DSIM_MD_FIFO (1 << 0) 173 174 /* DSIM_PHYACCHR */ 175 #define DSIM_AFC_EN (1 << 14) 176 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 177 178 /* DSIM_PLLCTRL */ 179 #define DSIM_FREQ_BAND(x) ((x) << 24) 180 #define DSIM_PLL_EN (1 << 23) 181 #define DSIM_PLL_P(x) ((x) << 13) 182 #define DSIM_PLL_M(x) ((x) << 4) 183 #define DSIM_PLL_S(x) ((x) << 1) 184 185 /* DSIM_PHYCTRL */ 186 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 187 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 188 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 189 190 /* DSIM_PHYTIMING */ 191 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 192 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 193 194 /* DSIM_PHYTIMING1 */ 195 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 196 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 197 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 198 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 199 200 /* DSIM_PHYTIMING2 */ 201 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 202 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 203 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 204 205 #define DSI_MAX_BUS_WIDTH 4 206 #define DSI_NUM_VIRTUAL_CHANNELS 4 207 #define DSI_TX_FIFO_SIZE 2048 208 #define DSI_RX_FIFO_SIZE 256 209 #define DSI_XFER_TIMEOUT_MS 100 210 #define DSI_RX_FIFO_EMPTY 0x30800002 211 212 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 213 214 static char *clk_names[5] = { "bus_clk", "sclk_mipi", 215 "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 216 "sclk_rgb_vclk_to_dsim0" }; 217 218 enum exynos_dsi_transfer_type { 219 EXYNOS_DSI_TX, 220 EXYNOS_DSI_RX, 221 }; 222 223 struct exynos_dsi_transfer { 224 struct list_head list; 225 struct completion completed; 226 int result; 227 struct mipi_dsi_packet packet; 228 u16 flags; 229 u16 tx_done; 230 231 u8 *rx_payload; 232 u16 rx_len; 233 u16 rx_done; 234 }; 235 236 #define DSIM_STATE_ENABLED BIT(0) 237 #define DSIM_STATE_INITIALIZED BIT(1) 238 #define DSIM_STATE_CMD_LPM BIT(2) 239 #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 240 241 struct exynos_dsi_driver_data { 242 const unsigned int *reg_ofs; 243 unsigned int plltmr_reg; 244 unsigned int has_freqband:1; 245 unsigned int has_clklane_stop:1; 246 unsigned int num_clks; 247 unsigned int max_freq; 248 unsigned int wait_for_reset; 249 unsigned int num_bits_resol; 250 const unsigned int *reg_values; 251 }; 252 253 struct exynos_dsi { 254 struct drm_encoder encoder; 255 struct mipi_dsi_host dsi_host; 256 struct drm_connector connector; 257 struct device_node *panel_node; 258 struct drm_panel *panel; 259 struct device *dev; 260 261 void __iomem *reg_base; 262 struct phy *phy; 263 struct clk **clks; 264 struct regulator_bulk_data supplies[2]; 265 int irq; 266 int te_gpio; 267 268 u32 pll_clk_rate; 269 u32 burst_clk_rate; 270 u32 esc_clk_rate; 271 u32 lanes; 272 u32 mode_flags; 273 u32 format; 274 struct videomode vm; 275 276 int state; 277 struct drm_property *brightness; 278 struct completion completed; 279 280 spinlock_t transfer_lock; /* protects transfer_list */ 281 struct list_head transfer_list; 282 283 const struct exynos_dsi_driver_data *driver_data; 284 struct device_node *bridge_node; 285 }; 286 287 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 288 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 289 290 static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) 291 { 292 return container_of(e, struct exynos_dsi, encoder); 293 } 294 295 enum reg_idx { 296 DSIM_STATUS_REG, /* Status register */ 297 DSIM_SWRST_REG, /* Software reset register */ 298 DSIM_CLKCTRL_REG, /* Clock control register */ 299 DSIM_TIMEOUT_REG, /* Time out register */ 300 DSIM_CONFIG_REG, /* Configuration register */ 301 DSIM_ESCMODE_REG, /* Escape mode register */ 302 DSIM_MDRESOL_REG, 303 DSIM_MVPORCH_REG, /* Main display Vporch register */ 304 DSIM_MHPORCH_REG, /* Main display Hporch register */ 305 DSIM_MSYNC_REG, /* Main display sync area register */ 306 DSIM_INTSRC_REG, /* Interrupt source register */ 307 DSIM_INTMSK_REG, /* Interrupt mask register */ 308 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 309 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 310 DSIM_RXFIFO_REG, /* Read FIFO register */ 311 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 312 DSIM_PLLCTRL_REG, /* PLL control register */ 313 DSIM_PHYCTRL_REG, 314 DSIM_PHYTIMING_REG, 315 DSIM_PHYTIMING1_REG, 316 DSIM_PHYTIMING2_REG, 317 NUM_REGS 318 }; 319 320 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 321 u32 val) 322 { 323 324 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 325 } 326 327 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 328 { 329 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 330 } 331 332 static const unsigned int exynos_reg_ofs[] = { 333 [DSIM_STATUS_REG] = 0x00, 334 [DSIM_SWRST_REG] = 0x04, 335 [DSIM_CLKCTRL_REG] = 0x08, 336 [DSIM_TIMEOUT_REG] = 0x0c, 337 [DSIM_CONFIG_REG] = 0x10, 338 [DSIM_ESCMODE_REG] = 0x14, 339 [DSIM_MDRESOL_REG] = 0x18, 340 [DSIM_MVPORCH_REG] = 0x1c, 341 [DSIM_MHPORCH_REG] = 0x20, 342 [DSIM_MSYNC_REG] = 0x24, 343 [DSIM_INTSRC_REG] = 0x2c, 344 [DSIM_INTMSK_REG] = 0x30, 345 [DSIM_PKTHDR_REG] = 0x34, 346 [DSIM_PAYLOAD_REG] = 0x38, 347 [DSIM_RXFIFO_REG] = 0x3c, 348 [DSIM_FIFOCTRL_REG] = 0x44, 349 [DSIM_PLLCTRL_REG] = 0x4c, 350 [DSIM_PHYCTRL_REG] = 0x5c, 351 [DSIM_PHYTIMING_REG] = 0x64, 352 [DSIM_PHYTIMING1_REG] = 0x68, 353 [DSIM_PHYTIMING2_REG] = 0x6c, 354 }; 355 356 static const unsigned int exynos5433_reg_ofs[] = { 357 [DSIM_STATUS_REG] = 0x04, 358 [DSIM_SWRST_REG] = 0x0C, 359 [DSIM_CLKCTRL_REG] = 0x10, 360 [DSIM_TIMEOUT_REG] = 0x14, 361 [DSIM_CONFIG_REG] = 0x18, 362 [DSIM_ESCMODE_REG] = 0x1C, 363 [DSIM_MDRESOL_REG] = 0x20, 364 [DSIM_MVPORCH_REG] = 0x24, 365 [DSIM_MHPORCH_REG] = 0x28, 366 [DSIM_MSYNC_REG] = 0x2C, 367 [DSIM_INTSRC_REG] = 0x34, 368 [DSIM_INTMSK_REG] = 0x38, 369 [DSIM_PKTHDR_REG] = 0x3C, 370 [DSIM_PAYLOAD_REG] = 0x40, 371 [DSIM_RXFIFO_REG] = 0x44, 372 [DSIM_FIFOCTRL_REG] = 0x4C, 373 [DSIM_PLLCTRL_REG] = 0x94, 374 [DSIM_PHYCTRL_REG] = 0xA4, 375 [DSIM_PHYTIMING_REG] = 0xB4, 376 [DSIM_PHYTIMING1_REG] = 0xB8, 377 [DSIM_PHYTIMING2_REG] = 0xBC, 378 }; 379 380 enum reg_value_idx { 381 RESET_TYPE, 382 PLL_TIMER, 383 STOP_STATE_CNT, 384 PHYCTRL_ULPS_EXIT, 385 PHYCTRL_VREG_LP, 386 PHYCTRL_SLEW_UP, 387 PHYTIMING_LPX, 388 PHYTIMING_HS_EXIT, 389 PHYTIMING_CLK_PREPARE, 390 PHYTIMING_CLK_ZERO, 391 PHYTIMING_CLK_POST, 392 PHYTIMING_CLK_TRAIL, 393 PHYTIMING_HS_PREPARE, 394 PHYTIMING_HS_ZERO, 395 PHYTIMING_HS_TRAIL 396 }; 397 398 static const unsigned int reg_values[] = { 399 [RESET_TYPE] = DSIM_SWRST, 400 [PLL_TIMER] = 500, 401 [STOP_STATE_CNT] = 0xf, 402 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 403 [PHYCTRL_VREG_LP] = 0, 404 [PHYCTRL_SLEW_UP] = 0, 405 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 406 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 407 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 408 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 409 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 410 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 411 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 412 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 413 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 414 }; 415 416 static const unsigned int exynos5422_reg_values[] = { 417 [RESET_TYPE] = DSIM_SWRST, 418 [PLL_TIMER] = 500, 419 [STOP_STATE_CNT] = 0xf, 420 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 421 [PHYCTRL_VREG_LP] = 0, 422 [PHYCTRL_SLEW_UP] = 0, 423 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 424 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 425 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 426 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 427 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 428 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 429 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 430 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 431 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 432 }; 433 434 static const unsigned int exynos5433_reg_values[] = { 435 [RESET_TYPE] = DSIM_FUNCRST, 436 [PLL_TIMER] = 22200, 437 [STOP_STATE_CNT] = 0xa, 438 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 439 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 440 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 441 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 442 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 443 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 444 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 445 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 446 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 447 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 448 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 449 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 450 }; 451 452 static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 453 .reg_ofs = exynos_reg_ofs, 454 .plltmr_reg = 0x50, 455 .has_freqband = 1, 456 .has_clklane_stop = 1, 457 .num_clks = 2, 458 .max_freq = 1000, 459 .wait_for_reset = 1, 460 .num_bits_resol = 11, 461 .reg_values = reg_values, 462 }; 463 464 static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 465 .reg_ofs = exynos_reg_ofs, 466 .plltmr_reg = 0x50, 467 .has_freqband = 1, 468 .has_clklane_stop = 1, 469 .num_clks = 2, 470 .max_freq = 1000, 471 .wait_for_reset = 1, 472 .num_bits_resol = 11, 473 .reg_values = reg_values, 474 }; 475 476 static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 477 .reg_ofs = exynos_reg_ofs, 478 .plltmr_reg = 0x58, 479 .num_clks = 2, 480 .max_freq = 1000, 481 .wait_for_reset = 1, 482 .num_bits_resol = 11, 483 .reg_values = reg_values, 484 }; 485 486 static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 487 .reg_ofs = exynos5433_reg_ofs, 488 .plltmr_reg = 0xa0, 489 .has_clklane_stop = 1, 490 .num_clks = 5, 491 .max_freq = 1500, 492 .wait_for_reset = 0, 493 .num_bits_resol = 12, 494 .reg_values = exynos5433_reg_values, 495 }; 496 497 static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 498 .reg_ofs = exynos5433_reg_ofs, 499 .plltmr_reg = 0xa0, 500 .has_clklane_stop = 1, 501 .num_clks = 2, 502 .max_freq = 1500, 503 .wait_for_reset = 1, 504 .num_bits_resol = 12, 505 .reg_values = exynos5422_reg_values, 506 }; 507 508 static const struct of_device_id exynos_dsi_of_match[] = { 509 { .compatible = "samsung,exynos3250-mipi-dsi", 510 .data = &exynos3_dsi_driver_data }, 511 { .compatible = "samsung,exynos4210-mipi-dsi", 512 .data = &exynos4_dsi_driver_data }, 513 { .compatible = "samsung,exynos5410-mipi-dsi", 514 .data = &exynos5_dsi_driver_data }, 515 { .compatible = "samsung,exynos5422-mipi-dsi", 516 .data = &exynos5422_dsi_driver_data }, 517 { .compatible = "samsung,exynos5433-mipi-dsi", 518 .data = &exynos5433_dsi_driver_data }, 519 { } 520 }; 521 522 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 523 { 524 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 525 return; 526 527 dev_err(dsi->dev, "timeout waiting for reset\n"); 528 } 529 530 static void exynos_dsi_reset(struct exynos_dsi *dsi) 531 { 532 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 533 534 reinit_completion(&dsi->completed); 535 exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 536 } 537 538 #ifndef MHZ 539 #define MHZ (1000*1000) 540 #endif 541 542 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 543 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 544 { 545 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 546 unsigned long best_freq = 0; 547 u32 min_delta = 0xffffffff; 548 u8 p_min, p_max; 549 u8 _p, uninitialized_var(best_p); 550 u16 _m, uninitialized_var(best_m); 551 u8 _s, uninitialized_var(best_s); 552 553 p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 554 p_max = fin / (6 * MHZ); 555 556 for (_p = p_min; _p <= p_max; ++_p) { 557 for (_s = 0; _s <= 5; ++_s) { 558 u64 tmp; 559 u32 delta; 560 561 tmp = (u64)fout * (_p << _s); 562 do_div(tmp, fin); 563 _m = tmp; 564 if (_m < 41 || _m > 125) 565 continue; 566 567 tmp = (u64)_m * fin; 568 do_div(tmp, _p); 569 if (tmp < 500 * MHZ || 570 tmp > driver_data->max_freq * MHZ) 571 continue; 572 573 tmp = (u64)_m * fin; 574 do_div(tmp, _p << _s); 575 576 delta = abs(fout - tmp); 577 if (delta < min_delta) { 578 best_p = _p; 579 best_m = _m; 580 best_s = _s; 581 min_delta = delta; 582 best_freq = tmp; 583 } 584 } 585 } 586 587 if (best_freq) { 588 *p = best_p; 589 *m = best_m; 590 *s = best_s; 591 } 592 593 return best_freq; 594 } 595 596 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 597 unsigned long freq) 598 { 599 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 600 unsigned long fin, fout; 601 int timeout; 602 u8 p, s; 603 u16 m; 604 u32 reg; 605 606 fin = dsi->pll_clk_rate; 607 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 608 if (!fout) { 609 dev_err(dsi->dev, 610 "failed to find PLL PMS for requested frequency\n"); 611 return 0; 612 } 613 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 614 615 writel(driver_data->reg_values[PLL_TIMER], 616 dsi->reg_base + driver_data->plltmr_reg); 617 618 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 619 620 if (driver_data->has_freqband) { 621 static const unsigned long freq_bands[] = { 622 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 623 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 624 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 625 770 * MHZ, 870 * MHZ, 950 * MHZ, 626 }; 627 int band; 628 629 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 630 if (fout < freq_bands[band]) 631 break; 632 633 dev_dbg(dsi->dev, "band %d\n", band); 634 635 reg |= DSIM_FREQ_BAND(band); 636 } 637 638 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 639 640 timeout = 1000; 641 do { 642 if (timeout-- == 0) { 643 dev_err(dsi->dev, "PLL failed to stabilize\n"); 644 return 0; 645 } 646 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 647 } while ((reg & DSIM_PLL_STABLE) == 0); 648 649 return fout; 650 } 651 652 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 653 { 654 unsigned long hs_clk, byte_clk, esc_clk; 655 unsigned long esc_div; 656 u32 reg; 657 658 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 659 if (!hs_clk) { 660 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 661 return -EFAULT; 662 } 663 664 byte_clk = hs_clk / 8; 665 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 666 esc_clk = byte_clk / esc_div; 667 668 if (esc_clk > 20 * MHZ) { 669 ++esc_div; 670 esc_clk = byte_clk / esc_div; 671 } 672 673 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 674 hs_clk, byte_clk, esc_clk); 675 676 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 677 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 678 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 679 | DSIM_BYTE_CLK_SRC_MASK); 680 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 681 | DSIM_ESC_PRESCALER(esc_div) 682 | DSIM_LANE_ESC_CLK_EN_CLK 683 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 684 | DSIM_BYTE_CLK_SRC(0) 685 | DSIM_TX_REQUEST_HSCLK; 686 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 687 688 return 0; 689 } 690 691 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 692 { 693 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 694 const unsigned int *reg_values = driver_data->reg_values; 695 u32 reg; 696 697 if (driver_data->has_freqband) 698 return; 699 700 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 701 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 702 reg_values[PHYCTRL_SLEW_UP]; 703 exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 704 705 /* 706 * T LPX: Transmitted length of any Low-Power state period 707 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 708 * burst 709 */ 710 reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 711 exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 712 713 /* 714 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 715 * Line state immediately before the HS-0 Line state starting the 716 * HS transmission 717 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 718 * transmitting the Clock. 719 * T CLK_POST: Time that the transmitter continues to send HS clock 720 * after the last associated Data Lane has transitioned to LP Mode 721 * Interval is defined as the period from the end of T HS-TRAIL to 722 * the beginning of T CLK-TRAIL 723 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 724 * the last payload clock bit of a HS transmission burst 725 */ 726 reg = reg_values[PHYTIMING_CLK_PREPARE] | 727 reg_values[PHYTIMING_CLK_ZERO] | 728 reg_values[PHYTIMING_CLK_POST] | 729 reg_values[PHYTIMING_CLK_TRAIL]; 730 731 exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 732 733 /* 734 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 735 * Line state immediately before the HS-0 Line state starting the 736 * HS transmission 737 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 738 * transmitting the Sync sequence. 739 * T HS-TRAIL: Time that the transmitter drives the flipped differential 740 * state after last payload data bit of a HS transmission burst 741 */ 742 reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 743 reg_values[PHYTIMING_HS_TRAIL]; 744 exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 745 } 746 747 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 748 { 749 u32 reg; 750 751 reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 752 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 753 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 754 exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 755 756 reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 757 reg &= ~DSIM_PLL_EN; 758 exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 759 } 760 761 static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 762 { 763 u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 764 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 765 DSIM_LANE_EN(lane)); 766 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 767 } 768 769 static int exynos_dsi_init_link(struct exynos_dsi *dsi) 770 { 771 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 772 int timeout; 773 u32 reg; 774 u32 lanes_mask; 775 776 /* Initialize FIFO pointers */ 777 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 778 reg &= ~0x1f; 779 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 780 781 usleep_range(9000, 11000); 782 783 reg |= 0x1f; 784 exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 785 usleep_range(9000, 11000); 786 787 /* DSI configuration */ 788 reg = 0; 789 790 /* 791 * The first bit of mode_flags specifies display configuration. 792 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 793 * mode, otherwise it will support command mode. 794 */ 795 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 796 reg |= DSIM_VIDEO_MODE; 797 798 /* 799 * The user manual describes that following bits are ignored in 800 * command mode. 801 */ 802 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 803 reg |= DSIM_MFLUSH_VS; 804 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 805 reg |= DSIM_SYNC_INFORM; 806 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 807 reg |= DSIM_BURST_MODE; 808 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 809 reg |= DSIM_AUTO_MODE; 810 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 811 reg |= DSIM_HSE_MODE; 812 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 813 reg |= DSIM_HFP_MODE; 814 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 815 reg |= DSIM_HBP_MODE; 816 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 817 reg |= DSIM_HSA_MODE; 818 } 819 820 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 821 reg |= DSIM_EOT_DISABLE; 822 823 switch (dsi->format) { 824 case MIPI_DSI_FMT_RGB888: 825 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 826 break; 827 case MIPI_DSI_FMT_RGB666: 828 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 829 break; 830 case MIPI_DSI_FMT_RGB666_PACKED: 831 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 832 break; 833 case MIPI_DSI_FMT_RGB565: 834 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 835 break; 836 default: 837 dev_err(dsi->dev, "invalid pixel format\n"); 838 return -EINVAL; 839 } 840 841 /* 842 * Use non-continuous clock mode if the periparal wants and 843 * host controller supports 844 * 845 * In non-continous clock mode, host controller will turn off 846 * the HS clock between high-speed transmissions to reduce 847 * power consumption. 848 */ 849 if (driver_data->has_clklane_stop && 850 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 851 reg |= DSIM_CLKLANE_STOP; 852 } 853 exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 854 855 lanes_mask = BIT(dsi->lanes) - 1; 856 exynos_dsi_enable_lane(dsi, lanes_mask); 857 858 /* Check clock and data lane state are stop state */ 859 timeout = 100; 860 do { 861 if (timeout-- == 0) { 862 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 863 return -EFAULT; 864 } 865 866 reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 867 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 868 != DSIM_STOP_STATE_DAT(lanes_mask)) 869 continue; 870 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 871 872 reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 873 reg &= ~DSIM_STOP_STATE_CNT_MASK; 874 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 875 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 876 877 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 878 exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 879 880 return 0; 881 } 882 883 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 884 { 885 struct videomode *vm = &dsi->vm; 886 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 887 u32 reg; 888 889 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 890 reg = DSIM_CMD_ALLOW(0xf) 891 | DSIM_STABLE_VFP(vm->vfront_porch) 892 | DSIM_MAIN_VBP(vm->vback_porch); 893 exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 894 895 reg = DSIM_MAIN_HFP(vm->hfront_porch) 896 | DSIM_MAIN_HBP(vm->hback_porch); 897 exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 898 899 reg = DSIM_MAIN_VSA(vm->vsync_len) 900 | DSIM_MAIN_HSA(vm->hsync_len); 901 exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 902 } 903 reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | 904 DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); 905 906 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 907 908 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 909 } 910 911 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 912 { 913 u32 reg; 914 915 reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 916 if (enable) 917 reg |= DSIM_MAIN_STAND_BY; 918 else 919 reg &= ~DSIM_MAIN_STAND_BY; 920 exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 921 } 922 923 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 924 { 925 int timeout = 2000; 926 927 do { 928 u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 929 930 if (!(reg & DSIM_SFR_HEADER_FULL)) 931 return 0; 932 933 if (!cond_resched()) 934 usleep_range(950, 1050); 935 } while (--timeout); 936 937 return -ETIMEDOUT; 938 } 939 940 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 941 { 942 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 943 944 if (lpm) 945 v |= DSIM_CMD_LPDT_LP; 946 else 947 v &= ~DSIM_CMD_LPDT_LP; 948 949 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 950 } 951 952 static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 953 { 954 u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 955 v |= DSIM_FORCE_BTA; 956 exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 957 } 958 959 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 960 struct exynos_dsi_transfer *xfer) 961 { 962 struct device *dev = dsi->dev; 963 struct mipi_dsi_packet *pkt = &xfer->packet; 964 const u8 *payload = pkt->payload + xfer->tx_done; 965 u16 length = pkt->payload_length - xfer->tx_done; 966 bool first = !xfer->tx_done; 967 u32 reg; 968 969 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 970 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 971 972 if (length > DSI_TX_FIFO_SIZE) 973 length = DSI_TX_FIFO_SIZE; 974 975 xfer->tx_done += length; 976 977 /* Send payload */ 978 while (length >= 4) { 979 reg = get_unaligned_le32(payload); 980 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 981 payload += 4; 982 length -= 4; 983 } 984 985 reg = 0; 986 switch (length) { 987 case 3: 988 reg |= payload[2] << 16; 989 /* Fall through */ 990 case 2: 991 reg |= payload[1] << 8; 992 /* Fall through */ 993 case 1: 994 reg |= payload[0]; 995 exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 996 break; 997 } 998 999 /* Send packet header */ 1000 if (!first) 1001 return; 1002 1003 reg = get_unaligned_le32(pkt->header); 1004 if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 1005 dev_err(dev, "waiting for header FIFO timed out\n"); 1006 return; 1007 } 1008 1009 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1010 dsi->state & DSIM_STATE_CMD_LPM)) { 1011 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1012 dsi->state ^= DSIM_STATE_CMD_LPM; 1013 } 1014 1015 exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 1016 1017 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1018 exynos_dsi_force_bta(dsi); 1019 } 1020 1021 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 1022 struct exynos_dsi_transfer *xfer) 1023 { 1024 u8 *payload = xfer->rx_payload + xfer->rx_done; 1025 bool first = !xfer->rx_done; 1026 struct device *dev = dsi->dev; 1027 u16 length; 1028 u32 reg; 1029 1030 if (first) { 1031 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1032 1033 switch (reg & 0x3f) { 1034 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1035 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1036 if (xfer->rx_len >= 2) { 1037 payload[1] = reg >> 16; 1038 ++xfer->rx_done; 1039 } 1040 /* Fall through */ 1041 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1042 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1043 payload[0] = reg >> 8; 1044 ++xfer->rx_done; 1045 xfer->rx_len = xfer->rx_done; 1046 xfer->result = 0; 1047 goto clear_fifo; 1048 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1049 dev_err(dev, "DSI Error Report: 0x%04x\n", 1050 (reg >> 8) & 0xffff); 1051 xfer->result = 0; 1052 goto clear_fifo; 1053 } 1054 1055 length = (reg >> 8) & 0xffff; 1056 if (length > xfer->rx_len) { 1057 dev_err(dev, 1058 "response too long (%u > %u bytes), stripping\n", 1059 xfer->rx_len, length); 1060 length = xfer->rx_len; 1061 } else if (length < xfer->rx_len) 1062 xfer->rx_len = length; 1063 } 1064 1065 length = xfer->rx_len - xfer->rx_done; 1066 xfer->rx_done += length; 1067 1068 /* Receive payload */ 1069 while (length >= 4) { 1070 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1071 payload[0] = (reg >> 0) & 0xff; 1072 payload[1] = (reg >> 8) & 0xff; 1073 payload[2] = (reg >> 16) & 0xff; 1074 payload[3] = (reg >> 24) & 0xff; 1075 payload += 4; 1076 length -= 4; 1077 } 1078 1079 if (length) { 1080 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1081 switch (length) { 1082 case 3: 1083 payload[2] = (reg >> 16) & 0xff; 1084 /* Fall through */ 1085 case 2: 1086 payload[1] = (reg >> 8) & 0xff; 1087 /* Fall through */ 1088 case 1: 1089 payload[0] = reg & 0xff; 1090 } 1091 } 1092 1093 if (xfer->rx_done == xfer->rx_len) 1094 xfer->result = 0; 1095 1096 clear_fifo: 1097 length = DSI_RX_FIFO_SIZE / 4; 1098 do { 1099 reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 1100 if (reg == DSI_RX_FIFO_EMPTY) 1101 break; 1102 } while (--length); 1103 } 1104 1105 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 1106 { 1107 unsigned long flags; 1108 struct exynos_dsi_transfer *xfer; 1109 bool start = false; 1110 1111 again: 1112 spin_lock_irqsave(&dsi->transfer_lock, flags); 1113 1114 if (list_empty(&dsi->transfer_list)) { 1115 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1116 return; 1117 } 1118 1119 xfer = list_first_entry(&dsi->transfer_list, 1120 struct exynos_dsi_transfer, list); 1121 1122 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1123 1124 if (xfer->packet.payload_length && 1125 xfer->tx_done == xfer->packet.payload_length) 1126 /* waiting for RX */ 1127 return; 1128 1129 exynos_dsi_send_to_fifo(dsi, xfer); 1130 1131 if (xfer->packet.payload_length || xfer->rx_len) 1132 return; 1133 1134 xfer->result = 0; 1135 complete(&xfer->completed); 1136 1137 spin_lock_irqsave(&dsi->transfer_lock, flags); 1138 1139 list_del_init(&xfer->list); 1140 start = !list_empty(&dsi->transfer_list); 1141 1142 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1143 1144 if (start) 1145 goto again; 1146 } 1147 1148 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 1149 { 1150 struct exynos_dsi_transfer *xfer; 1151 unsigned long flags; 1152 bool start = true; 1153 1154 spin_lock_irqsave(&dsi->transfer_lock, flags); 1155 1156 if (list_empty(&dsi->transfer_list)) { 1157 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1158 return false; 1159 } 1160 1161 xfer = list_first_entry(&dsi->transfer_list, 1162 struct exynos_dsi_transfer, list); 1163 1164 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1165 1166 dev_dbg(dsi->dev, 1167 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1168 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1169 xfer->rx_done); 1170 1171 if (xfer->tx_done != xfer->packet.payload_length) 1172 return true; 1173 1174 if (xfer->rx_done != xfer->rx_len) 1175 exynos_dsi_read_from_fifo(dsi, xfer); 1176 1177 if (xfer->rx_done != xfer->rx_len) 1178 return true; 1179 1180 spin_lock_irqsave(&dsi->transfer_lock, flags); 1181 1182 list_del_init(&xfer->list); 1183 start = !list_empty(&dsi->transfer_list); 1184 1185 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1186 1187 if (!xfer->rx_len) 1188 xfer->result = 0; 1189 complete(&xfer->completed); 1190 1191 return start; 1192 } 1193 1194 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 1195 struct exynos_dsi_transfer *xfer) 1196 { 1197 unsigned long flags; 1198 bool start; 1199 1200 spin_lock_irqsave(&dsi->transfer_lock, flags); 1201 1202 if (!list_empty(&dsi->transfer_list) && 1203 xfer == list_first_entry(&dsi->transfer_list, 1204 struct exynos_dsi_transfer, list)) { 1205 list_del_init(&xfer->list); 1206 start = !list_empty(&dsi->transfer_list); 1207 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1208 if (start) 1209 exynos_dsi_transfer_start(dsi); 1210 return; 1211 } 1212 1213 list_del_init(&xfer->list); 1214 1215 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1216 } 1217 1218 static int exynos_dsi_transfer(struct exynos_dsi *dsi, 1219 struct exynos_dsi_transfer *xfer) 1220 { 1221 unsigned long flags; 1222 bool stopped; 1223 1224 xfer->tx_done = 0; 1225 xfer->rx_done = 0; 1226 xfer->result = -ETIMEDOUT; 1227 init_completion(&xfer->completed); 1228 1229 spin_lock_irqsave(&dsi->transfer_lock, flags); 1230 1231 stopped = list_empty(&dsi->transfer_list); 1232 list_add_tail(&xfer->list, &dsi->transfer_list); 1233 1234 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1235 1236 if (stopped) 1237 exynos_dsi_transfer_start(dsi); 1238 1239 wait_for_completion_timeout(&xfer->completed, 1240 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1241 if (xfer->result == -ETIMEDOUT) { 1242 struct mipi_dsi_packet *pkt = &xfer->packet; 1243 exynos_dsi_remove_transfer(dsi, xfer); 1244 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1245 (int)pkt->payload_length, pkt->payload); 1246 return -ETIMEDOUT; 1247 } 1248 1249 /* Also covers hardware timeout condition */ 1250 return xfer->result; 1251 } 1252 1253 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 1254 { 1255 struct exynos_dsi *dsi = dev_id; 1256 u32 status; 1257 1258 status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 1259 if (!status) { 1260 static unsigned long int j; 1261 if (printk_timed_ratelimit(&j, 500)) 1262 dev_warn(dsi->dev, "spurious interrupt\n"); 1263 return IRQ_HANDLED; 1264 } 1265 exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 1266 1267 if (status & DSIM_INT_SW_RST_RELEASE) { 1268 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1269 DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | 1270 DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); 1271 exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 1272 complete(&dsi->completed); 1273 return IRQ_HANDLED; 1274 } 1275 1276 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1277 DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) 1278 return IRQ_HANDLED; 1279 1280 if (exynos_dsi_transfer_finish(dsi)) 1281 exynos_dsi_transfer_start(dsi); 1282 1283 return IRQ_HANDLED; 1284 } 1285 1286 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1287 { 1288 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 1289 struct drm_encoder *encoder = &dsi->encoder; 1290 1291 if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1292 exynos_drm_crtc_te_handler(encoder->crtc); 1293 1294 return IRQ_HANDLED; 1295 } 1296 1297 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1298 { 1299 enable_irq(dsi->irq); 1300 1301 if (gpio_is_valid(dsi->te_gpio)) 1302 enable_irq(gpio_to_irq(dsi->te_gpio)); 1303 } 1304 1305 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1306 { 1307 if (gpio_is_valid(dsi->te_gpio)) 1308 disable_irq(gpio_to_irq(dsi->te_gpio)); 1309 1310 disable_irq(dsi->irq); 1311 } 1312 1313 static int exynos_dsi_init(struct exynos_dsi *dsi) 1314 { 1315 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1316 1317 exynos_dsi_reset(dsi); 1318 exynos_dsi_enable_irq(dsi); 1319 1320 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1321 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1322 1323 exynos_dsi_enable_clock(dsi); 1324 if (driver_data->wait_for_reset) 1325 exynos_dsi_wait_for_reset(dsi); 1326 exynos_dsi_set_phy_ctrl(dsi); 1327 exynos_dsi_init_link(dsi); 1328 1329 return 0; 1330 } 1331 1332 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1333 { 1334 int ret; 1335 int te_gpio_irq; 1336 1337 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 1338 if (dsi->te_gpio == -ENOENT) 1339 return 0; 1340 1341 if (!gpio_is_valid(dsi->te_gpio)) { 1342 ret = dsi->te_gpio; 1343 dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret); 1344 goto out; 1345 } 1346 1347 ret = gpio_request(dsi->te_gpio, "te_gpio"); 1348 if (ret) { 1349 dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1350 goto out; 1351 } 1352 1353 te_gpio_irq = gpio_to_irq(dsi->te_gpio); 1354 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 1355 1356 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1357 IRQF_TRIGGER_RISING, "TE", dsi); 1358 if (ret) { 1359 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1360 gpio_free(dsi->te_gpio); 1361 goto out; 1362 } 1363 1364 out: 1365 return ret; 1366 } 1367 1368 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1369 { 1370 if (gpio_is_valid(dsi->te_gpio)) { 1371 free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1372 gpio_free(dsi->te_gpio); 1373 dsi->te_gpio = -ENOENT; 1374 } 1375 } 1376 1377 static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1378 struct mipi_dsi_device *device) 1379 { 1380 struct exynos_dsi *dsi = host_to_dsi(host); 1381 1382 dsi->lanes = device->lanes; 1383 dsi->format = device->format; 1384 dsi->mode_flags = device->mode_flags; 1385 dsi->panel_node = device->dev.of_node; 1386 1387 /* 1388 * This is a temporary solution and should be made by more generic way. 1389 * 1390 * If attached panel device is for command mode one, dsi should register 1391 * TE interrupt handler. 1392 */ 1393 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1394 int ret = exynos_dsi_register_te_irq(dsi); 1395 1396 if (ret) 1397 return ret; 1398 } 1399 1400 if (dsi->connector.dev) 1401 drm_helper_hpd_irq_event(dsi->connector.dev); 1402 1403 return 0; 1404 } 1405 1406 static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1407 struct mipi_dsi_device *device) 1408 { 1409 struct exynos_dsi *dsi = host_to_dsi(host); 1410 1411 exynos_dsi_unregister_te_irq(dsi); 1412 1413 dsi->panel_node = NULL; 1414 1415 if (dsi->connector.dev) 1416 drm_helper_hpd_irq_event(dsi->connector.dev); 1417 1418 return 0; 1419 } 1420 1421 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1422 const struct mipi_dsi_msg *msg) 1423 { 1424 struct exynos_dsi *dsi = host_to_dsi(host); 1425 struct exynos_dsi_transfer xfer; 1426 int ret; 1427 1428 if (!(dsi->state & DSIM_STATE_ENABLED)) 1429 return -EINVAL; 1430 1431 if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1432 ret = exynos_dsi_init(dsi); 1433 if (ret) 1434 return ret; 1435 dsi->state |= DSIM_STATE_INITIALIZED; 1436 } 1437 1438 ret = mipi_dsi_create_packet(&xfer.packet, msg); 1439 if (ret < 0) 1440 return ret; 1441 1442 xfer.rx_len = msg->rx_len; 1443 xfer.rx_payload = msg->rx_buf; 1444 xfer.flags = msg->flags; 1445 1446 ret = exynos_dsi_transfer(dsi, &xfer); 1447 return (ret < 0) ? ret : xfer.rx_done; 1448 } 1449 1450 static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1451 .attach = exynos_dsi_host_attach, 1452 .detach = exynos_dsi_host_detach, 1453 .transfer = exynos_dsi_host_transfer, 1454 }; 1455 1456 static void exynos_dsi_enable(struct drm_encoder *encoder) 1457 { 1458 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1459 int ret; 1460 1461 if (dsi->state & DSIM_STATE_ENABLED) 1462 return; 1463 1464 pm_runtime_get_sync(dsi->dev); 1465 1466 dsi->state |= DSIM_STATE_ENABLED; 1467 1468 ret = drm_panel_prepare(dsi->panel); 1469 if (ret < 0) { 1470 dsi->state &= ~DSIM_STATE_ENABLED; 1471 pm_runtime_put_sync(dsi->dev); 1472 return; 1473 } 1474 1475 exynos_dsi_set_display_mode(dsi); 1476 exynos_dsi_set_display_enable(dsi, true); 1477 1478 ret = drm_panel_enable(dsi->panel); 1479 if (ret < 0) { 1480 dsi->state &= ~DSIM_STATE_ENABLED; 1481 exynos_dsi_set_display_enable(dsi, false); 1482 drm_panel_unprepare(dsi->panel); 1483 pm_runtime_put_sync(dsi->dev); 1484 return; 1485 } 1486 1487 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1488 } 1489 1490 static void exynos_dsi_disable(struct drm_encoder *encoder) 1491 { 1492 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1493 1494 if (!(dsi->state & DSIM_STATE_ENABLED)) 1495 return; 1496 1497 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1498 1499 drm_panel_disable(dsi->panel); 1500 exynos_dsi_set_display_enable(dsi, false); 1501 drm_panel_unprepare(dsi->panel); 1502 1503 dsi->state &= ~DSIM_STATE_ENABLED; 1504 1505 pm_runtime_put_sync(dsi->dev); 1506 } 1507 1508 static enum drm_connector_status 1509 exynos_dsi_detect(struct drm_connector *connector, bool force) 1510 { 1511 struct exynos_dsi *dsi = connector_to_dsi(connector); 1512 1513 if (!dsi->panel) { 1514 dsi->panel = of_drm_find_panel(dsi->panel_node); 1515 if (dsi->panel) 1516 drm_panel_attach(dsi->panel, &dsi->connector); 1517 } else if (!dsi->panel_node) { 1518 struct drm_encoder *encoder; 1519 1520 encoder = platform_get_drvdata(to_platform_device(dsi->dev)); 1521 exynos_dsi_disable(encoder); 1522 drm_panel_detach(dsi->panel); 1523 dsi->panel = NULL; 1524 } 1525 1526 if (dsi->panel) 1527 return connector_status_connected; 1528 1529 return connector_status_disconnected; 1530 } 1531 1532 static void exynos_dsi_connector_destroy(struct drm_connector *connector) 1533 { 1534 drm_connector_unregister(connector); 1535 drm_connector_cleanup(connector); 1536 connector->dev = NULL; 1537 } 1538 1539 static const struct drm_connector_funcs exynos_dsi_connector_funcs = { 1540 .dpms = drm_atomic_helper_connector_dpms, 1541 .detect = exynos_dsi_detect, 1542 .fill_modes = drm_helper_probe_single_connector_modes, 1543 .destroy = exynos_dsi_connector_destroy, 1544 .reset = drm_atomic_helper_connector_reset, 1545 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1546 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1547 }; 1548 1549 static int exynos_dsi_get_modes(struct drm_connector *connector) 1550 { 1551 struct exynos_dsi *dsi = connector_to_dsi(connector); 1552 1553 if (dsi->panel) 1554 return dsi->panel->funcs->get_modes(dsi->panel); 1555 1556 return 0; 1557 } 1558 1559 static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 1560 .get_modes = exynos_dsi_get_modes, 1561 }; 1562 1563 static int exynos_dsi_create_connector(struct drm_encoder *encoder) 1564 { 1565 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1566 struct drm_connector *connector = &dsi->connector; 1567 int ret; 1568 1569 connector->polled = DRM_CONNECTOR_POLL_HPD; 1570 1571 ret = drm_connector_init(encoder->dev, connector, 1572 &exynos_dsi_connector_funcs, 1573 DRM_MODE_CONNECTOR_DSI); 1574 if (ret) { 1575 DRM_ERROR("Failed to initialize connector with drm\n"); 1576 return ret; 1577 } 1578 1579 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 1580 drm_mode_connector_attach_encoder(connector, encoder); 1581 1582 return 0; 1583 } 1584 1585 static void exynos_dsi_mode_set(struct drm_encoder *encoder, 1586 struct drm_display_mode *mode, 1587 struct drm_display_mode *adjusted_mode) 1588 { 1589 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1590 struct videomode *vm = &dsi->vm; 1591 struct drm_display_mode *m = adjusted_mode; 1592 1593 vm->hactive = m->hdisplay; 1594 vm->vactive = m->vdisplay; 1595 vm->vfront_porch = m->vsync_start - m->vdisplay; 1596 vm->vback_porch = m->vtotal - m->vsync_end; 1597 vm->vsync_len = m->vsync_end - m->vsync_start; 1598 vm->hfront_porch = m->hsync_start - m->hdisplay; 1599 vm->hback_porch = m->htotal - m->hsync_end; 1600 vm->hsync_len = m->hsync_end - m->hsync_start; 1601 } 1602 1603 static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { 1604 .mode_set = exynos_dsi_mode_set, 1605 .enable = exynos_dsi_enable, 1606 .disable = exynos_dsi_disable, 1607 }; 1608 1609 static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { 1610 .destroy = drm_encoder_cleanup, 1611 }; 1612 1613 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 1614 1615 static int exynos_dsi_of_read_u32(const struct device_node *np, 1616 const char *propname, u32 *out_value) 1617 { 1618 int ret = of_property_read_u32(np, propname, out_value); 1619 1620 if (ret < 0) 1621 pr_err("%s: failed to get '%s' property\n", np->full_name, 1622 propname); 1623 1624 return ret; 1625 } 1626 1627 enum { 1628 DSI_PORT_IN, 1629 DSI_PORT_OUT 1630 }; 1631 1632 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 1633 { 1634 struct device *dev = dsi->dev; 1635 struct device_node *node = dev->of_node; 1636 int ret; 1637 1638 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 1639 &dsi->pll_clk_rate); 1640 if (ret < 0) 1641 return ret; 1642 1643 ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 1644 &dsi->burst_clk_rate); 1645 if (ret < 0) 1646 return ret; 1647 1648 ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 1649 &dsi->esc_clk_rate); 1650 if (ret < 0) 1651 return ret; 1652 1653 dsi->bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0); 1654 1655 return 0; 1656 } 1657 1658 static int exynos_dsi_bind(struct device *dev, struct device *master, 1659 void *data) 1660 { 1661 struct drm_encoder *encoder = dev_get_drvdata(dev); 1662 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1663 struct drm_device *drm_dev = data; 1664 struct drm_bridge *bridge; 1665 int ret; 1666 1667 ret = exynos_drm_crtc_get_pipe_from_type(drm_dev, 1668 EXYNOS_DISPLAY_TYPE_LCD); 1669 if (ret < 0) 1670 return ret; 1671 1672 encoder->possible_crtcs = 1 << ret; 1673 1674 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 1675 1676 drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, 1677 DRM_MODE_ENCODER_TMDS, NULL); 1678 1679 drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); 1680 1681 ret = exynos_dsi_create_connector(encoder); 1682 if (ret) { 1683 DRM_ERROR("failed to create connector ret = %d\n", ret); 1684 drm_encoder_cleanup(encoder); 1685 return ret; 1686 } 1687 1688 if (dsi->bridge_node) { 1689 bridge = of_drm_find_bridge(dsi->bridge_node); 1690 if (bridge) 1691 drm_bridge_attach(encoder, bridge, NULL); 1692 } 1693 1694 return mipi_dsi_host_register(&dsi->dsi_host); 1695 } 1696 1697 static void exynos_dsi_unbind(struct device *dev, struct device *master, 1698 void *data) 1699 { 1700 struct drm_encoder *encoder = dev_get_drvdata(dev); 1701 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1702 1703 exynos_dsi_disable(encoder); 1704 1705 mipi_dsi_host_unregister(&dsi->dsi_host); 1706 } 1707 1708 static const struct component_ops exynos_dsi_component_ops = { 1709 .bind = exynos_dsi_bind, 1710 .unbind = exynos_dsi_unbind, 1711 }; 1712 1713 static int exynos_dsi_probe(struct platform_device *pdev) 1714 { 1715 struct device *dev = &pdev->dev; 1716 struct resource *res; 1717 struct exynos_dsi *dsi; 1718 int ret, i; 1719 1720 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1721 if (!dsi) 1722 return -ENOMEM; 1723 1724 /* To be checked as invalid one */ 1725 dsi->te_gpio = -ENOENT; 1726 1727 init_completion(&dsi->completed); 1728 spin_lock_init(&dsi->transfer_lock); 1729 INIT_LIST_HEAD(&dsi->transfer_list); 1730 1731 dsi->dsi_host.ops = &exynos_dsi_ops; 1732 dsi->dsi_host.dev = dev; 1733 1734 dsi->dev = dev; 1735 dsi->driver_data = of_device_get_match_data(dev); 1736 1737 ret = exynos_dsi_parse_dt(dsi); 1738 if (ret) 1739 return ret; 1740 1741 dsi->supplies[0].supply = "vddcore"; 1742 dsi->supplies[1].supply = "vddio"; 1743 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1744 dsi->supplies); 1745 if (ret) { 1746 dev_info(dev, "failed to get regulators: %d\n", ret); 1747 return -EPROBE_DEFER; 1748 } 1749 1750 dsi->clks = devm_kzalloc(dev, 1751 sizeof(*dsi->clks) * dsi->driver_data->num_clks, 1752 GFP_KERNEL); 1753 if (!dsi->clks) 1754 return -ENOMEM; 1755 1756 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1757 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1758 if (IS_ERR(dsi->clks[i])) { 1759 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1760 strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 1761 i--; 1762 continue; 1763 } 1764 1765 dev_info(dev, "failed to get the clock: %s\n", 1766 clk_names[i]); 1767 return PTR_ERR(dsi->clks[i]); 1768 } 1769 } 1770 1771 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1772 dsi->reg_base = devm_ioremap_resource(dev, res); 1773 if (IS_ERR(dsi->reg_base)) { 1774 dev_err(dev, "failed to remap io region\n"); 1775 return PTR_ERR(dsi->reg_base); 1776 } 1777 1778 dsi->phy = devm_phy_get(dev, "dsim"); 1779 if (IS_ERR(dsi->phy)) { 1780 dev_info(dev, "failed to get dsim phy\n"); 1781 return PTR_ERR(dsi->phy); 1782 } 1783 1784 dsi->irq = platform_get_irq(pdev, 0); 1785 if (dsi->irq < 0) { 1786 dev_err(dev, "failed to request dsi irq resource\n"); 1787 return dsi->irq; 1788 } 1789 1790 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1791 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1792 exynos_dsi_irq, IRQF_ONESHOT, 1793 dev_name(dev), dsi); 1794 if (ret) { 1795 dev_err(dev, "failed to request dsi irq\n"); 1796 return ret; 1797 } 1798 1799 platform_set_drvdata(pdev, &dsi->encoder); 1800 1801 pm_runtime_enable(dev); 1802 1803 return component_add(dev, &exynos_dsi_component_ops); 1804 } 1805 1806 static int exynos_dsi_remove(struct platform_device *pdev) 1807 { 1808 struct exynos_dsi *dsi = platform_get_drvdata(pdev); 1809 1810 of_node_put(dsi->bridge_node); 1811 1812 pm_runtime_disable(&pdev->dev); 1813 1814 component_del(&pdev->dev, &exynos_dsi_component_ops); 1815 1816 return 0; 1817 } 1818 1819 static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1820 { 1821 struct drm_encoder *encoder = dev_get_drvdata(dev); 1822 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1823 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1824 int ret, i; 1825 1826 usleep_range(10000, 20000); 1827 1828 if (dsi->state & DSIM_STATE_INITIALIZED) { 1829 dsi->state &= ~DSIM_STATE_INITIALIZED; 1830 1831 exynos_dsi_disable_clock(dsi); 1832 1833 exynos_dsi_disable_irq(dsi); 1834 } 1835 1836 dsi->state &= ~DSIM_STATE_CMD_LPM; 1837 1838 phy_power_off(dsi->phy); 1839 1840 for (i = driver_data->num_clks - 1; i > -1; i--) 1841 clk_disable_unprepare(dsi->clks[i]); 1842 1843 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1844 if (ret < 0) 1845 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1846 1847 return 0; 1848 } 1849 1850 static int __maybe_unused exynos_dsi_resume(struct device *dev) 1851 { 1852 struct drm_encoder *encoder = dev_get_drvdata(dev); 1853 struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1854 const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1855 int ret, i; 1856 1857 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1858 if (ret < 0) { 1859 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1860 return ret; 1861 } 1862 1863 for (i = 0; i < driver_data->num_clks; i++) { 1864 ret = clk_prepare_enable(dsi->clks[i]); 1865 if (ret < 0) 1866 goto err_clk; 1867 } 1868 1869 ret = phy_power_on(dsi->phy); 1870 if (ret < 0) { 1871 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1872 goto err_clk; 1873 } 1874 1875 return 0; 1876 1877 err_clk: 1878 while (--i > -1) 1879 clk_disable_unprepare(dsi->clks[i]); 1880 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1881 1882 return ret; 1883 } 1884 1885 static const struct dev_pm_ops exynos_dsi_pm_ops = { 1886 SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 1887 }; 1888 1889 struct platform_driver dsi_driver = { 1890 .probe = exynos_dsi_probe, 1891 .remove = exynos_dsi_remove, 1892 .driver = { 1893 .name = "exynos-dsi", 1894 .owner = THIS_MODULE, 1895 .pm = &exynos_dsi_pm_ops, 1896 .of_match_table = exynos_dsi_of_match, 1897 }, 1898 }; 1899 1900 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 1901 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 1902 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 1903 MODULE_LICENSE("GPL v2"); 1904