17eb8f069SAndrzej Hajda /* 27eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 37eb8f069SAndrzej Hajda * 47eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 57eb8f069SAndrzej Hajda * 67eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 77eb8f069SAndrzej Hajda * 87eb8f069SAndrzej Hajda * This program is free software; you can redistribute it and/or modify 97eb8f069SAndrzej Hajda * it under the terms of the GNU General Public License version 2 as 107eb8f069SAndrzej Hajda * published by the Free Software Foundation. 117eb8f069SAndrzej Hajda */ 127eb8f069SAndrzej Hajda 137eb8f069SAndrzej Hajda #include <drm/drmP.h> 147eb8f069SAndrzej Hajda #include <drm/drm_crtc_helper.h> 157eb8f069SAndrzej Hajda #include <drm/drm_mipi_dsi.h> 167eb8f069SAndrzej Hajda #include <drm/drm_panel.h> 174ea9526bSGustavo Padovan #include <drm/drm_atomic_helper.h> 187eb8f069SAndrzej Hajda 197eb8f069SAndrzej Hajda #include <linux/clk.h> 20e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 217eb8f069SAndrzej Hajda #include <linux/irq.h> 229a320415SYoungJun Cho #include <linux/of_device.h> 23e17ddeccSYoungJun Cho #include <linux/of_gpio.h> 24f5f3b9baSHyungwon Hwang #include <linux/of_graph.h> 257eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 267eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 27f37cd5e8SInki Dae #include <linux/component.h> 287eb8f069SAndrzej Hajda 297eb8f069SAndrzej Hajda #include <video/mipi_display.h> 307eb8f069SAndrzej Hajda #include <video/videomode.h> 317eb8f069SAndrzej Hajda 32e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 337eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 347eb8f069SAndrzej Hajda 357eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 367eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 377eb8f069SAndrzej Hajda 387eb8f069SAndrzej Hajda /* DSIM_STATUS */ 397eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 407eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 417eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 427eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 437eb8f069SAndrzej Hajda 447eb8f069SAndrzej Hajda /* DSIM_SWRST */ 457eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 467eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 477eb8f069SAndrzej Hajda 487eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 497eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 507eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 517eb8f069SAndrzej Hajda 527eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 537eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 547eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 557eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 567eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 587eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 597eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 617eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 627eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 637eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 647eb8f069SAndrzej Hajda 657eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 667eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 677eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 687eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 697eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 707eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 717eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 757eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 767eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 777eb8f069SAndrzej Hajda #define DSIM_HSA_MODE (1 << 20) 787eb8f069SAndrzej Hajda #define DSIM_HBP_MODE (1 << 21) 797eb8f069SAndrzej Hajda #define DSIM_HFP_MODE (1 << 22) 807eb8f069SAndrzej Hajda #define DSIM_HSE_MODE (1 << 23) 817eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 827eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 837eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 847eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 857eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 867eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 8778d3a8c6SInki Dae /* This flag is valid only for exynos3250/3472/4415/5260/5430 */ 8878d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 897eb8f069SAndrzej Hajda 907eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 917eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 927eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 937eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 947eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 957eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 967eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 977eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 987eb8f069SAndrzej Hajda 997eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 1007eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 101d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 102d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1037eb8f069SAndrzej Hajda 1047eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1057eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1067eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1077eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1087eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1097eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1107eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1117eb8f069SAndrzej Hajda 1127eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1137eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1147eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1157eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1167eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1177eb8f069SAndrzej Hajda 1187eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1197eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1207eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1217eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1227eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1237eb8f069SAndrzej Hajda 1247eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1257eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1267eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1277eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1287eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1297eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1307eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1317eb8f069SAndrzej Hajda 1327eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1337eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1347eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1357eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 136e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 1377eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1387eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1397eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1407eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1417eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1427eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1437eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1447eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1457eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1467eb8f069SAndrzej Hajda 1477eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1487eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1497eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1507eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1517eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1527eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1537eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1547eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1557eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1567eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1577eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1587eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1597eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1607eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1617eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1627eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1637eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1647eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1657eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1667eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1677eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1687eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1697eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1707eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1717eb8f069SAndrzej Hajda 1727eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1737eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1747eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1757eb8f069SAndrzej Hajda 1767eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1777eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1787eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 1797eb8f069SAndrzej Hajda #define DSIM_PLL_P(x) ((x) << 13) 1807eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1817eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 1827eb8f069SAndrzej Hajda 1839a320415SYoungJun Cho /* DSIM_PHYCTRL */ 1849a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 185e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 186e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 1879a320415SYoungJun Cho 1889a320415SYoungJun Cho /* DSIM_PHYTIMING */ 1899a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 1909a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 1919a320415SYoungJun Cho 1929a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 1939a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 1949a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 1959a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 1969a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 1979a320415SYoungJun Cho 1989a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 1999a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 2009a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 2019a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 2029a320415SYoungJun Cho 2037eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2047eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2057eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2067eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2077eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2087eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2097eb8f069SAndrzej Hajda 21026269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 21126269af9SHyungwon Hwang 212d668e8bfSHyungwon Hwang #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \ 213d668e8bfSHyungwon Hwang dsi->driver_data->reg_ofs[(reg_idx)]) 214d668e8bfSHyungwon Hwang #define DSI_WRITE(dsi, reg_idx, val) writel((val), \ 215d668e8bfSHyungwon Hwang REG_ADDR((dsi), (reg_idx))) 216d668e8bfSHyungwon Hwang #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) 217ba12ac2bSHyungwon Hwang 218e6f988a4SHyungwon Hwang static char *clk_names[5] = { "bus_clk", "sclk_mipi", 219e6f988a4SHyungwon Hwang "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 220e6f988a4SHyungwon Hwang "sclk_rgb_vclk_to_dsim0" }; 2210ff03fd1SHyungwon Hwang 2227eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2237eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2247eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2257eb8f069SAndrzej Hajda }; 2267eb8f069SAndrzej Hajda 2277eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2287eb8f069SAndrzej Hajda struct list_head list; 2297eb8f069SAndrzej Hajda struct completion completed; 2307eb8f069SAndrzej Hajda int result; 2317eb8f069SAndrzej Hajda u8 data_id; 2327eb8f069SAndrzej Hajda u8 data[2]; 2337eb8f069SAndrzej Hajda u16 flags; 2347eb8f069SAndrzej Hajda 2357eb8f069SAndrzej Hajda const u8 *tx_payload; 2367eb8f069SAndrzej Hajda u16 tx_len; 2377eb8f069SAndrzej Hajda u16 tx_done; 2387eb8f069SAndrzej Hajda 2397eb8f069SAndrzej Hajda u8 *rx_payload; 2407eb8f069SAndrzej Hajda u16 rx_len; 2417eb8f069SAndrzej Hajda u16 rx_done; 2427eb8f069SAndrzej Hajda }; 2437eb8f069SAndrzej Hajda 2447eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2457eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2467eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2470e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2487eb8f069SAndrzej Hajda 2499a320415SYoungJun Cho struct exynos_dsi_driver_data { 250d668e8bfSHyungwon Hwang unsigned int *reg_ofs; 2519a320415SYoungJun Cho unsigned int plltmr_reg; 2529a320415SYoungJun Cho unsigned int has_freqband:1; 25378d3a8c6SInki Dae unsigned int has_clklane_stop:1; 254d668e8bfSHyungwon Hwang unsigned int num_clks; 255d668e8bfSHyungwon Hwang unsigned int max_freq; 256d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 257d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 258d668e8bfSHyungwon Hwang unsigned int *reg_values; 2599a320415SYoungJun Cho }; 2609a320415SYoungJun Cho 2617eb8f069SAndrzej Hajda struct exynos_dsi { 2622b8376c8SGustavo Padovan struct drm_encoder encoder; 2637eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 2647eb8f069SAndrzej Hajda struct drm_connector connector; 2657eb8f069SAndrzej Hajda struct device_node *panel_node; 2667eb8f069SAndrzej Hajda struct drm_panel *panel; 2677eb8f069SAndrzej Hajda struct device *dev; 2687eb8f069SAndrzej Hajda 2697eb8f069SAndrzej Hajda void __iomem *reg_base; 2707eb8f069SAndrzej Hajda struct phy *phy; 2710ff03fd1SHyungwon Hwang struct clk **clks; 2727eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2737eb8f069SAndrzej Hajda int irq; 274e17ddeccSYoungJun Cho int te_gpio; 2757eb8f069SAndrzej Hajda 2767eb8f069SAndrzej Hajda u32 pll_clk_rate; 2777eb8f069SAndrzej Hajda u32 burst_clk_rate; 2787eb8f069SAndrzej Hajda u32 esc_clk_rate; 2797eb8f069SAndrzej Hajda u32 lanes; 2807eb8f069SAndrzej Hajda u32 mode_flags; 2817eb8f069SAndrzej Hajda u32 format; 2827eb8f069SAndrzej Hajda struct videomode vm; 2837eb8f069SAndrzej Hajda 2847eb8f069SAndrzej Hajda int state; 2857eb8f069SAndrzej Hajda struct drm_property *brightness; 2867eb8f069SAndrzej Hajda struct completion completed; 2877eb8f069SAndrzej Hajda 2887eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 2897eb8f069SAndrzej Hajda struct list_head transfer_list; 2909a320415SYoungJun Cho 2919a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data; 292f5f3b9baSHyungwon Hwang struct device_node *bridge_node; 2937eb8f069SAndrzej Hajda }; 2947eb8f069SAndrzej Hajda 2957eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 2967eb8f069SAndrzej Hajda #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 2977eb8f069SAndrzej Hajda 2982b8376c8SGustavo Padovan static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) 2995cd5db80SAndrzej Hajda { 300cf67cc9aSGustavo Padovan return container_of(e, struct exynos_dsi, encoder); 3015cd5db80SAndrzej Hajda } 3025cd5db80SAndrzej Hajda 303d668e8bfSHyungwon Hwang enum reg_idx { 304d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 305d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 306d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 307d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 308d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 309d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 310d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 311d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 312d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 313d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 314d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 315d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 316d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 317d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 318d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 319d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 320d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 321d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 322d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 323d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 324d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 325d668e8bfSHyungwon Hwang NUM_REGS 326d668e8bfSHyungwon Hwang }; 327d668e8bfSHyungwon Hwang static unsigned int exynos_reg_ofs[] = { 328d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 329d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 330d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 331d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 332d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 333d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 334d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 335d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 336d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 337d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 338d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 339d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 340d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 341d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 342d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 343d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 344d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 345d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 346d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 347d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 348d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 349d668e8bfSHyungwon Hwang }; 350d668e8bfSHyungwon Hwang 351e6f988a4SHyungwon Hwang static unsigned int exynos5433_reg_ofs[] = { 352e6f988a4SHyungwon Hwang [DSIM_STATUS_REG] = 0x04, 353e6f988a4SHyungwon Hwang [DSIM_SWRST_REG] = 0x0C, 354e6f988a4SHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x10, 355e6f988a4SHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x14, 356e6f988a4SHyungwon Hwang [DSIM_CONFIG_REG] = 0x18, 357e6f988a4SHyungwon Hwang [DSIM_ESCMODE_REG] = 0x1C, 358e6f988a4SHyungwon Hwang [DSIM_MDRESOL_REG] = 0x20, 359e6f988a4SHyungwon Hwang [DSIM_MVPORCH_REG] = 0x24, 360e6f988a4SHyungwon Hwang [DSIM_MHPORCH_REG] = 0x28, 361e6f988a4SHyungwon Hwang [DSIM_MSYNC_REG] = 0x2C, 362e6f988a4SHyungwon Hwang [DSIM_INTSRC_REG] = 0x34, 363e6f988a4SHyungwon Hwang [DSIM_INTMSK_REG] = 0x38, 364e6f988a4SHyungwon Hwang [DSIM_PKTHDR_REG] = 0x3C, 365e6f988a4SHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x40, 366e6f988a4SHyungwon Hwang [DSIM_RXFIFO_REG] = 0x44, 367e6f988a4SHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x4C, 368e6f988a4SHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x94, 369e6f988a4SHyungwon Hwang [DSIM_PHYCTRL_REG] = 0xA4, 370e6f988a4SHyungwon Hwang [DSIM_PHYTIMING_REG] = 0xB4, 371e6f988a4SHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0xB8, 372e6f988a4SHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0xBC, 373e6f988a4SHyungwon Hwang }; 374e6f988a4SHyungwon Hwang 375d668e8bfSHyungwon Hwang enum reg_value_idx { 376d668e8bfSHyungwon Hwang RESET_TYPE, 377d668e8bfSHyungwon Hwang PLL_TIMER, 378d668e8bfSHyungwon Hwang STOP_STATE_CNT, 379d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 380d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 381d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 382d668e8bfSHyungwon Hwang PHYTIMING_LPX, 383d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 384d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 385d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 386d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 387d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 388d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 389d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 390d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 391d668e8bfSHyungwon Hwang }; 392d668e8bfSHyungwon Hwang 393d668e8bfSHyungwon Hwang static unsigned int reg_values[] = { 394d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 395d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 396d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 397d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 398d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 399d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 400d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 401d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 402d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 403d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 404d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 405d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 406d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 407d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 408d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 409d668e8bfSHyungwon Hwang }; 410d668e8bfSHyungwon Hwang 411fdc2e108SChanho Park static unsigned int exynos5422_reg_values[] = { 412fdc2e108SChanho Park [RESET_TYPE] = DSIM_SWRST, 413fdc2e108SChanho Park [PLL_TIMER] = 500, 414fdc2e108SChanho Park [STOP_STATE_CNT] = 0xf, 415fdc2e108SChanho Park [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 416fdc2e108SChanho Park [PHYCTRL_VREG_LP] = 0, 417fdc2e108SChanho Park [PHYCTRL_SLEW_UP] = 0, 418fdc2e108SChanho Park [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 419fdc2e108SChanho Park [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 420fdc2e108SChanho Park [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 421fdc2e108SChanho Park [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 422fdc2e108SChanho Park [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 423fdc2e108SChanho Park [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 424fdc2e108SChanho Park [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 425fdc2e108SChanho Park [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 426fdc2e108SChanho Park [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 427fdc2e108SChanho Park }; 428fdc2e108SChanho Park 429e6f988a4SHyungwon Hwang static unsigned int exynos5433_reg_values[] = { 430e6f988a4SHyungwon Hwang [RESET_TYPE] = DSIM_FUNCRST, 431e6f988a4SHyungwon Hwang [PLL_TIMER] = 22200, 432e6f988a4SHyungwon Hwang [STOP_STATE_CNT] = 0xa, 433e6f988a4SHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 434e6f988a4SHyungwon Hwang [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 435e6f988a4SHyungwon Hwang [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 436e6f988a4SHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 437e6f988a4SHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 438e6f988a4SHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 439e6f988a4SHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 440e6f988a4SHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 441e6f988a4SHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 442e6f988a4SHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 443e6f988a4SHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 444e6f988a4SHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 445e6f988a4SHyungwon Hwang }; 446e6f988a4SHyungwon Hwang 447473462a1SInki Dae static struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 448d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 449473462a1SInki Dae .plltmr_reg = 0x50, 450473462a1SInki Dae .has_freqband = 1, 451473462a1SInki Dae .has_clklane_stop = 1, 452d668e8bfSHyungwon Hwang .num_clks = 2, 453d668e8bfSHyungwon Hwang .max_freq = 1000, 454d668e8bfSHyungwon Hwang .wait_for_reset = 1, 455d668e8bfSHyungwon Hwang .num_bits_resol = 11, 456d668e8bfSHyungwon Hwang .reg_values = reg_values, 457473462a1SInki Dae }; 458473462a1SInki Dae 4599a320415SYoungJun Cho static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 460d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4619a320415SYoungJun Cho .plltmr_reg = 0x50, 4629a320415SYoungJun Cho .has_freqband = 1, 46378d3a8c6SInki Dae .has_clklane_stop = 1, 464d668e8bfSHyungwon Hwang .num_clks = 2, 465d668e8bfSHyungwon Hwang .max_freq = 1000, 466d668e8bfSHyungwon Hwang .wait_for_reset = 1, 467d668e8bfSHyungwon Hwang .num_bits_resol = 11, 468d668e8bfSHyungwon Hwang .reg_values = reg_values, 4699a320415SYoungJun Cho }; 4709a320415SYoungJun Cho 4714bc6d644SYoungJun Cho static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = { 472d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4734bc6d644SYoungJun Cho .plltmr_reg = 0x58, 4744bc6d644SYoungJun Cho .has_clklane_stop = 1, 475d668e8bfSHyungwon Hwang .num_clks = 2, 476d668e8bfSHyungwon Hwang .max_freq = 1000, 477d668e8bfSHyungwon Hwang .wait_for_reset = 1, 478d668e8bfSHyungwon Hwang .num_bits_resol = 11, 479d668e8bfSHyungwon Hwang .reg_values = reg_values, 4804bc6d644SYoungJun Cho }; 4814bc6d644SYoungJun Cho 4829a320415SYoungJun Cho static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 483d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4849a320415SYoungJun Cho .plltmr_reg = 0x58, 485d668e8bfSHyungwon Hwang .num_clks = 2, 486d668e8bfSHyungwon Hwang .max_freq = 1000, 487d668e8bfSHyungwon Hwang .wait_for_reset = 1, 488d668e8bfSHyungwon Hwang .num_bits_resol = 11, 489d668e8bfSHyungwon Hwang .reg_values = reg_values, 4909a320415SYoungJun Cho }; 4919a320415SYoungJun Cho 492e6f988a4SHyungwon Hwang static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 493e6f988a4SHyungwon Hwang .reg_ofs = exynos5433_reg_ofs, 494e6f988a4SHyungwon Hwang .plltmr_reg = 0xa0, 495e6f988a4SHyungwon Hwang .has_clklane_stop = 1, 496e6f988a4SHyungwon Hwang .num_clks = 5, 497e6f988a4SHyungwon Hwang .max_freq = 1500, 498e6f988a4SHyungwon Hwang .wait_for_reset = 0, 499e6f988a4SHyungwon Hwang .num_bits_resol = 12, 500e6f988a4SHyungwon Hwang .reg_values = exynos5433_reg_values, 501e6f988a4SHyungwon Hwang }; 502e6f988a4SHyungwon Hwang 503fdc2e108SChanho Park static struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 504fdc2e108SChanho Park .reg_ofs = exynos5433_reg_ofs, 505fdc2e108SChanho Park .plltmr_reg = 0xa0, 506fdc2e108SChanho Park .has_clklane_stop = 1, 507fdc2e108SChanho Park .num_clks = 2, 508fdc2e108SChanho Park .max_freq = 1500, 509fdc2e108SChanho Park .wait_for_reset = 1, 510fdc2e108SChanho Park .num_bits_resol = 12, 511fdc2e108SChanho Park .reg_values = exynos5422_reg_values, 512fdc2e108SChanho Park }; 513fdc2e108SChanho Park 5149a320415SYoungJun Cho static struct of_device_id exynos_dsi_of_match[] = { 515473462a1SInki Dae { .compatible = "samsung,exynos3250-mipi-dsi", 516473462a1SInki Dae .data = &exynos3_dsi_driver_data }, 5179a320415SYoungJun Cho { .compatible = "samsung,exynos4210-mipi-dsi", 5189a320415SYoungJun Cho .data = &exynos4_dsi_driver_data }, 5194bc6d644SYoungJun Cho { .compatible = "samsung,exynos4415-mipi-dsi", 5204bc6d644SYoungJun Cho .data = &exynos4415_dsi_driver_data }, 5219a320415SYoungJun Cho { .compatible = "samsung,exynos5410-mipi-dsi", 5229a320415SYoungJun Cho .data = &exynos5_dsi_driver_data }, 523fdc2e108SChanho Park { .compatible = "samsung,exynos5422-mipi-dsi", 524fdc2e108SChanho Park .data = &exynos5422_dsi_driver_data }, 525e6f988a4SHyungwon Hwang { .compatible = "samsung,exynos5433-mipi-dsi", 526e6f988a4SHyungwon Hwang .data = &exynos5433_dsi_driver_data }, 5279a320415SYoungJun Cho { } 5289a320415SYoungJun Cho }; 5299a320415SYoungJun Cho 5309a320415SYoungJun Cho static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( 5319a320415SYoungJun Cho struct platform_device *pdev) 5329a320415SYoungJun Cho { 5339a320415SYoungJun Cho const struct of_device_id *of_id = 5349a320415SYoungJun Cho of_match_device(exynos_dsi_of_match, &pdev->dev); 5359a320415SYoungJun Cho 5369a320415SYoungJun Cho return (struct exynos_dsi_driver_data *)of_id->data; 5379a320415SYoungJun Cho } 5389a320415SYoungJun Cho 5397eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 5407eb8f069SAndrzej Hajda { 5417eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 5427eb8f069SAndrzej Hajda return; 5437eb8f069SAndrzej Hajda 5447eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 5457eb8f069SAndrzej Hajda } 5467eb8f069SAndrzej Hajda 5477eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 5487eb8f069SAndrzej Hajda { 549ba12ac2bSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 550ba12ac2bSHyungwon Hwang 5517eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 552d668e8bfSHyungwon Hwang DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); 5537eb8f069SAndrzej Hajda } 5547eb8f069SAndrzej Hajda 5557eb8f069SAndrzej Hajda #ifndef MHZ 5567eb8f069SAndrzej Hajda #define MHZ (1000*1000) 5577eb8f069SAndrzej Hajda #endif 5587eb8f069SAndrzej Hajda 5597eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 5607eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 5617eb8f069SAndrzej Hajda { 562ba12ac2bSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5637eb8f069SAndrzej Hajda unsigned long best_freq = 0; 5647eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 5657eb8f069SAndrzej Hajda u8 p_min, p_max; 5667eb8f069SAndrzej Hajda u8 _p, uninitialized_var(best_p); 5677eb8f069SAndrzej Hajda u16 _m, uninitialized_var(best_m); 5687eb8f069SAndrzej Hajda u8 _s, uninitialized_var(best_s); 5697eb8f069SAndrzej Hajda 5707eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 5717eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 5727eb8f069SAndrzej Hajda 5737eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 5747eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 5757eb8f069SAndrzej Hajda u64 tmp; 5767eb8f069SAndrzej Hajda u32 delta; 5777eb8f069SAndrzej Hajda 5787eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 5797eb8f069SAndrzej Hajda do_div(tmp, fin); 5807eb8f069SAndrzej Hajda _m = tmp; 5817eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 5827eb8f069SAndrzej Hajda continue; 5837eb8f069SAndrzej Hajda 5847eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5857eb8f069SAndrzej Hajda do_div(tmp, _p); 586d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 587d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 5887eb8f069SAndrzej Hajda continue; 5897eb8f069SAndrzej Hajda 5907eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5917eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 5927eb8f069SAndrzej Hajda 5937eb8f069SAndrzej Hajda delta = abs(fout - tmp); 5947eb8f069SAndrzej Hajda if (delta < min_delta) { 5957eb8f069SAndrzej Hajda best_p = _p; 5967eb8f069SAndrzej Hajda best_m = _m; 5977eb8f069SAndrzej Hajda best_s = _s; 5987eb8f069SAndrzej Hajda min_delta = delta; 5997eb8f069SAndrzej Hajda best_freq = tmp; 6007eb8f069SAndrzej Hajda } 6017eb8f069SAndrzej Hajda } 6027eb8f069SAndrzej Hajda } 6037eb8f069SAndrzej Hajda 6047eb8f069SAndrzej Hajda if (best_freq) { 6057eb8f069SAndrzej Hajda *p = best_p; 6067eb8f069SAndrzej Hajda *m = best_m; 6077eb8f069SAndrzej Hajda *s = best_s; 6087eb8f069SAndrzej Hajda } 6097eb8f069SAndrzej Hajda 6107eb8f069SAndrzej Hajda return best_freq; 6117eb8f069SAndrzej Hajda } 6127eb8f069SAndrzej Hajda 6137eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 6147eb8f069SAndrzej Hajda unsigned long freq) 6157eb8f069SAndrzej Hajda { 6169a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 6177eb8f069SAndrzej Hajda unsigned long fin, fout; 6189a320415SYoungJun Cho int timeout; 6197eb8f069SAndrzej Hajda u8 p, s; 6207eb8f069SAndrzej Hajda u16 m; 6217eb8f069SAndrzej Hajda u32 reg; 6227eb8f069SAndrzej Hajda 62326269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 6247eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 6257eb8f069SAndrzej Hajda if (!fout) { 6267eb8f069SAndrzej Hajda dev_err(dsi->dev, 6277eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 6288525b5ecSYoungJun Cho return 0; 6297eb8f069SAndrzej Hajda } 6309a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 6319a320415SYoungJun Cho 632d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 633d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 6349a320415SYoungJun Cho 6359a320415SYoungJun Cho reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 6369a320415SYoungJun Cho 6379a320415SYoungJun Cho if (driver_data->has_freqband) { 6389a320415SYoungJun Cho static const unsigned long freq_bands[] = { 6399a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 6409a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 6419a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 6429a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 6439a320415SYoungJun Cho }; 6449a320415SYoungJun Cho int band; 6457eb8f069SAndrzej Hajda 6467eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 6477eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 6487eb8f069SAndrzej Hajda break; 6497eb8f069SAndrzej Hajda 6509a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 6517eb8f069SAndrzej Hajda 6529a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 6539a320415SYoungJun Cho } 6547eb8f069SAndrzej Hajda 655ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 6567eb8f069SAndrzej Hajda 6577eb8f069SAndrzej Hajda timeout = 1000; 6587eb8f069SAndrzej Hajda do { 6597eb8f069SAndrzej Hajda if (timeout-- == 0) { 6607eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 6618525b5ecSYoungJun Cho return 0; 6627eb8f069SAndrzej Hajda } 663ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_STATUS_REG); 6647eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 6657eb8f069SAndrzej Hajda 6667eb8f069SAndrzej Hajda return fout; 6677eb8f069SAndrzej Hajda } 6687eb8f069SAndrzej Hajda 6697eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 6707eb8f069SAndrzej Hajda { 6717eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 6727eb8f069SAndrzej Hajda unsigned long esc_div; 6737eb8f069SAndrzej Hajda u32 reg; 6747eb8f069SAndrzej Hajda 6757eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 6767eb8f069SAndrzej Hajda if (!hs_clk) { 6777eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 6787eb8f069SAndrzej Hajda return -EFAULT; 6797eb8f069SAndrzej Hajda } 6807eb8f069SAndrzej Hajda 6817eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 6827eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 6837eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6847eb8f069SAndrzej Hajda 6857eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 6867eb8f069SAndrzej Hajda ++esc_div; 6877eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6887eb8f069SAndrzej Hajda } 6897eb8f069SAndrzej Hajda 6907eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 6917eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 6927eb8f069SAndrzej Hajda 693ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 6947eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 6957eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 6967eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 6977eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 6987eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 6997eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 7007eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 7017eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 7027eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 703ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 7047eb8f069SAndrzej Hajda 7057eb8f069SAndrzej Hajda return 0; 7067eb8f069SAndrzej Hajda } 7077eb8f069SAndrzej Hajda 7089a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 7099a320415SYoungJun Cho { 7109a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 711d668e8bfSHyungwon Hwang unsigned int *reg_values = driver_data->reg_values; 7129a320415SYoungJun Cho u32 reg; 7139a320415SYoungJun Cho 7149a320415SYoungJun Cho if (driver_data->has_freqband) 7159a320415SYoungJun Cho return; 7169a320415SYoungJun Cho 7179a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 718d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 719d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 720ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg); 7219a320415SYoungJun Cho 7229a320415SYoungJun Cho /* 7239a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 7249a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 7259a320415SYoungJun Cho * burst 7269a320415SYoungJun Cho */ 727d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 728ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg); 7299a320415SYoungJun Cho 7309a320415SYoungJun Cho /* 7319a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 7329a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7339a320415SYoungJun Cho * HS transmission 7349a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 7359a320415SYoungJun Cho * transmitting the Clock. 7369a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 7379a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 7389a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 7399a320415SYoungJun Cho * the beginning of T CLK-TRAIL 7409a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 7419a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 7429a320415SYoungJun Cho */ 743d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 744d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 745d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 746d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 747d668e8bfSHyungwon Hwang 748ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg); 7499a320415SYoungJun Cho 7509a320415SYoungJun Cho /* 7519a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 7529a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7539a320415SYoungJun Cho * HS transmission 7549a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 7559a320415SYoungJun Cho * transmitting the Sync sequence. 7569a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 7579a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 7589a320415SYoungJun Cho */ 759d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 760d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 761ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg); 7629a320415SYoungJun Cho } 7639a320415SYoungJun Cho 7647eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 7657eb8f069SAndrzej Hajda { 7667eb8f069SAndrzej Hajda u32 reg; 7677eb8f069SAndrzej Hajda 768ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 7697eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 7707eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 771ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 7727eb8f069SAndrzej Hajda 773ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_PLLCTRL_REG); 7747eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 775ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 7767eb8f069SAndrzej Hajda } 7777eb8f069SAndrzej Hajda 778e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 779e6f988a4SHyungwon Hwang { 780e6f988a4SHyungwon Hwang u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG); 781e6f988a4SHyungwon Hwang reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 782e6f988a4SHyungwon Hwang DSIM_LANE_EN(lane)); 783e6f988a4SHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 784e6f988a4SHyungwon Hwang } 785e6f988a4SHyungwon Hwang 7867eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 7877eb8f069SAndrzej Hajda { 78878d3a8c6SInki Dae struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 7897eb8f069SAndrzej Hajda int timeout; 7907eb8f069SAndrzej Hajda u32 reg; 7917eb8f069SAndrzej Hajda u32 lanes_mask; 7927eb8f069SAndrzej Hajda 7937eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 794ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 7957eb8f069SAndrzej Hajda reg &= ~0x1f; 796ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 7977eb8f069SAndrzej Hajda 7987eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7997eb8f069SAndrzej Hajda 8007eb8f069SAndrzej Hajda reg |= 0x1f; 801ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 8027eb8f069SAndrzej Hajda usleep_range(9000, 11000); 8037eb8f069SAndrzej Hajda 8047eb8f069SAndrzej Hajda /* DSI configuration */ 8057eb8f069SAndrzej Hajda reg = 0; 8067eb8f069SAndrzej Hajda 8072f36e33aSYoungJun Cho /* 8082f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 8092f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 8102f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 8112f36e33aSYoungJun Cho */ 8127eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8137eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 8147eb8f069SAndrzej Hajda 8152f36e33aSYoungJun Cho /* 8162f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 8172f36e33aSYoungJun Cho * command mode. 8182f36e33aSYoungJun Cho */ 8197eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 8207eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 8217eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 8227eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 8237eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 8247eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 8257eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 8267eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 8277eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 8287eb8f069SAndrzej Hajda reg |= DSIM_HSE_MODE; 8297eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 8307eb8f069SAndrzej Hajda reg |= DSIM_HFP_MODE; 8317eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 8327eb8f069SAndrzej Hajda reg |= DSIM_HBP_MODE; 8337eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 8347eb8f069SAndrzej Hajda reg |= DSIM_HSA_MODE; 8357eb8f069SAndrzej Hajda } 8367eb8f069SAndrzej Hajda 8372f36e33aSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 8382f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 8392f36e33aSYoungJun Cho 8407eb8f069SAndrzej Hajda switch (dsi->format) { 8417eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 8427eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 8437eb8f069SAndrzej Hajda break; 8447eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 8457eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 8467eb8f069SAndrzej Hajda break; 8477eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 8487eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 8497eb8f069SAndrzej Hajda break; 8507eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 8517eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 8527eb8f069SAndrzej Hajda break; 8537eb8f069SAndrzej Hajda default: 8547eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 8557eb8f069SAndrzej Hajda return -EINVAL; 8567eb8f069SAndrzej Hajda } 8577eb8f069SAndrzej Hajda 85878d3a8c6SInki Dae /* 85978d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 86078d3a8c6SInki Dae * host controller supports 86178d3a8c6SInki Dae * 86278d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 86378d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 86478d3a8c6SInki Dae * power consumption. 86578d3a8c6SInki Dae */ 86678d3a8c6SInki Dae if (driver_data->has_clklane_stop && 86778d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 86878d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 86978d3a8c6SInki Dae } 870e6f988a4SHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 871e6f988a4SHyungwon Hwang 872e6f988a4SHyungwon Hwang lanes_mask = BIT(dsi->lanes) - 1; 873e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, lanes_mask); 87478d3a8c6SInki Dae 8757eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 8767eb8f069SAndrzej Hajda timeout = 100; 8777eb8f069SAndrzej Hajda do { 8787eb8f069SAndrzej Hajda if (timeout-- == 0) { 8797eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 8807eb8f069SAndrzej Hajda return -EFAULT; 8817eb8f069SAndrzej Hajda } 8827eb8f069SAndrzej Hajda 883ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_STATUS_REG); 8847eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 8857eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 8867eb8f069SAndrzej Hajda continue; 8877eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 8887eb8f069SAndrzej Hajda 889ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_ESCMODE_REG); 8907eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 891d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 892ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg); 8937eb8f069SAndrzej Hajda 8947eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 895ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg); 8967eb8f069SAndrzej Hajda 8977eb8f069SAndrzej Hajda return 0; 8987eb8f069SAndrzej Hajda } 8997eb8f069SAndrzej Hajda 9007eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 9017eb8f069SAndrzej Hajda { 9027eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 903d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 9047eb8f069SAndrzej Hajda u32 reg; 9057eb8f069SAndrzej Hajda 9067eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 9077eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 9087eb8f069SAndrzej Hajda | DSIM_STABLE_VFP(vm->vfront_porch) 9097eb8f069SAndrzej Hajda | DSIM_MAIN_VBP(vm->vback_porch); 910ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg); 9117eb8f069SAndrzej Hajda 9127eb8f069SAndrzej Hajda reg = DSIM_MAIN_HFP(vm->hfront_porch) 9137eb8f069SAndrzej Hajda | DSIM_MAIN_HBP(vm->hback_porch); 914ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg); 9157eb8f069SAndrzej Hajda 9167eb8f069SAndrzej Hajda reg = DSIM_MAIN_VSA(vm->vsync_len) 9177eb8f069SAndrzej Hajda | DSIM_MAIN_HSA(vm->hsync_len); 918ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MSYNC_REG, reg); 9197eb8f069SAndrzej Hajda } 920d668e8bfSHyungwon Hwang reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | 921d668e8bfSHyungwon Hwang DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); 9227eb8f069SAndrzej Hajda 923ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 9247eb8f069SAndrzej Hajda 9257eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 9267eb8f069SAndrzej Hajda } 9277eb8f069SAndrzej Hajda 9287eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 9297eb8f069SAndrzej Hajda { 9307eb8f069SAndrzej Hajda u32 reg; 9317eb8f069SAndrzej Hajda 932ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_MDRESOL_REG); 9337eb8f069SAndrzej Hajda if (enable) 9347eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 9357eb8f069SAndrzej Hajda else 9367eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 937ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 9387eb8f069SAndrzej Hajda } 9397eb8f069SAndrzej Hajda 9407eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 9417eb8f069SAndrzej Hajda { 9427eb8f069SAndrzej Hajda int timeout = 2000; 9437eb8f069SAndrzej Hajda 9447eb8f069SAndrzej Hajda do { 945ba12ac2bSHyungwon Hwang u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 9467eb8f069SAndrzej Hajda 9477eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 9487eb8f069SAndrzej Hajda return 0; 9497eb8f069SAndrzej Hajda 9507eb8f069SAndrzej Hajda if (!cond_resched()) 9517eb8f069SAndrzej Hajda usleep_range(950, 1050); 9527eb8f069SAndrzej Hajda } while (--timeout); 9537eb8f069SAndrzej Hajda 9547eb8f069SAndrzej Hajda return -ETIMEDOUT; 9557eb8f069SAndrzej Hajda } 9567eb8f069SAndrzej Hajda 9577eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 9587eb8f069SAndrzej Hajda { 959ba12ac2bSHyungwon Hwang u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 9607eb8f069SAndrzej Hajda 9617eb8f069SAndrzej Hajda if (lpm) 9627eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 9637eb8f069SAndrzej Hajda else 9647eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 9657eb8f069SAndrzej Hajda 966ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 9677eb8f069SAndrzej Hajda } 9687eb8f069SAndrzej Hajda 9697eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 9707eb8f069SAndrzej Hajda { 971ba12ac2bSHyungwon Hwang u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 9727eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 973ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 9747eb8f069SAndrzej Hajda } 9757eb8f069SAndrzej Hajda 9767eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 9777eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9787eb8f069SAndrzej Hajda { 9797eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9807eb8f069SAndrzej Hajda const u8 *payload = xfer->tx_payload + xfer->tx_done; 9817eb8f069SAndrzej Hajda u16 length = xfer->tx_len - xfer->tx_done; 9827eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 9837eb8f069SAndrzej Hajda u32 reg; 9847eb8f069SAndrzej Hajda 9857eb8f069SAndrzej Hajda dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 9867eb8f069SAndrzej Hajda xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 9877eb8f069SAndrzej Hajda 9887eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 9897eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 9907eb8f069SAndrzej Hajda 9917eb8f069SAndrzej Hajda xfer->tx_done += length; 9927eb8f069SAndrzej Hajda 9937eb8f069SAndrzej Hajda /* Send payload */ 9947eb8f069SAndrzej Hajda while (length >= 4) { 9957eb8f069SAndrzej Hajda reg = (payload[3] << 24) | (payload[2] << 16) 9967eb8f069SAndrzej Hajda | (payload[1] << 8) | payload[0]; 997ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 9987eb8f069SAndrzej Hajda payload += 4; 9997eb8f069SAndrzej Hajda length -= 4; 10007eb8f069SAndrzej Hajda } 10017eb8f069SAndrzej Hajda 10027eb8f069SAndrzej Hajda reg = 0; 10037eb8f069SAndrzej Hajda switch (length) { 10047eb8f069SAndrzej Hajda case 3: 10057eb8f069SAndrzej Hajda reg |= payload[2] << 16; 10067eb8f069SAndrzej Hajda /* Fall through */ 10077eb8f069SAndrzej Hajda case 2: 10087eb8f069SAndrzej Hajda reg |= payload[1] << 8; 10097eb8f069SAndrzej Hajda /* Fall through */ 10107eb8f069SAndrzej Hajda case 1: 10117eb8f069SAndrzej Hajda reg |= payload[0]; 1012ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 10137eb8f069SAndrzej Hajda break; 10147eb8f069SAndrzej Hajda case 0: 10157eb8f069SAndrzej Hajda /* Do nothing */ 10167eb8f069SAndrzej Hajda break; 10177eb8f069SAndrzej Hajda } 10187eb8f069SAndrzej Hajda 10197eb8f069SAndrzej Hajda /* Send packet header */ 10207eb8f069SAndrzej Hajda if (!first) 10217eb8f069SAndrzej Hajda return; 10227eb8f069SAndrzej Hajda 10237eb8f069SAndrzej Hajda reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; 10247eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 10257eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 10267eb8f069SAndrzej Hajda return; 10277eb8f069SAndrzej Hajda } 10287eb8f069SAndrzej Hajda 10297eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 10307eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 10317eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 10327eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 10337eb8f069SAndrzej Hajda } 10347eb8f069SAndrzej Hajda 1035ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg); 10367eb8f069SAndrzej Hajda 10377eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 10387eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 10397eb8f069SAndrzej Hajda } 10407eb8f069SAndrzej Hajda 10417eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 10427eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 10437eb8f069SAndrzej Hajda { 10447eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 10457eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 10467eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 10477eb8f069SAndrzej Hajda u16 length; 10487eb8f069SAndrzej Hajda u32 reg; 10497eb8f069SAndrzej Hajda 10507eb8f069SAndrzej Hajda if (first) { 1051ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10527eb8f069SAndrzej Hajda 10537eb8f069SAndrzej Hajda switch (reg & 0x3f) { 10547eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 10557eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 10567eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 10577eb8f069SAndrzej Hajda payload[1] = reg >> 16; 10587eb8f069SAndrzej Hajda ++xfer->rx_done; 10597eb8f069SAndrzej Hajda } 10607eb8f069SAndrzej Hajda /* Fall through */ 10617eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 10627eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 10637eb8f069SAndrzej Hajda payload[0] = reg >> 8; 10647eb8f069SAndrzej Hajda ++xfer->rx_done; 10657eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 10667eb8f069SAndrzej Hajda xfer->result = 0; 10677eb8f069SAndrzej Hajda goto clear_fifo; 10687eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 10697eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 10707eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 10717eb8f069SAndrzej Hajda xfer->result = 0; 10727eb8f069SAndrzej Hajda goto clear_fifo; 10737eb8f069SAndrzej Hajda } 10747eb8f069SAndrzej Hajda 10757eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 10767eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 10777eb8f069SAndrzej Hajda dev_err(dev, 10787eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 10797eb8f069SAndrzej Hajda xfer->rx_len, length); 10807eb8f069SAndrzej Hajda length = xfer->rx_len; 10817eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 10827eb8f069SAndrzej Hajda xfer->rx_len = length; 10837eb8f069SAndrzej Hajda } 10847eb8f069SAndrzej Hajda 10857eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 10867eb8f069SAndrzej Hajda xfer->rx_done += length; 10877eb8f069SAndrzej Hajda 10887eb8f069SAndrzej Hajda /* Receive payload */ 10897eb8f069SAndrzej Hajda while (length >= 4) { 1090ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10917eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 10927eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10937eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10947eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 10957eb8f069SAndrzej Hajda payload += 4; 10967eb8f069SAndrzej Hajda length -= 4; 10977eb8f069SAndrzej Hajda } 10987eb8f069SAndrzej Hajda 10997eb8f069SAndrzej Hajda if (length) { 1100ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 11017eb8f069SAndrzej Hajda switch (length) { 11027eb8f069SAndrzej Hajda case 3: 11037eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 11047eb8f069SAndrzej Hajda /* Fall through */ 11057eb8f069SAndrzej Hajda case 2: 11067eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 11077eb8f069SAndrzej Hajda /* Fall through */ 11087eb8f069SAndrzej Hajda case 1: 11097eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 11107eb8f069SAndrzej Hajda } 11117eb8f069SAndrzej Hajda } 11127eb8f069SAndrzej Hajda 11137eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 11147eb8f069SAndrzej Hajda xfer->result = 0; 11157eb8f069SAndrzej Hajda 11167eb8f069SAndrzej Hajda clear_fifo: 11177eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 11187eb8f069SAndrzej Hajda do { 1119ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 11207eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 11217eb8f069SAndrzej Hajda break; 11227eb8f069SAndrzej Hajda } while (--length); 11237eb8f069SAndrzej Hajda } 11247eb8f069SAndrzej Hajda 11257eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 11267eb8f069SAndrzej Hajda { 11277eb8f069SAndrzej Hajda unsigned long flags; 11287eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11297eb8f069SAndrzej Hajda bool start = false; 11307eb8f069SAndrzej Hajda 11317eb8f069SAndrzej Hajda again: 11327eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11337eb8f069SAndrzej Hajda 11347eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11357eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11367eb8f069SAndrzej Hajda return; 11377eb8f069SAndrzej Hajda } 11387eb8f069SAndrzej Hajda 11397eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11407eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11417eb8f069SAndrzej Hajda 11427eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11437eb8f069SAndrzej Hajda 11447eb8f069SAndrzej Hajda if (xfer->tx_len && xfer->tx_done == xfer->tx_len) 11457eb8f069SAndrzej Hajda /* waiting for RX */ 11467eb8f069SAndrzej Hajda return; 11477eb8f069SAndrzej Hajda 11487eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 11497eb8f069SAndrzej Hajda 11507eb8f069SAndrzej Hajda if (xfer->tx_len || xfer->rx_len) 11517eb8f069SAndrzej Hajda return; 11527eb8f069SAndrzej Hajda 11537eb8f069SAndrzej Hajda xfer->result = 0; 11547eb8f069SAndrzej Hajda complete(&xfer->completed); 11557eb8f069SAndrzej Hajda 11567eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11577eb8f069SAndrzej Hajda 11587eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11597eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11607eb8f069SAndrzej Hajda 11617eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11627eb8f069SAndrzej Hajda 11637eb8f069SAndrzej Hajda if (start) 11647eb8f069SAndrzej Hajda goto again; 11657eb8f069SAndrzej Hajda } 11667eb8f069SAndrzej Hajda 11677eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 11687eb8f069SAndrzej Hajda { 11697eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11707eb8f069SAndrzej Hajda unsigned long flags; 11717eb8f069SAndrzej Hajda bool start = true; 11727eb8f069SAndrzej Hajda 11737eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11747eb8f069SAndrzej Hajda 11757eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11767eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11777eb8f069SAndrzej Hajda return false; 11787eb8f069SAndrzej Hajda } 11797eb8f069SAndrzej Hajda 11807eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11817eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11827eb8f069SAndrzej Hajda 11837eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11847eb8f069SAndrzej Hajda 11857eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 11867eb8f069SAndrzej Hajda "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", 11877eb8f069SAndrzej Hajda xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 11887eb8f069SAndrzej Hajda 11897eb8f069SAndrzej Hajda if (xfer->tx_done != xfer->tx_len) 11907eb8f069SAndrzej Hajda return true; 11917eb8f069SAndrzej Hajda 11927eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11937eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 11947eb8f069SAndrzej Hajda 11957eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11967eb8f069SAndrzej Hajda return true; 11977eb8f069SAndrzej Hajda 11987eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11997eb8f069SAndrzej Hajda 12007eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12017eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12027eb8f069SAndrzej Hajda 12037eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12047eb8f069SAndrzej Hajda 12057eb8f069SAndrzej Hajda if (!xfer->rx_len) 12067eb8f069SAndrzej Hajda xfer->result = 0; 12077eb8f069SAndrzej Hajda complete(&xfer->completed); 12087eb8f069SAndrzej Hajda 12097eb8f069SAndrzej Hajda return start; 12107eb8f069SAndrzej Hajda } 12117eb8f069SAndrzej Hajda 12127eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 12137eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12147eb8f069SAndrzej Hajda { 12157eb8f069SAndrzej Hajda unsigned long flags; 12167eb8f069SAndrzej Hajda bool start; 12177eb8f069SAndrzej Hajda 12187eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12197eb8f069SAndrzej Hajda 12207eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 12217eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 12227eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 12237eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12247eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12257eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12267eb8f069SAndrzej Hajda if (start) 12277eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12287eb8f069SAndrzej Hajda return; 12297eb8f069SAndrzej Hajda } 12307eb8f069SAndrzej Hajda 12317eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12327eb8f069SAndrzej Hajda 12337eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12347eb8f069SAndrzej Hajda } 12357eb8f069SAndrzej Hajda 12367eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 12377eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12387eb8f069SAndrzej Hajda { 12397eb8f069SAndrzej Hajda unsigned long flags; 12407eb8f069SAndrzej Hajda bool stopped; 12417eb8f069SAndrzej Hajda 12427eb8f069SAndrzej Hajda xfer->tx_done = 0; 12437eb8f069SAndrzej Hajda xfer->rx_done = 0; 12447eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 12457eb8f069SAndrzej Hajda init_completion(&xfer->completed); 12467eb8f069SAndrzej Hajda 12477eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12487eb8f069SAndrzej Hajda 12497eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 12507eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 12517eb8f069SAndrzej Hajda 12527eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12537eb8f069SAndrzej Hajda 12547eb8f069SAndrzej Hajda if (stopped) 12557eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12567eb8f069SAndrzej Hajda 12577eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 12587eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 12597eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 12607eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 12617eb8f069SAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, 12627eb8f069SAndrzej Hajda xfer->tx_len, xfer->tx_payload); 12637eb8f069SAndrzej Hajda return -ETIMEDOUT; 12647eb8f069SAndrzej Hajda } 12657eb8f069SAndrzej Hajda 12667eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 12677eb8f069SAndrzej Hajda return xfer->result; 12687eb8f069SAndrzej Hajda } 12697eb8f069SAndrzej Hajda 12707eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 12717eb8f069SAndrzej Hajda { 12727eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 12737eb8f069SAndrzej Hajda u32 status; 12747eb8f069SAndrzej Hajda 1275ba12ac2bSHyungwon Hwang status = DSI_READ(dsi, DSIM_INTSRC_REG); 12767eb8f069SAndrzej Hajda if (!status) { 12777eb8f069SAndrzej Hajda static unsigned long int j; 12787eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 12797eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 12807eb8f069SAndrzej Hajda return IRQ_HANDLED; 12817eb8f069SAndrzej Hajda } 1282ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_INTSRC_REG, status); 12837eb8f069SAndrzej Hajda 12847eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 1285e6f988a4SHyungwon Hwang u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1286e6f988a4SHyungwon Hwang DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | 1287e6f988a4SHyungwon Hwang DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); 1288ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); 12897eb8f069SAndrzej Hajda complete(&dsi->completed); 12907eb8f069SAndrzej Hajda return IRQ_HANDLED; 12917eb8f069SAndrzej Hajda } 12927eb8f069SAndrzej Hajda 1293e6f988a4SHyungwon Hwang if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1294e6f988a4SHyungwon Hwang DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) 12957eb8f069SAndrzej Hajda return IRQ_HANDLED; 12967eb8f069SAndrzej Hajda 12977eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 12987eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12997eb8f069SAndrzej Hajda 13007eb8f069SAndrzej Hajda return IRQ_HANDLED; 13017eb8f069SAndrzej Hajda } 13027eb8f069SAndrzej Hajda 1303e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1304e17ddeccSYoungJun Cho { 1305e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 13062b8376c8SGustavo Padovan struct drm_encoder *encoder = &dsi->encoder; 1307e17ddeccSYoungJun Cho 13080e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1309e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1310e17ddeccSYoungJun Cho 1311e17ddeccSYoungJun Cho return IRQ_HANDLED; 1312e17ddeccSYoungJun Cho } 1313e17ddeccSYoungJun Cho 1314e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1315e17ddeccSYoungJun Cho { 1316e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1317e17ddeccSYoungJun Cho 1318e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1319e17ddeccSYoungJun Cho enable_irq(gpio_to_irq(dsi->te_gpio)); 1320e17ddeccSYoungJun Cho } 1321e17ddeccSYoungJun Cho 1322e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1323e17ddeccSYoungJun Cho { 1324e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1325e17ddeccSYoungJun Cho disable_irq(gpio_to_irq(dsi->te_gpio)); 1326e17ddeccSYoungJun Cho 1327e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1328e17ddeccSYoungJun Cho } 1329e17ddeccSYoungJun Cho 13307eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 13317eb8f069SAndrzej Hajda { 1332d668e8bfSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1333d668e8bfSHyungwon Hwang 13347eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1335e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 1336e6f988a4SHyungwon Hwang 1337e6f988a4SHyungwon Hwang if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1338e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1339e6f988a4SHyungwon Hwang 13409a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1341d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 13427eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 13439a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 13447eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 13457eb8f069SAndrzej Hajda 13467eb8f069SAndrzej Hajda return 0; 13477eb8f069SAndrzej Hajda } 13487eb8f069SAndrzej Hajda 1349e17ddeccSYoungJun Cho static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1350e17ddeccSYoungJun Cho { 1351e17ddeccSYoungJun Cho int ret; 13520cef83a5SYoungJun Cho int te_gpio_irq; 1353e17ddeccSYoungJun Cho 1354e17ddeccSYoungJun Cho dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 1355e17ddeccSYoungJun Cho if (!gpio_is_valid(dsi->te_gpio)) { 1356e17ddeccSYoungJun Cho dev_err(dsi->dev, "no te-gpios specified\n"); 1357e17ddeccSYoungJun Cho ret = dsi->te_gpio; 1358e17ddeccSYoungJun Cho goto out; 1359e17ddeccSYoungJun Cho } 1360e17ddeccSYoungJun Cho 136151d1decaSHyungwon Hwang ret = gpio_request(dsi->te_gpio, "te_gpio"); 1362e17ddeccSYoungJun Cho if (ret) { 1363e17ddeccSYoungJun Cho dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1364e17ddeccSYoungJun Cho goto out; 1365e17ddeccSYoungJun Cho } 1366e17ddeccSYoungJun Cho 13670cef83a5SYoungJun Cho te_gpio_irq = gpio_to_irq(dsi->te_gpio); 13680cef83a5SYoungJun Cho irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 136951d1decaSHyungwon Hwang 13700cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1371e17ddeccSYoungJun Cho IRQF_TRIGGER_RISING, "TE", dsi); 1372e17ddeccSYoungJun Cho if (ret) { 1373e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1374e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1375e17ddeccSYoungJun Cho goto out; 1376e17ddeccSYoungJun Cho } 1377e17ddeccSYoungJun Cho 1378e17ddeccSYoungJun Cho out: 1379e17ddeccSYoungJun Cho return ret; 1380e17ddeccSYoungJun Cho } 1381e17ddeccSYoungJun Cho 1382e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1383e17ddeccSYoungJun Cho { 1384e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) { 1385e17ddeccSYoungJun Cho free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1386e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1387e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1388e17ddeccSYoungJun Cho } 1389e17ddeccSYoungJun Cho } 1390e17ddeccSYoungJun Cho 13917eb8f069SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 13927eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 13937eb8f069SAndrzej Hajda { 13947eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 13957eb8f069SAndrzej Hajda 13967eb8f069SAndrzej Hajda dsi->lanes = device->lanes; 13977eb8f069SAndrzej Hajda dsi->format = device->format; 13987eb8f069SAndrzej Hajda dsi->mode_flags = device->mode_flags; 13997eb8f069SAndrzej Hajda dsi->panel_node = device->dev.of_node; 14007eb8f069SAndrzej Hajda 1401e17ddeccSYoungJun Cho /* 1402e17ddeccSYoungJun Cho * This is a temporary solution and should be made by more generic way. 1403e17ddeccSYoungJun Cho * 1404e17ddeccSYoungJun Cho * If attached panel device is for command mode one, dsi should register 1405e17ddeccSYoungJun Cho * TE interrupt handler. 1406e17ddeccSYoungJun Cho */ 1407e17ddeccSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1408e17ddeccSYoungJun Cho int ret = exynos_dsi_register_te_irq(dsi); 1409e17ddeccSYoungJun Cho 1410e17ddeccSYoungJun Cho if (ret) 1411e17ddeccSYoungJun Cho return ret; 1412e17ddeccSYoungJun Cho } 1413e17ddeccSYoungJun Cho 1414ecb84157SYoungJun Cho if (dsi->connector.dev) 1415ecb84157SYoungJun Cho drm_helper_hpd_irq_event(dsi->connector.dev); 1416ecb84157SYoungJun Cho 14177eb8f069SAndrzej Hajda return 0; 14187eb8f069SAndrzej Hajda } 14197eb8f069SAndrzej Hajda 14207eb8f069SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 14217eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 14227eb8f069SAndrzej Hajda { 14237eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 14247eb8f069SAndrzej Hajda 1425e17ddeccSYoungJun Cho exynos_dsi_unregister_te_irq(dsi); 1426e17ddeccSYoungJun Cho 14277eb8f069SAndrzej Hajda dsi->panel_node = NULL; 14287eb8f069SAndrzej Hajda 14297eb8f069SAndrzej Hajda if (dsi->connector.dev) 14307eb8f069SAndrzej Hajda drm_helper_hpd_irq_event(dsi->connector.dev); 14317eb8f069SAndrzej Hajda 14327eb8f069SAndrzej Hajda return 0; 14337eb8f069SAndrzej Hajda } 14347eb8f069SAndrzej Hajda 14357eb8f069SAndrzej Hajda /* distinguish between short and long DSI packet types */ 14367eb8f069SAndrzej Hajda static bool exynos_dsi_is_short_dsi_type(u8 type) 14377eb8f069SAndrzej Hajda { 14387eb8f069SAndrzej Hajda return (type & 0x0f) <= 8; 14397eb8f069SAndrzej Hajda } 14407eb8f069SAndrzej Hajda 14417eb8f069SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1442ed6ff40eSThierry Reding const struct mipi_dsi_msg *msg) 14437eb8f069SAndrzej Hajda { 14447eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 14457eb8f069SAndrzej Hajda struct exynos_dsi_transfer xfer; 14467eb8f069SAndrzej Hajda int ret; 14477eb8f069SAndrzej Hajda 14480e480f6fSHyungwon Hwang if (!(dsi->state & DSIM_STATE_ENABLED)) 14490e480f6fSHyungwon Hwang return -EINVAL; 14500e480f6fSHyungwon Hwang 14517eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 14527eb8f069SAndrzej Hajda ret = exynos_dsi_init(dsi); 14537eb8f069SAndrzej Hajda if (ret) 14547eb8f069SAndrzej Hajda return ret; 14557eb8f069SAndrzej Hajda dsi->state |= DSIM_STATE_INITIALIZED; 14567eb8f069SAndrzej Hajda } 14577eb8f069SAndrzej Hajda 14587eb8f069SAndrzej Hajda if (msg->tx_len == 0) 14597eb8f069SAndrzej Hajda return -EINVAL; 14607eb8f069SAndrzej Hajda 14617eb8f069SAndrzej Hajda xfer.data_id = msg->type | (msg->channel << 6); 14627eb8f069SAndrzej Hajda 14637eb8f069SAndrzej Hajda if (exynos_dsi_is_short_dsi_type(msg->type)) { 14647eb8f069SAndrzej Hajda const char *tx_buf = msg->tx_buf; 14657eb8f069SAndrzej Hajda 14667eb8f069SAndrzej Hajda if (msg->tx_len > 2) 14677eb8f069SAndrzej Hajda return -EINVAL; 14687eb8f069SAndrzej Hajda xfer.tx_len = 0; 14697eb8f069SAndrzej Hajda xfer.data[0] = tx_buf[0]; 14707eb8f069SAndrzej Hajda xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; 14717eb8f069SAndrzej Hajda } else { 14727eb8f069SAndrzej Hajda xfer.tx_len = msg->tx_len; 14737eb8f069SAndrzej Hajda xfer.data[0] = msg->tx_len & 0xff; 14747eb8f069SAndrzej Hajda xfer.data[1] = msg->tx_len >> 8; 14757eb8f069SAndrzej Hajda xfer.tx_payload = msg->tx_buf; 14767eb8f069SAndrzej Hajda } 14777eb8f069SAndrzej Hajda 14787eb8f069SAndrzej Hajda xfer.rx_len = msg->rx_len; 14797eb8f069SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 14807eb8f069SAndrzej Hajda xfer.flags = msg->flags; 14817eb8f069SAndrzej Hajda 14827eb8f069SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 14837eb8f069SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 14847eb8f069SAndrzej Hajda } 14857eb8f069SAndrzej Hajda 14867eb8f069SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 14877eb8f069SAndrzej Hajda .attach = exynos_dsi_host_attach, 14887eb8f069SAndrzej Hajda .detach = exynos_dsi_host_detach, 14897eb8f069SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 14907eb8f069SAndrzej Hajda }; 14917eb8f069SAndrzej Hajda 14922b8376c8SGustavo Padovan static void exynos_dsi_enable(struct drm_encoder *encoder) 14937eb8f069SAndrzej Hajda { 1494cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 14957eb8f069SAndrzej Hajda int ret; 14967eb8f069SAndrzej Hajda 14977eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 1498b6595dc7SGustavo Padovan return; 14997eb8f069SAndrzej Hajda 1500ba6e4779SInki Dae pm_runtime_get_sync(dsi->dev); 15017eb8f069SAndrzej Hajda 15020e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 15030e480f6fSHyungwon Hwang 1504cdfb8694SAjay Kumar ret = drm_panel_prepare(dsi->panel); 15057eb8f069SAndrzej Hajda if (ret < 0) { 15060e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_ENABLED; 1507ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 1508b6595dc7SGustavo Padovan return; 15097eb8f069SAndrzej Hajda } 15107eb8f069SAndrzej Hajda 15117eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 15127eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 15137eb8f069SAndrzej Hajda 1514cdfb8694SAjay Kumar ret = drm_panel_enable(dsi->panel); 1515cdfb8694SAjay Kumar if (ret < 0) { 1516d41bb38fSYoungJun Cho dsi->state &= ~DSIM_STATE_ENABLED; 1517cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1518cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 1519ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 1520b6595dc7SGustavo Padovan return; 1521cdfb8694SAjay Kumar } 1522cdfb8694SAjay Kumar 15230e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 15247eb8f069SAndrzej Hajda } 15257eb8f069SAndrzej Hajda 15262b8376c8SGustavo Padovan static void exynos_dsi_disable(struct drm_encoder *encoder) 15277eb8f069SAndrzej Hajda { 1528cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1529b6595dc7SGustavo Padovan 15307eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 15317eb8f069SAndrzej Hajda return; 15327eb8f069SAndrzej Hajda 15330e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 15340e480f6fSHyungwon Hwang 15357eb8f069SAndrzej Hajda drm_panel_disable(dsi->panel); 1536cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1537cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 15387eb8f069SAndrzej Hajda 15397eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 15400e480f6fSHyungwon Hwang 1541ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 15427eb8f069SAndrzej Hajda } 15437eb8f069SAndrzej Hajda 15447eb8f069SAndrzej Hajda static enum drm_connector_status 15457eb8f069SAndrzej Hajda exynos_dsi_detect(struct drm_connector *connector, bool force) 15467eb8f069SAndrzej Hajda { 15477eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15487eb8f069SAndrzej Hajda 15497eb8f069SAndrzej Hajda if (!dsi->panel) { 15507eb8f069SAndrzej Hajda dsi->panel = of_drm_find_panel(dsi->panel_node); 15517eb8f069SAndrzej Hajda if (dsi->panel) 15527eb8f069SAndrzej Hajda drm_panel_attach(dsi->panel, &dsi->connector); 15537eb8f069SAndrzej Hajda } else if (!dsi->panel_node) { 15542b8376c8SGustavo Padovan struct drm_encoder *encoder; 15557eb8f069SAndrzej Hajda 1556cf67cc9aSGustavo Padovan encoder = platform_get_drvdata(to_platform_device(dsi->dev)); 1557cf67cc9aSGustavo Padovan exynos_dsi_disable(encoder); 15587eb8f069SAndrzej Hajda drm_panel_detach(dsi->panel); 15597eb8f069SAndrzej Hajda dsi->panel = NULL; 15607eb8f069SAndrzej Hajda } 15617eb8f069SAndrzej Hajda 15627eb8f069SAndrzej Hajda if (dsi->panel) 15637eb8f069SAndrzej Hajda return connector_status_connected; 15647eb8f069SAndrzej Hajda 15657eb8f069SAndrzej Hajda return connector_status_disconnected; 15667eb8f069SAndrzej Hajda } 15677eb8f069SAndrzej Hajda 15687eb8f069SAndrzej Hajda static void exynos_dsi_connector_destroy(struct drm_connector *connector) 15697eb8f069SAndrzej Hajda { 15700ae46015SAndrzej Hajda drm_connector_unregister(connector); 15710ae46015SAndrzej Hajda drm_connector_cleanup(connector); 15720ae46015SAndrzej Hajda connector->dev = NULL; 15737eb8f069SAndrzej Hajda } 15747eb8f069SAndrzej Hajda 1575800ba2b5SVille Syrjälä static const struct drm_connector_funcs exynos_dsi_connector_funcs = { 157663498e30SGustavo Padovan .dpms = drm_atomic_helper_connector_dpms, 15777eb8f069SAndrzej Hajda .detect = exynos_dsi_detect, 15787eb8f069SAndrzej Hajda .fill_modes = drm_helper_probe_single_connector_modes, 15797eb8f069SAndrzej Hajda .destroy = exynos_dsi_connector_destroy, 15804ea9526bSGustavo Padovan .reset = drm_atomic_helper_connector_reset, 15814ea9526bSGustavo Padovan .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 15824ea9526bSGustavo Padovan .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 15837eb8f069SAndrzej Hajda }; 15847eb8f069SAndrzej Hajda 15857eb8f069SAndrzej Hajda static int exynos_dsi_get_modes(struct drm_connector *connector) 15867eb8f069SAndrzej Hajda { 15877eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15887eb8f069SAndrzej Hajda 15897eb8f069SAndrzej Hajda if (dsi->panel) 15907eb8f069SAndrzej Hajda return dsi->panel->funcs->get_modes(dsi->panel); 15917eb8f069SAndrzej Hajda 15927eb8f069SAndrzej Hajda return 0; 15937eb8f069SAndrzej Hajda } 15947eb8f069SAndrzej Hajda 15957eb8f069SAndrzej Hajda static struct drm_encoder * 15967eb8f069SAndrzej Hajda exynos_dsi_best_encoder(struct drm_connector *connector) 15977eb8f069SAndrzej Hajda { 15987eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15997eb8f069SAndrzej Hajda 16002b8376c8SGustavo Padovan return &dsi->encoder; 16017eb8f069SAndrzej Hajda } 16027eb8f069SAndrzej Hajda 1603800ba2b5SVille Syrjälä static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 16047eb8f069SAndrzej Hajda .get_modes = exynos_dsi_get_modes, 16057eb8f069SAndrzej Hajda .best_encoder = exynos_dsi_best_encoder, 16067eb8f069SAndrzej Hajda }; 16077eb8f069SAndrzej Hajda 16082b8376c8SGustavo Padovan static int exynos_dsi_create_connector(struct drm_encoder *encoder) 16097eb8f069SAndrzej Hajda { 16102b8376c8SGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 16117eb8f069SAndrzej Hajda struct drm_connector *connector = &dsi->connector; 16127eb8f069SAndrzej Hajda int ret; 16137eb8f069SAndrzej Hajda 16147eb8f069SAndrzej Hajda connector->polled = DRM_CONNECTOR_POLL_HPD; 16157eb8f069SAndrzej Hajda 16167eb8f069SAndrzej Hajda ret = drm_connector_init(encoder->dev, connector, 16177eb8f069SAndrzej Hajda &exynos_dsi_connector_funcs, 16187eb8f069SAndrzej Hajda DRM_MODE_CONNECTOR_DSI); 16197eb8f069SAndrzej Hajda if (ret) { 16207eb8f069SAndrzej Hajda DRM_ERROR("Failed to initialize connector with drm\n"); 16217eb8f069SAndrzej Hajda return ret; 16227eb8f069SAndrzej Hajda } 16237eb8f069SAndrzej Hajda 16247eb8f069SAndrzej Hajda drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 162534ea3d38SThomas Wood drm_connector_register(connector); 16267eb8f069SAndrzej Hajda drm_mode_connector_attach_encoder(connector, encoder); 16277eb8f069SAndrzej Hajda 16287eb8f069SAndrzej Hajda return 0; 16297eb8f069SAndrzej Hajda } 16307eb8f069SAndrzej Hajda 16312b8376c8SGustavo Padovan static void exynos_dsi_mode_set(struct drm_encoder *encoder, 16322b8376c8SGustavo Padovan struct drm_display_mode *mode, 16332b8376c8SGustavo Padovan struct drm_display_mode *adjusted_mode) 16347eb8f069SAndrzej Hajda { 1635cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 16367eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 16372b8376c8SGustavo Padovan struct drm_display_mode *m = adjusted_mode; 16387eb8f069SAndrzej Hajda 16392b8376c8SGustavo Padovan vm->hactive = m->hdisplay; 16402b8376c8SGustavo Padovan vm->vactive = m->vdisplay; 16412b8376c8SGustavo Padovan vm->vfront_porch = m->vsync_start - m->vdisplay; 16422b8376c8SGustavo Padovan vm->vback_porch = m->vtotal - m->vsync_end; 16432b8376c8SGustavo Padovan vm->vsync_len = m->vsync_end - m->vsync_start; 16442b8376c8SGustavo Padovan vm->hfront_porch = m->hsync_start - m->hdisplay; 16452b8376c8SGustavo Padovan vm->hback_porch = m->htotal - m->hsync_end; 16462b8376c8SGustavo Padovan vm->hsync_len = m->hsync_end - m->hsync_start; 16477eb8f069SAndrzej Hajda } 16487eb8f069SAndrzej Hajda 1649800ba2b5SVille Syrjälä static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { 16507eb8f069SAndrzej Hajda .mode_set = exynos_dsi_mode_set, 1651b6595dc7SGustavo Padovan .enable = exynos_dsi_enable, 1652b6595dc7SGustavo Padovan .disable = exynos_dsi_disable, 16537eb8f069SAndrzej Hajda }; 16547eb8f069SAndrzej Hajda 1655800ba2b5SVille Syrjälä static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { 16562b8376c8SGustavo Padovan .destroy = drm_encoder_cleanup, 16572b8376c8SGustavo Padovan }; 16582b8376c8SGustavo Padovan 1659bd024b86SSjoerd Simons MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 16607eb8f069SAndrzej Hajda 16617eb8f069SAndrzej Hajda /* of_* functions will be removed after merge of of_graph patches */ 16627eb8f069SAndrzej Hajda static struct device_node * 16637eb8f069SAndrzej Hajda of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) 16647eb8f069SAndrzej Hajda { 16657eb8f069SAndrzej Hajda struct device_node *np; 16667eb8f069SAndrzej Hajda 16677eb8f069SAndrzej Hajda for_each_child_of_node(parent, np) { 16687eb8f069SAndrzej Hajda u32 r; 16697eb8f069SAndrzej Hajda 16707eb8f069SAndrzej Hajda if (!np->name || of_node_cmp(np->name, name)) 16717eb8f069SAndrzej Hajda continue; 16727eb8f069SAndrzej Hajda 16737eb8f069SAndrzej Hajda if (of_property_read_u32(np, "reg", &r) < 0) 16747eb8f069SAndrzej Hajda r = 0; 16757eb8f069SAndrzej Hajda 16767eb8f069SAndrzej Hajda if (reg == r) 16777eb8f069SAndrzej Hajda break; 16787eb8f069SAndrzej Hajda } 16797eb8f069SAndrzej Hajda 16807eb8f069SAndrzej Hajda return np; 16817eb8f069SAndrzej Hajda } 16827eb8f069SAndrzej Hajda 16837eb8f069SAndrzej Hajda static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, 16847eb8f069SAndrzej Hajda u32 reg) 16857eb8f069SAndrzej Hajda { 16867eb8f069SAndrzej Hajda struct device_node *ports, *port; 16877eb8f069SAndrzej Hajda 16887eb8f069SAndrzej Hajda ports = of_get_child_by_name(parent, "ports"); 16897eb8f069SAndrzej Hajda if (ports) 16907eb8f069SAndrzej Hajda parent = ports; 16917eb8f069SAndrzej Hajda 16927eb8f069SAndrzej Hajda port = of_get_child_by_name_reg(parent, "port", reg); 16937eb8f069SAndrzej Hajda 16947eb8f069SAndrzej Hajda of_node_put(ports); 16957eb8f069SAndrzej Hajda 16967eb8f069SAndrzej Hajda return port; 16977eb8f069SAndrzej Hajda } 16987eb8f069SAndrzej Hajda 16997eb8f069SAndrzej Hajda static struct device_node * 17007eb8f069SAndrzej Hajda of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) 17017eb8f069SAndrzej Hajda { 17027eb8f069SAndrzej Hajda return of_get_child_by_name_reg(port, "endpoint", reg); 17037eb8f069SAndrzej Hajda } 17047eb8f069SAndrzej Hajda 17057eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 17067eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 17077eb8f069SAndrzej Hajda { 17087eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 17097eb8f069SAndrzej Hajda 17107eb8f069SAndrzej Hajda if (ret < 0) 17117eb8f069SAndrzej Hajda pr_err("%s: failed to get '%s' property\n", np->full_name, 17127eb8f069SAndrzej Hajda propname); 17137eb8f069SAndrzej Hajda 17147eb8f069SAndrzej Hajda return ret; 17157eb8f069SAndrzej Hajda } 17167eb8f069SAndrzej Hajda 17177eb8f069SAndrzej Hajda enum { 17187eb8f069SAndrzej Hajda DSI_PORT_IN, 17197eb8f069SAndrzej Hajda DSI_PORT_OUT 17207eb8f069SAndrzej Hajda }; 17217eb8f069SAndrzej Hajda 17227eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 17237eb8f069SAndrzej Hajda { 17247eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 17257eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 17267eb8f069SAndrzej Hajda struct device_node *port, *ep; 17277eb8f069SAndrzej Hajda int ret; 17287eb8f069SAndrzej Hajda 17297eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 17307eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 17317eb8f069SAndrzej Hajda if (ret < 0) 17327eb8f069SAndrzej Hajda return ret; 17337eb8f069SAndrzej Hajda 17347eb8f069SAndrzej Hajda port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); 17357eb8f069SAndrzej Hajda if (!port) { 17367eb8f069SAndrzej Hajda dev_err(dev, "no output port specified\n"); 17377eb8f069SAndrzej Hajda return -EINVAL; 17387eb8f069SAndrzej Hajda } 17397eb8f069SAndrzej Hajda 17407eb8f069SAndrzej Hajda ep = of_graph_get_endpoint_by_reg(port, 0); 17417eb8f069SAndrzej Hajda of_node_put(port); 17427eb8f069SAndrzej Hajda if (!ep) { 17437eb8f069SAndrzej Hajda dev_err(dev, "no endpoint specified in output port\n"); 17447eb8f069SAndrzej Hajda return -EINVAL; 17457eb8f069SAndrzej Hajda } 17467eb8f069SAndrzej Hajda 17477eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", 17487eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 17497eb8f069SAndrzej Hajda if (ret < 0) 17507eb8f069SAndrzej Hajda goto end; 17517eb8f069SAndrzej Hajda 17527eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", 17537eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 1754f5f3b9baSHyungwon Hwang if (ret < 0) 1755f5f3b9baSHyungwon Hwang goto end; 17567eb8f069SAndrzej Hajda 1757f5f3b9baSHyungwon Hwang of_node_put(ep); 1758f5f3b9baSHyungwon Hwang 1759f5f3b9baSHyungwon Hwang ep = of_graph_get_next_endpoint(node, NULL); 1760f5f3b9baSHyungwon Hwang if (!ep) { 17611b256fa4SInki Dae ret = -EINVAL; 1762f5f3b9baSHyungwon Hwang goto end; 1763f5f3b9baSHyungwon Hwang } 1764f5f3b9baSHyungwon Hwang 1765f5f3b9baSHyungwon Hwang dsi->bridge_node = of_graph_get_remote_port_parent(ep); 1766f5f3b9baSHyungwon Hwang if (!dsi->bridge_node) { 17671b256fa4SInki Dae ret = -EINVAL; 1768f5f3b9baSHyungwon Hwang goto end; 1769f5f3b9baSHyungwon Hwang } 17707eb8f069SAndrzej Hajda end: 17717eb8f069SAndrzej Hajda of_node_put(ep); 17727eb8f069SAndrzej Hajda 17737eb8f069SAndrzej Hajda return ret; 17747eb8f069SAndrzej Hajda } 17757eb8f069SAndrzej Hajda 1776f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1777f37cd5e8SInki Dae void *data) 1778f37cd5e8SInki Dae { 17792b8376c8SGustavo Padovan struct drm_encoder *encoder = dev_get_drvdata(dev); 17802b8376c8SGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1781f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1782f5f3b9baSHyungwon Hwang struct drm_bridge *bridge; 1783f37cd5e8SInki Dae int ret; 1784f37cd5e8SInki Dae 17852b8376c8SGustavo Padovan ret = exynos_drm_crtc_get_pipe_from_type(drm_dev, 1786cf67cc9aSGustavo Padovan EXYNOS_DISPLAY_TYPE_LCD); 17872b8376c8SGustavo Padovan if (ret < 0) 1788a2986e80SGustavo Padovan return ret; 1789a2986e80SGustavo Padovan 17902b8376c8SGustavo Padovan encoder->possible_crtcs = 1 << ret; 17912b8376c8SGustavo Padovan 17922b8376c8SGustavo Padovan DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 17932b8376c8SGustavo Padovan 17942b8376c8SGustavo Padovan drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, 179513a3d91fSVille Syrjälä DRM_MODE_ENCODER_TMDS, NULL); 17962b8376c8SGustavo Padovan 17972b8376c8SGustavo Padovan drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); 17982b8376c8SGustavo Padovan 17992b8376c8SGustavo Padovan ret = exynos_dsi_create_connector(encoder); 1800a2986e80SGustavo Padovan if (ret) { 1801a2986e80SGustavo Padovan DRM_ERROR("failed to create connector ret = %d\n", ret); 18022b8376c8SGustavo Padovan drm_encoder_cleanup(encoder); 1803f37cd5e8SInki Dae return ret; 1804f37cd5e8SInki Dae } 1805f37cd5e8SInki Dae 1806f5f3b9baSHyungwon Hwang bridge = of_drm_find_bridge(dsi->bridge_node); 1807f5f3b9baSHyungwon Hwang if (bridge) { 18086fe9dbf7SMarek Szyprowski encoder->bridge = bridge; 1809f5f3b9baSHyungwon Hwang drm_bridge_attach(drm_dev, bridge); 1810f5f3b9baSHyungwon Hwang } 1811f5f3b9baSHyungwon Hwang 1812f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1813f37cd5e8SInki Dae } 1814f37cd5e8SInki Dae 1815f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1816f37cd5e8SInki Dae void *data) 1817f37cd5e8SInki Dae { 18182b8376c8SGustavo Padovan struct drm_encoder *encoder = dev_get_drvdata(dev); 1819cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1820f37cd5e8SInki Dae 1821cf67cc9aSGustavo Padovan exynos_dsi_disable(encoder); 1822f37cd5e8SInki Dae 18230ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1824f37cd5e8SInki Dae } 1825f37cd5e8SInki Dae 1826f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1827f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1828f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1829f37cd5e8SInki Dae }; 1830f37cd5e8SInki Dae 18317eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 18327eb8f069SAndrzej Hajda { 18332900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 18347eb8f069SAndrzej Hajda struct resource *res; 18357eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 18360ff03fd1SHyungwon Hwang int ret, i; 18377eb8f069SAndrzej Hajda 18382900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 18392900c69cSAndrzej Hajda if (!dsi) 18402900c69cSAndrzej Hajda return -ENOMEM; 18412900c69cSAndrzej Hajda 1842e17ddeccSYoungJun Cho /* To be checked as invalid one */ 1843e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1844e17ddeccSYoungJun Cho 18457eb8f069SAndrzej Hajda init_completion(&dsi->completed); 18467eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 18477eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 18487eb8f069SAndrzej Hajda 18497eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1850e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 18517eb8f069SAndrzej Hajda 1852e2d2a1e0SAndrzej Hajda dsi->dev = dev; 18539a320415SYoungJun Cho dsi->driver_data = exynos_dsi_get_driver_data(pdev); 18547eb8f069SAndrzej Hajda 18557eb8f069SAndrzej Hajda ret = exynos_dsi_parse_dt(dsi); 18567eb8f069SAndrzej Hajda if (ret) 185786650408SAndrzej Hajda return ret; 18587eb8f069SAndrzej Hajda 18597eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 18607eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1861e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 18627eb8f069SAndrzej Hajda dsi->supplies); 18637eb8f069SAndrzej Hajda if (ret) { 1864e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get regulators: %d\n", ret); 18657eb8f069SAndrzej Hajda return -EPROBE_DEFER; 18667eb8f069SAndrzej Hajda } 18677eb8f069SAndrzej Hajda 18680ff03fd1SHyungwon Hwang dsi->clks = devm_kzalloc(dev, 18690ff03fd1SHyungwon Hwang sizeof(*dsi->clks) * dsi->driver_data->num_clks, 18700ff03fd1SHyungwon Hwang GFP_KERNEL); 1871e6f988a4SHyungwon Hwang if (!dsi->clks) 1872e6f988a4SHyungwon Hwang return -ENOMEM; 1873e6f988a4SHyungwon Hwang 18740ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 18750ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 18760ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 18770ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 18780ff03fd1SHyungwon Hwang strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 18790ff03fd1SHyungwon Hwang i--; 18800ff03fd1SHyungwon Hwang continue; 18817eb8f069SAndrzej Hajda } 18827eb8f069SAndrzej Hajda 18830ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 18840ff03fd1SHyungwon Hwang clk_names[i]); 18850ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 18860ff03fd1SHyungwon Hwang } 18877eb8f069SAndrzej Hajda } 18887eb8f069SAndrzej Hajda 18897eb8f069SAndrzej Hajda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1890e2d2a1e0SAndrzej Hajda dsi->reg_base = devm_ioremap_resource(dev, res); 1891293d3f6aSJingoo Han if (IS_ERR(dsi->reg_base)) { 1892e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to remap io region\n"); 189386650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 18947eb8f069SAndrzej Hajda } 18957eb8f069SAndrzej Hajda 1896e2d2a1e0SAndrzej Hajda dsi->phy = devm_phy_get(dev, "dsim"); 18977eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1898e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 189986650408SAndrzej Hajda return PTR_ERR(dsi->phy); 19007eb8f069SAndrzej Hajda } 19017eb8f069SAndrzej Hajda 19027eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 19037eb8f069SAndrzej Hajda if (dsi->irq < 0) { 1904e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq resource\n"); 190586650408SAndrzej Hajda return dsi->irq; 19067eb8f069SAndrzej Hajda } 19077eb8f069SAndrzej Hajda 19087eb8f069SAndrzej Hajda irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1909e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 19107eb8f069SAndrzej Hajda exynos_dsi_irq, IRQF_ONESHOT, 1911e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 19127eb8f069SAndrzej Hajda if (ret) { 1913e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 191486650408SAndrzej Hajda return ret; 19157eb8f069SAndrzej Hajda } 19167eb8f069SAndrzej Hajda 1917cf67cc9aSGustavo Padovan platform_set_drvdata(pdev, &dsi->encoder); 19187eb8f069SAndrzej Hajda 1919ba6e4779SInki Dae pm_runtime_enable(dev); 1920ba6e4779SInki Dae 192186650408SAndrzej Hajda return component_add(dev, &exynos_dsi_component_ops); 19227eb8f069SAndrzej Hajda } 19237eb8f069SAndrzej Hajda 19247eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 19257eb8f069SAndrzej Hajda { 1926ba6e4779SInki Dae pm_runtime_disable(&pdev->dev); 1927ba6e4779SInki Dae 1928df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1929df5225bcSInki Dae 19307eb8f069SAndrzej Hajda return 0; 19317eb8f069SAndrzej Hajda } 19327eb8f069SAndrzej Hajda 1933010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1934ba6e4779SInki Dae { 1935ba6e4779SInki Dae struct drm_encoder *encoder = dev_get_drvdata(dev); 1936ba6e4779SInki Dae struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1937ba6e4779SInki Dae struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1938ba6e4779SInki Dae int ret, i; 1939ba6e4779SInki Dae 1940ba6e4779SInki Dae usleep_range(10000, 20000); 1941ba6e4779SInki Dae 1942ba6e4779SInki Dae if (dsi->state & DSIM_STATE_INITIALIZED) { 1943ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_INITIALIZED; 1944ba6e4779SInki Dae 1945ba6e4779SInki Dae exynos_dsi_disable_clock(dsi); 1946ba6e4779SInki Dae 1947ba6e4779SInki Dae exynos_dsi_disable_irq(dsi); 1948ba6e4779SInki Dae } 1949ba6e4779SInki Dae 1950ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_CMD_LPM; 1951ba6e4779SInki Dae 1952ba6e4779SInki Dae phy_power_off(dsi->phy); 1953ba6e4779SInki Dae 1954ba6e4779SInki Dae for (i = driver_data->num_clks - 1; i > -1; i--) 1955ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1956ba6e4779SInki Dae 1957ba6e4779SInki Dae ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1958ba6e4779SInki Dae if (ret < 0) 1959ba6e4779SInki Dae dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1960ba6e4779SInki Dae 1961ba6e4779SInki Dae return 0; 1962ba6e4779SInki Dae } 1963ba6e4779SInki Dae 1964010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_resume(struct device *dev) 1965ba6e4779SInki Dae { 1966ba6e4779SInki Dae struct drm_encoder *encoder = dev_get_drvdata(dev); 1967ba6e4779SInki Dae struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1968ba6e4779SInki Dae struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1969ba6e4779SInki Dae int ret, i; 1970ba6e4779SInki Dae 1971ba6e4779SInki Dae ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1972ba6e4779SInki Dae if (ret < 0) { 1973ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1974ba6e4779SInki Dae return ret; 1975ba6e4779SInki Dae } 1976ba6e4779SInki Dae 1977ba6e4779SInki Dae for (i = 0; i < driver_data->num_clks; i++) { 1978ba6e4779SInki Dae ret = clk_prepare_enable(dsi->clks[i]); 1979ba6e4779SInki Dae if (ret < 0) 1980ba6e4779SInki Dae goto err_clk; 1981ba6e4779SInki Dae } 1982ba6e4779SInki Dae 1983ba6e4779SInki Dae ret = phy_power_on(dsi->phy); 1984ba6e4779SInki Dae if (ret < 0) { 1985ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1986ba6e4779SInki Dae goto err_clk; 1987ba6e4779SInki Dae } 1988ba6e4779SInki Dae 1989ba6e4779SInki Dae return 0; 1990ba6e4779SInki Dae 1991ba6e4779SInki Dae err_clk: 1992ba6e4779SInki Dae while (--i > -1) 1993ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1994ba6e4779SInki Dae regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1995ba6e4779SInki Dae 1996ba6e4779SInki Dae return ret; 1997ba6e4779SInki Dae } 1998ba6e4779SInki Dae 1999ba6e4779SInki Dae static const struct dev_pm_ops exynos_dsi_pm_ops = { 2000ba6e4779SInki Dae SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 2001ba6e4779SInki Dae }; 2002ba6e4779SInki Dae 20037eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 20047eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 20057eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 20067eb8f069SAndrzej Hajda .driver = { 20077eb8f069SAndrzej Hajda .name = "exynos-dsi", 20087eb8f069SAndrzej Hajda .owner = THIS_MODULE, 2009ba6e4779SInki Dae .pm = &exynos_dsi_pm_ops, 20107eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 20117eb8f069SAndrzej Hajda }, 20127eb8f069SAndrzej Hajda }; 20137eb8f069SAndrzej Hajda 20147eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 20157eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 20167eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 20177eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 2018