1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
27eb8f069SAndrzej Hajda /*
37eb8f069SAndrzej Hajda  * Samsung SoC MIPI DSI Master driver.
47eb8f069SAndrzej Hajda  *
57eb8f069SAndrzej Hajda  * Copyright (c) 2014 Samsung Electronics Co., Ltd
67eb8f069SAndrzej Hajda  *
77eb8f069SAndrzej Hajda  * Contacts: Tomasz Figa <t.figa@samsung.com>
87eb8f069SAndrzej Hajda */
97eb8f069SAndrzej Hajda 
107eb8f069SAndrzej Hajda #include <linux/clk.h>
112bda34d7SSam Ravnborg #include <linux/delay.h>
122bda34d7SSam Ravnborg #include <linux/component.h>
13e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h>
147eb8f069SAndrzej Hajda #include <linux/irq.h>
159a320415SYoungJun Cho #include <linux/of_device.h>
16e17ddeccSYoungJun Cho #include <linux/of_gpio.h>
17f5f3b9baSHyungwon Hwang #include <linux/of_graph.h>
187eb8f069SAndrzej Hajda #include <linux/phy/phy.h>
197eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h>
202bda34d7SSam Ravnborg 
212bda34d7SSam Ravnborg #include <asm/unaligned.h>
227eb8f069SAndrzej Hajda 
237eb8f069SAndrzej Hajda #include <video/mipi_display.h>
247eb8f069SAndrzej Hajda #include <video/videomode.h>
257eb8f069SAndrzej Hajda 
262bda34d7SSam Ravnborg #include <drm/drm_atomic_helper.h>
27ee68c743SBoris Brezillon #include <drm/drm_bridge.h>
282bda34d7SSam Ravnborg #include <drm/drm_fb_helper.h>
292bda34d7SSam Ravnborg #include <drm/drm_mipi_dsi.h>
302bda34d7SSam Ravnborg #include <drm/drm_panel.h>
312bda34d7SSam Ravnborg #include <drm/drm_print.h>
322bda34d7SSam Ravnborg #include <drm/drm_probe_helper.h>
332bda34d7SSam Ravnborg 
34e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h"
357eb8f069SAndrzej Hajda #include "exynos_drm_drv.h"
367eb8f069SAndrzej Hajda 
377eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */
387eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b))
397eb8f069SAndrzej Hajda 
407eb8f069SAndrzej Hajda /* DSIM_STATUS */
417eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x)		(((x) & 0xf) << 0)
427eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK		(1 << 8)
437eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK		(1 << 10)
447eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE			(1 << 31)
457eb8f069SAndrzej Hajda 
467eb8f069SAndrzej Hajda /* DSIM_SWRST */
477eb8f069SAndrzej Hajda #define DSIM_FUNCRST			(1 << 16)
487eb8f069SAndrzej Hajda #define DSIM_SWRST			(1 << 0)
497eb8f069SAndrzej Hajda 
507eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */
517eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x)		((x) << 0)
527eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x)		((x) << 16)
537eb8f069SAndrzej Hajda 
547eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */
557eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << 0)
567eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK		(0xffff << 0)
577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK	(1 << 19)
587eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x)	(((x) & 0xf) << 20)
597eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK	(0xf << 20)
607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN			(1 << 24)
617eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x)		(((x) & 0x3) << 25)
627eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK		(0x3 << 25)
637eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS			(1 << 27)
647eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN			(1 << 28)
657eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK		(1 << 31)
667eb8f069SAndrzej Hajda 
677eb8f069SAndrzej Hajda /* DSIM_CONFIG */
687eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK		(1 << 0)
697eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x)			(((x) & 0xf) << 1)
707eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x)	(((x) & 0x3) << 5)
717eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x)		(((x) & 0x7) << 8)
727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK	(0x7 << 12)
737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888	(0x7 << 12)
747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666	(0x6 << 12)
757eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P	(0x5 << 12)
767eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565	(0x4 << 12)
777eb8f069SAndrzej Hajda #define DSIM_SUB_VC			(((x) & 0x3) << 16)
787eb8f069SAndrzej Hajda #define DSIM_MAIN_VC			(((x) & 0x3) << 18)
797eb8f069SAndrzej Hajda #define DSIM_HSA_MODE			(1 << 20)
807eb8f069SAndrzej Hajda #define DSIM_HBP_MODE			(1 << 21)
817eb8f069SAndrzej Hajda #define DSIM_HFP_MODE			(1 << 22)
827eb8f069SAndrzej Hajda #define DSIM_HSE_MODE			(1 << 23)
837eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE			(1 << 24)
847eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE			(1 << 25)
857eb8f069SAndrzej Hajda #define DSIM_BURST_MODE			(1 << 26)
867eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM		(1 << 27)
877eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE		(1 << 28)
887eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS			(1 << 29)
896bdc92eeSKrzysztof Kozlowski /* This flag is valid only for exynos3250/3472/5260/5430 */
9078d3a8c6SInki Dae #define DSIM_CLKLANE_STOP		(1 << 30)
917eb8f069SAndrzej Hajda 
927eb8f069SAndrzej Hajda /* DSIM_ESCMODE */
937eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST		(1 << 4)
947eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP			(1 << 6)
957eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP		(1 << 7)
967eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA			(1 << 16)
977eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE		(1 << 20)
987eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x)		(((x) & 0x7ff) << 21)
997eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK	(0x7ff << 21)
1007eb8f069SAndrzej Hajda 
1017eb8f069SAndrzej Hajda /* DSIM_MDRESOL */
1027eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY		(1 << 31)
103d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 16)
104d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits)	(((x) & ((1 << (num_bits)) - 1)) << 0)
1057eb8f069SAndrzej Hajda 
1067eb8f069SAndrzej Hajda /* DSIM_MVPORCH */
1077eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x)		((x) << 28)
1087eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x)		((x) << 16)
1097eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x)		((x) << 0)
1107eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK		(0xf << 28)
1117eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK		(0x7ff << 16)
1127eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK		(0x7ff << 0)
1137eb8f069SAndrzej Hajda 
1147eb8f069SAndrzej Hajda /* DSIM_MHPORCH */
1157eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x)		((x) << 16)
1167eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x)		((x) << 0)
1177eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK		((0xffff) << 16)
1187eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK		((0xffff) << 0)
1197eb8f069SAndrzej Hajda 
1207eb8f069SAndrzej Hajda /* DSIM_MSYNC */
1217eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x)		((x) << 22)
1227eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x)		((x) << 0)
1237eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)
1247eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK		((0xffff) << 0)
1257eb8f069SAndrzej Hajda 
1267eb8f069SAndrzej Hajda /* DSIM_SDRESOL */
1277eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x)		((x) << 31)
1287eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x)		((x) << 16)
1297eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x)		((x) << 0)
1307eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK		((0x1) << 31)
1317eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK		((0x7ff) << 16)
1327eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK		((0x7ff) << 0)
1337eb8f069SAndrzej Hajda 
1347eb8f069SAndrzej Hajda /* DSIM_INTSRC */
1357eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE		(1 << 31)
1367eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE		(1 << 30)
1377eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY		(1 << 29)
138e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY	(1 << 28)
1397eb8f069SAndrzej Hajda #define DSIM_INT_BTA			(1 << 25)
1407eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE		(1 << 24)
1417eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT		(1 << 21)
1427eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT		(1 << 20)
1437eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE		(1 << 18)
1447eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE			(1 << 17)
1457eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK			(1 << 16)
1467eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR		(1 << 15)
1477eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR		(1 << 14)
1487eb8f069SAndrzej Hajda 
1497eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */
1507eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL		(1 << 25)
1517eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY		(1 << 24)
1527eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL		(1 << 23)
1537eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY		(1 << 22)
1547eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL		(1 << 21)
1557eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY		(1 << 20)
1567eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL		(1 << 19)
1577eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY		(1 << 18)
1587eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL		(1 << 17)
1597eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY		(1 << 16)
1607eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL		(1 << 15)
1617eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY		(1 << 14)
1627eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL		(1 << 13)
1637eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY		(1 << 12)
1647eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL		(1 << 11)
1657eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY		(1 << 10)
1667eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL		(1 << 9)
1677eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY		(1 << 8)
1687eb8f069SAndrzej Hajda #define DSIM_RX_FIFO			(1 << 4)
1697eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO			(1 << 3)
1707eb8f069SAndrzej Hajda #define DSIM_I80_FIFO			(1 << 2)
1717eb8f069SAndrzej Hajda #define DSIM_SD_FIFO			(1 << 1)
1727eb8f069SAndrzej Hajda #define DSIM_MD_FIFO			(1 << 0)
1737eb8f069SAndrzej Hajda 
1747eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */
1757eb8f069SAndrzej Hajda #define DSIM_AFC_EN			(1 << 14)
1767eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
1777eb8f069SAndrzej Hajda 
1787eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */
1797eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x)		((x) << 24)
1807eb8f069SAndrzej Hajda #define DSIM_PLL_EN			(1 << 23)
1817eb8f069SAndrzej Hajda #define DSIM_PLL_P(x)			((x) << 13)
1827eb8f069SAndrzej Hajda #define DSIM_PLL_M(x)			((x) << 4)
1837eb8f069SAndrzej Hajda #define DSIM_PLL_S(x)			((x) << 1)
1847eb8f069SAndrzej Hajda 
1859a320415SYoungJun Cho /* DSIM_PHYCTRL */
1869a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x)	(((x) & 0x1ff) << 0)
187e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP	(1 << 30)
188e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP	(1 << 14)
1899a320415SYoungJun Cho 
1909a320415SYoungJun Cho /* DSIM_PHYTIMING */
1919a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x)		((x) << 8)
1929a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x)	((x) << 0)
1939a320415SYoungJun Cho 
1949a320415SYoungJun Cho /* DSIM_PHYTIMING1 */
1959a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x)	((x) << 24)
1969a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x)	((x) << 16)
1979a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x)	((x) << 8)
1989a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x)	((x) << 0)
1999a320415SYoungJun Cho 
2009a320415SYoungJun Cho /* DSIM_PHYTIMING2 */
2019a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x)	((x) << 16)
2029a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x)	((x) << 8)
2039a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x)	((x) << 0)
2049a320415SYoungJun Cho 
2057eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH		4
2067eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS	4
2077eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE		2048
2087eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE		256
2097eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS		100
2107eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY		0x30800002
2117eb8f069SAndrzej Hajda 
21226269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
21326269af9SHyungwon Hwang 
214e6f988a4SHyungwon Hwang static char *clk_names[5] = { "bus_clk", "sclk_mipi",
215e6f988a4SHyungwon Hwang 	"phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0",
216e6f988a4SHyungwon Hwang 	"sclk_rgb_vclk_to_dsim0" };
2170ff03fd1SHyungwon Hwang 
2187eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type {
2197eb8f069SAndrzej Hajda 	EXYNOS_DSI_TX,
2207eb8f069SAndrzej Hajda 	EXYNOS_DSI_RX,
2217eb8f069SAndrzej Hajda };
2227eb8f069SAndrzej Hajda 
2237eb8f069SAndrzej Hajda struct exynos_dsi_transfer {
2247eb8f069SAndrzej Hajda 	struct list_head list;
2257eb8f069SAndrzej Hajda 	struct completion completed;
2267eb8f069SAndrzej Hajda 	int result;
2276c81e96dSAndrzej Hajda 	struct mipi_dsi_packet packet;
2287eb8f069SAndrzej Hajda 	u16 flags;
2297eb8f069SAndrzej Hajda 	u16 tx_done;
2307eb8f069SAndrzej Hajda 
2317eb8f069SAndrzej Hajda 	u8 *rx_payload;
2327eb8f069SAndrzej Hajda 	u16 rx_len;
2337eb8f069SAndrzej Hajda 	u16 rx_done;
2347eb8f069SAndrzej Hajda };
2357eb8f069SAndrzej Hajda 
2367eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED		BIT(0)
2377eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED		BIT(1)
2387eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM		BIT(2)
2390e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE	BIT(3)
2407eb8f069SAndrzej Hajda 
2419a320415SYoungJun Cho struct exynos_dsi_driver_data {
242b115361eSAndrzej Hajda 	const unsigned int *reg_ofs;
2439a320415SYoungJun Cho 	unsigned int plltmr_reg;
2449a320415SYoungJun Cho 	unsigned int has_freqband:1;
24578d3a8c6SInki Dae 	unsigned int has_clklane_stop:1;
246d668e8bfSHyungwon Hwang 	unsigned int num_clks;
247d668e8bfSHyungwon Hwang 	unsigned int max_freq;
248d668e8bfSHyungwon Hwang 	unsigned int wait_for_reset;
249d668e8bfSHyungwon Hwang 	unsigned int num_bits_resol;
250b115361eSAndrzej Hajda 	const unsigned int *reg_values;
2519a320415SYoungJun Cho };
2529a320415SYoungJun Cho 
2537eb8f069SAndrzej Hajda struct exynos_dsi {
2542b8376c8SGustavo Padovan 	struct drm_encoder encoder;
2557eb8f069SAndrzej Hajda 	struct mipi_dsi_host dsi_host;
2567eb8f069SAndrzej Hajda 	struct drm_connector connector;
2577eb8f069SAndrzej Hajda 	struct drm_panel *panel;
2586afb7721SMaciej Purski 	struct drm_bridge *out_bridge;
2597eb8f069SAndrzej Hajda 	struct device *dev;
2607eb8f069SAndrzej Hajda 
2617eb8f069SAndrzej Hajda 	void __iomem *reg_base;
2627eb8f069SAndrzej Hajda 	struct phy *phy;
2630ff03fd1SHyungwon Hwang 	struct clk **clks;
2647eb8f069SAndrzej Hajda 	struct regulator_bulk_data supplies[2];
2657eb8f069SAndrzej Hajda 	int irq;
266e17ddeccSYoungJun Cho 	int te_gpio;
2677eb8f069SAndrzej Hajda 
2687eb8f069SAndrzej Hajda 	u32 pll_clk_rate;
2697eb8f069SAndrzej Hajda 	u32 burst_clk_rate;
2707eb8f069SAndrzej Hajda 	u32 esc_clk_rate;
2717eb8f069SAndrzej Hajda 	u32 lanes;
2727eb8f069SAndrzej Hajda 	u32 mode_flags;
2737eb8f069SAndrzej Hajda 	u32 format;
2747eb8f069SAndrzej Hajda 
2757eb8f069SAndrzej Hajda 	int state;
2767eb8f069SAndrzej Hajda 	struct drm_property *brightness;
2777eb8f069SAndrzej Hajda 	struct completion completed;
2787eb8f069SAndrzej Hajda 
2797eb8f069SAndrzej Hajda 	spinlock_t transfer_lock; /* protects transfer_list */
2807eb8f069SAndrzej Hajda 	struct list_head transfer_list;
2819a320415SYoungJun Cho 
2822154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data;
2832782622eSMaciej Purski 	struct device_node *in_bridge_node;
2847eb8f069SAndrzej Hajda };
2857eb8f069SAndrzej Hajda 
2867eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
2877eb8f069SAndrzej Hajda #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
2887eb8f069SAndrzej Hajda 
2892b8376c8SGustavo Padovan static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e)
2905cd5db80SAndrzej Hajda {
291cf67cc9aSGustavo Padovan 	return container_of(e, struct exynos_dsi, encoder);
2925cd5db80SAndrzej Hajda }
2935cd5db80SAndrzej Hajda 
294d668e8bfSHyungwon Hwang enum reg_idx {
295d668e8bfSHyungwon Hwang 	DSIM_STATUS_REG,	/* Status register */
296d668e8bfSHyungwon Hwang 	DSIM_SWRST_REG,		/* Software reset register */
297d668e8bfSHyungwon Hwang 	DSIM_CLKCTRL_REG,	/* Clock control register */
298d668e8bfSHyungwon Hwang 	DSIM_TIMEOUT_REG,	/* Time out register */
299d668e8bfSHyungwon Hwang 	DSIM_CONFIG_REG,	/* Configuration register */
300d668e8bfSHyungwon Hwang 	DSIM_ESCMODE_REG,	/* Escape mode register */
301d668e8bfSHyungwon Hwang 	DSIM_MDRESOL_REG,
302d668e8bfSHyungwon Hwang 	DSIM_MVPORCH_REG,	/* Main display Vporch register */
303d668e8bfSHyungwon Hwang 	DSIM_MHPORCH_REG,	/* Main display Hporch register */
304d668e8bfSHyungwon Hwang 	DSIM_MSYNC_REG,		/* Main display sync area register */
305d668e8bfSHyungwon Hwang 	DSIM_INTSRC_REG,	/* Interrupt source register */
306d668e8bfSHyungwon Hwang 	DSIM_INTMSK_REG,	/* Interrupt mask register */
307d668e8bfSHyungwon Hwang 	DSIM_PKTHDR_REG,	/* Packet Header FIFO register */
308d668e8bfSHyungwon Hwang 	DSIM_PAYLOAD_REG,	/* Payload FIFO register */
309d668e8bfSHyungwon Hwang 	DSIM_RXFIFO_REG,	/* Read FIFO register */
310d668e8bfSHyungwon Hwang 	DSIM_FIFOCTRL_REG,	/* FIFO status and control register */
311d668e8bfSHyungwon Hwang 	DSIM_PLLCTRL_REG,	/* PLL control register */
312d668e8bfSHyungwon Hwang 	DSIM_PHYCTRL_REG,
313d668e8bfSHyungwon Hwang 	DSIM_PHYTIMING_REG,
314d668e8bfSHyungwon Hwang 	DSIM_PHYTIMING1_REG,
315d668e8bfSHyungwon Hwang 	DSIM_PHYTIMING2_REG,
316d668e8bfSHyungwon Hwang 	NUM_REGS
317d668e8bfSHyungwon Hwang };
318bb32e408SAndrzej Hajda 
319bb32e408SAndrzej Hajda static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx,
320bb32e408SAndrzej Hajda 				    u32 val)
321bb32e408SAndrzej Hajda {
3226c81e96dSAndrzej Hajda 
323bb32e408SAndrzej Hajda 	writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
324bb32e408SAndrzej Hajda }
325bb32e408SAndrzej Hajda 
326bb32e408SAndrzej Hajda static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx)
327bb32e408SAndrzej Hajda {
328bb32e408SAndrzej Hajda 	return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
329bb32e408SAndrzej Hajda }
330bb32e408SAndrzej Hajda 
331b115361eSAndrzej Hajda static const unsigned int exynos_reg_ofs[] = {
332d668e8bfSHyungwon Hwang 	[DSIM_STATUS_REG] =  0x00,
333d668e8bfSHyungwon Hwang 	[DSIM_SWRST_REG] =  0x04,
334d668e8bfSHyungwon Hwang 	[DSIM_CLKCTRL_REG] =  0x08,
335d668e8bfSHyungwon Hwang 	[DSIM_TIMEOUT_REG] =  0x0c,
336d668e8bfSHyungwon Hwang 	[DSIM_CONFIG_REG] =  0x10,
337d668e8bfSHyungwon Hwang 	[DSIM_ESCMODE_REG] =  0x14,
338d668e8bfSHyungwon Hwang 	[DSIM_MDRESOL_REG] =  0x18,
339d668e8bfSHyungwon Hwang 	[DSIM_MVPORCH_REG] =  0x1c,
340d668e8bfSHyungwon Hwang 	[DSIM_MHPORCH_REG] =  0x20,
341d668e8bfSHyungwon Hwang 	[DSIM_MSYNC_REG] =  0x24,
342d668e8bfSHyungwon Hwang 	[DSIM_INTSRC_REG] =  0x2c,
343d668e8bfSHyungwon Hwang 	[DSIM_INTMSK_REG] =  0x30,
344d668e8bfSHyungwon Hwang 	[DSIM_PKTHDR_REG] =  0x34,
345d668e8bfSHyungwon Hwang 	[DSIM_PAYLOAD_REG] =  0x38,
346d668e8bfSHyungwon Hwang 	[DSIM_RXFIFO_REG] =  0x3c,
347d668e8bfSHyungwon Hwang 	[DSIM_FIFOCTRL_REG] =  0x44,
348d668e8bfSHyungwon Hwang 	[DSIM_PLLCTRL_REG] =  0x4c,
349d668e8bfSHyungwon Hwang 	[DSIM_PHYCTRL_REG] =  0x5c,
350d668e8bfSHyungwon Hwang 	[DSIM_PHYTIMING_REG] =  0x64,
351d668e8bfSHyungwon Hwang 	[DSIM_PHYTIMING1_REG] =  0x68,
352d668e8bfSHyungwon Hwang 	[DSIM_PHYTIMING2_REG] =  0x6c,
353d668e8bfSHyungwon Hwang };
354d668e8bfSHyungwon Hwang 
355b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_ofs[] = {
356e6f988a4SHyungwon Hwang 	[DSIM_STATUS_REG] = 0x04,
357e6f988a4SHyungwon Hwang 	[DSIM_SWRST_REG] = 0x0C,
358e6f988a4SHyungwon Hwang 	[DSIM_CLKCTRL_REG] = 0x10,
359e6f988a4SHyungwon Hwang 	[DSIM_TIMEOUT_REG] = 0x14,
360e6f988a4SHyungwon Hwang 	[DSIM_CONFIG_REG] = 0x18,
361e6f988a4SHyungwon Hwang 	[DSIM_ESCMODE_REG] = 0x1C,
362e6f988a4SHyungwon Hwang 	[DSIM_MDRESOL_REG] = 0x20,
363e6f988a4SHyungwon Hwang 	[DSIM_MVPORCH_REG] = 0x24,
364e6f988a4SHyungwon Hwang 	[DSIM_MHPORCH_REG] = 0x28,
365e6f988a4SHyungwon Hwang 	[DSIM_MSYNC_REG] = 0x2C,
366e6f988a4SHyungwon Hwang 	[DSIM_INTSRC_REG] = 0x34,
367e6f988a4SHyungwon Hwang 	[DSIM_INTMSK_REG] = 0x38,
368e6f988a4SHyungwon Hwang 	[DSIM_PKTHDR_REG] = 0x3C,
369e6f988a4SHyungwon Hwang 	[DSIM_PAYLOAD_REG] = 0x40,
370e6f988a4SHyungwon Hwang 	[DSIM_RXFIFO_REG] = 0x44,
371e6f988a4SHyungwon Hwang 	[DSIM_FIFOCTRL_REG] = 0x4C,
372e6f988a4SHyungwon Hwang 	[DSIM_PLLCTRL_REG] = 0x94,
373e6f988a4SHyungwon Hwang 	[DSIM_PHYCTRL_REG] = 0xA4,
374e6f988a4SHyungwon Hwang 	[DSIM_PHYTIMING_REG] = 0xB4,
375e6f988a4SHyungwon Hwang 	[DSIM_PHYTIMING1_REG] = 0xB8,
376e6f988a4SHyungwon Hwang 	[DSIM_PHYTIMING2_REG] = 0xBC,
377e6f988a4SHyungwon Hwang };
378e6f988a4SHyungwon Hwang 
379d668e8bfSHyungwon Hwang enum reg_value_idx {
380d668e8bfSHyungwon Hwang 	RESET_TYPE,
381d668e8bfSHyungwon Hwang 	PLL_TIMER,
382d668e8bfSHyungwon Hwang 	STOP_STATE_CNT,
383d668e8bfSHyungwon Hwang 	PHYCTRL_ULPS_EXIT,
384d668e8bfSHyungwon Hwang 	PHYCTRL_VREG_LP,
385d668e8bfSHyungwon Hwang 	PHYCTRL_SLEW_UP,
386d668e8bfSHyungwon Hwang 	PHYTIMING_LPX,
387d668e8bfSHyungwon Hwang 	PHYTIMING_HS_EXIT,
388d668e8bfSHyungwon Hwang 	PHYTIMING_CLK_PREPARE,
389d668e8bfSHyungwon Hwang 	PHYTIMING_CLK_ZERO,
390d668e8bfSHyungwon Hwang 	PHYTIMING_CLK_POST,
391d668e8bfSHyungwon Hwang 	PHYTIMING_CLK_TRAIL,
392d668e8bfSHyungwon Hwang 	PHYTIMING_HS_PREPARE,
393d668e8bfSHyungwon Hwang 	PHYTIMING_HS_ZERO,
394d668e8bfSHyungwon Hwang 	PHYTIMING_HS_TRAIL
395d668e8bfSHyungwon Hwang };
396d668e8bfSHyungwon Hwang 
397b115361eSAndrzej Hajda static const unsigned int reg_values[] = {
398d668e8bfSHyungwon Hwang 	[RESET_TYPE] = DSIM_SWRST,
399d668e8bfSHyungwon Hwang 	[PLL_TIMER] = 500,
400d668e8bfSHyungwon Hwang 	[STOP_STATE_CNT] = 0xf,
401d668e8bfSHyungwon Hwang 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
402d668e8bfSHyungwon Hwang 	[PHYCTRL_VREG_LP] = 0,
403d668e8bfSHyungwon Hwang 	[PHYCTRL_SLEW_UP] = 0,
404d668e8bfSHyungwon Hwang 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
405d668e8bfSHyungwon Hwang 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
406d668e8bfSHyungwon Hwang 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
407d668e8bfSHyungwon Hwang 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
408d668e8bfSHyungwon Hwang 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
409d668e8bfSHyungwon Hwang 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
410d668e8bfSHyungwon Hwang 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
411d668e8bfSHyungwon Hwang 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
412d668e8bfSHyungwon Hwang 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
413d668e8bfSHyungwon Hwang };
414d668e8bfSHyungwon Hwang 
415b115361eSAndrzej Hajda static const unsigned int exynos5422_reg_values[] = {
416fdc2e108SChanho Park 	[RESET_TYPE] = DSIM_SWRST,
417fdc2e108SChanho Park 	[PLL_TIMER] = 500,
418fdc2e108SChanho Park 	[STOP_STATE_CNT] = 0xf,
419fdc2e108SChanho Park 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
420fdc2e108SChanho Park 	[PHYCTRL_VREG_LP] = 0,
421fdc2e108SChanho Park 	[PHYCTRL_SLEW_UP] = 0,
422fdc2e108SChanho Park 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
423fdc2e108SChanho Park 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
424fdc2e108SChanho Park 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
425fdc2e108SChanho Park 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
426fdc2e108SChanho Park 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
427fdc2e108SChanho Park 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
428fdc2e108SChanho Park 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
429fdc2e108SChanho Park 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
430fdc2e108SChanho Park 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
431fdc2e108SChanho Park };
432fdc2e108SChanho Park 
433b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_values[] = {
434e6f988a4SHyungwon Hwang 	[RESET_TYPE] = DSIM_FUNCRST,
435e6f988a4SHyungwon Hwang 	[PLL_TIMER] = 22200,
436e6f988a4SHyungwon Hwang 	[STOP_STATE_CNT] = 0xa,
437e6f988a4SHyungwon Hwang 	[PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
438e6f988a4SHyungwon Hwang 	[PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
439e6f988a4SHyungwon Hwang 	[PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
440e6f988a4SHyungwon Hwang 	[PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
441e6f988a4SHyungwon Hwang 	[PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
442e6f988a4SHyungwon Hwang 	[PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
443e6f988a4SHyungwon Hwang 	[PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
444e6f988a4SHyungwon Hwang 	[PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
445e6f988a4SHyungwon Hwang 	[PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
446e6f988a4SHyungwon Hwang 	[PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
447e6f988a4SHyungwon Hwang 	[PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
448e6f988a4SHyungwon Hwang 	[PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
449e6f988a4SHyungwon Hwang };
450e6f988a4SHyungwon Hwang 
451b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
452d668e8bfSHyungwon Hwang 	.reg_ofs = exynos_reg_ofs,
453473462a1SInki Dae 	.plltmr_reg = 0x50,
454473462a1SInki Dae 	.has_freqband = 1,
455473462a1SInki Dae 	.has_clklane_stop = 1,
456d668e8bfSHyungwon Hwang 	.num_clks = 2,
457d668e8bfSHyungwon Hwang 	.max_freq = 1000,
458d668e8bfSHyungwon Hwang 	.wait_for_reset = 1,
459d668e8bfSHyungwon Hwang 	.num_bits_resol = 11,
460d668e8bfSHyungwon Hwang 	.reg_values = reg_values,
461473462a1SInki Dae };
462473462a1SInki Dae 
463b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
464d668e8bfSHyungwon Hwang 	.reg_ofs = exynos_reg_ofs,
4659a320415SYoungJun Cho 	.plltmr_reg = 0x50,
4669a320415SYoungJun Cho 	.has_freqband = 1,
46778d3a8c6SInki Dae 	.has_clklane_stop = 1,
468d668e8bfSHyungwon Hwang 	.num_clks = 2,
469d668e8bfSHyungwon Hwang 	.max_freq = 1000,
470d668e8bfSHyungwon Hwang 	.wait_for_reset = 1,
471d668e8bfSHyungwon Hwang 	.num_bits_resol = 11,
472d668e8bfSHyungwon Hwang 	.reg_values = reg_values,
4739a320415SYoungJun Cho };
4749a320415SYoungJun Cho 
475b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
476d668e8bfSHyungwon Hwang 	.reg_ofs = exynos_reg_ofs,
4779a320415SYoungJun Cho 	.plltmr_reg = 0x58,
478d668e8bfSHyungwon Hwang 	.num_clks = 2,
479d668e8bfSHyungwon Hwang 	.max_freq = 1000,
480d668e8bfSHyungwon Hwang 	.wait_for_reset = 1,
481d668e8bfSHyungwon Hwang 	.num_bits_resol = 11,
482d668e8bfSHyungwon Hwang 	.reg_values = reg_values,
4839a320415SYoungJun Cho };
4849a320415SYoungJun Cho 
485b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = {
486e6f988a4SHyungwon Hwang 	.reg_ofs = exynos5433_reg_ofs,
487e6f988a4SHyungwon Hwang 	.plltmr_reg = 0xa0,
488e6f988a4SHyungwon Hwang 	.has_clklane_stop = 1,
489e6f988a4SHyungwon Hwang 	.num_clks = 5,
490e6f988a4SHyungwon Hwang 	.max_freq = 1500,
491e6f988a4SHyungwon Hwang 	.wait_for_reset = 0,
492e6f988a4SHyungwon Hwang 	.num_bits_resol = 12,
493e6f988a4SHyungwon Hwang 	.reg_values = exynos5433_reg_values,
494e6f988a4SHyungwon Hwang };
495e6f988a4SHyungwon Hwang 
496b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = {
497fdc2e108SChanho Park 	.reg_ofs = exynos5433_reg_ofs,
498fdc2e108SChanho Park 	.plltmr_reg = 0xa0,
499fdc2e108SChanho Park 	.has_clklane_stop = 1,
500fdc2e108SChanho Park 	.num_clks = 2,
501fdc2e108SChanho Park 	.max_freq = 1500,
502fdc2e108SChanho Park 	.wait_for_reset = 1,
503fdc2e108SChanho Park 	.num_bits_resol = 12,
504fdc2e108SChanho Park 	.reg_values = exynos5422_reg_values,
505fdc2e108SChanho Park };
506fdc2e108SChanho Park 
507b115361eSAndrzej Hajda static const struct of_device_id exynos_dsi_of_match[] = {
508473462a1SInki Dae 	{ .compatible = "samsung,exynos3250-mipi-dsi",
509473462a1SInki Dae 	  .data = &exynos3_dsi_driver_data },
5109a320415SYoungJun Cho 	{ .compatible = "samsung,exynos4210-mipi-dsi",
5119a320415SYoungJun Cho 	  .data = &exynos4_dsi_driver_data },
5129a320415SYoungJun Cho 	{ .compatible = "samsung,exynos5410-mipi-dsi",
5139a320415SYoungJun Cho 	  .data = &exynos5_dsi_driver_data },
514fdc2e108SChanho Park 	{ .compatible = "samsung,exynos5422-mipi-dsi",
515fdc2e108SChanho Park 	  .data = &exynos5422_dsi_driver_data },
516e6f988a4SHyungwon Hwang 	{ .compatible = "samsung,exynos5433-mipi-dsi",
517e6f988a4SHyungwon Hwang 	  .data = &exynos5433_dsi_driver_data },
5189a320415SYoungJun Cho 	{ }
5199a320415SYoungJun Cho };
5209a320415SYoungJun Cho 
5217eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
5227eb8f069SAndrzej Hajda {
5237eb8f069SAndrzej Hajda 	if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
5247eb8f069SAndrzej Hajda 		return;
5257eb8f069SAndrzej Hajda 
5267eb8f069SAndrzej Hajda 	dev_err(dsi->dev, "timeout waiting for reset\n");
5277eb8f069SAndrzej Hajda }
5287eb8f069SAndrzej Hajda 
5297eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi)
5307eb8f069SAndrzej Hajda {
531bb32e408SAndrzej Hajda 	u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
532ba12ac2bSHyungwon Hwang 
5337eb8f069SAndrzej Hajda 	reinit_completion(&dsi->completed);
534bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val);
5357eb8f069SAndrzej Hajda }
5367eb8f069SAndrzej Hajda 
5377eb8f069SAndrzej Hajda #ifndef MHZ
5387eb8f069SAndrzej Hajda #define MHZ	(1000*1000)
5397eb8f069SAndrzej Hajda #endif
5407eb8f069SAndrzej Hajda 
5417eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
5427eb8f069SAndrzej Hajda 		unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
5437eb8f069SAndrzej Hajda {
5442154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
5457eb8f069SAndrzej Hajda 	unsigned long best_freq = 0;
5467eb8f069SAndrzej Hajda 	u32 min_delta = 0xffffffff;
5477eb8f069SAndrzej Hajda 	u8 p_min, p_max;
5487eb8f069SAndrzej Hajda 	u8 _p, uninitialized_var(best_p);
5497eb8f069SAndrzej Hajda 	u16 _m, uninitialized_var(best_m);
5507eb8f069SAndrzej Hajda 	u8 _s, uninitialized_var(best_s);
5517eb8f069SAndrzej Hajda 
5527eb8f069SAndrzej Hajda 	p_min = DIV_ROUND_UP(fin, (12 * MHZ));
5537eb8f069SAndrzej Hajda 	p_max = fin / (6 * MHZ);
5547eb8f069SAndrzej Hajda 
5557eb8f069SAndrzej Hajda 	for (_p = p_min; _p <= p_max; ++_p) {
5567eb8f069SAndrzej Hajda 		for (_s = 0; _s <= 5; ++_s) {
5577eb8f069SAndrzej Hajda 			u64 tmp;
5587eb8f069SAndrzej Hajda 			u32 delta;
5597eb8f069SAndrzej Hajda 
5607eb8f069SAndrzej Hajda 			tmp = (u64)fout * (_p << _s);
5617eb8f069SAndrzej Hajda 			do_div(tmp, fin);
5627eb8f069SAndrzej Hajda 			_m = tmp;
5637eb8f069SAndrzej Hajda 			if (_m < 41 || _m > 125)
5647eb8f069SAndrzej Hajda 				continue;
5657eb8f069SAndrzej Hajda 
5667eb8f069SAndrzej Hajda 			tmp = (u64)_m * fin;
5677eb8f069SAndrzej Hajda 			do_div(tmp, _p);
568d668e8bfSHyungwon Hwang 			if (tmp < 500 * MHZ ||
569d668e8bfSHyungwon Hwang 					tmp > driver_data->max_freq * MHZ)
5707eb8f069SAndrzej Hajda 				continue;
5717eb8f069SAndrzej Hajda 
5727eb8f069SAndrzej Hajda 			tmp = (u64)_m * fin;
5737eb8f069SAndrzej Hajda 			do_div(tmp, _p << _s);
5747eb8f069SAndrzej Hajda 
5757eb8f069SAndrzej Hajda 			delta = abs(fout - tmp);
5767eb8f069SAndrzej Hajda 			if (delta < min_delta) {
5777eb8f069SAndrzej Hajda 				best_p = _p;
5787eb8f069SAndrzej Hajda 				best_m = _m;
5797eb8f069SAndrzej Hajda 				best_s = _s;
5807eb8f069SAndrzej Hajda 				min_delta = delta;
5817eb8f069SAndrzej Hajda 				best_freq = tmp;
5827eb8f069SAndrzej Hajda 			}
5837eb8f069SAndrzej Hajda 		}
5847eb8f069SAndrzej Hajda 	}
5857eb8f069SAndrzej Hajda 
5867eb8f069SAndrzej Hajda 	if (best_freq) {
5877eb8f069SAndrzej Hajda 		*p = best_p;
5887eb8f069SAndrzej Hajda 		*m = best_m;
5897eb8f069SAndrzej Hajda 		*s = best_s;
5907eb8f069SAndrzej Hajda 	}
5917eb8f069SAndrzej Hajda 
5927eb8f069SAndrzej Hajda 	return best_freq;
5937eb8f069SAndrzej Hajda }
5947eb8f069SAndrzej Hajda 
5957eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
5967eb8f069SAndrzej Hajda 					unsigned long freq)
5977eb8f069SAndrzej Hajda {
5982154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
5997eb8f069SAndrzej Hajda 	unsigned long fin, fout;
6009a320415SYoungJun Cho 	int timeout;
6017eb8f069SAndrzej Hajda 	u8 p, s;
6027eb8f069SAndrzej Hajda 	u16 m;
6037eb8f069SAndrzej Hajda 	u32 reg;
6047eb8f069SAndrzej Hajda 
60526269af9SHyungwon Hwang 	fin = dsi->pll_clk_rate;
6067eb8f069SAndrzej Hajda 	fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
6077eb8f069SAndrzej Hajda 	if (!fout) {
6087eb8f069SAndrzej Hajda 		dev_err(dsi->dev,
6097eb8f069SAndrzej Hajda 			"failed to find PLL PMS for requested frequency\n");
6108525b5ecSYoungJun Cho 		return 0;
6117eb8f069SAndrzej Hajda 	}
6129a320415SYoungJun Cho 	dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
6139a320415SYoungJun Cho 
614d668e8bfSHyungwon Hwang 	writel(driver_data->reg_values[PLL_TIMER],
615d668e8bfSHyungwon Hwang 			dsi->reg_base + driver_data->plltmr_reg);
6169a320415SYoungJun Cho 
6179a320415SYoungJun Cho 	reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
6189a320415SYoungJun Cho 
6199a320415SYoungJun Cho 	if (driver_data->has_freqband) {
6209a320415SYoungJun Cho 		static const unsigned long freq_bands[] = {
6219a320415SYoungJun Cho 			100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
6229a320415SYoungJun Cho 			270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
6239a320415SYoungJun Cho 			510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
6249a320415SYoungJun Cho 			770 * MHZ, 870 * MHZ, 950 * MHZ,
6259a320415SYoungJun Cho 		};
6269a320415SYoungJun Cho 		int band;
6277eb8f069SAndrzej Hajda 
6287eb8f069SAndrzej Hajda 		for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
6297eb8f069SAndrzej Hajda 			if (fout < freq_bands[band])
6307eb8f069SAndrzej Hajda 				break;
6317eb8f069SAndrzej Hajda 
6329a320415SYoungJun Cho 		dev_dbg(dsi->dev, "band %d\n", band);
6337eb8f069SAndrzej Hajda 
6349a320415SYoungJun Cho 		reg |= DSIM_FREQ_BAND(band);
6359a320415SYoungJun Cho 	}
6367eb8f069SAndrzej Hajda 
637bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
6387eb8f069SAndrzej Hajda 
6397eb8f069SAndrzej Hajda 	timeout = 1000;
6407eb8f069SAndrzej Hajda 	do {
6417eb8f069SAndrzej Hajda 		if (timeout-- == 0) {
6427eb8f069SAndrzej Hajda 			dev_err(dsi->dev, "PLL failed to stabilize\n");
6438525b5ecSYoungJun Cho 			return 0;
6447eb8f069SAndrzej Hajda 		}
645bb32e408SAndrzej Hajda 		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
6467eb8f069SAndrzej Hajda 	} while ((reg & DSIM_PLL_STABLE) == 0);
6477eb8f069SAndrzej Hajda 
6487eb8f069SAndrzej Hajda 	return fout;
6497eb8f069SAndrzej Hajda }
6507eb8f069SAndrzej Hajda 
6517eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
6527eb8f069SAndrzej Hajda {
6537eb8f069SAndrzej Hajda 	unsigned long hs_clk, byte_clk, esc_clk;
6547eb8f069SAndrzej Hajda 	unsigned long esc_div;
6557eb8f069SAndrzej Hajda 	u32 reg;
6567eb8f069SAndrzej Hajda 
6577eb8f069SAndrzej Hajda 	hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
6587eb8f069SAndrzej Hajda 	if (!hs_clk) {
6597eb8f069SAndrzej Hajda 		dev_err(dsi->dev, "failed to configure DSI PLL\n");
6607eb8f069SAndrzej Hajda 		return -EFAULT;
6617eb8f069SAndrzej Hajda 	}
6627eb8f069SAndrzej Hajda 
6637eb8f069SAndrzej Hajda 	byte_clk = hs_clk / 8;
6647eb8f069SAndrzej Hajda 	esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
6657eb8f069SAndrzej Hajda 	esc_clk = byte_clk / esc_div;
6667eb8f069SAndrzej Hajda 
6677eb8f069SAndrzej Hajda 	if (esc_clk > 20 * MHZ) {
6687eb8f069SAndrzej Hajda 		++esc_div;
6697eb8f069SAndrzej Hajda 		esc_clk = byte_clk / esc_div;
6707eb8f069SAndrzej Hajda 	}
6717eb8f069SAndrzej Hajda 
6727eb8f069SAndrzej Hajda 	dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
6737eb8f069SAndrzej Hajda 		hs_clk, byte_clk, esc_clk);
6747eb8f069SAndrzej Hajda 
675bb32e408SAndrzej Hajda 	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
6767eb8f069SAndrzej Hajda 	reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
6777eb8f069SAndrzej Hajda 			| DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
6787eb8f069SAndrzej Hajda 			| DSIM_BYTE_CLK_SRC_MASK);
6797eb8f069SAndrzej Hajda 	reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
6807eb8f069SAndrzej Hajda 			| DSIM_ESC_PRESCALER(esc_div)
6817eb8f069SAndrzej Hajda 			| DSIM_LANE_ESC_CLK_EN_CLK
6827eb8f069SAndrzej Hajda 			| DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
6837eb8f069SAndrzej Hajda 			| DSIM_BYTE_CLK_SRC(0)
6847eb8f069SAndrzej Hajda 			| DSIM_TX_REQUEST_HSCLK;
685bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
6867eb8f069SAndrzej Hajda 
6877eb8f069SAndrzej Hajda 	return 0;
6887eb8f069SAndrzej Hajda }
6897eb8f069SAndrzej Hajda 
6909a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
6919a320415SYoungJun Cho {
6922154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
693b115361eSAndrzej Hajda 	const unsigned int *reg_values = driver_data->reg_values;
6949a320415SYoungJun Cho 	u32 reg;
6959a320415SYoungJun Cho 
6969a320415SYoungJun Cho 	if (driver_data->has_freqband)
6979a320415SYoungJun Cho 		return;
6989a320415SYoungJun Cho 
6999a320415SYoungJun Cho 	/* B D-PHY: D-PHY Master & Slave Analog Block control */
700d668e8bfSHyungwon Hwang 	reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
701d668e8bfSHyungwon Hwang 		reg_values[PHYCTRL_SLEW_UP];
702bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg);
7039a320415SYoungJun Cho 
7049a320415SYoungJun Cho 	/*
7059a320415SYoungJun Cho 	 * T LPX: Transmitted length of any Low-Power state period
7069a320415SYoungJun Cho 	 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
7079a320415SYoungJun Cho 	 *	burst
7089a320415SYoungJun Cho 	 */
709d668e8bfSHyungwon Hwang 	reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT];
710bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg);
7119a320415SYoungJun Cho 
7129a320415SYoungJun Cho 	/*
7139a320415SYoungJun Cho 	 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
7149a320415SYoungJun Cho 	 *	Line state immediately before the HS-0 Line state starting the
7159a320415SYoungJun Cho 	 *	HS transmission
7169a320415SYoungJun Cho 	 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
7179a320415SYoungJun Cho 	 *	transmitting the Clock.
7189a320415SYoungJun Cho 	 * T CLK_POST: Time that the transmitter continues to send HS clock
7199a320415SYoungJun Cho 	 *	after the last associated Data Lane has transitioned to LP Mode
7209a320415SYoungJun Cho 	 *	Interval is defined as the period from the end of T HS-TRAIL to
7219a320415SYoungJun Cho 	 *	the beginning of T CLK-TRAIL
7229a320415SYoungJun Cho 	 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
7239a320415SYoungJun Cho 	 *	the last payload clock bit of a HS transmission burst
7249a320415SYoungJun Cho 	 */
725d668e8bfSHyungwon Hwang 	reg = reg_values[PHYTIMING_CLK_PREPARE] |
726d668e8bfSHyungwon Hwang 		reg_values[PHYTIMING_CLK_ZERO] |
727d668e8bfSHyungwon Hwang 		reg_values[PHYTIMING_CLK_POST] |
728d668e8bfSHyungwon Hwang 		reg_values[PHYTIMING_CLK_TRAIL];
729d668e8bfSHyungwon Hwang 
730bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg);
7319a320415SYoungJun Cho 
7329a320415SYoungJun Cho 	/*
7339a320415SYoungJun Cho 	 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
7349a320415SYoungJun Cho 	 *	Line state immediately before the HS-0 Line state starting the
7359a320415SYoungJun Cho 	 *	HS transmission
7369a320415SYoungJun Cho 	 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
7379a320415SYoungJun Cho 	 *	transmitting the Sync sequence.
7389a320415SYoungJun Cho 	 * T HS-TRAIL: Time that the transmitter drives the flipped differential
7399a320415SYoungJun Cho 	 *	state after last payload data bit of a HS transmission burst
7409a320415SYoungJun Cho 	 */
741d668e8bfSHyungwon Hwang 	reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] |
742d668e8bfSHyungwon Hwang 		reg_values[PHYTIMING_HS_TRAIL];
743bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg);
7449a320415SYoungJun Cho }
7459a320415SYoungJun Cho 
7467eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
7477eb8f069SAndrzej Hajda {
7487eb8f069SAndrzej Hajda 	u32 reg;
7497eb8f069SAndrzej Hajda 
750bb32e408SAndrzej Hajda 	reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG);
7517eb8f069SAndrzej Hajda 	reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
7527eb8f069SAndrzej Hajda 			| DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
753bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg);
7547eb8f069SAndrzej Hajda 
755bb32e408SAndrzej Hajda 	reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG);
7567eb8f069SAndrzej Hajda 	reg &= ~DSIM_PLL_EN;
757bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg);
7587eb8f069SAndrzej Hajda }
7597eb8f069SAndrzej Hajda 
760e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane)
761e6f988a4SHyungwon Hwang {
762bb32e408SAndrzej Hajda 	u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG);
763e6f988a4SHyungwon Hwang 	reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
764e6f988a4SHyungwon Hwang 			DSIM_LANE_EN(lane));
765bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
766e6f988a4SHyungwon Hwang }
767e6f988a4SHyungwon Hwang 
7687eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi)
7697eb8f069SAndrzej Hajda {
7702154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
7717eb8f069SAndrzej Hajda 	int timeout;
7727eb8f069SAndrzej Hajda 	u32 reg;
7737eb8f069SAndrzej Hajda 	u32 lanes_mask;
7747eb8f069SAndrzej Hajda 
7757eb8f069SAndrzej Hajda 	/* Initialize FIFO pointers */
776bb32e408SAndrzej Hajda 	reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
7777eb8f069SAndrzej Hajda 	reg &= ~0x1f;
778bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
7797eb8f069SAndrzej Hajda 
7807eb8f069SAndrzej Hajda 	usleep_range(9000, 11000);
7817eb8f069SAndrzej Hajda 
7827eb8f069SAndrzej Hajda 	reg |= 0x1f;
783bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg);
7847eb8f069SAndrzej Hajda 	usleep_range(9000, 11000);
7857eb8f069SAndrzej Hajda 
7867eb8f069SAndrzej Hajda 	/* DSI configuration */
7877eb8f069SAndrzej Hajda 	reg = 0;
7887eb8f069SAndrzej Hajda 
7892f36e33aSYoungJun Cho 	/*
7902f36e33aSYoungJun Cho 	 * The first bit of mode_flags specifies display configuration.
7912f36e33aSYoungJun Cho 	 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
7922f36e33aSYoungJun Cho 	 * mode, otherwise it will support command mode.
7932f36e33aSYoungJun Cho 	 */
7947eb8f069SAndrzej Hajda 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
7957eb8f069SAndrzej Hajda 		reg |= DSIM_VIDEO_MODE;
7967eb8f069SAndrzej Hajda 
7972f36e33aSYoungJun Cho 		/*
7982f36e33aSYoungJun Cho 		 * The user manual describes that following bits are ignored in
7992f36e33aSYoungJun Cho 		 * command mode.
8002f36e33aSYoungJun Cho 		 */
8017eb8f069SAndrzej Hajda 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
8027eb8f069SAndrzej Hajda 			reg |= DSIM_MFLUSH_VS;
8037eb8f069SAndrzej Hajda 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
8047eb8f069SAndrzej Hajda 			reg |= DSIM_SYNC_INFORM;
8057eb8f069SAndrzej Hajda 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
8067eb8f069SAndrzej Hajda 			reg |= DSIM_BURST_MODE;
8077eb8f069SAndrzej Hajda 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
8087eb8f069SAndrzej Hajda 			reg |= DSIM_AUTO_MODE;
8097eb8f069SAndrzej Hajda 		if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
8107eb8f069SAndrzej Hajda 			reg |= DSIM_HSE_MODE;
8117eb8f069SAndrzej Hajda 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
8127eb8f069SAndrzej Hajda 			reg |= DSIM_HFP_MODE;
8137eb8f069SAndrzej Hajda 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
8147eb8f069SAndrzej Hajda 			reg |= DSIM_HBP_MODE;
8157eb8f069SAndrzej Hajda 		if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
8167eb8f069SAndrzej Hajda 			reg |= DSIM_HSA_MODE;
8177eb8f069SAndrzej Hajda 	}
8187eb8f069SAndrzej Hajda 
8192f36e33aSYoungJun Cho 	if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
8202f36e33aSYoungJun Cho 		reg |= DSIM_EOT_DISABLE;
8212f36e33aSYoungJun Cho 
8227eb8f069SAndrzej Hajda 	switch (dsi->format) {
8237eb8f069SAndrzej Hajda 	case MIPI_DSI_FMT_RGB888:
8247eb8f069SAndrzej Hajda 		reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
8257eb8f069SAndrzej Hajda 		break;
8267eb8f069SAndrzej Hajda 	case MIPI_DSI_FMT_RGB666:
8277eb8f069SAndrzej Hajda 		reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
8287eb8f069SAndrzej Hajda 		break;
8297eb8f069SAndrzej Hajda 	case MIPI_DSI_FMT_RGB666_PACKED:
8307eb8f069SAndrzej Hajda 		reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
8317eb8f069SAndrzej Hajda 		break;
8327eb8f069SAndrzej Hajda 	case MIPI_DSI_FMT_RGB565:
8337eb8f069SAndrzej Hajda 		reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
8347eb8f069SAndrzej Hajda 		break;
8357eb8f069SAndrzej Hajda 	default:
8367eb8f069SAndrzej Hajda 		dev_err(dsi->dev, "invalid pixel format\n");
8377eb8f069SAndrzej Hajda 		return -EINVAL;
8387eb8f069SAndrzej Hajda 	}
8397eb8f069SAndrzej Hajda 
84078d3a8c6SInki Dae 	/*
84178d3a8c6SInki Dae 	 * Use non-continuous clock mode if the periparal wants and
84278d3a8c6SInki Dae 	 * host controller supports
84378d3a8c6SInki Dae 	 *
84478d3a8c6SInki Dae 	 * In non-continous clock mode, host controller will turn off
84578d3a8c6SInki Dae 	 * the HS clock between high-speed transmissions to reduce
84678d3a8c6SInki Dae 	 * power consumption.
84778d3a8c6SInki Dae 	 */
84878d3a8c6SInki Dae 	if (driver_data->has_clklane_stop &&
84978d3a8c6SInki Dae 			dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
85078d3a8c6SInki Dae 		reg |= DSIM_CLKLANE_STOP;
85178d3a8c6SInki Dae 	}
852bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg);
853e6f988a4SHyungwon Hwang 
854e6f988a4SHyungwon Hwang 	lanes_mask = BIT(dsi->lanes) - 1;
855e6f988a4SHyungwon Hwang 	exynos_dsi_enable_lane(dsi, lanes_mask);
85678d3a8c6SInki Dae 
8577eb8f069SAndrzej Hajda 	/* Check clock and data lane state are stop state */
8587eb8f069SAndrzej Hajda 	timeout = 100;
8597eb8f069SAndrzej Hajda 	do {
8607eb8f069SAndrzej Hajda 		if (timeout-- == 0) {
8617eb8f069SAndrzej Hajda 			dev_err(dsi->dev, "waiting for bus lanes timed out\n");
8627eb8f069SAndrzej Hajda 			return -EFAULT;
8637eb8f069SAndrzej Hajda 		}
8647eb8f069SAndrzej Hajda 
865bb32e408SAndrzej Hajda 		reg = exynos_dsi_read(dsi, DSIM_STATUS_REG);
8667eb8f069SAndrzej Hajda 		if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
8677eb8f069SAndrzej Hajda 		    != DSIM_STOP_STATE_DAT(lanes_mask))
8687eb8f069SAndrzej Hajda 			continue;
8697eb8f069SAndrzej Hajda 	} while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
8707eb8f069SAndrzej Hajda 
871bb32e408SAndrzej Hajda 	reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
8727eb8f069SAndrzej Hajda 	reg &= ~DSIM_STOP_STATE_CNT_MASK;
873d668e8bfSHyungwon Hwang 	reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
874bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg);
8757eb8f069SAndrzej Hajda 
8767eb8f069SAndrzej Hajda 	reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
877bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg);
8787eb8f069SAndrzej Hajda 
8797eb8f069SAndrzej Hajda 	return 0;
8807eb8f069SAndrzej Hajda }
8817eb8f069SAndrzej Hajda 
8827eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
8837eb8f069SAndrzej Hajda {
884e8929999SAndrzej Hajda 	struct drm_display_mode *m = &dsi->encoder.crtc->state->adjusted_mode;
885d668e8bfSHyungwon Hwang 	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
8867eb8f069SAndrzej Hajda 	u32 reg;
8877eb8f069SAndrzej Hajda 
8887eb8f069SAndrzej Hajda 	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
8897eb8f069SAndrzej Hajda 		reg = DSIM_CMD_ALLOW(0xf)
890e8929999SAndrzej Hajda 			| DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
891e8929999SAndrzej Hajda 			| DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
892bb32e408SAndrzej Hajda 		exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg);
8937eb8f069SAndrzej Hajda 
894e8929999SAndrzej Hajda 		reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
895e8929999SAndrzej Hajda 			| DSIM_MAIN_HBP(m->htotal - m->hsync_end);
896bb32e408SAndrzej Hajda 		exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg);
8977eb8f069SAndrzej Hajda 
898e8929999SAndrzej Hajda 		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
899e8929999SAndrzej Hajda 			| DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
900bb32e408SAndrzej Hajda 		exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg);
9017eb8f069SAndrzej Hajda 	}
902e8929999SAndrzej Hajda 	reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
903e8929999SAndrzej Hajda 		DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
9047eb8f069SAndrzej Hajda 
905bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
9067eb8f069SAndrzej Hajda 
907e8929999SAndrzej Hajda 	dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
9087eb8f069SAndrzej Hajda }
9097eb8f069SAndrzej Hajda 
9107eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
9117eb8f069SAndrzej Hajda {
9127eb8f069SAndrzej Hajda 	u32 reg;
9137eb8f069SAndrzej Hajda 
914bb32e408SAndrzej Hajda 	reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG);
9157eb8f069SAndrzej Hajda 	if (enable)
9167eb8f069SAndrzej Hajda 		reg |= DSIM_MAIN_STAND_BY;
9177eb8f069SAndrzej Hajda 	else
9187eb8f069SAndrzej Hajda 		reg &= ~DSIM_MAIN_STAND_BY;
919bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg);
9207eb8f069SAndrzej Hajda }
9217eb8f069SAndrzej Hajda 
9227eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
9237eb8f069SAndrzej Hajda {
9247eb8f069SAndrzej Hajda 	int timeout = 2000;
9257eb8f069SAndrzej Hajda 
9267eb8f069SAndrzej Hajda 	do {
927bb32e408SAndrzej Hajda 		u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG);
9287eb8f069SAndrzej Hajda 
9297eb8f069SAndrzej Hajda 		if (!(reg & DSIM_SFR_HEADER_FULL))
9307eb8f069SAndrzej Hajda 			return 0;
9317eb8f069SAndrzej Hajda 
9327eb8f069SAndrzej Hajda 		if (!cond_resched())
9337eb8f069SAndrzej Hajda 			usleep_range(950, 1050);
9347eb8f069SAndrzej Hajda 	} while (--timeout);
9357eb8f069SAndrzej Hajda 
9367eb8f069SAndrzej Hajda 	return -ETIMEDOUT;
9377eb8f069SAndrzej Hajda }
9387eb8f069SAndrzej Hajda 
9397eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
9407eb8f069SAndrzej Hajda {
941bb32e408SAndrzej Hajda 	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
9427eb8f069SAndrzej Hajda 
9437eb8f069SAndrzej Hajda 	if (lpm)
9447eb8f069SAndrzej Hajda 		v |= DSIM_CMD_LPDT_LP;
9457eb8f069SAndrzej Hajda 	else
9467eb8f069SAndrzej Hajda 		v &= ~DSIM_CMD_LPDT_LP;
9477eb8f069SAndrzej Hajda 
948bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
9497eb8f069SAndrzej Hajda }
9507eb8f069SAndrzej Hajda 
9517eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
9527eb8f069SAndrzej Hajda {
953bb32e408SAndrzej Hajda 	u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG);
9547eb8f069SAndrzej Hajda 	v |= DSIM_FORCE_BTA;
955bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v);
9567eb8f069SAndrzej Hajda }
9577eb8f069SAndrzej Hajda 
9587eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
9597eb8f069SAndrzej Hajda 					struct exynos_dsi_transfer *xfer)
9607eb8f069SAndrzej Hajda {
9617eb8f069SAndrzej Hajda 	struct device *dev = dsi->dev;
9626c81e96dSAndrzej Hajda 	struct mipi_dsi_packet *pkt = &xfer->packet;
9636c81e96dSAndrzej Hajda 	const u8 *payload = pkt->payload + xfer->tx_done;
9646c81e96dSAndrzej Hajda 	u16 length = pkt->payload_length - xfer->tx_done;
9657eb8f069SAndrzej Hajda 	bool first = !xfer->tx_done;
9667eb8f069SAndrzej Hajda 	u32 reg;
9677eb8f069SAndrzej Hajda 
9689cdf0ed2SKrzysztof Kozlowski 	dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
9696c81e96dSAndrzej Hajda 		xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
9707eb8f069SAndrzej Hajda 
9717eb8f069SAndrzej Hajda 	if (length > DSI_TX_FIFO_SIZE)
9727eb8f069SAndrzej Hajda 		length = DSI_TX_FIFO_SIZE;
9737eb8f069SAndrzej Hajda 
9747eb8f069SAndrzej Hajda 	xfer->tx_done += length;
9757eb8f069SAndrzej Hajda 
9767eb8f069SAndrzej Hajda 	/* Send payload */
9777eb8f069SAndrzej Hajda 	while (length >= 4) {
9786c81e96dSAndrzej Hajda 		reg = get_unaligned_le32(payload);
979bb32e408SAndrzej Hajda 		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
9807eb8f069SAndrzej Hajda 		payload += 4;
9817eb8f069SAndrzej Hajda 		length -= 4;
9827eb8f069SAndrzej Hajda 	}
9837eb8f069SAndrzej Hajda 
9847eb8f069SAndrzej Hajda 	reg = 0;
9857eb8f069SAndrzej Hajda 	switch (length) {
9867eb8f069SAndrzej Hajda 	case 3:
9877eb8f069SAndrzej Hajda 		reg |= payload[2] << 16;
9887eb8f069SAndrzej Hajda 		/* Fall through */
9897eb8f069SAndrzej Hajda 	case 2:
9907eb8f069SAndrzej Hajda 		reg |= payload[1] << 8;
9917eb8f069SAndrzej Hajda 		/* Fall through */
9927eb8f069SAndrzej Hajda 	case 1:
9937eb8f069SAndrzej Hajda 		reg |= payload[0];
994bb32e408SAndrzej Hajda 		exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg);
9957eb8f069SAndrzej Hajda 		break;
9967eb8f069SAndrzej Hajda 	}
9977eb8f069SAndrzej Hajda 
9987eb8f069SAndrzej Hajda 	/* Send packet header */
9997eb8f069SAndrzej Hajda 	if (!first)
10007eb8f069SAndrzej Hajda 		return;
10017eb8f069SAndrzej Hajda 
10026c81e96dSAndrzej Hajda 	reg = get_unaligned_le32(pkt->header);
10037eb8f069SAndrzej Hajda 	if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
10047eb8f069SAndrzej Hajda 		dev_err(dev, "waiting for header FIFO timed out\n");
10057eb8f069SAndrzej Hajda 		return;
10067eb8f069SAndrzej Hajda 	}
10077eb8f069SAndrzej Hajda 
10087eb8f069SAndrzej Hajda 	if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
10097eb8f069SAndrzej Hajda 		 dsi->state & DSIM_STATE_CMD_LPM)) {
10107eb8f069SAndrzej Hajda 		exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
10117eb8f069SAndrzej Hajda 		dsi->state ^= DSIM_STATE_CMD_LPM;
10127eb8f069SAndrzej Hajda 	}
10137eb8f069SAndrzej Hajda 
1014bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg);
10157eb8f069SAndrzej Hajda 
10167eb8f069SAndrzej Hajda 	if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
10177eb8f069SAndrzej Hajda 		exynos_dsi_force_bta(dsi);
10187eb8f069SAndrzej Hajda }
10197eb8f069SAndrzej Hajda 
10207eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
10217eb8f069SAndrzej Hajda 					struct exynos_dsi_transfer *xfer)
10227eb8f069SAndrzej Hajda {
10237eb8f069SAndrzej Hajda 	u8 *payload = xfer->rx_payload + xfer->rx_done;
10247eb8f069SAndrzej Hajda 	bool first = !xfer->rx_done;
10257eb8f069SAndrzej Hajda 	struct device *dev = dsi->dev;
10267eb8f069SAndrzej Hajda 	u16 length;
10277eb8f069SAndrzej Hajda 	u32 reg;
10287eb8f069SAndrzej Hajda 
10297eb8f069SAndrzej Hajda 	if (first) {
1030bb32e408SAndrzej Hajda 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
10317eb8f069SAndrzej Hajda 
10327eb8f069SAndrzej Hajda 		switch (reg & 0x3f) {
10337eb8f069SAndrzej Hajda 		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
10347eb8f069SAndrzej Hajda 		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
10357eb8f069SAndrzej Hajda 			if (xfer->rx_len >= 2) {
10367eb8f069SAndrzej Hajda 				payload[1] = reg >> 16;
10377eb8f069SAndrzej Hajda 				++xfer->rx_done;
10387eb8f069SAndrzej Hajda 			}
10397eb8f069SAndrzej Hajda 			/* Fall through */
10407eb8f069SAndrzej Hajda 		case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
10417eb8f069SAndrzej Hajda 		case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
10427eb8f069SAndrzej Hajda 			payload[0] = reg >> 8;
10437eb8f069SAndrzej Hajda 			++xfer->rx_done;
10447eb8f069SAndrzej Hajda 			xfer->rx_len = xfer->rx_done;
10457eb8f069SAndrzej Hajda 			xfer->result = 0;
10467eb8f069SAndrzej Hajda 			goto clear_fifo;
10477eb8f069SAndrzej Hajda 		case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
10487eb8f069SAndrzej Hajda 			dev_err(dev, "DSI Error Report: 0x%04x\n",
10497eb8f069SAndrzej Hajda 				(reg >> 8) & 0xffff);
10507eb8f069SAndrzej Hajda 			xfer->result = 0;
10517eb8f069SAndrzej Hajda 			goto clear_fifo;
10527eb8f069SAndrzej Hajda 		}
10537eb8f069SAndrzej Hajda 
10547eb8f069SAndrzej Hajda 		length = (reg >> 8) & 0xffff;
10557eb8f069SAndrzej Hajda 		if (length > xfer->rx_len) {
10567eb8f069SAndrzej Hajda 			dev_err(dev,
10577eb8f069SAndrzej Hajda 				"response too long (%u > %u bytes), stripping\n",
10587eb8f069SAndrzej Hajda 				xfer->rx_len, length);
10597eb8f069SAndrzej Hajda 			length = xfer->rx_len;
10607eb8f069SAndrzej Hajda 		} else if (length < xfer->rx_len)
10617eb8f069SAndrzej Hajda 			xfer->rx_len = length;
10627eb8f069SAndrzej Hajda 	}
10637eb8f069SAndrzej Hajda 
10647eb8f069SAndrzej Hajda 	length = xfer->rx_len - xfer->rx_done;
10657eb8f069SAndrzej Hajda 	xfer->rx_done += length;
10667eb8f069SAndrzej Hajda 
10677eb8f069SAndrzej Hajda 	/* Receive payload */
10687eb8f069SAndrzej Hajda 	while (length >= 4) {
1069bb32e408SAndrzej Hajda 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
10707eb8f069SAndrzej Hajda 		payload[0] = (reg >>  0) & 0xff;
10717eb8f069SAndrzej Hajda 		payload[1] = (reg >>  8) & 0xff;
10727eb8f069SAndrzej Hajda 		payload[2] = (reg >> 16) & 0xff;
10737eb8f069SAndrzej Hajda 		payload[3] = (reg >> 24) & 0xff;
10747eb8f069SAndrzej Hajda 		payload += 4;
10757eb8f069SAndrzej Hajda 		length -= 4;
10767eb8f069SAndrzej Hajda 	}
10777eb8f069SAndrzej Hajda 
10787eb8f069SAndrzej Hajda 	if (length) {
1079bb32e408SAndrzej Hajda 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
10807eb8f069SAndrzej Hajda 		switch (length) {
10817eb8f069SAndrzej Hajda 		case 3:
10827eb8f069SAndrzej Hajda 			payload[2] = (reg >> 16) & 0xff;
10837eb8f069SAndrzej Hajda 			/* Fall through */
10847eb8f069SAndrzej Hajda 		case 2:
10857eb8f069SAndrzej Hajda 			payload[1] = (reg >> 8) & 0xff;
10867eb8f069SAndrzej Hajda 			/* Fall through */
10877eb8f069SAndrzej Hajda 		case 1:
10887eb8f069SAndrzej Hajda 			payload[0] = reg & 0xff;
10897eb8f069SAndrzej Hajda 		}
10907eb8f069SAndrzej Hajda 	}
10917eb8f069SAndrzej Hajda 
10927eb8f069SAndrzej Hajda 	if (xfer->rx_done == xfer->rx_len)
10937eb8f069SAndrzej Hajda 		xfer->result = 0;
10947eb8f069SAndrzej Hajda 
10957eb8f069SAndrzej Hajda clear_fifo:
10967eb8f069SAndrzej Hajda 	length = DSI_RX_FIFO_SIZE / 4;
10977eb8f069SAndrzej Hajda 	do {
1098bb32e408SAndrzej Hajda 		reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG);
10997eb8f069SAndrzej Hajda 		if (reg == DSI_RX_FIFO_EMPTY)
11007eb8f069SAndrzej Hajda 			break;
11017eb8f069SAndrzej Hajda 	} while (--length);
11027eb8f069SAndrzej Hajda }
11037eb8f069SAndrzej Hajda 
11047eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
11057eb8f069SAndrzej Hajda {
11067eb8f069SAndrzej Hajda 	unsigned long flags;
11077eb8f069SAndrzej Hajda 	struct exynos_dsi_transfer *xfer;
11087eb8f069SAndrzej Hajda 	bool start = false;
11097eb8f069SAndrzej Hajda 
11107eb8f069SAndrzej Hajda again:
11117eb8f069SAndrzej Hajda 	spin_lock_irqsave(&dsi->transfer_lock, flags);
11127eb8f069SAndrzej Hajda 
11137eb8f069SAndrzej Hajda 	if (list_empty(&dsi->transfer_list)) {
11147eb8f069SAndrzej Hajda 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
11157eb8f069SAndrzej Hajda 		return;
11167eb8f069SAndrzej Hajda 	}
11177eb8f069SAndrzej Hajda 
11187eb8f069SAndrzej Hajda 	xfer = list_first_entry(&dsi->transfer_list,
11197eb8f069SAndrzej Hajda 					struct exynos_dsi_transfer, list);
11207eb8f069SAndrzej Hajda 
11217eb8f069SAndrzej Hajda 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
11227eb8f069SAndrzej Hajda 
11236c81e96dSAndrzej Hajda 	if (xfer->packet.payload_length &&
11246c81e96dSAndrzej Hajda 	    xfer->tx_done == xfer->packet.payload_length)
11257eb8f069SAndrzej Hajda 		/* waiting for RX */
11267eb8f069SAndrzej Hajda 		return;
11277eb8f069SAndrzej Hajda 
11287eb8f069SAndrzej Hajda 	exynos_dsi_send_to_fifo(dsi, xfer);
11297eb8f069SAndrzej Hajda 
11306c81e96dSAndrzej Hajda 	if (xfer->packet.payload_length || xfer->rx_len)
11317eb8f069SAndrzej Hajda 		return;
11327eb8f069SAndrzej Hajda 
11337eb8f069SAndrzej Hajda 	xfer->result = 0;
11347eb8f069SAndrzej Hajda 	complete(&xfer->completed);
11357eb8f069SAndrzej Hajda 
11367eb8f069SAndrzej Hajda 	spin_lock_irqsave(&dsi->transfer_lock, flags);
11377eb8f069SAndrzej Hajda 
11387eb8f069SAndrzej Hajda 	list_del_init(&xfer->list);
11397eb8f069SAndrzej Hajda 	start = !list_empty(&dsi->transfer_list);
11407eb8f069SAndrzej Hajda 
11417eb8f069SAndrzej Hajda 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
11427eb8f069SAndrzej Hajda 
11437eb8f069SAndrzej Hajda 	if (start)
11447eb8f069SAndrzej Hajda 		goto again;
11457eb8f069SAndrzej Hajda }
11467eb8f069SAndrzej Hajda 
11477eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
11487eb8f069SAndrzej Hajda {
11497eb8f069SAndrzej Hajda 	struct exynos_dsi_transfer *xfer;
11507eb8f069SAndrzej Hajda 	unsigned long flags;
11517eb8f069SAndrzej Hajda 	bool start = true;
11527eb8f069SAndrzej Hajda 
11537eb8f069SAndrzej Hajda 	spin_lock_irqsave(&dsi->transfer_lock, flags);
11547eb8f069SAndrzej Hajda 
11557eb8f069SAndrzej Hajda 	if (list_empty(&dsi->transfer_list)) {
11567eb8f069SAndrzej Hajda 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
11577eb8f069SAndrzej Hajda 		return false;
11587eb8f069SAndrzej Hajda 	}
11597eb8f069SAndrzej Hajda 
11607eb8f069SAndrzej Hajda 	xfer = list_first_entry(&dsi->transfer_list,
11617eb8f069SAndrzej Hajda 					struct exynos_dsi_transfer, list);
11627eb8f069SAndrzej Hajda 
11637eb8f069SAndrzej Hajda 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
11647eb8f069SAndrzej Hajda 
11657eb8f069SAndrzej Hajda 	dev_dbg(dsi->dev,
11669cdf0ed2SKrzysztof Kozlowski 		"> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
11676c81e96dSAndrzej Hajda 		xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
11686c81e96dSAndrzej Hajda 		xfer->rx_done);
11697eb8f069SAndrzej Hajda 
11706c81e96dSAndrzej Hajda 	if (xfer->tx_done != xfer->packet.payload_length)
11717eb8f069SAndrzej Hajda 		return true;
11727eb8f069SAndrzej Hajda 
11737eb8f069SAndrzej Hajda 	if (xfer->rx_done != xfer->rx_len)
11747eb8f069SAndrzej Hajda 		exynos_dsi_read_from_fifo(dsi, xfer);
11757eb8f069SAndrzej Hajda 
11767eb8f069SAndrzej Hajda 	if (xfer->rx_done != xfer->rx_len)
11777eb8f069SAndrzej Hajda 		return true;
11787eb8f069SAndrzej Hajda 
11797eb8f069SAndrzej Hajda 	spin_lock_irqsave(&dsi->transfer_lock, flags);
11807eb8f069SAndrzej Hajda 
11817eb8f069SAndrzej Hajda 	list_del_init(&xfer->list);
11827eb8f069SAndrzej Hajda 	start = !list_empty(&dsi->transfer_list);
11837eb8f069SAndrzej Hajda 
11847eb8f069SAndrzej Hajda 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
11857eb8f069SAndrzej Hajda 
11867eb8f069SAndrzej Hajda 	if (!xfer->rx_len)
11877eb8f069SAndrzej Hajda 		xfer->result = 0;
11887eb8f069SAndrzej Hajda 	complete(&xfer->completed);
11897eb8f069SAndrzej Hajda 
11907eb8f069SAndrzej Hajda 	return start;
11917eb8f069SAndrzej Hajda }
11927eb8f069SAndrzej Hajda 
11937eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
11947eb8f069SAndrzej Hajda 					struct exynos_dsi_transfer *xfer)
11957eb8f069SAndrzej Hajda {
11967eb8f069SAndrzej Hajda 	unsigned long flags;
11977eb8f069SAndrzej Hajda 	bool start;
11987eb8f069SAndrzej Hajda 
11997eb8f069SAndrzej Hajda 	spin_lock_irqsave(&dsi->transfer_lock, flags);
12007eb8f069SAndrzej Hajda 
12017eb8f069SAndrzej Hajda 	if (!list_empty(&dsi->transfer_list) &&
12027eb8f069SAndrzej Hajda 	    xfer == list_first_entry(&dsi->transfer_list,
12037eb8f069SAndrzej Hajda 				     struct exynos_dsi_transfer, list)) {
12047eb8f069SAndrzej Hajda 		list_del_init(&xfer->list);
12057eb8f069SAndrzej Hajda 		start = !list_empty(&dsi->transfer_list);
12067eb8f069SAndrzej Hajda 		spin_unlock_irqrestore(&dsi->transfer_lock, flags);
12077eb8f069SAndrzej Hajda 		if (start)
12087eb8f069SAndrzej Hajda 			exynos_dsi_transfer_start(dsi);
12097eb8f069SAndrzej Hajda 		return;
12107eb8f069SAndrzej Hajda 	}
12117eb8f069SAndrzej Hajda 
12127eb8f069SAndrzej Hajda 	list_del_init(&xfer->list);
12137eb8f069SAndrzej Hajda 
12147eb8f069SAndrzej Hajda 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
12157eb8f069SAndrzej Hajda }
12167eb8f069SAndrzej Hajda 
12177eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi,
12187eb8f069SAndrzej Hajda 					struct exynos_dsi_transfer *xfer)
12197eb8f069SAndrzej Hajda {
12207eb8f069SAndrzej Hajda 	unsigned long flags;
12217eb8f069SAndrzej Hajda 	bool stopped;
12227eb8f069SAndrzej Hajda 
12237eb8f069SAndrzej Hajda 	xfer->tx_done = 0;
12247eb8f069SAndrzej Hajda 	xfer->rx_done = 0;
12257eb8f069SAndrzej Hajda 	xfer->result = -ETIMEDOUT;
12267eb8f069SAndrzej Hajda 	init_completion(&xfer->completed);
12277eb8f069SAndrzej Hajda 
12287eb8f069SAndrzej Hajda 	spin_lock_irqsave(&dsi->transfer_lock, flags);
12297eb8f069SAndrzej Hajda 
12307eb8f069SAndrzej Hajda 	stopped = list_empty(&dsi->transfer_list);
12317eb8f069SAndrzej Hajda 	list_add_tail(&xfer->list, &dsi->transfer_list);
12327eb8f069SAndrzej Hajda 
12337eb8f069SAndrzej Hajda 	spin_unlock_irqrestore(&dsi->transfer_lock, flags);
12347eb8f069SAndrzej Hajda 
12357eb8f069SAndrzej Hajda 	if (stopped)
12367eb8f069SAndrzej Hajda 		exynos_dsi_transfer_start(dsi);
12377eb8f069SAndrzej Hajda 
12387eb8f069SAndrzej Hajda 	wait_for_completion_timeout(&xfer->completed,
12397eb8f069SAndrzej Hajda 				    msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
12407eb8f069SAndrzej Hajda 	if (xfer->result == -ETIMEDOUT) {
12416c81e96dSAndrzej Hajda 		struct mipi_dsi_packet *pkt = &xfer->packet;
12427eb8f069SAndrzej Hajda 		exynos_dsi_remove_transfer(dsi, xfer);
12436c81e96dSAndrzej Hajda 		dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
12446c81e96dSAndrzej Hajda 			(int)pkt->payload_length, pkt->payload);
12457eb8f069SAndrzej Hajda 		return -ETIMEDOUT;
12467eb8f069SAndrzej Hajda 	}
12477eb8f069SAndrzej Hajda 
12487eb8f069SAndrzej Hajda 	/* Also covers hardware timeout condition */
12497eb8f069SAndrzej Hajda 	return xfer->result;
12507eb8f069SAndrzej Hajda }
12517eb8f069SAndrzej Hajda 
12527eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
12537eb8f069SAndrzej Hajda {
12547eb8f069SAndrzej Hajda 	struct exynos_dsi *dsi = dev_id;
12557eb8f069SAndrzej Hajda 	u32 status;
12567eb8f069SAndrzej Hajda 
1257bb32e408SAndrzej Hajda 	status = exynos_dsi_read(dsi, DSIM_INTSRC_REG);
12587eb8f069SAndrzej Hajda 	if (!status) {
12597eb8f069SAndrzej Hajda 		static unsigned long int j;
12607eb8f069SAndrzej Hajda 		if (printk_timed_ratelimit(&j, 500))
12617eb8f069SAndrzej Hajda 			dev_warn(dsi->dev, "spurious interrupt\n");
12627eb8f069SAndrzej Hajda 		return IRQ_HANDLED;
12637eb8f069SAndrzej Hajda 	}
1264bb32e408SAndrzej Hajda 	exynos_dsi_write(dsi, DSIM_INTSRC_REG, status);
12657eb8f069SAndrzej Hajda 
12667eb8f069SAndrzej Hajda 	if (status & DSIM_INT_SW_RST_RELEASE) {
1267e6f988a4SHyungwon Hwang 		u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1268ecf81ed9SAndrzej Hajda 			DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR |
1269ecf81ed9SAndrzej Hajda 			DSIM_INT_SW_RST_RELEASE);
1270bb32e408SAndrzej Hajda 		exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask);
12717eb8f069SAndrzej Hajda 		complete(&dsi->completed);
12727eb8f069SAndrzej Hajda 		return IRQ_HANDLED;
12737eb8f069SAndrzej Hajda 	}
12747eb8f069SAndrzej Hajda 
1275e6f988a4SHyungwon Hwang 	if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1276ecf81ed9SAndrzej Hajda 			DSIM_INT_PLL_STABLE)))
12777eb8f069SAndrzej Hajda 		return IRQ_HANDLED;
12787eb8f069SAndrzej Hajda 
12797eb8f069SAndrzej Hajda 	if (exynos_dsi_transfer_finish(dsi))
12807eb8f069SAndrzej Hajda 		exynos_dsi_transfer_start(dsi);
12817eb8f069SAndrzej Hajda 
12827eb8f069SAndrzej Hajda 	return IRQ_HANDLED;
12837eb8f069SAndrzej Hajda }
12847eb8f069SAndrzej Hajda 
1285e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1286e17ddeccSYoungJun Cho {
1287e17ddeccSYoungJun Cho 	struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
12882b8376c8SGustavo Padovan 	struct drm_encoder *encoder = &dsi->encoder;
1289e17ddeccSYoungJun Cho 
12900e480f6fSHyungwon Hwang 	if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE)
1291e17ddeccSYoungJun Cho 		exynos_drm_crtc_te_handler(encoder->crtc);
1292e17ddeccSYoungJun Cho 
1293e17ddeccSYoungJun Cho 	return IRQ_HANDLED;
1294e17ddeccSYoungJun Cho }
1295e17ddeccSYoungJun Cho 
1296e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1297e17ddeccSYoungJun Cho {
1298e17ddeccSYoungJun Cho 	enable_irq(dsi->irq);
1299e17ddeccSYoungJun Cho 
1300e17ddeccSYoungJun Cho 	if (gpio_is_valid(dsi->te_gpio))
1301e17ddeccSYoungJun Cho 		enable_irq(gpio_to_irq(dsi->te_gpio));
1302e17ddeccSYoungJun Cho }
1303e17ddeccSYoungJun Cho 
1304e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1305e17ddeccSYoungJun Cho {
1306e17ddeccSYoungJun Cho 	if (gpio_is_valid(dsi->te_gpio))
1307e17ddeccSYoungJun Cho 		disable_irq(gpio_to_irq(dsi->te_gpio));
1308e17ddeccSYoungJun Cho 
1309e17ddeccSYoungJun Cho 	disable_irq(dsi->irq);
1310e17ddeccSYoungJun Cho }
1311e17ddeccSYoungJun Cho 
13127eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi)
13137eb8f069SAndrzej Hajda {
13142154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1315d668e8bfSHyungwon Hwang 
13167eb8f069SAndrzej Hajda 	exynos_dsi_reset(dsi);
1317e17ddeccSYoungJun Cho 	exynos_dsi_enable_irq(dsi);
1318e6f988a4SHyungwon Hwang 
1319e6f988a4SHyungwon Hwang 	if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1320e6f988a4SHyungwon Hwang 		exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1);
1321e6f988a4SHyungwon Hwang 
13229a320415SYoungJun Cho 	exynos_dsi_enable_clock(dsi);
1323d668e8bfSHyungwon Hwang 	if (driver_data->wait_for_reset)
13247eb8f069SAndrzej Hajda 		exynos_dsi_wait_for_reset(dsi);
13259a320415SYoungJun Cho 	exynos_dsi_set_phy_ctrl(dsi);
13267eb8f069SAndrzej Hajda 	exynos_dsi_init_link(dsi);
13277eb8f069SAndrzej Hajda 
13287eb8f069SAndrzej Hajda 	return 0;
13297eb8f069SAndrzej Hajda }
13307eb8f069SAndrzej Hajda 
1331295e7954SAndrzej Hajda static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi,
1332295e7954SAndrzej Hajda 				      struct device *panel)
1333e17ddeccSYoungJun Cho {
1334e17ddeccSYoungJun Cho 	int ret;
13350cef83a5SYoungJun Cho 	int te_gpio_irq;
1336e17ddeccSYoungJun Cho 
1337295e7954SAndrzej Hajda 	dsi->te_gpio = of_get_named_gpio(panel->of_node, "te-gpios", 0);
133822e098daSAndrzej Hajda 	if (dsi->te_gpio == -ENOENT)
133922e098daSAndrzej Hajda 		return 0;
134022e098daSAndrzej Hajda 
1341e17ddeccSYoungJun Cho 	if (!gpio_is_valid(dsi->te_gpio)) {
1342e17ddeccSYoungJun Cho 		ret = dsi->te_gpio;
134322e098daSAndrzej Hajda 		dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret);
1344e17ddeccSYoungJun Cho 		goto out;
1345e17ddeccSYoungJun Cho 	}
1346e17ddeccSYoungJun Cho 
134751d1decaSHyungwon Hwang 	ret = gpio_request(dsi->te_gpio, "te_gpio");
1348e17ddeccSYoungJun Cho 	if (ret) {
1349e17ddeccSYoungJun Cho 		dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1350e17ddeccSYoungJun Cho 		goto out;
1351e17ddeccSYoungJun Cho 	}
1352e17ddeccSYoungJun Cho 
13530cef83a5SYoungJun Cho 	te_gpio_irq = gpio_to_irq(dsi->te_gpio);
13540cef83a5SYoungJun Cho 	irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
135551d1decaSHyungwon Hwang 
13560cef83a5SYoungJun Cho 	ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1357e17ddeccSYoungJun Cho 					IRQF_TRIGGER_RISING, "TE", dsi);
1358e17ddeccSYoungJun Cho 	if (ret) {
1359e17ddeccSYoungJun Cho 		dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1360e17ddeccSYoungJun Cho 		gpio_free(dsi->te_gpio);
1361e17ddeccSYoungJun Cho 		goto out;
1362e17ddeccSYoungJun Cho 	}
1363e17ddeccSYoungJun Cho 
1364e17ddeccSYoungJun Cho out:
1365e17ddeccSYoungJun Cho 	return ret;
1366e17ddeccSYoungJun Cho }
1367e17ddeccSYoungJun Cho 
1368e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1369e17ddeccSYoungJun Cho {
1370e17ddeccSYoungJun Cho 	if (gpio_is_valid(dsi->te_gpio)) {
1371e17ddeccSYoungJun Cho 		free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1372e17ddeccSYoungJun Cho 		gpio_free(dsi->te_gpio);
1373e17ddeccSYoungJun Cho 		dsi->te_gpio = -ENOENT;
1374e17ddeccSYoungJun Cho 	}
1375e17ddeccSYoungJun Cho }
1376e17ddeccSYoungJun Cho 
13772b8376c8SGustavo Padovan static void exynos_dsi_enable(struct drm_encoder *encoder)
13787eb8f069SAndrzej Hajda {
1379cf67cc9aSGustavo Padovan 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
13807eb8f069SAndrzej Hajda 	int ret;
13817eb8f069SAndrzej Hajda 
13827eb8f069SAndrzej Hajda 	if (dsi->state & DSIM_STATE_ENABLED)
1383b6595dc7SGustavo Padovan 		return;
13847eb8f069SAndrzej Hajda 
1385ba6e4779SInki Dae 	pm_runtime_get_sync(dsi->dev);
13860e480f6fSHyungwon Hwang 	dsi->state |= DSIM_STATE_ENABLED;
13870e480f6fSHyungwon Hwang 
13888a08f671SMaciej Purski 	if (dsi->panel) {
1389cdfb8694SAjay Kumar 		ret = drm_panel_prepare(dsi->panel);
13908a08f671SMaciej Purski 		if (ret < 0)
13918a08f671SMaciej Purski 			goto err_put_sync;
13928a08f671SMaciej Purski 	} else {
13938a08f671SMaciej Purski 		drm_bridge_pre_enable(dsi->out_bridge);
13947eb8f069SAndrzej Hajda 	}
13957eb8f069SAndrzej Hajda 
13967eb8f069SAndrzej Hajda 	exynos_dsi_set_display_mode(dsi);
13977eb8f069SAndrzej Hajda 	exynos_dsi_set_display_enable(dsi, true);
13987eb8f069SAndrzej Hajda 
13998a08f671SMaciej Purski 	if (dsi->panel) {
1400cdfb8694SAjay Kumar 		ret = drm_panel_enable(dsi->panel);
14018a08f671SMaciej Purski 		if (ret < 0)
14028a08f671SMaciej Purski 			goto err_display_disable;
14038a08f671SMaciej Purski 	} else {
14048a08f671SMaciej Purski 		drm_bridge_enable(dsi->out_bridge);
1405cdfb8694SAjay Kumar 	}
1406cdfb8694SAjay Kumar 
14070e480f6fSHyungwon Hwang 	dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
14088a08f671SMaciej Purski 	return;
14098a08f671SMaciej Purski 
14108a08f671SMaciej Purski err_display_disable:
14118a08f671SMaciej Purski 	exynos_dsi_set_display_enable(dsi, false);
14128a08f671SMaciej Purski 	drm_panel_unprepare(dsi->panel);
14138a08f671SMaciej Purski 
14148a08f671SMaciej Purski err_put_sync:
14158a08f671SMaciej Purski 	dsi->state &= ~DSIM_STATE_ENABLED;
14168a08f671SMaciej Purski 	pm_runtime_put(dsi->dev);
14177eb8f069SAndrzej Hajda }
14187eb8f069SAndrzej Hajda 
14192b8376c8SGustavo Padovan static void exynos_dsi_disable(struct drm_encoder *encoder)
14207eb8f069SAndrzej Hajda {
1421cf67cc9aSGustavo Padovan 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1422b6595dc7SGustavo Padovan 
14237eb8f069SAndrzej Hajda 	if (!(dsi->state & DSIM_STATE_ENABLED))
14247eb8f069SAndrzej Hajda 		return;
14257eb8f069SAndrzej Hajda 
14260e480f6fSHyungwon Hwang 	dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
14270e480f6fSHyungwon Hwang 
14287eb8f069SAndrzej Hajda 	drm_panel_disable(dsi->panel);
14298a08f671SMaciej Purski 	drm_bridge_disable(dsi->out_bridge);
1430cdfb8694SAjay Kumar 	exynos_dsi_set_display_enable(dsi, false);
1431cdfb8694SAjay Kumar 	drm_panel_unprepare(dsi->panel);
14328a08f671SMaciej Purski 	drm_bridge_post_disable(dsi->out_bridge);
14337eb8f069SAndrzej Hajda 	dsi->state &= ~DSIM_STATE_ENABLED;
1434ba6e4779SInki Dae 	pm_runtime_put_sync(dsi->dev);
14357eb8f069SAndrzej Hajda }
14367eb8f069SAndrzej Hajda 
14377eb8f069SAndrzej Hajda static enum drm_connector_status
14387eb8f069SAndrzej Hajda exynos_dsi_detect(struct drm_connector *connector, bool force)
14397eb8f069SAndrzej Hajda {
1440295e7954SAndrzej Hajda 	return connector->status;
14417eb8f069SAndrzej Hajda }
14427eb8f069SAndrzej Hajda 
14437eb8f069SAndrzej Hajda static void exynos_dsi_connector_destroy(struct drm_connector *connector)
14447eb8f069SAndrzej Hajda {
14450ae46015SAndrzej Hajda 	drm_connector_unregister(connector);
14460ae46015SAndrzej Hajda 	drm_connector_cleanup(connector);
14470ae46015SAndrzej Hajda 	connector->dev = NULL;
14487eb8f069SAndrzej Hajda }
14497eb8f069SAndrzej Hajda 
1450800ba2b5SVille Syrjälä static const struct drm_connector_funcs exynos_dsi_connector_funcs = {
14517eb8f069SAndrzej Hajda 	.detect = exynos_dsi_detect,
14527eb8f069SAndrzej Hajda 	.fill_modes = drm_helper_probe_single_connector_modes,
14537eb8f069SAndrzej Hajda 	.destroy = exynos_dsi_connector_destroy,
14544ea9526bSGustavo Padovan 	.reset = drm_atomic_helper_connector_reset,
14554ea9526bSGustavo Padovan 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
14564ea9526bSGustavo Padovan 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
14577eb8f069SAndrzej Hajda };
14587eb8f069SAndrzej Hajda 
14597eb8f069SAndrzej Hajda static int exynos_dsi_get_modes(struct drm_connector *connector)
14607eb8f069SAndrzej Hajda {
14617eb8f069SAndrzej Hajda 	struct exynos_dsi *dsi = connector_to_dsi(connector);
14627eb8f069SAndrzej Hajda 
14637eb8f069SAndrzej Hajda 	if (dsi->panel)
14647eb8f069SAndrzej Hajda 		return dsi->panel->funcs->get_modes(dsi->panel);
14657eb8f069SAndrzej Hajda 
14667eb8f069SAndrzej Hajda 	return 0;
14677eb8f069SAndrzej Hajda }
14687eb8f069SAndrzej Hajda 
1469800ba2b5SVille Syrjälä static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
14707eb8f069SAndrzej Hajda 	.get_modes = exynos_dsi_get_modes,
14717eb8f069SAndrzej Hajda };
14727eb8f069SAndrzej Hajda 
14732b8376c8SGustavo Padovan static int exynos_dsi_create_connector(struct drm_encoder *encoder)
14747eb8f069SAndrzej Hajda {
14752b8376c8SGustavo Padovan 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
14767eb8f069SAndrzej Hajda 	struct drm_connector *connector = &dsi->connector;
1477deee3284SAndrzej Hajda 	struct drm_device *drm = encoder->dev;
14787eb8f069SAndrzej Hajda 	int ret;
14797eb8f069SAndrzej Hajda 
14807eb8f069SAndrzej Hajda 	connector->polled = DRM_CONNECTOR_POLL_HPD;
14817eb8f069SAndrzej Hajda 
1482deee3284SAndrzej Hajda 	ret = drm_connector_init(drm, connector, &exynos_dsi_connector_funcs,
14837eb8f069SAndrzej Hajda 				 DRM_MODE_CONNECTOR_DSI);
14847eb8f069SAndrzej Hajda 	if (ret) {
14856f83d208SInki Dae 		DRM_DEV_ERROR(dsi->dev,
14866f83d208SInki Dae 			      "Failed to initialize connector with drm\n");
14877eb8f069SAndrzej Hajda 		return ret;
14887eb8f069SAndrzej Hajda 	}
14897eb8f069SAndrzej Hajda 
1490295e7954SAndrzej Hajda 	connector->status = connector_status_disconnected;
14917eb8f069SAndrzej Hajda 	drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1492cde4c44dSDaniel Vetter 	drm_connector_attach_encoder(connector, encoder);
1493deee3284SAndrzej Hajda 	if (!drm->registered)
1494deee3284SAndrzej Hajda 		return 0;
14957eb8f069SAndrzej Hajda 
1496deee3284SAndrzej Hajda 	connector->funcs->reset(connector);
1497deee3284SAndrzej Hajda 	drm_fb_helper_add_one_connector(drm->fb_helper, connector);
1498deee3284SAndrzej Hajda 	drm_connector_register(connector);
14997eb8f069SAndrzej Hajda 	return 0;
15007eb8f069SAndrzej Hajda }
15017eb8f069SAndrzej Hajda 
1502800ba2b5SVille Syrjälä static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
1503b6595dc7SGustavo Padovan 	.enable = exynos_dsi_enable,
1504b6595dc7SGustavo Padovan 	.disable = exynos_dsi_disable,
15057eb8f069SAndrzej Hajda };
15067eb8f069SAndrzej Hajda 
1507800ba2b5SVille Syrjälä static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = {
15082b8376c8SGustavo Padovan 	.destroy = drm_encoder_cleanup,
15092b8376c8SGustavo Padovan };
15102b8376c8SGustavo Padovan 
1511bd024b86SSjoerd Simons MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
15127eb8f069SAndrzej Hajda 
1513295e7954SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1514295e7954SAndrzej Hajda 				  struct mipi_dsi_device *device)
1515295e7954SAndrzej Hajda {
1516295e7954SAndrzej Hajda 	struct exynos_dsi *dsi = host_to_dsi(host);
15176afb7721SMaciej Purski 	struct drm_encoder *encoder = &dsi->encoder;
15186afb7721SMaciej Purski 	struct drm_device *drm = encoder->dev;
15196afb7721SMaciej Purski 	struct drm_bridge *out_bridge;
15206afb7721SMaciej Purski 
15216afb7721SMaciej Purski 	out_bridge  = of_drm_find_bridge(device->dev.of_node);
15226afb7721SMaciej Purski 	if (out_bridge) {
15236afb7721SMaciej Purski 		drm_bridge_attach(encoder, out_bridge, NULL);
15246afb7721SMaciej Purski 		dsi->out_bridge = out_bridge;
15256afb7721SMaciej Purski 		encoder->bridge = NULL;
15266afb7721SMaciej Purski 	} else {
15276afb7721SMaciej Purski 		int ret = exynos_dsi_create_connector(encoder);
15286afb7721SMaciej Purski 
15296afb7721SMaciej Purski 		if (ret) {
15306f83d208SInki Dae 			DRM_DEV_ERROR(dsi->dev,
15316f83d208SInki Dae 				      "failed to create connector ret = %d\n",
15326f83d208SInki Dae 				      ret);
15336afb7721SMaciej Purski 			drm_encoder_cleanup(encoder);
15346afb7721SMaciej Purski 			return ret;
15356afb7721SMaciej Purski 		}
15366afb7721SMaciej Purski 
15376afb7721SMaciej Purski 		dsi->panel = of_drm_find_panel(device->dev.of_node);
15388727b230SDan Carpenter 		if (IS_ERR(dsi->panel)) {
15398727b230SDan Carpenter 			dsi->panel = NULL;
15408727b230SDan Carpenter 		} else {
15416afb7721SMaciej Purski 			drm_panel_attach(dsi->panel, &dsi->connector);
15426afb7721SMaciej Purski 			dsi->connector.status = connector_status_connected;
15436afb7721SMaciej Purski 		}
15446afb7721SMaciej Purski 	}
1545295e7954SAndrzej Hajda 
1546295e7954SAndrzej Hajda 	/*
1547295e7954SAndrzej Hajda 	 * This is a temporary solution and should be made by more generic way.
1548295e7954SAndrzej Hajda 	 *
1549295e7954SAndrzej Hajda 	 * If attached panel device is for command mode one, dsi should register
1550295e7954SAndrzej Hajda 	 * TE interrupt handler.
1551295e7954SAndrzej Hajda 	 */
1552295e7954SAndrzej Hajda 	if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1553295e7954SAndrzej Hajda 		int ret = exynos_dsi_register_te_irq(dsi, &device->dev);
1554295e7954SAndrzej Hajda 		if (ret)
1555295e7954SAndrzej Hajda 			return ret;
1556295e7954SAndrzej Hajda 	}
1557295e7954SAndrzej Hajda 
1558295e7954SAndrzej Hajda 	mutex_lock(&drm->mode_config.mutex);
1559295e7954SAndrzej Hajda 
1560295e7954SAndrzej Hajda 	dsi->lanes = device->lanes;
1561295e7954SAndrzej Hajda 	dsi->format = device->format;
1562295e7954SAndrzej Hajda 	dsi->mode_flags = device->mode_flags;
1563c038f538SAndrzej Hajda 	exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode =
1564c038f538SAndrzej Hajda 			!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO);
1565295e7954SAndrzej Hajda 
1566295e7954SAndrzej Hajda 	mutex_unlock(&drm->mode_config.mutex);
1567295e7954SAndrzej Hajda 
1568295e7954SAndrzej Hajda 	if (drm->mode_config.poll_enabled)
1569295e7954SAndrzej Hajda 		drm_kms_helper_hotplug_event(drm);
1570295e7954SAndrzej Hajda 
1571295e7954SAndrzej Hajda 	return 0;
1572295e7954SAndrzej Hajda }
1573295e7954SAndrzej Hajda 
1574295e7954SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1575295e7954SAndrzej Hajda 				  struct mipi_dsi_device *device)
1576295e7954SAndrzej Hajda {
1577295e7954SAndrzej Hajda 	struct exynos_dsi *dsi = host_to_dsi(host);
15786afb7721SMaciej Purski 	struct drm_device *drm = dsi->encoder.dev;
1579295e7954SAndrzej Hajda 
1580295e7954SAndrzej Hajda 	if (dsi->panel) {
15816afb7721SMaciej Purski 		mutex_lock(&drm->mode_config.mutex);
1582295e7954SAndrzej Hajda 		exynos_dsi_disable(&dsi->encoder);
1583295e7954SAndrzej Hajda 		drm_panel_detach(dsi->panel);
1584295e7954SAndrzej Hajda 		dsi->panel = NULL;
1585295e7954SAndrzej Hajda 		dsi->connector.status = connector_status_disconnected;
1586295e7954SAndrzej Hajda 		mutex_unlock(&drm->mode_config.mutex);
15876afb7721SMaciej Purski 	} else {
15886afb7721SMaciej Purski 		if (dsi->out_bridge->funcs->detach)
15896afb7721SMaciej Purski 			dsi->out_bridge->funcs->detach(dsi->out_bridge);
15906afb7721SMaciej Purski 		dsi->out_bridge = NULL;
15916afb7721SMaciej Purski 	}
1592295e7954SAndrzej Hajda 
1593295e7954SAndrzej Hajda 	if (drm->mode_config.poll_enabled)
1594295e7954SAndrzej Hajda 		drm_kms_helper_hotplug_event(drm);
1595295e7954SAndrzej Hajda 
1596295e7954SAndrzej Hajda 	exynos_dsi_unregister_te_irq(dsi);
1597295e7954SAndrzej Hajda 
1598295e7954SAndrzej Hajda 	return 0;
1599295e7954SAndrzej Hajda }
1600295e7954SAndrzej Hajda 
1601295e7954SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1602295e7954SAndrzej Hajda 					 const struct mipi_dsi_msg *msg)
1603295e7954SAndrzej Hajda {
1604295e7954SAndrzej Hajda 	struct exynos_dsi *dsi = host_to_dsi(host);
1605295e7954SAndrzej Hajda 	struct exynos_dsi_transfer xfer;
1606295e7954SAndrzej Hajda 	int ret;
1607295e7954SAndrzej Hajda 
1608295e7954SAndrzej Hajda 	if (!(dsi->state & DSIM_STATE_ENABLED))
1609295e7954SAndrzej Hajda 		return -EINVAL;
1610295e7954SAndrzej Hajda 
1611295e7954SAndrzej Hajda 	if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1612295e7954SAndrzej Hajda 		ret = exynos_dsi_init(dsi);
1613295e7954SAndrzej Hajda 		if (ret)
1614295e7954SAndrzej Hajda 			return ret;
1615295e7954SAndrzej Hajda 		dsi->state |= DSIM_STATE_INITIALIZED;
1616295e7954SAndrzej Hajda 	}
1617295e7954SAndrzej Hajda 
1618295e7954SAndrzej Hajda 	ret = mipi_dsi_create_packet(&xfer.packet, msg);
1619295e7954SAndrzej Hajda 	if (ret < 0)
1620295e7954SAndrzej Hajda 		return ret;
1621295e7954SAndrzej Hajda 
1622295e7954SAndrzej Hajda 	xfer.rx_len = msg->rx_len;
1623295e7954SAndrzej Hajda 	xfer.rx_payload = msg->rx_buf;
1624295e7954SAndrzej Hajda 	xfer.flags = msg->flags;
1625295e7954SAndrzej Hajda 
1626295e7954SAndrzej Hajda 	ret = exynos_dsi_transfer(dsi, &xfer);
1627295e7954SAndrzej Hajda 	return (ret < 0) ? ret : xfer.rx_done;
1628295e7954SAndrzej Hajda }
1629295e7954SAndrzej Hajda 
1630295e7954SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1631295e7954SAndrzej Hajda 	.attach = exynos_dsi_host_attach,
1632295e7954SAndrzej Hajda 	.detach = exynos_dsi_host_detach,
1633295e7954SAndrzej Hajda 	.transfer = exynos_dsi_host_transfer,
1634295e7954SAndrzej Hajda };
1635295e7954SAndrzej Hajda 
16367eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np,
16377eb8f069SAndrzej Hajda 				  const char *propname, u32 *out_value)
16387eb8f069SAndrzej Hajda {
16397eb8f069SAndrzej Hajda 	int ret = of_property_read_u32(np, propname, out_value);
16407eb8f069SAndrzej Hajda 
16417eb8f069SAndrzej Hajda 	if (ret < 0)
16424bf99144SRob Herring 		pr_err("%pOF: failed to get '%s' property\n", np, propname);
16437eb8f069SAndrzej Hajda 
16447eb8f069SAndrzej Hajda 	return ret;
16457eb8f069SAndrzej Hajda }
16467eb8f069SAndrzej Hajda 
16477eb8f069SAndrzej Hajda enum {
16487eb8f069SAndrzej Hajda 	DSI_PORT_IN,
16497eb8f069SAndrzej Hajda 	DSI_PORT_OUT
16507eb8f069SAndrzej Hajda };
16517eb8f069SAndrzej Hajda 
16527eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
16537eb8f069SAndrzej Hajda {
16547eb8f069SAndrzej Hajda 	struct device *dev = dsi->dev;
16557eb8f069SAndrzej Hajda 	struct device_node *node = dev->of_node;
16567eb8f069SAndrzej Hajda 	int ret;
16577eb8f069SAndrzej Hajda 
16587eb8f069SAndrzej Hajda 	ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
16597eb8f069SAndrzej Hajda 				     &dsi->pll_clk_rate);
16607eb8f069SAndrzej Hajda 	if (ret < 0)
16617eb8f069SAndrzej Hajda 		return ret;
16627eb8f069SAndrzej Hajda 
1663f2921d8cSHoegeun Kwon 	ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency",
16647eb8f069SAndrzej Hajda 				     &dsi->burst_clk_rate);
16657eb8f069SAndrzej Hajda 	if (ret < 0)
1666f2921d8cSHoegeun Kwon 		return ret;
16677eb8f069SAndrzej Hajda 
1668f2921d8cSHoegeun Kwon 	ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency",
16697eb8f069SAndrzej Hajda 				     &dsi->esc_clk_rate);
1670f5f3b9baSHyungwon Hwang 	if (ret < 0)
1671f2921d8cSHoegeun Kwon 		return ret;
1672f5f3b9baSHyungwon Hwang 
16732782622eSMaciej Purski 	dsi->in_bridge_node = of_graph_get_remote_node(node, DSI_PORT_IN, 0);
1674f5f3b9baSHyungwon Hwang 
1675f2921d8cSHoegeun Kwon 	return 0;
16767eb8f069SAndrzej Hajda }
16777eb8f069SAndrzej Hajda 
1678f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master,
1679f37cd5e8SInki Dae 				void *data)
1680f37cd5e8SInki Dae {
16812b8376c8SGustavo Padovan 	struct drm_encoder *encoder = dev_get_drvdata(dev);
16822b8376c8SGustavo Padovan 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1683f37cd5e8SInki Dae 	struct drm_device *drm_dev = data;
16842782622eSMaciej Purski 	struct drm_bridge *in_bridge;
1685f37cd5e8SInki Dae 	int ret;
1686f37cd5e8SInki Dae 
16872b8376c8SGustavo Padovan 	drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs,
168813a3d91fSVille Syrjälä 			 DRM_MODE_ENCODER_TMDS, NULL);
16892b8376c8SGustavo Padovan 
16902b8376c8SGustavo Padovan 	drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs);
16912b8376c8SGustavo Padovan 
16921ca582f1SAndrzej Hajda 	ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD);
16931ca582f1SAndrzej Hajda 	if (ret < 0)
16941ca582f1SAndrzej Hajda 		return ret;
16951ca582f1SAndrzej Hajda 
16962782622eSMaciej Purski 	if (dsi->in_bridge_node) {
16972782622eSMaciej Purski 		in_bridge = of_drm_find_bridge(dsi->in_bridge_node);
16982782622eSMaciej Purski 		if (in_bridge)
16992782622eSMaciej Purski 			drm_bridge_attach(encoder, in_bridge, NULL);
1700c9948920SInki Dae 	}
1701f5f3b9baSHyungwon Hwang 
1702f37cd5e8SInki Dae 	return mipi_dsi_host_register(&dsi->dsi_host);
1703f37cd5e8SInki Dae }
1704f37cd5e8SInki Dae 
1705f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master,
1706f37cd5e8SInki Dae 				void *data)
1707f37cd5e8SInki Dae {
17082b8376c8SGustavo Padovan 	struct drm_encoder *encoder = dev_get_drvdata(dev);
1709cf67cc9aSGustavo Padovan 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
1710f37cd5e8SInki Dae 
1711cf67cc9aSGustavo Padovan 	exynos_dsi_disable(encoder);
1712f37cd5e8SInki Dae 
17130ae46015SAndrzej Hajda 	mipi_dsi_host_unregister(&dsi->dsi_host);
1714f37cd5e8SInki Dae }
1715f37cd5e8SInki Dae 
1716f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = {
1717f37cd5e8SInki Dae 	.bind	= exynos_dsi_bind,
1718f37cd5e8SInki Dae 	.unbind	= exynos_dsi_unbind,
1719f37cd5e8SInki Dae };
1720f37cd5e8SInki Dae 
17217eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev)
17227eb8f069SAndrzej Hajda {
17232900c69cSAndrzej Hajda 	struct device *dev = &pdev->dev;
17247eb8f069SAndrzej Hajda 	struct resource *res;
17257eb8f069SAndrzej Hajda 	struct exynos_dsi *dsi;
17260ff03fd1SHyungwon Hwang 	int ret, i;
17277eb8f069SAndrzej Hajda 
17282900c69cSAndrzej Hajda 	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
17292900c69cSAndrzej Hajda 	if (!dsi)
17302900c69cSAndrzej Hajda 		return -ENOMEM;
17312900c69cSAndrzej Hajda 
1732e17ddeccSYoungJun Cho 	/* To be checked as invalid one */
1733e17ddeccSYoungJun Cho 	dsi->te_gpio = -ENOENT;
1734e17ddeccSYoungJun Cho 
17357eb8f069SAndrzej Hajda 	init_completion(&dsi->completed);
17367eb8f069SAndrzej Hajda 	spin_lock_init(&dsi->transfer_lock);
17377eb8f069SAndrzej Hajda 	INIT_LIST_HEAD(&dsi->transfer_list);
17387eb8f069SAndrzej Hajda 
17397eb8f069SAndrzej Hajda 	dsi->dsi_host.ops = &exynos_dsi_ops;
1740e2d2a1e0SAndrzej Hajda 	dsi->dsi_host.dev = dev;
17417eb8f069SAndrzej Hajda 
1742e2d2a1e0SAndrzej Hajda 	dsi->dev = dev;
17432154ac92SMarek Szyprowski 	dsi->driver_data = of_device_get_match_data(dev);
17447eb8f069SAndrzej Hajda 
17457eb8f069SAndrzej Hajda 	ret = exynos_dsi_parse_dt(dsi);
17467eb8f069SAndrzej Hajda 	if (ret)
174786650408SAndrzej Hajda 		return ret;
17487eb8f069SAndrzej Hajda 
17497eb8f069SAndrzej Hajda 	dsi->supplies[0].supply = "vddcore";
17507eb8f069SAndrzej Hajda 	dsi->supplies[1].supply = "vddio";
1751e2d2a1e0SAndrzej Hajda 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
17527eb8f069SAndrzej Hajda 				      dsi->supplies);
17537eb8f069SAndrzej Hajda 	if (ret) {
1754e2d2a1e0SAndrzej Hajda 		dev_info(dev, "failed to get regulators: %d\n", ret);
17557eb8f069SAndrzej Hajda 		return -EPROBE_DEFER;
17567eb8f069SAndrzej Hajda 	}
17577eb8f069SAndrzej Hajda 
1758a86854d0SKees Cook 	dsi->clks = devm_kcalloc(dev,
1759a86854d0SKees Cook 			dsi->driver_data->num_clks, sizeof(*dsi->clks),
17600ff03fd1SHyungwon Hwang 			GFP_KERNEL);
1761e6f988a4SHyungwon Hwang 	if (!dsi->clks)
1762e6f988a4SHyungwon Hwang 		return -ENOMEM;
1763e6f988a4SHyungwon Hwang 
17640ff03fd1SHyungwon Hwang 	for (i = 0; i < dsi->driver_data->num_clks; i++) {
17650ff03fd1SHyungwon Hwang 		dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
17660ff03fd1SHyungwon Hwang 		if (IS_ERR(dsi->clks[i])) {
17670ff03fd1SHyungwon Hwang 			if (strcmp(clk_names[i], "sclk_mipi") == 0) {
17680ff03fd1SHyungwon Hwang 				strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME);
17690ff03fd1SHyungwon Hwang 				i--;
17700ff03fd1SHyungwon Hwang 				continue;
17717eb8f069SAndrzej Hajda 			}
17727eb8f069SAndrzej Hajda 
17730ff03fd1SHyungwon Hwang 			dev_info(dev, "failed to get the clock: %s\n",
17740ff03fd1SHyungwon Hwang 					clk_names[i]);
17750ff03fd1SHyungwon Hwang 			return PTR_ERR(dsi->clks[i]);
17760ff03fd1SHyungwon Hwang 		}
17777eb8f069SAndrzej Hajda 	}
17787eb8f069SAndrzej Hajda 
17797eb8f069SAndrzej Hajda 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1780e2d2a1e0SAndrzej Hajda 	dsi->reg_base = devm_ioremap_resource(dev, res);
1781293d3f6aSJingoo Han 	if (IS_ERR(dsi->reg_base)) {
1782e2d2a1e0SAndrzej Hajda 		dev_err(dev, "failed to remap io region\n");
178386650408SAndrzej Hajda 		return PTR_ERR(dsi->reg_base);
17847eb8f069SAndrzej Hajda 	}
17857eb8f069SAndrzej Hajda 
1786e2d2a1e0SAndrzej Hajda 	dsi->phy = devm_phy_get(dev, "dsim");
17877eb8f069SAndrzej Hajda 	if (IS_ERR(dsi->phy)) {
1788e2d2a1e0SAndrzej Hajda 		dev_info(dev, "failed to get dsim phy\n");
178986650408SAndrzej Hajda 		return PTR_ERR(dsi->phy);
17907eb8f069SAndrzej Hajda 	}
17917eb8f069SAndrzej Hajda 
17927eb8f069SAndrzej Hajda 	dsi->irq = platform_get_irq(pdev, 0);
17937eb8f069SAndrzej Hajda 	if (dsi->irq < 0) {
1794e2d2a1e0SAndrzej Hajda 		dev_err(dev, "failed to request dsi irq resource\n");
179586650408SAndrzej Hajda 		return dsi->irq;
17967eb8f069SAndrzej Hajda 	}
17977eb8f069SAndrzej Hajda 
17987eb8f069SAndrzej Hajda 	irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1799e2d2a1e0SAndrzej Hajda 	ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
18007eb8f069SAndrzej Hajda 					exynos_dsi_irq, IRQF_ONESHOT,
1801e2d2a1e0SAndrzej Hajda 					dev_name(dev), dsi);
18027eb8f069SAndrzej Hajda 	if (ret) {
1803e2d2a1e0SAndrzej Hajda 		dev_err(dev, "failed to request dsi irq\n");
180486650408SAndrzej Hajda 		return ret;
18057eb8f069SAndrzej Hajda 	}
18067eb8f069SAndrzej Hajda 
1807cf67cc9aSGustavo Padovan 	platform_set_drvdata(pdev, &dsi->encoder);
18087eb8f069SAndrzej Hajda 
1809ba6e4779SInki Dae 	pm_runtime_enable(dev);
1810ba6e4779SInki Dae 
181186650408SAndrzej Hajda 	return component_add(dev, &exynos_dsi_component_ops);
18127eb8f069SAndrzej Hajda }
18137eb8f069SAndrzej Hajda 
18147eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev)
18157eb8f069SAndrzej Hajda {
181670505c2eSHoegeun Kwon 	struct exynos_dsi *dsi = platform_get_drvdata(pdev);
181770505c2eSHoegeun Kwon 
18182782622eSMaciej Purski 	of_node_put(dsi->in_bridge_node);
181970505c2eSHoegeun Kwon 
1820ba6e4779SInki Dae 	pm_runtime_disable(&pdev->dev);
1821ba6e4779SInki Dae 
1822df5225bcSInki Dae 	component_del(&pdev->dev, &exynos_dsi_component_ops);
1823df5225bcSInki Dae 
18247eb8f069SAndrzej Hajda 	return 0;
18257eb8f069SAndrzej Hajda }
18267eb8f069SAndrzej Hajda 
1827010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1828ba6e4779SInki Dae {
1829ba6e4779SInki Dae 	struct drm_encoder *encoder = dev_get_drvdata(dev);
1830ba6e4779SInki Dae 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
18312154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1832ba6e4779SInki Dae 	int ret, i;
1833ba6e4779SInki Dae 
1834ba6e4779SInki Dae 	usleep_range(10000, 20000);
1835ba6e4779SInki Dae 
1836ba6e4779SInki Dae 	if (dsi->state & DSIM_STATE_INITIALIZED) {
1837ba6e4779SInki Dae 		dsi->state &= ~DSIM_STATE_INITIALIZED;
1838ba6e4779SInki Dae 
1839ba6e4779SInki Dae 		exynos_dsi_disable_clock(dsi);
1840ba6e4779SInki Dae 
1841ba6e4779SInki Dae 		exynos_dsi_disable_irq(dsi);
1842ba6e4779SInki Dae 	}
1843ba6e4779SInki Dae 
1844ba6e4779SInki Dae 	dsi->state &= ~DSIM_STATE_CMD_LPM;
1845ba6e4779SInki Dae 
1846ba6e4779SInki Dae 	phy_power_off(dsi->phy);
1847ba6e4779SInki Dae 
1848ba6e4779SInki Dae 	for (i = driver_data->num_clks - 1; i > -1; i--)
1849ba6e4779SInki Dae 		clk_disable_unprepare(dsi->clks[i]);
1850ba6e4779SInki Dae 
1851ba6e4779SInki Dae 	ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1852ba6e4779SInki Dae 	if (ret < 0)
1853ba6e4779SInki Dae 		dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1854ba6e4779SInki Dae 
1855ba6e4779SInki Dae 	return 0;
1856ba6e4779SInki Dae }
1857ba6e4779SInki Dae 
1858010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_resume(struct device *dev)
1859ba6e4779SInki Dae {
1860ba6e4779SInki Dae 	struct drm_encoder *encoder = dev_get_drvdata(dev);
1861ba6e4779SInki Dae 	struct exynos_dsi *dsi = encoder_to_dsi(encoder);
18622154ac92SMarek Szyprowski 	const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
1863ba6e4779SInki Dae 	int ret, i;
1864ba6e4779SInki Dae 
1865ba6e4779SInki Dae 	ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1866ba6e4779SInki Dae 	if (ret < 0) {
1867ba6e4779SInki Dae 		dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1868ba6e4779SInki Dae 		return ret;
1869ba6e4779SInki Dae 	}
1870ba6e4779SInki Dae 
1871ba6e4779SInki Dae 	for (i = 0; i < driver_data->num_clks; i++) {
1872ba6e4779SInki Dae 		ret = clk_prepare_enable(dsi->clks[i]);
1873ba6e4779SInki Dae 		if (ret < 0)
1874ba6e4779SInki Dae 			goto err_clk;
1875ba6e4779SInki Dae 	}
1876ba6e4779SInki Dae 
1877ba6e4779SInki Dae 	ret = phy_power_on(dsi->phy);
1878ba6e4779SInki Dae 	if (ret < 0) {
1879ba6e4779SInki Dae 		dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1880ba6e4779SInki Dae 		goto err_clk;
1881ba6e4779SInki Dae 	}
1882ba6e4779SInki Dae 
1883ba6e4779SInki Dae 	return 0;
1884ba6e4779SInki Dae 
1885ba6e4779SInki Dae err_clk:
1886ba6e4779SInki Dae 	while (--i > -1)
1887ba6e4779SInki Dae 		clk_disable_unprepare(dsi->clks[i]);
1888ba6e4779SInki Dae 	regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1889ba6e4779SInki Dae 
1890ba6e4779SInki Dae 	return ret;
1891ba6e4779SInki Dae }
1892ba6e4779SInki Dae 
1893ba6e4779SInki Dae static const struct dev_pm_ops exynos_dsi_pm_ops = {
1894ba6e4779SInki Dae 	SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
18957e915746SMarek Szyprowski 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
18967e915746SMarek Szyprowski 				pm_runtime_force_resume)
1897ba6e4779SInki Dae };
1898ba6e4779SInki Dae 
18997eb8f069SAndrzej Hajda struct platform_driver dsi_driver = {
19007eb8f069SAndrzej Hajda 	.probe = exynos_dsi_probe,
19017eb8f069SAndrzej Hajda 	.remove = exynos_dsi_remove,
19027eb8f069SAndrzej Hajda 	.driver = {
19037eb8f069SAndrzej Hajda 		   .name = "exynos-dsi",
19047eb8f069SAndrzej Hajda 		   .owner = THIS_MODULE,
1905ba6e4779SInki Dae 		   .pm = &exynos_dsi_pm_ops,
19067eb8f069SAndrzej Hajda 		   .of_match_table = exynos_dsi_of_match,
19077eb8f069SAndrzej Hajda 	},
19087eb8f069SAndrzej Hajda };
19097eb8f069SAndrzej Hajda 
19107eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
19117eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
19127eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
19137eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2");
1914