1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 27eb8f069SAndrzej Hajda /* 37eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 47eb8f069SAndrzej Hajda * 57eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 67eb8f069SAndrzej Hajda * 77eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 87eb8f069SAndrzej Hajda */ 97eb8f069SAndrzej Hajda 107eb8f069SAndrzej Hajda #include <linux/clk.h> 112bda34d7SSam Ravnborg #include <linux/delay.h> 122bda34d7SSam Ravnborg #include <linux/component.h> 13e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 147eb8f069SAndrzej Hajda #include <linux/irq.h> 159a320415SYoungJun Cho #include <linux/of_device.h> 16f5f3b9baSHyungwon Hwang #include <linux/of_graph.h> 177eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 187eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 192bda34d7SSam Ravnborg 202bda34d7SSam Ravnborg #include <asm/unaligned.h> 217eb8f069SAndrzej Hajda 227eb8f069SAndrzej Hajda #include <video/mipi_display.h> 237eb8f069SAndrzej Hajda #include <video/videomode.h> 247eb8f069SAndrzej Hajda 252bda34d7SSam Ravnborg #include <drm/drm_atomic_helper.h> 26ee68c743SBoris Brezillon #include <drm/drm_bridge.h> 272bda34d7SSam Ravnborg #include <drm/drm_mipi_dsi.h> 28ea16c74cSJagan Teki #include <drm/drm_panel.h> 292bda34d7SSam Ravnborg #include <drm/drm_print.h> 302bda34d7SSam Ravnborg #include <drm/drm_probe_helper.h> 313e1fe32dSThomas Zimmermann #include <drm/drm_simple_kms_helper.h> 322bda34d7SSam Ravnborg 33e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 347eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 357eb8f069SAndrzej Hajda 367eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 377eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 387eb8f069SAndrzej Hajda 397eb8f069SAndrzej Hajda /* DSIM_STATUS */ 407eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 417eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 427eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 437eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 447eb8f069SAndrzej Hajda 457eb8f069SAndrzej Hajda /* DSIM_SWRST */ 467eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 477eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 487eb8f069SAndrzej Hajda 497eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 507eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 517eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 527eb8f069SAndrzej Hajda 537eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 547eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 557eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 567eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 587eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 597eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 617eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 627eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 637eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 647eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 657eb8f069SAndrzej Hajda 667eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 677eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 687eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 697eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 707eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 717eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 757eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 767eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 777eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 787eb8f069SAndrzej Hajda #define DSIM_HSA_MODE (1 << 20) 797eb8f069SAndrzej Hajda #define DSIM_HBP_MODE (1 << 21) 807eb8f069SAndrzej Hajda #define DSIM_HFP_MODE (1 << 22) 817eb8f069SAndrzej Hajda #define DSIM_HSE_MODE (1 << 23) 827eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 837eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 847eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 857eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 867eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 877eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 886bdc92eeSKrzysztof Kozlowski /* This flag is valid only for exynos3250/3472/5260/5430 */ 8978d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 907eb8f069SAndrzej Hajda 917eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 927eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 937eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 947eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 957eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 967eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 977eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 987eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 997eb8f069SAndrzej Hajda 1007eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 1017eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 102d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 103d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1047eb8f069SAndrzej Hajda 1057eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1067eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1077eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1087eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1097eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1107eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1117eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1127eb8f069SAndrzej Hajda 1137eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1147eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1157eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1167eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1177eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1187eb8f069SAndrzej Hajda 1197eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1207eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1217eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1227eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1237eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1247eb8f069SAndrzej Hajda 1257eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1267eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1277eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1287eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1297eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1307eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1317eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1327eb8f069SAndrzej Hajda 1337eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1347eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1357eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1367eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 137e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 1387eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1397eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1407eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1417eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1427eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1437eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1447eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1457eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1467eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1477eb8f069SAndrzej Hajda 1487eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1497eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1507eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1517eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1527eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1537eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1547eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1557eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1567eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1577eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1587eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1597eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1607eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1617eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1627eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1637eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1647eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1657eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1667eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1677eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1687eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1697eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1707eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1717eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1727eb8f069SAndrzej Hajda 1737eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1747eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1757eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1767eb8f069SAndrzej Hajda 1777eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1787eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1797eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 1807eb8f069SAndrzej Hajda #define DSIM_PLL_P(x) ((x) << 13) 1817eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1827eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 1837eb8f069SAndrzej Hajda 1849a320415SYoungJun Cho /* DSIM_PHYCTRL */ 1859a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 186e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 187e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 1889a320415SYoungJun Cho 1899a320415SYoungJun Cho /* DSIM_PHYTIMING */ 1909a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 1919a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 1929a320415SYoungJun Cho 1939a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 1949a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 1959a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 1969a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 1979a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 1989a320415SYoungJun Cho 1999a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 2009a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 2019a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 2029a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 2039a320415SYoungJun Cho 2047eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2057eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2067eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2077eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2087eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2097eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2107eb8f069SAndrzej Hajda 21126269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 21226269af9SHyungwon Hwang 213a046e7bfSBernard Zhao static const char *const clk_names[5] = { "bus_clk", "sclk_mipi", 214e6f988a4SHyungwon Hwang "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 215e6f988a4SHyungwon Hwang "sclk_rgb_vclk_to_dsim0" }; 2160ff03fd1SHyungwon Hwang 2177eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2187eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2197eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2207eb8f069SAndrzej Hajda }; 2217eb8f069SAndrzej Hajda 2227eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2237eb8f069SAndrzej Hajda struct list_head list; 2247eb8f069SAndrzej Hajda struct completion completed; 2257eb8f069SAndrzej Hajda int result; 2266c81e96dSAndrzej Hajda struct mipi_dsi_packet packet; 2277eb8f069SAndrzej Hajda u16 flags; 2287eb8f069SAndrzej Hajda u16 tx_done; 2297eb8f069SAndrzej Hajda 2307eb8f069SAndrzej Hajda u8 *rx_payload; 2317eb8f069SAndrzej Hajda u16 rx_len; 2327eb8f069SAndrzej Hajda u16 rx_done; 2337eb8f069SAndrzej Hajda }; 2347eb8f069SAndrzej Hajda 2357eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2367eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2377eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2380e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2397eb8f069SAndrzej Hajda 2409a320415SYoungJun Cho struct exynos_dsi_driver_data { 241b115361eSAndrzej Hajda const unsigned int *reg_ofs; 2429a320415SYoungJun Cho unsigned int plltmr_reg; 2439a320415SYoungJun Cho unsigned int has_freqband:1; 24478d3a8c6SInki Dae unsigned int has_clklane_stop:1; 245d668e8bfSHyungwon Hwang unsigned int num_clks; 246d668e8bfSHyungwon Hwang unsigned int max_freq; 247d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 248d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 249b115361eSAndrzej Hajda const unsigned int *reg_values; 2509a320415SYoungJun Cho }; 2519a320415SYoungJun Cho 2527eb8f069SAndrzej Hajda struct exynos_dsi { 2532b8376c8SGustavo Padovan struct drm_encoder encoder; 2547eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 255f9bfd326SJagan Teki struct drm_bridge bridge; 2566afb7721SMaciej Purski struct drm_bridge *out_bridge; 2577eb8f069SAndrzej Hajda struct device *dev; 258aee039e6SJagan Teki struct drm_display_mode mode; 2597eb8f069SAndrzej Hajda 2607eb8f069SAndrzej Hajda void __iomem *reg_base; 2617eb8f069SAndrzej Hajda struct phy *phy; 2620ff03fd1SHyungwon Hwang struct clk **clks; 2637eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2647eb8f069SAndrzej Hajda int irq; 265ee6c8b5aSMaíra Canal struct gpio_desc *te_gpio; 2667eb8f069SAndrzej Hajda 2677eb8f069SAndrzej Hajda u32 pll_clk_rate; 2687eb8f069SAndrzej Hajda u32 burst_clk_rate; 2697eb8f069SAndrzej Hajda u32 esc_clk_rate; 2707eb8f069SAndrzej Hajda u32 lanes; 2717eb8f069SAndrzej Hajda u32 mode_flags; 2727eb8f069SAndrzej Hajda u32 format; 2737eb8f069SAndrzej Hajda 2747eb8f069SAndrzej Hajda int state; 2757eb8f069SAndrzej Hajda struct drm_property *brightness; 2767eb8f069SAndrzej Hajda struct completion completed; 2777eb8f069SAndrzej Hajda 2787eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 2797eb8f069SAndrzej Hajda struct list_head transfer_list; 2809a320415SYoungJun Cho 2812154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data; 2827eb8f069SAndrzej Hajda }; 2837eb8f069SAndrzej Hajda 2847eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 2857eb8f069SAndrzej Hajda 286f9bfd326SJagan Teki static inline struct exynos_dsi *bridge_to_dsi(struct drm_bridge *b) 2875cd5db80SAndrzej Hajda { 288f9bfd326SJagan Teki return container_of(b, struct exynos_dsi, bridge); 2895cd5db80SAndrzej Hajda } 2905cd5db80SAndrzej Hajda 291d668e8bfSHyungwon Hwang enum reg_idx { 292d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 293d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 294d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 295d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 296d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 297d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 298d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 299d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 300d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 301d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 302d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 303d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 304d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 305d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 306d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 307d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 308d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 309d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 310d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 311d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 312d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 313d668e8bfSHyungwon Hwang NUM_REGS 314d668e8bfSHyungwon Hwang }; 315bb32e408SAndrzej Hajda 316bb32e408SAndrzej Hajda static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 317bb32e408SAndrzej Hajda u32 val) 318bb32e408SAndrzej Hajda { 3196c81e96dSAndrzej Hajda 320bb32e408SAndrzej Hajda writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 321bb32e408SAndrzej Hajda } 322bb32e408SAndrzej Hajda 323bb32e408SAndrzej Hajda static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 324bb32e408SAndrzej Hajda { 325bb32e408SAndrzej Hajda return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 326bb32e408SAndrzej Hajda } 327bb32e408SAndrzej Hajda 328b115361eSAndrzej Hajda static const unsigned int exynos_reg_ofs[] = { 329d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 330d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 331d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 332d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 333d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 334d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 335d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 336d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 337d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 338d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 339d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 340d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 341d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 342d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 343d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 344d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 345d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 346d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 347d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 348d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 349d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 350d668e8bfSHyungwon Hwang }; 351d668e8bfSHyungwon Hwang 352b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_ofs[] = { 353e6f988a4SHyungwon Hwang [DSIM_STATUS_REG] = 0x04, 354e6f988a4SHyungwon Hwang [DSIM_SWRST_REG] = 0x0C, 355e6f988a4SHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x10, 356e6f988a4SHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x14, 357e6f988a4SHyungwon Hwang [DSIM_CONFIG_REG] = 0x18, 358e6f988a4SHyungwon Hwang [DSIM_ESCMODE_REG] = 0x1C, 359e6f988a4SHyungwon Hwang [DSIM_MDRESOL_REG] = 0x20, 360e6f988a4SHyungwon Hwang [DSIM_MVPORCH_REG] = 0x24, 361e6f988a4SHyungwon Hwang [DSIM_MHPORCH_REG] = 0x28, 362e6f988a4SHyungwon Hwang [DSIM_MSYNC_REG] = 0x2C, 363e6f988a4SHyungwon Hwang [DSIM_INTSRC_REG] = 0x34, 364e6f988a4SHyungwon Hwang [DSIM_INTMSK_REG] = 0x38, 365e6f988a4SHyungwon Hwang [DSIM_PKTHDR_REG] = 0x3C, 366e6f988a4SHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x40, 367e6f988a4SHyungwon Hwang [DSIM_RXFIFO_REG] = 0x44, 368e6f988a4SHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x4C, 369e6f988a4SHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x94, 370e6f988a4SHyungwon Hwang [DSIM_PHYCTRL_REG] = 0xA4, 371e6f988a4SHyungwon Hwang [DSIM_PHYTIMING_REG] = 0xB4, 372e6f988a4SHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0xB8, 373e6f988a4SHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0xBC, 374e6f988a4SHyungwon Hwang }; 375e6f988a4SHyungwon Hwang 376d668e8bfSHyungwon Hwang enum reg_value_idx { 377d668e8bfSHyungwon Hwang RESET_TYPE, 378d668e8bfSHyungwon Hwang PLL_TIMER, 379d668e8bfSHyungwon Hwang STOP_STATE_CNT, 380d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 381d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 382d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 383d668e8bfSHyungwon Hwang PHYTIMING_LPX, 384d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 385d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 386d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 387d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 388d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 389d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 390d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 391d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 392d668e8bfSHyungwon Hwang }; 393d668e8bfSHyungwon Hwang 394b115361eSAndrzej Hajda static const unsigned int reg_values[] = { 395d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 396d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 397d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 398d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 399d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 400d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 401d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 402d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 403d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 404d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 405d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 406d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 407d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 408d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 409d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 410d668e8bfSHyungwon Hwang }; 411d668e8bfSHyungwon Hwang 412b115361eSAndrzej Hajda static const unsigned int exynos5422_reg_values[] = { 413fdc2e108SChanho Park [RESET_TYPE] = DSIM_SWRST, 414fdc2e108SChanho Park [PLL_TIMER] = 500, 415fdc2e108SChanho Park [STOP_STATE_CNT] = 0xf, 416fdc2e108SChanho Park [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 417fdc2e108SChanho Park [PHYCTRL_VREG_LP] = 0, 418fdc2e108SChanho Park [PHYCTRL_SLEW_UP] = 0, 419fdc2e108SChanho Park [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 420fdc2e108SChanho Park [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 421fdc2e108SChanho Park [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 422fdc2e108SChanho Park [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 423fdc2e108SChanho Park [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 424fdc2e108SChanho Park [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 425fdc2e108SChanho Park [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 426fdc2e108SChanho Park [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 427fdc2e108SChanho Park [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 428fdc2e108SChanho Park }; 429fdc2e108SChanho Park 430b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_values[] = { 431e6f988a4SHyungwon Hwang [RESET_TYPE] = DSIM_FUNCRST, 432e6f988a4SHyungwon Hwang [PLL_TIMER] = 22200, 433e6f988a4SHyungwon Hwang [STOP_STATE_CNT] = 0xa, 434e6f988a4SHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 435e6f988a4SHyungwon Hwang [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 436e6f988a4SHyungwon Hwang [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 437e6f988a4SHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 438e6f988a4SHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 439e6f988a4SHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 440e6f988a4SHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 441e6f988a4SHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 442e6f988a4SHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 443e6f988a4SHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 444e6f988a4SHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 445e6f988a4SHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 446e6f988a4SHyungwon Hwang }; 447e6f988a4SHyungwon Hwang 448b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 449d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 450473462a1SInki Dae .plltmr_reg = 0x50, 451473462a1SInki Dae .has_freqband = 1, 452473462a1SInki Dae .has_clklane_stop = 1, 453d668e8bfSHyungwon Hwang .num_clks = 2, 454d668e8bfSHyungwon Hwang .max_freq = 1000, 455d668e8bfSHyungwon Hwang .wait_for_reset = 1, 456d668e8bfSHyungwon Hwang .num_bits_resol = 11, 457d668e8bfSHyungwon Hwang .reg_values = reg_values, 458473462a1SInki Dae }; 459473462a1SInki Dae 460b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 461d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4629a320415SYoungJun Cho .plltmr_reg = 0x50, 4639a320415SYoungJun Cho .has_freqband = 1, 46478d3a8c6SInki Dae .has_clklane_stop = 1, 465d668e8bfSHyungwon Hwang .num_clks = 2, 466d668e8bfSHyungwon Hwang .max_freq = 1000, 467d668e8bfSHyungwon Hwang .wait_for_reset = 1, 468d668e8bfSHyungwon Hwang .num_bits_resol = 11, 469d668e8bfSHyungwon Hwang .reg_values = reg_values, 4709a320415SYoungJun Cho }; 4719a320415SYoungJun Cho 472b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 473d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4749a320415SYoungJun Cho .plltmr_reg = 0x58, 475d668e8bfSHyungwon Hwang .num_clks = 2, 476d668e8bfSHyungwon Hwang .max_freq = 1000, 477d668e8bfSHyungwon Hwang .wait_for_reset = 1, 478d668e8bfSHyungwon Hwang .num_bits_resol = 11, 479d668e8bfSHyungwon Hwang .reg_values = reg_values, 4809a320415SYoungJun Cho }; 4819a320415SYoungJun Cho 482b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 483e6f988a4SHyungwon Hwang .reg_ofs = exynos5433_reg_ofs, 484e6f988a4SHyungwon Hwang .plltmr_reg = 0xa0, 485e6f988a4SHyungwon Hwang .has_clklane_stop = 1, 486e6f988a4SHyungwon Hwang .num_clks = 5, 487e6f988a4SHyungwon Hwang .max_freq = 1500, 488e6f988a4SHyungwon Hwang .wait_for_reset = 0, 489e6f988a4SHyungwon Hwang .num_bits_resol = 12, 490e6f988a4SHyungwon Hwang .reg_values = exynos5433_reg_values, 491e6f988a4SHyungwon Hwang }; 492e6f988a4SHyungwon Hwang 493b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 494fdc2e108SChanho Park .reg_ofs = exynos5433_reg_ofs, 495fdc2e108SChanho Park .plltmr_reg = 0xa0, 496fdc2e108SChanho Park .has_clklane_stop = 1, 497fdc2e108SChanho Park .num_clks = 2, 498fdc2e108SChanho Park .max_freq = 1500, 499fdc2e108SChanho Park .wait_for_reset = 1, 500fdc2e108SChanho Park .num_bits_resol = 12, 501fdc2e108SChanho Park .reg_values = exynos5422_reg_values, 502fdc2e108SChanho Park }; 503fdc2e108SChanho Park 504b115361eSAndrzej Hajda static const struct of_device_id exynos_dsi_of_match[] = { 505473462a1SInki Dae { .compatible = "samsung,exynos3250-mipi-dsi", 506473462a1SInki Dae .data = &exynos3_dsi_driver_data }, 5079a320415SYoungJun Cho { .compatible = "samsung,exynos4210-mipi-dsi", 5089a320415SYoungJun Cho .data = &exynos4_dsi_driver_data }, 5099a320415SYoungJun Cho { .compatible = "samsung,exynos5410-mipi-dsi", 5109a320415SYoungJun Cho .data = &exynos5_dsi_driver_data }, 511fdc2e108SChanho Park { .compatible = "samsung,exynos5422-mipi-dsi", 512fdc2e108SChanho Park .data = &exynos5422_dsi_driver_data }, 513e6f988a4SHyungwon Hwang { .compatible = "samsung,exynos5433-mipi-dsi", 514e6f988a4SHyungwon Hwang .data = &exynos5433_dsi_driver_data }, 5159a320415SYoungJun Cho { } 5169a320415SYoungJun Cho }; 5179a320415SYoungJun Cho 5187eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 5197eb8f069SAndrzej Hajda { 5207eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 5217eb8f069SAndrzej Hajda return; 5227eb8f069SAndrzej Hajda 5237eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 5247eb8f069SAndrzej Hajda } 5257eb8f069SAndrzej Hajda 5267eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 5277eb8f069SAndrzej Hajda { 528bb32e408SAndrzej Hajda u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 529ba12ac2bSHyungwon Hwang 5307eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 531bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 5327eb8f069SAndrzej Hajda } 5337eb8f069SAndrzej Hajda 5347eb8f069SAndrzej Hajda #ifndef MHZ 5357eb8f069SAndrzej Hajda #define MHZ (1000*1000) 5367eb8f069SAndrzej Hajda #endif 5377eb8f069SAndrzej Hajda 5387eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 5397eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 5407eb8f069SAndrzej Hajda { 5412154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5427eb8f069SAndrzej Hajda unsigned long best_freq = 0; 5437eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 5447eb8f069SAndrzej Hajda u8 p_min, p_max; 5453f649ab7SKees Cook u8 _p, best_p; 5463f649ab7SKees Cook u16 _m, best_m; 5473f649ab7SKees Cook u8 _s, best_s; 5487eb8f069SAndrzej Hajda 5497eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 5507eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 5517eb8f069SAndrzej Hajda 5527eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 5537eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 5547eb8f069SAndrzej Hajda u64 tmp; 5557eb8f069SAndrzej Hajda u32 delta; 5567eb8f069SAndrzej Hajda 5577eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 5587eb8f069SAndrzej Hajda do_div(tmp, fin); 5597eb8f069SAndrzej Hajda _m = tmp; 5607eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 5617eb8f069SAndrzej Hajda continue; 5627eb8f069SAndrzej Hajda 5637eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5647eb8f069SAndrzej Hajda do_div(tmp, _p); 565d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 566d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 5677eb8f069SAndrzej Hajda continue; 5687eb8f069SAndrzej Hajda 5697eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5707eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 5717eb8f069SAndrzej Hajda 5727eb8f069SAndrzej Hajda delta = abs(fout - tmp); 5737eb8f069SAndrzej Hajda if (delta < min_delta) { 5747eb8f069SAndrzej Hajda best_p = _p; 5757eb8f069SAndrzej Hajda best_m = _m; 5767eb8f069SAndrzej Hajda best_s = _s; 5777eb8f069SAndrzej Hajda min_delta = delta; 5787eb8f069SAndrzej Hajda best_freq = tmp; 5797eb8f069SAndrzej Hajda } 5807eb8f069SAndrzej Hajda } 5817eb8f069SAndrzej Hajda } 5827eb8f069SAndrzej Hajda 5837eb8f069SAndrzej Hajda if (best_freq) { 5847eb8f069SAndrzej Hajda *p = best_p; 5857eb8f069SAndrzej Hajda *m = best_m; 5867eb8f069SAndrzej Hajda *s = best_s; 5877eb8f069SAndrzej Hajda } 5887eb8f069SAndrzej Hajda 5897eb8f069SAndrzej Hajda return best_freq; 5907eb8f069SAndrzej Hajda } 5917eb8f069SAndrzej Hajda 5927eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 5937eb8f069SAndrzej Hajda unsigned long freq) 5947eb8f069SAndrzej Hajda { 5952154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5967eb8f069SAndrzej Hajda unsigned long fin, fout; 5979a320415SYoungJun Cho int timeout; 5987eb8f069SAndrzej Hajda u8 p, s; 5997eb8f069SAndrzej Hajda u16 m; 6007eb8f069SAndrzej Hajda u32 reg; 6017eb8f069SAndrzej Hajda 60226269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 6037eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 6047eb8f069SAndrzej Hajda if (!fout) { 6057eb8f069SAndrzej Hajda dev_err(dsi->dev, 6067eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 6078525b5ecSYoungJun Cho return 0; 6087eb8f069SAndrzej Hajda } 6099a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 6109a320415SYoungJun Cho 611d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 612d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 6139a320415SYoungJun Cho 6149a320415SYoungJun Cho reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 6159a320415SYoungJun Cho 6169a320415SYoungJun Cho if (driver_data->has_freqband) { 6179a320415SYoungJun Cho static const unsigned long freq_bands[] = { 6189a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 6199a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 6209a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 6219a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 6229a320415SYoungJun Cho }; 6239a320415SYoungJun Cho int band; 6247eb8f069SAndrzej Hajda 6257eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 6267eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 6277eb8f069SAndrzej Hajda break; 6287eb8f069SAndrzej Hajda 6299a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 6307eb8f069SAndrzej Hajda 6319a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 6329a320415SYoungJun Cho } 6337eb8f069SAndrzej Hajda 634bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 6357eb8f069SAndrzej Hajda 6367eb8f069SAndrzej Hajda timeout = 1000; 6377eb8f069SAndrzej Hajda do { 6387eb8f069SAndrzej Hajda if (timeout-- == 0) { 6397eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 6408525b5ecSYoungJun Cho return 0; 6417eb8f069SAndrzej Hajda } 642bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 6437eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 6447eb8f069SAndrzej Hajda 6457eb8f069SAndrzej Hajda return fout; 6467eb8f069SAndrzej Hajda } 6477eb8f069SAndrzej Hajda 6487eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 6497eb8f069SAndrzej Hajda { 6507eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 6517eb8f069SAndrzej Hajda unsigned long esc_div; 6527eb8f069SAndrzej Hajda u32 reg; 6537eb8f069SAndrzej Hajda 6547eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 6557eb8f069SAndrzej Hajda if (!hs_clk) { 6567eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 6577eb8f069SAndrzej Hajda return -EFAULT; 6587eb8f069SAndrzej Hajda } 6597eb8f069SAndrzej Hajda 6607eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 6617eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 6627eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6637eb8f069SAndrzej Hajda 6647eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 6657eb8f069SAndrzej Hajda ++esc_div; 6667eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6677eb8f069SAndrzej Hajda } 6687eb8f069SAndrzej Hajda 6697eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 6707eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 6717eb8f069SAndrzej Hajda 672bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 6737eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 6747eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 6757eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 6767eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 6777eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 6787eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 6797eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 6807eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 6817eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 682bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 6837eb8f069SAndrzej Hajda 6847eb8f069SAndrzej Hajda return 0; 6857eb8f069SAndrzej Hajda } 6867eb8f069SAndrzej Hajda 6879a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 6889a320415SYoungJun Cho { 6892154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 690b115361eSAndrzej Hajda const unsigned int *reg_values = driver_data->reg_values; 6919a320415SYoungJun Cho u32 reg; 6929a320415SYoungJun Cho 6939a320415SYoungJun Cho if (driver_data->has_freqband) 6949a320415SYoungJun Cho return; 6959a320415SYoungJun Cho 6969a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 697d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 698d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 699bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 7009a320415SYoungJun Cho 7019a320415SYoungJun Cho /* 7029a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 7039a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 7049a320415SYoungJun Cho * burst 7059a320415SYoungJun Cho */ 706d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 707bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 7089a320415SYoungJun Cho 7099a320415SYoungJun Cho /* 7109a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 7119a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7129a320415SYoungJun Cho * HS transmission 7139a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 7149a320415SYoungJun Cho * transmitting the Clock. 7159a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 7169a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 7179a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 7189a320415SYoungJun Cho * the beginning of T CLK-TRAIL 7199a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 7209a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 7219a320415SYoungJun Cho */ 722d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 723d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 724d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 725d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 726d668e8bfSHyungwon Hwang 727bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 7289a320415SYoungJun Cho 7299a320415SYoungJun Cho /* 7309a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 7319a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7329a320415SYoungJun Cho * HS transmission 7339a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 7349a320415SYoungJun Cho * transmitting the Sync sequence. 7359a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 7369a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 7379a320415SYoungJun Cho */ 738d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 739d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 740bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 7419a320415SYoungJun Cho } 7429a320415SYoungJun Cho 7437eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 7447eb8f069SAndrzej Hajda { 7457eb8f069SAndrzej Hajda u32 reg; 7467eb8f069SAndrzej Hajda 747bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 7487eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 7497eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 750bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 7517eb8f069SAndrzej Hajda 752bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 7537eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 754bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 7557eb8f069SAndrzej Hajda } 7567eb8f069SAndrzej Hajda 757e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 758e6f988a4SHyungwon Hwang { 759bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 760e6f988a4SHyungwon Hwang reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 761e6f988a4SHyungwon Hwang DSIM_LANE_EN(lane)); 762bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 763e6f988a4SHyungwon Hwang } 764e6f988a4SHyungwon Hwang 7657eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 7667eb8f069SAndrzej Hajda { 7672154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 7687eb8f069SAndrzej Hajda int timeout; 7697eb8f069SAndrzej Hajda u32 reg; 7707eb8f069SAndrzej Hajda u32 lanes_mask; 7717eb8f069SAndrzej Hajda 7727eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 773bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 7747eb8f069SAndrzej Hajda reg &= ~0x1f; 775bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 7767eb8f069SAndrzej Hajda 7777eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7787eb8f069SAndrzej Hajda 7797eb8f069SAndrzej Hajda reg |= 0x1f; 780bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 7817eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7827eb8f069SAndrzej Hajda 7837eb8f069SAndrzej Hajda /* DSI configuration */ 7847eb8f069SAndrzej Hajda reg = 0; 7857eb8f069SAndrzej Hajda 7862f36e33aSYoungJun Cho /* 7872f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 7882f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 7892f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 7902f36e33aSYoungJun Cho */ 7917eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 7927eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 7937eb8f069SAndrzej Hajda 7942f36e33aSYoungJun Cho /* 7952f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 7962f36e33aSYoungJun Cho * command mode. 7972f36e33aSYoungJun Cho */ 7987eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 7997eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 8007eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 8017eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 8027eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 8037eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 8047eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 8057eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 8067eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 8077eb8f069SAndrzej Hajda reg |= DSIM_HSE_MODE; 808*996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 8097eb8f069SAndrzej Hajda reg |= DSIM_HFP_MODE; 810*996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 8117eb8f069SAndrzej Hajda reg |= DSIM_HBP_MODE; 812*996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 8137eb8f069SAndrzej Hajda reg |= DSIM_HSA_MODE; 8147eb8f069SAndrzej Hajda } 8157eb8f069SAndrzej Hajda 816*996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 8172f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 8182f36e33aSYoungJun Cho 8197eb8f069SAndrzej Hajda switch (dsi->format) { 8207eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 8217eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 8227eb8f069SAndrzej Hajda break; 8237eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 8247eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 8257eb8f069SAndrzej Hajda break; 8267eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 8277eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 8287eb8f069SAndrzej Hajda break; 8297eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 8307eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 8317eb8f069SAndrzej Hajda break; 8327eb8f069SAndrzej Hajda default: 8337eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 8347eb8f069SAndrzej Hajda return -EINVAL; 8357eb8f069SAndrzej Hajda } 8367eb8f069SAndrzej Hajda 83778d3a8c6SInki Dae /* 83878d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 83978d3a8c6SInki Dae * host controller supports 84078d3a8c6SInki Dae * 84178d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 84278d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 84378d3a8c6SInki Dae * power consumption. 84478d3a8c6SInki Dae */ 84578d3a8c6SInki Dae if (driver_data->has_clklane_stop && 84678d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 84778d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 84878d3a8c6SInki Dae } 849bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 850e6f988a4SHyungwon Hwang 851e6f988a4SHyungwon Hwang lanes_mask = BIT(dsi->lanes) - 1; 852e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, lanes_mask); 85378d3a8c6SInki Dae 8547eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 8557eb8f069SAndrzej Hajda timeout = 100; 8567eb8f069SAndrzej Hajda do { 8577eb8f069SAndrzej Hajda if (timeout-- == 0) { 8587eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 8597eb8f069SAndrzej Hajda return -EFAULT; 8607eb8f069SAndrzej Hajda } 8617eb8f069SAndrzej Hajda 862bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 8637eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 8647eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 8657eb8f069SAndrzej Hajda continue; 8667eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 8677eb8f069SAndrzej Hajda 868bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 8697eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 870d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 871bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 8727eb8f069SAndrzej Hajda 8737eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 874bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 8757eb8f069SAndrzej Hajda 8767eb8f069SAndrzej Hajda return 0; 8777eb8f069SAndrzej Hajda } 8787eb8f069SAndrzej Hajda 8797eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 8807eb8f069SAndrzej Hajda { 881aee039e6SJagan Teki struct drm_display_mode *m = &dsi->mode; 882d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 8837eb8f069SAndrzej Hajda u32 reg; 8847eb8f069SAndrzej Hajda 8857eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8867eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 887e8929999SAndrzej Hajda | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 888e8929999SAndrzej Hajda | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 889bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 8907eb8f069SAndrzej Hajda 891e8929999SAndrzej Hajda reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) 892e8929999SAndrzej Hajda | DSIM_MAIN_HBP(m->htotal - m->hsync_end); 893bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 8947eb8f069SAndrzej Hajda 895e8929999SAndrzej Hajda reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 896e8929999SAndrzej Hajda | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); 897bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 8987eb8f069SAndrzej Hajda } 899e8929999SAndrzej Hajda reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 900e8929999SAndrzej Hajda DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 9017eb8f069SAndrzej Hajda 902bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9037eb8f069SAndrzej Hajda 904e8929999SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 9057eb8f069SAndrzej Hajda } 9067eb8f069SAndrzej Hajda 9077eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 9087eb8f069SAndrzej Hajda { 9097eb8f069SAndrzej Hajda u32 reg; 9107eb8f069SAndrzej Hajda 911bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 9127eb8f069SAndrzej Hajda if (enable) 9137eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 9147eb8f069SAndrzej Hajda else 9157eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 916bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9177eb8f069SAndrzej Hajda } 9187eb8f069SAndrzej Hajda 9197eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 9207eb8f069SAndrzej Hajda { 9217eb8f069SAndrzej Hajda int timeout = 2000; 9227eb8f069SAndrzej Hajda 9237eb8f069SAndrzej Hajda do { 924bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 9257eb8f069SAndrzej Hajda 9267eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 9277eb8f069SAndrzej Hajda return 0; 9287eb8f069SAndrzej Hajda 9297eb8f069SAndrzej Hajda if (!cond_resched()) 9307eb8f069SAndrzej Hajda usleep_range(950, 1050); 9317eb8f069SAndrzej Hajda } while (--timeout); 9327eb8f069SAndrzej Hajda 9337eb8f069SAndrzej Hajda return -ETIMEDOUT; 9347eb8f069SAndrzej Hajda } 9357eb8f069SAndrzej Hajda 9367eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 9377eb8f069SAndrzej Hajda { 938bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9397eb8f069SAndrzej Hajda 9407eb8f069SAndrzej Hajda if (lpm) 9417eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 9427eb8f069SAndrzej Hajda else 9437eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 9447eb8f069SAndrzej Hajda 945bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9467eb8f069SAndrzej Hajda } 9477eb8f069SAndrzej Hajda 9487eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 9497eb8f069SAndrzej Hajda { 950bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9517eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 952bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9537eb8f069SAndrzej Hajda } 9547eb8f069SAndrzej Hajda 9557eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 9567eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9577eb8f069SAndrzej Hajda { 9587eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9596c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 9606c81e96dSAndrzej Hajda const u8 *payload = pkt->payload + xfer->tx_done; 9616c81e96dSAndrzej Hajda u16 length = pkt->payload_length - xfer->tx_done; 9627eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 9637eb8f069SAndrzej Hajda u32 reg; 9647eb8f069SAndrzej Hajda 9659cdf0ed2SKrzysztof Kozlowski dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 9666c81e96dSAndrzej Hajda xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 9677eb8f069SAndrzej Hajda 9687eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 9697eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 9707eb8f069SAndrzej Hajda 9717eb8f069SAndrzej Hajda xfer->tx_done += length; 9727eb8f069SAndrzej Hajda 9737eb8f069SAndrzej Hajda /* Send payload */ 9747eb8f069SAndrzej Hajda while (length >= 4) { 9756c81e96dSAndrzej Hajda reg = get_unaligned_le32(payload); 976bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 9777eb8f069SAndrzej Hajda payload += 4; 9787eb8f069SAndrzej Hajda length -= 4; 9797eb8f069SAndrzej Hajda } 9807eb8f069SAndrzej Hajda 9817eb8f069SAndrzej Hajda reg = 0; 9827eb8f069SAndrzej Hajda switch (length) { 9837eb8f069SAndrzej Hajda case 3: 9847eb8f069SAndrzej Hajda reg |= payload[2] << 16; 985df561f66SGustavo A. R. Silva fallthrough; 9867eb8f069SAndrzej Hajda case 2: 9877eb8f069SAndrzej Hajda reg |= payload[1] << 8; 988df561f66SGustavo A. R. Silva fallthrough; 9897eb8f069SAndrzej Hajda case 1: 9907eb8f069SAndrzej Hajda reg |= payload[0]; 991bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 9927eb8f069SAndrzej Hajda break; 9937eb8f069SAndrzej Hajda } 9947eb8f069SAndrzej Hajda 9957eb8f069SAndrzej Hajda /* Send packet header */ 9967eb8f069SAndrzej Hajda if (!first) 9977eb8f069SAndrzej Hajda return; 9987eb8f069SAndrzej Hajda 9996c81e96dSAndrzej Hajda reg = get_unaligned_le32(pkt->header); 10007eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 10017eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 10027eb8f069SAndrzej Hajda return; 10037eb8f069SAndrzej Hajda } 10047eb8f069SAndrzej Hajda 10057eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 10067eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 10077eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 10087eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 10097eb8f069SAndrzej Hajda } 10107eb8f069SAndrzej Hajda 1011bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 10127eb8f069SAndrzej Hajda 10137eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 10147eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 10157eb8f069SAndrzej Hajda } 10167eb8f069SAndrzej Hajda 10177eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 10187eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 10197eb8f069SAndrzej Hajda { 10207eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 10217eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 10227eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 10237eb8f069SAndrzej Hajda u16 length; 10247eb8f069SAndrzej Hajda u32 reg; 10257eb8f069SAndrzej Hajda 10267eb8f069SAndrzej Hajda if (first) { 1027bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10287eb8f069SAndrzej Hajda 10297eb8f069SAndrzej Hajda switch (reg & 0x3f) { 10307eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 10317eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 10327eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 10337eb8f069SAndrzej Hajda payload[1] = reg >> 16; 10347eb8f069SAndrzej Hajda ++xfer->rx_done; 10357eb8f069SAndrzej Hajda } 1036df561f66SGustavo A. R. Silva fallthrough; 10377eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 10387eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 10397eb8f069SAndrzej Hajda payload[0] = reg >> 8; 10407eb8f069SAndrzej Hajda ++xfer->rx_done; 10417eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 10427eb8f069SAndrzej Hajda xfer->result = 0; 10437eb8f069SAndrzej Hajda goto clear_fifo; 10447eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 10457eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 10467eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 10477eb8f069SAndrzej Hajda xfer->result = 0; 10487eb8f069SAndrzej Hajda goto clear_fifo; 10497eb8f069SAndrzej Hajda } 10507eb8f069SAndrzej Hajda 10517eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 10527eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 10537eb8f069SAndrzej Hajda dev_err(dev, 10547eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 10557eb8f069SAndrzej Hajda xfer->rx_len, length); 10567eb8f069SAndrzej Hajda length = xfer->rx_len; 10577eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 10587eb8f069SAndrzej Hajda xfer->rx_len = length; 10597eb8f069SAndrzej Hajda } 10607eb8f069SAndrzej Hajda 10617eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 10627eb8f069SAndrzej Hajda xfer->rx_done += length; 10637eb8f069SAndrzej Hajda 10647eb8f069SAndrzej Hajda /* Receive payload */ 10657eb8f069SAndrzej Hajda while (length >= 4) { 1066bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10677eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 10687eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10697eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10707eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 10717eb8f069SAndrzej Hajda payload += 4; 10727eb8f069SAndrzej Hajda length -= 4; 10737eb8f069SAndrzej Hajda } 10747eb8f069SAndrzej Hajda 10757eb8f069SAndrzej Hajda if (length) { 1076bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10777eb8f069SAndrzej Hajda switch (length) { 10787eb8f069SAndrzej Hajda case 3: 10797eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 1080df561f66SGustavo A. R. Silva fallthrough; 10817eb8f069SAndrzej Hajda case 2: 10827eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 1083df561f66SGustavo A. R. Silva fallthrough; 10847eb8f069SAndrzej Hajda case 1: 10857eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 10867eb8f069SAndrzej Hajda } 10877eb8f069SAndrzej Hajda } 10887eb8f069SAndrzej Hajda 10897eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 10907eb8f069SAndrzej Hajda xfer->result = 0; 10917eb8f069SAndrzej Hajda 10927eb8f069SAndrzej Hajda clear_fifo: 10937eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 10947eb8f069SAndrzej Hajda do { 1095bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10967eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 10977eb8f069SAndrzej Hajda break; 10987eb8f069SAndrzej Hajda } while (--length); 10997eb8f069SAndrzej Hajda } 11007eb8f069SAndrzej Hajda 11017eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 11027eb8f069SAndrzej Hajda { 11037eb8f069SAndrzej Hajda unsigned long flags; 11047eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11057eb8f069SAndrzej Hajda bool start = false; 11067eb8f069SAndrzej Hajda 11077eb8f069SAndrzej Hajda again: 11087eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11097eb8f069SAndrzej Hajda 11107eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11117eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11127eb8f069SAndrzej Hajda return; 11137eb8f069SAndrzej Hajda } 11147eb8f069SAndrzej Hajda 11157eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11167eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11177eb8f069SAndrzej Hajda 11187eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11197eb8f069SAndrzej Hajda 11206c81e96dSAndrzej Hajda if (xfer->packet.payload_length && 11216c81e96dSAndrzej Hajda xfer->tx_done == xfer->packet.payload_length) 11227eb8f069SAndrzej Hajda /* waiting for RX */ 11237eb8f069SAndrzej Hajda return; 11247eb8f069SAndrzej Hajda 11257eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 11267eb8f069SAndrzej Hajda 11276c81e96dSAndrzej Hajda if (xfer->packet.payload_length || xfer->rx_len) 11287eb8f069SAndrzej Hajda return; 11297eb8f069SAndrzej Hajda 11307eb8f069SAndrzej Hajda xfer->result = 0; 11317eb8f069SAndrzej Hajda complete(&xfer->completed); 11327eb8f069SAndrzej Hajda 11337eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11347eb8f069SAndrzej Hajda 11357eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11367eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11377eb8f069SAndrzej Hajda 11387eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11397eb8f069SAndrzej Hajda 11407eb8f069SAndrzej Hajda if (start) 11417eb8f069SAndrzej Hajda goto again; 11427eb8f069SAndrzej Hajda } 11437eb8f069SAndrzej Hajda 11447eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 11457eb8f069SAndrzej Hajda { 11467eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11477eb8f069SAndrzej Hajda unsigned long flags; 11487eb8f069SAndrzej Hajda bool start = true; 11497eb8f069SAndrzej Hajda 11507eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11517eb8f069SAndrzej Hajda 11527eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11537eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11547eb8f069SAndrzej Hajda return false; 11557eb8f069SAndrzej Hajda } 11567eb8f069SAndrzej Hajda 11577eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11587eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11597eb8f069SAndrzej Hajda 11607eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11617eb8f069SAndrzej Hajda 11627eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 11639cdf0ed2SKrzysztof Kozlowski "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 11646c81e96dSAndrzej Hajda xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 11656c81e96dSAndrzej Hajda xfer->rx_done); 11667eb8f069SAndrzej Hajda 11676c81e96dSAndrzej Hajda if (xfer->tx_done != xfer->packet.payload_length) 11687eb8f069SAndrzej Hajda return true; 11697eb8f069SAndrzej Hajda 11707eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11717eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 11727eb8f069SAndrzej Hajda 11737eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11747eb8f069SAndrzej Hajda return true; 11757eb8f069SAndrzej Hajda 11767eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11777eb8f069SAndrzej Hajda 11787eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11797eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11807eb8f069SAndrzej Hajda 11817eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11827eb8f069SAndrzej Hajda 11837eb8f069SAndrzej Hajda if (!xfer->rx_len) 11847eb8f069SAndrzej Hajda xfer->result = 0; 11857eb8f069SAndrzej Hajda complete(&xfer->completed); 11867eb8f069SAndrzej Hajda 11877eb8f069SAndrzej Hajda return start; 11887eb8f069SAndrzej Hajda } 11897eb8f069SAndrzej Hajda 11907eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 11917eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 11927eb8f069SAndrzej Hajda { 11937eb8f069SAndrzej Hajda unsigned long flags; 11947eb8f069SAndrzej Hajda bool start; 11957eb8f069SAndrzej Hajda 11967eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11977eb8f069SAndrzej Hajda 11987eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 11997eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 12007eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 12017eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12027eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12037eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12047eb8f069SAndrzej Hajda if (start) 12057eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12067eb8f069SAndrzej Hajda return; 12077eb8f069SAndrzej Hajda } 12087eb8f069SAndrzej Hajda 12097eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12107eb8f069SAndrzej Hajda 12117eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12127eb8f069SAndrzej Hajda } 12137eb8f069SAndrzej Hajda 12147eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 12157eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12167eb8f069SAndrzej Hajda { 12177eb8f069SAndrzej Hajda unsigned long flags; 12187eb8f069SAndrzej Hajda bool stopped; 12197eb8f069SAndrzej Hajda 12207eb8f069SAndrzej Hajda xfer->tx_done = 0; 12217eb8f069SAndrzej Hajda xfer->rx_done = 0; 12227eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 12237eb8f069SAndrzej Hajda init_completion(&xfer->completed); 12247eb8f069SAndrzej Hajda 12257eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12267eb8f069SAndrzej Hajda 12277eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 12287eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 12297eb8f069SAndrzej Hajda 12307eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12317eb8f069SAndrzej Hajda 12327eb8f069SAndrzej Hajda if (stopped) 12337eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12347eb8f069SAndrzej Hajda 12357eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 12367eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 12377eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 12386c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 12397eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 12406c81e96dSAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 12416c81e96dSAndrzej Hajda (int)pkt->payload_length, pkt->payload); 12427eb8f069SAndrzej Hajda return -ETIMEDOUT; 12437eb8f069SAndrzej Hajda } 12447eb8f069SAndrzej Hajda 12457eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 12467eb8f069SAndrzej Hajda return xfer->result; 12477eb8f069SAndrzej Hajda } 12487eb8f069SAndrzej Hajda 12497eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 12507eb8f069SAndrzej Hajda { 12517eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 12527eb8f069SAndrzej Hajda u32 status; 12537eb8f069SAndrzej Hajda 1254bb32e408SAndrzej Hajda status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 12557eb8f069SAndrzej Hajda if (!status) { 12567eb8f069SAndrzej Hajda static unsigned long int j; 12577eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 12587eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 12597eb8f069SAndrzej Hajda return IRQ_HANDLED; 12607eb8f069SAndrzej Hajda } 1261bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 12627eb8f069SAndrzej Hajda 12637eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 1264e6f988a4SHyungwon Hwang u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1265ecf81ed9SAndrzej Hajda DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | 1266ecf81ed9SAndrzej Hajda DSIM_INT_SW_RST_RELEASE); 1267bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 12687eb8f069SAndrzej Hajda complete(&dsi->completed); 12697eb8f069SAndrzej Hajda return IRQ_HANDLED; 12707eb8f069SAndrzej Hajda } 12717eb8f069SAndrzej Hajda 1272e6f988a4SHyungwon Hwang if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1273ecf81ed9SAndrzej Hajda DSIM_INT_PLL_STABLE))) 12747eb8f069SAndrzej Hajda return IRQ_HANDLED; 12757eb8f069SAndrzej Hajda 12767eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 12777eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12787eb8f069SAndrzej Hajda 12797eb8f069SAndrzej Hajda return IRQ_HANDLED; 12807eb8f069SAndrzej Hajda } 12817eb8f069SAndrzej Hajda 1282e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1283e17ddeccSYoungJun Cho { 1284e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 12852b8376c8SGustavo Padovan struct drm_encoder *encoder = &dsi->encoder; 1286e17ddeccSYoungJun Cho 12870e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1288e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1289e17ddeccSYoungJun Cho 1290e17ddeccSYoungJun Cho return IRQ_HANDLED; 1291e17ddeccSYoungJun Cho } 1292e17ddeccSYoungJun Cho 1293e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1294e17ddeccSYoungJun Cho { 1295e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1296e17ddeccSYoungJun Cho 1297ee6c8b5aSMaíra Canal if (dsi->te_gpio) 1298ee6c8b5aSMaíra Canal enable_irq(gpiod_to_irq(dsi->te_gpio)); 1299e17ddeccSYoungJun Cho } 1300e17ddeccSYoungJun Cho 1301e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1302e17ddeccSYoungJun Cho { 1303ee6c8b5aSMaíra Canal if (dsi->te_gpio) 1304ee6c8b5aSMaíra Canal disable_irq(gpiod_to_irq(dsi->te_gpio)); 1305e17ddeccSYoungJun Cho 1306e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1307e17ddeccSYoungJun Cho } 1308e17ddeccSYoungJun Cho 13097eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 13107eb8f069SAndrzej Hajda { 13112154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1312d668e8bfSHyungwon Hwang 13137eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1314e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 1315e6f988a4SHyungwon Hwang 1316e6f988a4SHyungwon Hwang if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1317e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1318e6f988a4SHyungwon Hwang 13199a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1320d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 13217eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 13229a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 13237eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 13247eb8f069SAndrzej Hajda 13257eb8f069SAndrzej Hajda return 0; 13267eb8f069SAndrzej Hajda } 13277eb8f069SAndrzej Hajda 1328295e7954SAndrzej Hajda static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, 1329295e7954SAndrzej Hajda struct device *panel) 1330e17ddeccSYoungJun Cho { 1331e17ddeccSYoungJun Cho int ret; 13320cef83a5SYoungJun Cho int te_gpio_irq; 1333e17ddeccSYoungJun Cho 1334fedc8982SMarek Szyprowski dsi->te_gpio = gpiod_get_optional(panel, "te", GPIOD_IN); 13358e3fa9d8SMarek Szyprowski if (!dsi->te_gpio) { 13368e3fa9d8SMarek Szyprowski return 0; 13378e3fa9d8SMarek Szyprowski } else if (IS_ERR(dsi->te_gpio)) { 1338ee6c8b5aSMaíra Canal dev_err(dsi->dev, "gpio request failed with %ld\n", 1339ee6c8b5aSMaíra Canal PTR_ERR(dsi->te_gpio)); 1340760cceffSInki Dae return PTR_ERR(dsi->te_gpio); 1341e17ddeccSYoungJun Cho } 1342e17ddeccSYoungJun Cho 1343ee6c8b5aSMaíra Canal te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 134451d1decaSHyungwon Hwang 13450cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1346a4e5eed2STian Tao IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1347e17ddeccSYoungJun Cho if (ret) { 1348e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1349ee6c8b5aSMaíra Canal gpiod_put(dsi->te_gpio); 1350760cceffSInki Dae return ret; 1351e17ddeccSYoungJun Cho } 1352e17ddeccSYoungJun Cho 1353760cceffSInki Dae return 0; 1354e17ddeccSYoungJun Cho } 1355e17ddeccSYoungJun Cho 1356e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1357e17ddeccSYoungJun Cho { 1358ee6c8b5aSMaíra Canal if (dsi->te_gpio) { 1359ee6c8b5aSMaíra Canal free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1360ee6c8b5aSMaíra Canal gpiod_put(dsi->te_gpio); 1361e17ddeccSYoungJun Cho } 1362e17ddeccSYoungJun Cho } 1363e17ddeccSYoungJun Cho 136495a2441eSJagan Teki static void exynos_dsi_atomic_pre_enable(struct drm_bridge *bridge, 136595a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 13667eb8f069SAndrzej Hajda { 1367f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 13687eb8f069SAndrzej Hajda int ret; 13697eb8f069SAndrzej Hajda 13707eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 1371b6595dc7SGustavo Padovan return; 13727eb8f069SAndrzej Hajda 1373445d3bedSInki Dae ret = pm_runtime_resume_and_get(dsi->dev); 1374445d3bedSInki Dae if (ret < 0) { 1375445d3bedSInki Dae dev_err(dsi->dev, "failed to enable DSI device.\n"); 1376445d3bedSInki Dae return; 1377445d3bedSInki Dae } 1378445d3bedSInki Dae 13790e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 1380f66ff55aSBoris Brezillon } 13817eb8f069SAndrzej Hajda 138295a2441eSJagan Teki static void exynos_dsi_atomic_enable(struct drm_bridge *bridge, 138395a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 1384f9bfd326SJagan Teki { 1385f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1386f9bfd326SJagan Teki 13877eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 13887eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 13897eb8f069SAndrzej Hajda 13900e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1391f9bfd326SJagan Teki 13928a08f671SMaciej Purski return; 13937eb8f069SAndrzej Hajda } 13947eb8f069SAndrzej Hajda 139595a2441eSJagan Teki static void exynos_dsi_atomic_disable(struct drm_bridge *bridge, 139695a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 13977eb8f069SAndrzej Hajda { 1398f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1399b6595dc7SGustavo Padovan 14007eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 14017eb8f069SAndrzej Hajda return; 14027eb8f069SAndrzej Hajda 14030e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1404f66ff55aSBoris Brezillon } 1405f66ff55aSBoris Brezillon 140695a2441eSJagan Teki static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, 140795a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 1408f9bfd326SJagan Teki { 1409f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1410f9bfd326SJagan Teki 1411cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1412f66ff55aSBoris Brezillon 14137eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 1414ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 14157eb8f069SAndrzej Hajda } 14167eb8f069SAndrzej Hajda 1417f9bfd326SJagan Teki static void exynos_dsi_mode_set(struct drm_bridge *bridge, 1418f9bfd326SJagan Teki const struct drm_display_mode *mode, 1419f9bfd326SJagan Teki const struct drm_display_mode *adjusted_mode) 1420bd29823eSJagan Teki { 1421f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1422bd29823eSJagan Teki 1423bd29823eSJagan Teki drm_mode_copy(&dsi->mode, adjusted_mode); 1424bd29823eSJagan Teki } 1425bd29823eSJagan Teki 1426f9bfd326SJagan Teki static int exynos_dsi_attach(struct drm_bridge *bridge, 1427f9bfd326SJagan Teki enum drm_bridge_attach_flags flags) 1428f9bfd326SJagan Teki { 1429f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1430f9bfd326SJagan Teki 1431f9bfd326SJagan Teki return drm_bridge_attach(bridge->encoder, dsi->out_bridge, NULL, flags); 1432f9bfd326SJagan Teki } 1433f9bfd326SJagan Teki 1434f9bfd326SJagan Teki static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { 143595a2441eSJagan Teki .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 143695a2441eSJagan Teki .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 143795a2441eSJagan Teki .atomic_reset = drm_atomic_helper_bridge_reset, 143895a2441eSJagan Teki .atomic_pre_enable = exynos_dsi_atomic_pre_enable, 143995a2441eSJagan Teki .atomic_enable = exynos_dsi_atomic_enable, 144095a2441eSJagan Teki .atomic_disable = exynos_dsi_atomic_disable, 144195a2441eSJagan Teki .atomic_post_disable = exynos_dsi_atomic_post_disable, 1442aee039e6SJagan Teki .mode_set = exynos_dsi_mode_set, 1443f9bfd326SJagan Teki .attach = exynos_dsi_attach, 14447eb8f069SAndrzej Hajda }; 14457eb8f069SAndrzej Hajda 1446bd024b86SSjoerd Simons MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 14477eb8f069SAndrzej Hajda 1448295e7954SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1449295e7954SAndrzej Hajda struct mipi_dsi_device *device) 1450295e7954SAndrzej Hajda { 1451295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 1452711c7adcSJagan Teki struct device *dev = dsi->dev; 14536afb7721SMaciej Purski struct drm_encoder *encoder = &dsi->encoder; 14546afb7721SMaciej Purski struct drm_device *drm = encoder->dev; 1455ea16c74cSJagan Teki struct drm_panel *panel; 1456711c7adcSJagan Teki int ret; 14576afb7721SMaciej Purski 1458ea16c74cSJagan Teki panel = of_drm_find_panel(device->dev.of_node); 1459ea16c74cSJagan Teki if (!IS_ERR(panel)) { 1460ea16c74cSJagan Teki dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1461ea16c74cSJagan Teki } else { 1462ea16c74cSJagan Teki dsi->out_bridge = of_drm_find_bridge(device->dev.of_node); 1463ea16c74cSJagan Teki if (!dsi->out_bridge) 1464ea16c74cSJagan Teki dsi->out_bridge = ERR_PTR(-EINVAL); 1465ea16c74cSJagan Teki } 1466ea16c74cSJagan Teki 1467711c7adcSJagan Teki if (IS_ERR(dsi->out_bridge)) { 1468711c7adcSJagan Teki ret = PTR_ERR(dsi->out_bridge); 1469711c7adcSJagan Teki DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 14706afb7721SMaciej Purski return ret; 14716afb7721SMaciej Purski } 14726afb7721SMaciej Purski 1473711c7adcSJagan Teki DRM_DEV_INFO(dev, "Attached %s device\n", device->name); 1474711c7adcSJagan Teki 1475f9bfd326SJagan Teki drm_bridge_add(&dsi->bridge); 1476f9bfd326SJagan Teki 1477f9bfd326SJagan Teki drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1478295e7954SAndrzej Hajda 1479295e7954SAndrzej Hajda /* 1480295e7954SAndrzej Hajda * This is a temporary solution and should be made by more generic way. 1481295e7954SAndrzej Hajda * 1482295e7954SAndrzej Hajda * If attached panel device is for command mode one, dsi should register 1483295e7954SAndrzej Hajda * TE interrupt handler. 1484295e7954SAndrzej Hajda */ 1485295e7954SAndrzej Hajda if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1486711c7adcSJagan Teki ret = exynos_dsi_register_te_irq(dsi, &device->dev); 1487295e7954SAndrzej Hajda if (ret) 1488295e7954SAndrzej Hajda return ret; 1489295e7954SAndrzej Hajda } 1490295e7954SAndrzej Hajda 1491295e7954SAndrzej Hajda mutex_lock(&drm->mode_config.mutex); 1492295e7954SAndrzej Hajda 1493295e7954SAndrzej Hajda dsi->lanes = device->lanes; 1494295e7954SAndrzej Hajda dsi->format = device->format; 1495295e7954SAndrzej Hajda dsi->mode_flags = device->mode_flags; 1496c038f538SAndrzej Hajda exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = 1497c038f538SAndrzej Hajda !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); 1498295e7954SAndrzej Hajda 1499295e7954SAndrzej Hajda mutex_unlock(&drm->mode_config.mutex); 1500295e7954SAndrzej Hajda 1501295e7954SAndrzej Hajda if (drm->mode_config.poll_enabled) 1502295e7954SAndrzej Hajda drm_kms_helper_hotplug_event(drm); 1503295e7954SAndrzej Hajda 1504295e7954SAndrzej Hajda return 0; 1505295e7954SAndrzej Hajda } 1506295e7954SAndrzej Hajda 1507295e7954SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1508295e7954SAndrzej Hajda struct mipi_dsi_device *device) 1509295e7954SAndrzej Hajda { 1510295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 15116afb7721SMaciej Purski struct drm_device *drm = dsi->encoder.dev; 1512295e7954SAndrzej Hajda 15136afb7721SMaciej Purski if (dsi->out_bridge->funcs->detach) 15146afb7721SMaciej Purski dsi->out_bridge->funcs->detach(dsi->out_bridge); 15156afb7721SMaciej Purski dsi->out_bridge = NULL; 1516295e7954SAndrzej Hajda 1517295e7954SAndrzej Hajda if (drm->mode_config.poll_enabled) 1518295e7954SAndrzej Hajda drm_kms_helper_hotplug_event(drm); 1519295e7954SAndrzej Hajda 1520295e7954SAndrzej Hajda exynos_dsi_unregister_te_irq(dsi); 1521295e7954SAndrzej Hajda 1522f9bfd326SJagan Teki drm_bridge_remove(&dsi->bridge); 1523f9bfd326SJagan Teki 1524295e7954SAndrzej Hajda return 0; 1525295e7954SAndrzej Hajda } 1526295e7954SAndrzej Hajda 1527295e7954SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1528295e7954SAndrzej Hajda const struct mipi_dsi_msg *msg) 1529295e7954SAndrzej Hajda { 1530295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 1531295e7954SAndrzej Hajda struct exynos_dsi_transfer xfer; 1532295e7954SAndrzej Hajda int ret; 1533295e7954SAndrzej Hajda 1534295e7954SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 1535295e7954SAndrzej Hajda return -EINVAL; 1536295e7954SAndrzej Hajda 1537295e7954SAndrzej Hajda if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1538295e7954SAndrzej Hajda ret = exynos_dsi_init(dsi); 1539295e7954SAndrzej Hajda if (ret) 1540295e7954SAndrzej Hajda return ret; 1541295e7954SAndrzej Hajda dsi->state |= DSIM_STATE_INITIALIZED; 1542295e7954SAndrzej Hajda } 1543295e7954SAndrzej Hajda 1544295e7954SAndrzej Hajda ret = mipi_dsi_create_packet(&xfer.packet, msg); 1545295e7954SAndrzej Hajda if (ret < 0) 1546295e7954SAndrzej Hajda return ret; 1547295e7954SAndrzej Hajda 1548295e7954SAndrzej Hajda xfer.rx_len = msg->rx_len; 1549295e7954SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 1550295e7954SAndrzej Hajda xfer.flags = msg->flags; 1551295e7954SAndrzej Hajda 1552295e7954SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 1553295e7954SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 1554295e7954SAndrzej Hajda } 1555295e7954SAndrzej Hajda 1556295e7954SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1557295e7954SAndrzej Hajda .attach = exynos_dsi_host_attach, 1558295e7954SAndrzej Hajda .detach = exynos_dsi_host_detach, 1559295e7954SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 1560295e7954SAndrzej Hajda }; 1561295e7954SAndrzej Hajda 15627eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 15637eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 15647eb8f069SAndrzej Hajda { 15657eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 15667eb8f069SAndrzej Hajda 15677eb8f069SAndrzej Hajda if (ret < 0) 15684bf99144SRob Herring pr_err("%pOF: failed to get '%s' property\n", np, propname); 15697eb8f069SAndrzej Hajda 15707eb8f069SAndrzej Hajda return ret; 15717eb8f069SAndrzej Hajda } 15727eb8f069SAndrzej Hajda 15737eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 15747eb8f069SAndrzej Hajda { 15757eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 15767eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 15777eb8f069SAndrzej Hajda int ret; 15787eb8f069SAndrzej Hajda 15797eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 15807eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 15817eb8f069SAndrzej Hajda if (ret < 0) 15827eb8f069SAndrzej Hajda return ret; 15837eb8f069SAndrzej Hajda 1584f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 15857eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 15867eb8f069SAndrzej Hajda if (ret < 0) 1587f2921d8cSHoegeun Kwon return ret; 15887eb8f069SAndrzej Hajda 1589f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 15907eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 1591f5f3b9baSHyungwon Hwang if (ret < 0) 1592f2921d8cSHoegeun Kwon return ret; 1593f5f3b9baSHyungwon Hwang 1594f2921d8cSHoegeun Kwon return 0; 15957eb8f069SAndrzej Hajda } 15967eb8f069SAndrzej Hajda 1597f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1598f37cd5e8SInki Dae void *data) 1599f37cd5e8SInki Dae { 1600e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 1601e11e6df2SMichael Tretter struct drm_encoder *encoder = &dsi->encoder; 1602f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1603f37cd5e8SInki Dae int ret; 1604f37cd5e8SInki Dae 16053e1fe32dSThomas Zimmermann drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS); 16062b8376c8SGustavo Padovan 16071ca582f1SAndrzej Hajda ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); 16081ca582f1SAndrzej Hajda if (ret < 0) 16091ca582f1SAndrzej Hajda return ret; 16101ca582f1SAndrzej Hajda 1611f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1612f37cd5e8SInki Dae } 1613f37cd5e8SInki Dae 1614f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1615f37cd5e8SInki Dae void *data) 1616f37cd5e8SInki Dae { 1617e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 1618f37cd5e8SInki Dae 161995a2441eSJagan Teki exynos_dsi_atomic_disable(&dsi->bridge, NULL); 1620f37cd5e8SInki Dae 16210ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1622f37cd5e8SInki Dae } 1623f37cd5e8SInki Dae 1624f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1625f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1626f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1627f37cd5e8SInki Dae }; 1628f37cd5e8SInki Dae 16297eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 16307eb8f069SAndrzej Hajda { 16312900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 16327eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 16330ff03fd1SHyungwon Hwang int ret, i; 16347eb8f069SAndrzej Hajda 16352900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 16362900c69cSAndrzej Hajda if (!dsi) 16372900c69cSAndrzej Hajda return -ENOMEM; 16382900c69cSAndrzej Hajda 16397eb8f069SAndrzej Hajda init_completion(&dsi->completed); 16407eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 16417eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 16427eb8f069SAndrzej Hajda 16437eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1644e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 16457eb8f069SAndrzej Hajda 1646e2d2a1e0SAndrzej Hajda dsi->dev = dev; 16472154ac92SMarek Szyprowski dsi->driver_data = of_device_get_match_data(dev); 16487eb8f069SAndrzej Hajda 16497eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 16507eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1651e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 16527eb8f069SAndrzej Hajda dsi->supplies); 165373bb394cSKrzysztof Kozlowski if (ret) 165473bb394cSKrzysztof Kozlowski return dev_err_probe(dev, ret, "failed to get regulators\n"); 16557eb8f069SAndrzej Hajda 1656a86854d0SKees Cook dsi->clks = devm_kcalloc(dev, 1657a86854d0SKees Cook dsi->driver_data->num_clks, sizeof(*dsi->clks), 16580ff03fd1SHyungwon Hwang GFP_KERNEL); 1659e6f988a4SHyungwon Hwang if (!dsi->clks) 1660e6f988a4SHyungwon Hwang return -ENOMEM; 1661e6f988a4SHyungwon Hwang 16620ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 16630ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 16640ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 16650ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1666c0fd99d6SMarek Szyprowski dsi->clks[i] = devm_clk_get(dev, 1667c0fd99d6SMarek Szyprowski OLD_SCLK_MIPI_CLK_NAME); 1668c0fd99d6SMarek Szyprowski if (!IS_ERR(dsi->clks[i])) 16690ff03fd1SHyungwon Hwang continue; 16707eb8f069SAndrzej Hajda } 16717eb8f069SAndrzej Hajda 16720ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 16730ff03fd1SHyungwon Hwang clk_names[i]); 16740ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 16750ff03fd1SHyungwon Hwang } 16767eb8f069SAndrzej Hajda } 16777eb8f069SAndrzej Hajda 167817ac76e0SCai Huoqing dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 167904562956SZhen Lei if (IS_ERR(dsi->reg_base)) 168086650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 16817eb8f069SAndrzej Hajda 1682e2d2a1e0SAndrzej Hajda dsi->phy = devm_phy_get(dev, "dsim"); 16837eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1684e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 168586650408SAndrzej Hajda return PTR_ERR(dsi->phy); 16867eb8f069SAndrzej Hajda } 16877eb8f069SAndrzej Hajda 16887eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 1689fdd79b0dSMarkus Elfring if (dsi->irq < 0) 169086650408SAndrzej Hajda return dsi->irq; 16917eb8f069SAndrzej Hajda 1692e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1693a4e5eed2STian Tao exynos_dsi_irq, 1694a4e5eed2STian Tao IRQF_ONESHOT | IRQF_NO_AUTOEN, 1695e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 16967eb8f069SAndrzej Hajda if (ret) { 1697e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 169886650408SAndrzej Hajda return ret; 16997eb8f069SAndrzej Hajda } 17007eb8f069SAndrzej Hajda 1701547a7348SChristophe JAILLET ret = exynos_dsi_parse_dt(dsi); 1702547a7348SChristophe JAILLET if (ret) 1703547a7348SChristophe JAILLET return ret; 1704547a7348SChristophe JAILLET 1705e11e6df2SMichael Tretter platform_set_drvdata(pdev, dsi); 17067eb8f069SAndrzej Hajda 1707ba6e4779SInki Dae pm_runtime_enable(dev); 1708ba6e4779SInki Dae 1709f9bfd326SJagan Teki dsi->bridge.funcs = &exynos_dsi_bridge_funcs; 1710f9bfd326SJagan Teki dsi->bridge.of_node = dev->of_node; 1711f9bfd326SJagan Teki dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1712f9bfd326SJagan Teki 1713547a7348SChristophe JAILLET ret = component_add(dev, &exynos_dsi_component_ops); 1714547a7348SChristophe JAILLET if (ret) 1715547a7348SChristophe JAILLET goto err_disable_runtime; 1716547a7348SChristophe JAILLET 1717547a7348SChristophe JAILLET return 0; 1718547a7348SChristophe JAILLET 1719547a7348SChristophe JAILLET err_disable_runtime: 1720547a7348SChristophe JAILLET pm_runtime_disable(dev); 1721547a7348SChristophe JAILLET 1722547a7348SChristophe JAILLET return ret; 17237eb8f069SAndrzej Hajda } 17247eb8f069SAndrzej Hajda 17257eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 17267eb8f069SAndrzej Hajda { 1727ba6e4779SInki Dae pm_runtime_disable(&pdev->dev); 1728ba6e4779SInki Dae 1729df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1730df5225bcSInki Dae 17317eb8f069SAndrzej Hajda return 0; 17327eb8f069SAndrzej Hajda } 17337eb8f069SAndrzej Hajda 1734010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1735ba6e4779SInki Dae { 1736e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 17372154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1738ba6e4779SInki Dae int ret, i; 1739ba6e4779SInki Dae 1740ba6e4779SInki Dae usleep_range(10000, 20000); 1741ba6e4779SInki Dae 1742ba6e4779SInki Dae if (dsi->state & DSIM_STATE_INITIALIZED) { 1743ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_INITIALIZED; 1744ba6e4779SInki Dae 1745ba6e4779SInki Dae exynos_dsi_disable_clock(dsi); 1746ba6e4779SInki Dae 1747ba6e4779SInki Dae exynos_dsi_disable_irq(dsi); 1748ba6e4779SInki Dae } 1749ba6e4779SInki Dae 1750ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_CMD_LPM; 1751ba6e4779SInki Dae 1752ba6e4779SInki Dae phy_power_off(dsi->phy); 1753ba6e4779SInki Dae 1754ba6e4779SInki Dae for (i = driver_data->num_clks - 1; i > -1; i--) 1755ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1756ba6e4779SInki Dae 1757ba6e4779SInki Dae ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1758ba6e4779SInki Dae if (ret < 0) 1759ba6e4779SInki Dae dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1760ba6e4779SInki Dae 1761ba6e4779SInki Dae return 0; 1762ba6e4779SInki Dae } 1763ba6e4779SInki Dae 1764010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_resume(struct device *dev) 1765ba6e4779SInki Dae { 1766e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 17672154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1768ba6e4779SInki Dae int ret, i; 1769ba6e4779SInki Dae 1770ba6e4779SInki Dae ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1771ba6e4779SInki Dae if (ret < 0) { 1772ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1773ba6e4779SInki Dae return ret; 1774ba6e4779SInki Dae } 1775ba6e4779SInki Dae 1776ba6e4779SInki Dae for (i = 0; i < driver_data->num_clks; i++) { 1777ba6e4779SInki Dae ret = clk_prepare_enable(dsi->clks[i]); 1778ba6e4779SInki Dae if (ret < 0) 1779ba6e4779SInki Dae goto err_clk; 1780ba6e4779SInki Dae } 1781ba6e4779SInki Dae 1782ba6e4779SInki Dae ret = phy_power_on(dsi->phy); 1783ba6e4779SInki Dae if (ret < 0) { 1784ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1785ba6e4779SInki Dae goto err_clk; 1786ba6e4779SInki Dae } 1787ba6e4779SInki Dae 1788ba6e4779SInki Dae return 0; 1789ba6e4779SInki Dae 1790ba6e4779SInki Dae err_clk: 1791ba6e4779SInki Dae while (--i > -1) 1792ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1793ba6e4779SInki Dae regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1794ba6e4779SInki Dae 1795ba6e4779SInki Dae return ret; 1796ba6e4779SInki Dae } 1797ba6e4779SInki Dae 1798ba6e4779SInki Dae static const struct dev_pm_ops exynos_dsi_pm_ops = { 1799ba6e4779SInki Dae SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 18007e915746SMarek Szyprowski SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 18017e915746SMarek Szyprowski pm_runtime_force_resume) 1802ba6e4779SInki Dae }; 1803ba6e4779SInki Dae 18047eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 18057eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 18067eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 18077eb8f069SAndrzej Hajda .driver = { 18087eb8f069SAndrzej Hajda .name = "exynos-dsi", 18097eb8f069SAndrzej Hajda .owner = THIS_MODULE, 1810ba6e4779SInki Dae .pm = &exynos_dsi_pm_ops, 18117eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 18127eb8f069SAndrzej Hajda }, 18137eb8f069SAndrzej Hajda }; 18147eb8f069SAndrzej Hajda 18157eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 18167eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 18177eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 18187eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 1819