1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 27eb8f069SAndrzej Hajda /* 37eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 47eb8f069SAndrzej Hajda * 57eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 67eb8f069SAndrzej Hajda * 77eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 87eb8f069SAndrzej Hajda */ 97eb8f069SAndrzej Hajda 107eb8f069SAndrzej Hajda #include <linux/clk.h> 112bda34d7SSam Ravnborg #include <linux/delay.h> 122bda34d7SSam Ravnborg #include <linux/component.h> 13e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 147eb8f069SAndrzej Hajda #include <linux/irq.h> 159a320415SYoungJun Cho #include <linux/of_device.h> 16f5f3b9baSHyungwon Hwang #include <linux/of_graph.h> 177eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 187eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 192bda34d7SSam Ravnborg 202bda34d7SSam Ravnborg #include <asm/unaligned.h> 217eb8f069SAndrzej Hajda 227eb8f069SAndrzej Hajda #include <video/mipi_display.h> 237eb8f069SAndrzej Hajda #include <video/videomode.h> 247eb8f069SAndrzej Hajda 252bda34d7SSam Ravnborg #include <drm/drm_atomic_helper.h> 26ee68c743SBoris Brezillon #include <drm/drm_bridge.h> 272bda34d7SSam Ravnborg #include <drm/drm_mipi_dsi.h> 28ea16c74cSJagan Teki #include <drm/drm_panel.h> 292bda34d7SSam Ravnborg #include <drm/drm_print.h> 302bda34d7SSam Ravnborg #include <drm/drm_probe_helper.h> 313e1fe32dSThomas Zimmermann #include <drm/drm_simple_kms_helper.h> 322bda34d7SSam Ravnborg 33e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 347eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 357eb8f069SAndrzej Hajda 367eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 377eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 387eb8f069SAndrzej Hajda 397eb8f069SAndrzej Hajda /* DSIM_STATUS */ 407eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 417eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 427eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 437eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 447eb8f069SAndrzej Hajda 457eb8f069SAndrzej Hajda /* DSIM_SWRST */ 467eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 477eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 487eb8f069SAndrzej Hajda 497eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 507eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 517eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 527eb8f069SAndrzej Hajda 537eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 547eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 557eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 567eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 587eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 597eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 617eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 627eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 637eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 647eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 657eb8f069SAndrzej Hajda 667eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 677eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 687eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 697eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 707eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 717eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 757eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 767eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 777eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 782e337a8dSJagan Teki #define DSIM_HSA_DISABLE_MODE (1 << 20) 792e337a8dSJagan Teki #define DSIM_HBP_DISABLE_MODE (1 << 21) 802e337a8dSJagan Teki #define DSIM_HFP_DISABLE_MODE (1 << 22) 812e337a8dSJagan Teki /* 822e337a8dSJagan Teki * The i.MX 8M Mini Applications Processor Reference Manual, 832e337a8dSJagan Teki * Rev. 3, 11/2020 Page 4091 842e337a8dSJagan Teki * The i.MX 8M Nano Applications Processor Reference Manual, 852e337a8dSJagan Teki * Rev. 2, 07/2022 Page 3058 862e337a8dSJagan Teki * The i.MX 8M Plus Applications Processor Reference Manual, 872e337a8dSJagan Teki * Rev. 1, 06/2021 Page 5436 882e337a8dSJagan Teki * named this bit as 'HseDisableMode' but the bit definition 892e337a8dSJagan Teki * is quite opposite like 902e337a8dSJagan Teki * 0 = Disables transfer 912e337a8dSJagan Teki * 1 = Enables transfer 922e337a8dSJagan Teki * which clearly states that HSE is not a disable bit. 932e337a8dSJagan Teki * 942e337a8dSJagan Teki * This bit is named as per the manual even though it is not 952e337a8dSJagan Teki * a disable bit however the driver logic for handling HSE 962e337a8dSJagan Teki * is based on the MIPI_DSI_MODE_VIDEO_HSE flag itself. 972e337a8dSJagan Teki */ 982e337a8dSJagan Teki #define DSIM_HSE_DISABLE_MODE (1 << 23) 997eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 1007eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 1017eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 1027eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 1037eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 1047eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 1056bdc92eeSKrzysztof Kozlowski /* This flag is valid only for exynos3250/3472/5260/5430 */ 10678d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 1077eb8f069SAndrzej Hajda 1087eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 1097eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 1107eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 1117eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 1127eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 1137eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 1147eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 1157eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 1167eb8f069SAndrzej Hajda 1177eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 1187eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 119d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 120d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1217eb8f069SAndrzej Hajda 1227eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1237eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1247eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1257eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1267eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1277eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1287eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1297eb8f069SAndrzej Hajda 1307eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1317eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1327eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1337eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1347eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1357eb8f069SAndrzej Hajda 1367eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1377eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1387eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1397eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1407eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1417eb8f069SAndrzej Hajda 1427eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1437eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1447eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1457eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1467eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1477eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1487eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1497eb8f069SAndrzej Hajda 1507eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1517eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1527eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1537eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 154e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 1557eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1567eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1577eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1587eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1597eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1607eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1617eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1627eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1637eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1647eb8f069SAndrzej Hajda 1657eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1667eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1677eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1687eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1697eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1707eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1717eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1727eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1737eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1747eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1757eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1767eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1777eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1787eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1797eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1807eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1817eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1827eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1837eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1847eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1857eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1867eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1877eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1887eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1897eb8f069SAndrzej Hajda 1907eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1917eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1927eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1937eb8f069SAndrzej Hajda 1947eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1957eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1967eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 197c4f8bdadSJagan Teki #define DSIM_PLL_P(x, offset) ((x) << (offset)) 1987eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1997eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 2007eb8f069SAndrzej Hajda 2019a320415SYoungJun Cho /* DSIM_PHYCTRL */ 2029a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 203e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 204e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 2059a320415SYoungJun Cho 2069a320415SYoungJun Cho /* DSIM_PHYTIMING */ 2079a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 2089a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 2099a320415SYoungJun Cho 2109a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 2119a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 2129a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 2139a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 2149a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 2159a320415SYoungJun Cho 2169a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 2179a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 2189a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 2199a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 2209a320415SYoungJun Cho 2217eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2227eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2237eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2247eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2257eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2267eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2277eb8f069SAndrzej Hajda 22826269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 22926269af9SHyungwon Hwang 230a046e7bfSBernard Zhao static const char *const clk_names[5] = { "bus_clk", "sclk_mipi", 231e6f988a4SHyungwon Hwang "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 232e6f988a4SHyungwon Hwang "sclk_rgb_vclk_to_dsim0" }; 2330ff03fd1SHyungwon Hwang 2347eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2357eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2367eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2377eb8f069SAndrzej Hajda }; 2387eb8f069SAndrzej Hajda 2397eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2407eb8f069SAndrzej Hajda struct list_head list; 2417eb8f069SAndrzej Hajda struct completion completed; 2427eb8f069SAndrzej Hajda int result; 2436c81e96dSAndrzej Hajda struct mipi_dsi_packet packet; 2447eb8f069SAndrzej Hajda u16 flags; 2457eb8f069SAndrzej Hajda u16 tx_done; 2467eb8f069SAndrzej Hajda 2477eb8f069SAndrzej Hajda u8 *rx_payload; 2487eb8f069SAndrzej Hajda u16 rx_len; 2497eb8f069SAndrzej Hajda u16 rx_done; 2507eb8f069SAndrzej Hajda }; 2517eb8f069SAndrzej Hajda 2527eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2537eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2547eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2550e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2567eb8f069SAndrzej Hajda 257bb57453dSMarek Szyprowski #define exynos_dsi_hw_is_exynos(hw) \ 258bb57453dSMarek Szyprowski ((hw) >= DSIM_TYPE_EXYNOS3250 && (hw) <= DSIM_TYPE_EXYNOS5433) 259bb57453dSMarek Szyprowski 2607e9f0d32SJagan Teki enum exynos_dsi_type { 2617e9f0d32SJagan Teki DSIM_TYPE_EXYNOS3250, 2627e9f0d32SJagan Teki DSIM_TYPE_EXYNOS4210, 2637e9f0d32SJagan Teki DSIM_TYPE_EXYNOS5410, 2647e9f0d32SJagan Teki DSIM_TYPE_EXYNOS5422, 2657e9f0d32SJagan Teki DSIM_TYPE_EXYNOS5433, 266*88576e23SJagan Teki DSIM_TYPE_IMX8MM, 2677e9f0d32SJagan Teki DSIM_TYPE_COUNT, 2687e9f0d32SJagan Teki }; 2697e9f0d32SJagan Teki 2709a320415SYoungJun Cho struct exynos_dsi_driver_data { 271b115361eSAndrzej Hajda const unsigned int *reg_ofs; 2729a320415SYoungJun Cho unsigned int plltmr_reg; 2739a320415SYoungJun Cho unsigned int has_freqband:1; 27478d3a8c6SInki Dae unsigned int has_clklane_stop:1; 275d668e8bfSHyungwon Hwang unsigned int num_clks; 276d668e8bfSHyungwon Hwang unsigned int max_freq; 277d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 278d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 279c4f8bdadSJagan Teki unsigned int pll_p_offset; 280b115361eSAndrzej Hajda const unsigned int *reg_values; 2819a320415SYoungJun Cho }; 2829a320415SYoungJun Cho 2837e9f0d32SJagan Teki struct exynos_dsi_plat_data { 2847e9f0d32SJagan Teki enum exynos_dsi_type hw_type; 2857e9f0d32SJagan Teki }; 2867e9f0d32SJagan Teki 2877eb8f069SAndrzej Hajda struct exynos_dsi { 2882b8376c8SGustavo Padovan struct drm_encoder encoder; 2897eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 290f9bfd326SJagan Teki struct drm_bridge bridge; 2916afb7721SMaciej Purski struct drm_bridge *out_bridge; 2927eb8f069SAndrzej Hajda struct device *dev; 293aee039e6SJagan Teki struct drm_display_mode mode; 2947eb8f069SAndrzej Hajda 2957eb8f069SAndrzej Hajda void __iomem *reg_base; 2967eb8f069SAndrzej Hajda struct phy *phy; 2970ff03fd1SHyungwon Hwang struct clk **clks; 2987eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2997eb8f069SAndrzej Hajda int irq; 300ee6c8b5aSMaíra Canal struct gpio_desc *te_gpio; 3017eb8f069SAndrzej Hajda 3027eb8f069SAndrzej Hajda u32 pll_clk_rate; 3037eb8f069SAndrzej Hajda u32 burst_clk_rate; 3047eb8f069SAndrzej Hajda u32 esc_clk_rate; 3057eb8f069SAndrzej Hajda u32 lanes; 3067eb8f069SAndrzej Hajda u32 mode_flags; 3077eb8f069SAndrzej Hajda u32 format; 3087eb8f069SAndrzej Hajda 3097eb8f069SAndrzej Hajda int state; 3107eb8f069SAndrzej Hajda struct drm_property *brightness; 3117eb8f069SAndrzej Hajda struct completion completed; 3127eb8f069SAndrzej Hajda 3137eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 3147eb8f069SAndrzej Hajda struct list_head transfer_list; 3159a320415SYoungJun Cho 3162154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data; 3177e9f0d32SJagan Teki const struct exynos_dsi_plat_data *plat_data; 3187eb8f069SAndrzej Hajda }; 3197eb8f069SAndrzej Hajda 3207eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 3217eb8f069SAndrzej Hajda 322f9bfd326SJagan Teki static inline struct exynos_dsi *bridge_to_dsi(struct drm_bridge *b) 3235cd5db80SAndrzej Hajda { 324f9bfd326SJagan Teki return container_of(b, struct exynos_dsi, bridge); 3255cd5db80SAndrzej Hajda } 3265cd5db80SAndrzej Hajda 327d668e8bfSHyungwon Hwang enum reg_idx { 328d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 329d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 330d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 331d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 332d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 333d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 334d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 335d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 336d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 337d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 338d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 339d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 340d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 341d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 342d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 343d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 344d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 345d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 346d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 347d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 348d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 349d668e8bfSHyungwon Hwang NUM_REGS 350d668e8bfSHyungwon Hwang }; 351bb32e408SAndrzej Hajda 352bb32e408SAndrzej Hajda static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 353bb32e408SAndrzej Hajda u32 val) 354bb32e408SAndrzej Hajda { 3556c81e96dSAndrzej Hajda 356bb32e408SAndrzej Hajda writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 357bb32e408SAndrzej Hajda } 358bb32e408SAndrzej Hajda 359bb32e408SAndrzej Hajda static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 360bb32e408SAndrzej Hajda { 361bb32e408SAndrzej Hajda return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 362bb32e408SAndrzej Hajda } 363bb32e408SAndrzej Hajda 364b115361eSAndrzej Hajda static const unsigned int exynos_reg_ofs[] = { 365d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 366d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 367d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 368d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 369d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 370d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 371d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 372d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 373d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 374d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 375d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 376d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 377d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 378d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 379d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 380d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 381d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 382d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 383d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 384d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 385d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 386d668e8bfSHyungwon Hwang }; 387d668e8bfSHyungwon Hwang 388b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_ofs[] = { 389e6f988a4SHyungwon Hwang [DSIM_STATUS_REG] = 0x04, 390e6f988a4SHyungwon Hwang [DSIM_SWRST_REG] = 0x0C, 391e6f988a4SHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x10, 392e6f988a4SHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x14, 393e6f988a4SHyungwon Hwang [DSIM_CONFIG_REG] = 0x18, 394e6f988a4SHyungwon Hwang [DSIM_ESCMODE_REG] = 0x1C, 395e6f988a4SHyungwon Hwang [DSIM_MDRESOL_REG] = 0x20, 396e6f988a4SHyungwon Hwang [DSIM_MVPORCH_REG] = 0x24, 397e6f988a4SHyungwon Hwang [DSIM_MHPORCH_REG] = 0x28, 398e6f988a4SHyungwon Hwang [DSIM_MSYNC_REG] = 0x2C, 399e6f988a4SHyungwon Hwang [DSIM_INTSRC_REG] = 0x34, 400e6f988a4SHyungwon Hwang [DSIM_INTMSK_REG] = 0x38, 401e6f988a4SHyungwon Hwang [DSIM_PKTHDR_REG] = 0x3C, 402e6f988a4SHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x40, 403e6f988a4SHyungwon Hwang [DSIM_RXFIFO_REG] = 0x44, 404e6f988a4SHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x4C, 405e6f988a4SHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x94, 406e6f988a4SHyungwon Hwang [DSIM_PHYCTRL_REG] = 0xA4, 407e6f988a4SHyungwon Hwang [DSIM_PHYTIMING_REG] = 0xB4, 408e6f988a4SHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0xB8, 409e6f988a4SHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0xBC, 410e6f988a4SHyungwon Hwang }; 411e6f988a4SHyungwon Hwang 412d668e8bfSHyungwon Hwang enum reg_value_idx { 413d668e8bfSHyungwon Hwang RESET_TYPE, 414d668e8bfSHyungwon Hwang PLL_TIMER, 415d668e8bfSHyungwon Hwang STOP_STATE_CNT, 416d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 417d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 418d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 419d668e8bfSHyungwon Hwang PHYTIMING_LPX, 420d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 421d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 422d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 423d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 424d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 425d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 426d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 427d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 428d668e8bfSHyungwon Hwang }; 429d668e8bfSHyungwon Hwang 430b115361eSAndrzej Hajda static const unsigned int reg_values[] = { 431d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 432d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 433d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 434d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 435d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 436d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 437d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 438d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 439d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 440d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 441d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 442d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 443d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 444d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 445d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 446d668e8bfSHyungwon Hwang }; 447d668e8bfSHyungwon Hwang 448b115361eSAndrzej Hajda static const unsigned int exynos5422_reg_values[] = { 449fdc2e108SChanho Park [RESET_TYPE] = DSIM_SWRST, 450fdc2e108SChanho Park [PLL_TIMER] = 500, 451fdc2e108SChanho Park [STOP_STATE_CNT] = 0xf, 452fdc2e108SChanho Park [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 453fdc2e108SChanho Park [PHYCTRL_VREG_LP] = 0, 454fdc2e108SChanho Park [PHYCTRL_SLEW_UP] = 0, 455fdc2e108SChanho Park [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 456fdc2e108SChanho Park [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 457fdc2e108SChanho Park [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 458fdc2e108SChanho Park [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 459fdc2e108SChanho Park [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 460fdc2e108SChanho Park [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 461fdc2e108SChanho Park [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 462fdc2e108SChanho Park [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 463fdc2e108SChanho Park [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 464fdc2e108SChanho Park }; 465fdc2e108SChanho Park 466b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_values[] = { 467e6f988a4SHyungwon Hwang [RESET_TYPE] = DSIM_FUNCRST, 468e6f988a4SHyungwon Hwang [PLL_TIMER] = 22200, 469e6f988a4SHyungwon Hwang [STOP_STATE_CNT] = 0xa, 470e6f988a4SHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 471e6f988a4SHyungwon Hwang [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 472e6f988a4SHyungwon Hwang [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 473e6f988a4SHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 474e6f988a4SHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 475e6f988a4SHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 476e6f988a4SHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 477e6f988a4SHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 478e6f988a4SHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 479e6f988a4SHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 480e6f988a4SHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 481e6f988a4SHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 482e6f988a4SHyungwon Hwang }; 483e6f988a4SHyungwon Hwang 484b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 485d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 486473462a1SInki Dae .plltmr_reg = 0x50, 487473462a1SInki Dae .has_freqband = 1, 488473462a1SInki Dae .has_clklane_stop = 1, 489d668e8bfSHyungwon Hwang .num_clks = 2, 490d668e8bfSHyungwon Hwang .max_freq = 1000, 491d668e8bfSHyungwon Hwang .wait_for_reset = 1, 492d668e8bfSHyungwon Hwang .num_bits_resol = 11, 493c4f8bdadSJagan Teki .pll_p_offset = 13, 494d668e8bfSHyungwon Hwang .reg_values = reg_values, 495473462a1SInki Dae }; 496473462a1SInki Dae 497b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 498d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4999a320415SYoungJun Cho .plltmr_reg = 0x50, 5009a320415SYoungJun Cho .has_freqband = 1, 50178d3a8c6SInki Dae .has_clklane_stop = 1, 502d668e8bfSHyungwon Hwang .num_clks = 2, 503d668e8bfSHyungwon Hwang .max_freq = 1000, 504d668e8bfSHyungwon Hwang .wait_for_reset = 1, 505d668e8bfSHyungwon Hwang .num_bits_resol = 11, 506c4f8bdadSJagan Teki .pll_p_offset = 13, 507d668e8bfSHyungwon Hwang .reg_values = reg_values, 5089a320415SYoungJun Cho }; 5099a320415SYoungJun Cho 510b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 511d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 5129a320415SYoungJun Cho .plltmr_reg = 0x58, 513d668e8bfSHyungwon Hwang .num_clks = 2, 514d668e8bfSHyungwon Hwang .max_freq = 1000, 515d668e8bfSHyungwon Hwang .wait_for_reset = 1, 516d668e8bfSHyungwon Hwang .num_bits_resol = 11, 517c4f8bdadSJagan Teki .pll_p_offset = 13, 518d668e8bfSHyungwon Hwang .reg_values = reg_values, 5199a320415SYoungJun Cho }; 5209a320415SYoungJun Cho 521b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 522e6f988a4SHyungwon Hwang .reg_ofs = exynos5433_reg_ofs, 523e6f988a4SHyungwon Hwang .plltmr_reg = 0xa0, 524e6f988a4SHyungwon Hwang .has_clklane_stop = 1, 525e6f988a4SHyungwon Hwang .num_clks = 5, 526e6f988a4SHyungwon Hwang .max_freq = 1500, 527e6f988a4SHyungwon Hwang .wait_for_reset = 0, 528e6f988a4SHyungwon Hwang .num_bits_resol = 12, 529c4f8bdadSJagan Teki .pll_p_offset = 13, 530e6f988a4SHyungwon Hwang .reg_values = exynos5433_reg_values, 531e6f988a4SHyungwon Hwang }; 532e6f988a4SHyungwon Hwang 533b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 534fdc2e108SChanho Park .reg_ofs = exynos5433_reg_ofs, 535fdc2e108SChanho Park .plltmr_reg = 0xa0, 536fdc2e108SChanho Park .has_clklane_stop = 1, 537fdc2e108SChanho Park .num_clks = 2, 538fdc2e108SChanho Park .max_freq = 1500, 539fdc2e108SChanho Park .wait_for_reset = 1, 540fdc2e108SChanho Park .num_bits_resol = 12, 541c4f8bdadSJagan Teki .pll_p_offset = 13, 542fdc2e108SChanho Park .reg_values = exynos5422_reg_values, 543fdc2e108SChanho Park }; 544fdc2e108SChanho Park 5457e9f0d32SJagan Teki static const struct exynos_dsi_driver_data * 5467e9f0d32SJagan Teki exynos_dsi_types[DSIM_TYPE_COUNT] = { 5477e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, 5487e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, 5497e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, 5507e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, 5517e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, 5529a320415SYoungJun Cho }; 5539a320415SYoungJun Cho 5547eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 5557eb8f069SAndrzej Hajda { 5567eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 5577eb8f069SAndrzej Hajda return; 5587eb8f069SAndrzej Hajda 5597eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 5607eb8f069SAndrzej Hajda } 5617eb8f069SAndrzej Hajda 5627eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 5637eb8f069SAndrzej Hajda { 564bb32e408SAndrzej Hajda u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 565ba12ac2bSHyungwon Hwang 5667eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 567bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 5687eb8f069SAndrzej Hajda } 5697eb8f069SAndrzej Hajda 5707eb8f069SAndrzej Hajda #ifndef MHZ 5717eb8f069SAndrzej Hajda #define MHZ (1000*1000) 5727eb8f069SAndrzej Hajda #endif 5737eb8f069SAndrzej Hajda 5747eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 5757eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 5767eb8f069SAndrzej Hajda { 5772154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5787eb8f069SAndrzej Hajda unsigned long best_freq = 0; 5797eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 5807eb8f069SAndrzej Hajda u8 p_min, p_max; 5813f649ab7SKees Cook u8 _p, best_p; 5823f649ab7SKees Cook u16 _m, best_m; 5833f649ab7SKees Cook u8 _s, best_s; 5847eb8f069SAndrzej Hajda 5857eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 5867eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 5877eb8f069SAndrzej Hajda 5887eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 5897eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 5907eb8f069SAndrzej Hajda u64 tmp; 5917eb8f069SAndrzej Hajda u32 delta; 5927eb8f069SAndrzej Hajda 5937eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 5947eb8f069SAndrzej Hajda do_div(tmp, fin); 5957eb8f069SAndrzej Hajda _m = tmp; 5967eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 5977eb8f069SAndrzej Hajda continue; 5987eb8f069SAndrzej Hajda 5997eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 6007eb8f069SAndrzej Hajda do_div(tmp, _p); 601d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 602d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 6037eb8f069SAndrzej Hajda continue; 6047eb8f069SAndrzej Hajda 6057eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 6067eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 6077eb8f069SAndrzej Hajda 6087eb8f069SAndrzej Hajda delta = abs(fout - tmp); 6097eb8f069SAndrzej Hajda if (delta < min_delta) { 6107eb8f069SAndrzej Hajda best_p = _p; 6117eb8f069SAndrzej Hajda best_m = _m; 6127eb8f069SAndrzej Hajda best_s = _s; 6137eb8f069SAndrzej Hajda min_delta = delta; 6147eb8f069SAndrzej Hajda best_freq = tmp; 6157eb8f069SAndrzej Hajda } 6167eb8f069SAndrzej Hajda } 6177eb8f069SAndrzej Hajda } 6187eb8f069SAndrzej Hajda 6197eb8f069SAndrzej Hajda if (best_freq) { 6207eb8f069SAndrzej Hajda *p = best_p; 6217eb8f069SAndrzej Hajda *m = best_m; 6227eb8f069SAndrzej Hajda *s = best_s; 6237eb8f069SAndrzej Hajda } 6247eb8f069SAndrzej Hajda 6257eb8f069SAndrzej Hajda return best_freq; 6267eb8f069SAndrzej Hajda } 6277eb8f069SAndrzej Hajda 6287eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 6297eb8f069SAndrzej Hajda unsigned long freq) 6307eb8f069SAndrzej Hajda { 6312154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 6327eb8f069SAndrzej Hajda unsigned long fin, fout; 6339a320415SYoungJun Cho int timeout; 6347eb8f069SAndrzej Hajda u8 p, s; 6357eb8f069SAndrzej Hajda u16 m; 6367eb8f069SAndrzej Hajda u32 reg; 6377eb8f069SAndrzej Hajda 63826269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 6397eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 6407eb8f069SAndrzej Hajda if (!fout) { 6417eb8f069SAndrzej Hajda dev_err(dsi->dev, 6427eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 6438525b5ecSYoungJun Cho return 0; 6447eb8f069SAndrzej Hajda } 6459a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 6469a320415SYoungJun Cho 647d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 648d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 6499a320415SYoungJun Cho 650c4f8bdadSJagan Teki reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | 651c4f8bdadSJagan Teki DSIM_PLL_M(m) | DSIM_PLL_S(s); 6529a320415SYoungJun Cho 6539a320415SYoungJun Cho if (driver_data->has_freqband) { 6549a320415SYoungJun Cho static const unsigned long freq_bands[] = { 6559a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 6569a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 6579a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 6589a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 6599a320415SYoungJun Cho }; 6609a320415SYoungJun Cho int band; 6617eb8f069SAndrzej Hajda 6627eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 6637eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 6647eb8f069SAndrzej Hajda break; 6657eb8f069SAndrzej Hajda 6669a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 6677eb8f069SAndrzej Hajda 6689a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 6699a320415SYoungJun Cho } 6707eb8f069SAndrzej Hajda 671bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 6727eb8f069SAndrzej Hajda 6737eb8f069SAndrzej Hajda timeout = 1000; 6747eb8f069SAndrzej Hajda do { 6757eb8f069SAndrzej Hajda if (timeout-- == 0) { 6767eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 6778525b5ecSYoungJun Cho return 0; 6787eb8f069SAndrzej Hajda } 679bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 6807eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 6817eb8f069SAndrzej Hajda 6827eb8f069SAndrzej Hajda return fout; 6837eb8f069SAndrzej Hajda } 6847eb8f069SAndrzej Hajda 6857eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 6867eb8f069SAndrzej Hajda { 6877eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 6887eb8f069SAndrzej Hajda unsigned long esc_div; 6897eb8f069SAndrzej Hajda u32 reg; 6907eb8f069SAndrzej Hajda 6917eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 6927eb8f069SAndrzej Hajda if (!hs_clk) { 6937eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 6947eb8f069SAndrzej Hajda return -EFAULT; 6957eb8f069SAndrzej Hajda } 6967eb8f069SAndrzej Hajda 6977eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 6987eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 6997eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 7007eb8f069SAndrzej Hajda 7017eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 7027eb8f069SAndrzej Hajda ++esc_div; 7037eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 7047eb8f069SAndrzej Hajda } 7057eb8f069SAndrzej Hajda 7067eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 7077eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 7087eb8f069SAndrzej Hajda 709bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 7107eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 7117eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 7127eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 7137eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 7147eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 7157eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 7167eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 7177eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 7187eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 719bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 7207eb8f069SAndrzej Hajda 7217eb8f069SAndrzej Hajda return 0; 7227eb8f069SAndrzej Hajda } 7237eb8f069SAndrzej Hajda 7249a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 7259a320415SYoungJun Cho { 7262154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 727b115361eSAndrzej Hajda const unsigned int *reg_values = driver_data->reg_values; 7289a320415SYoungJun Cho u32 reg; 7299a320415SYoungJun Cho 7309a320415SYoungJun Cho if (driver_data->has_freqband) 7319a320415SYoungJun Cho return; 7329a320415SYoungJun Cho 7339a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 734d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 735d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 736bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 7379a320415SYoungJun Cho 7389a320415SYoungJun Cho /* 7399a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 7409a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 7419a320415SYoungJun Cho * burst 7429a320415SYoungJun Cho */ 743d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 744bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 7459a320415SYoungJun Cho 7469a320415SYoungJun Cho /* 7479a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 7489a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7499a320415SYoungJun Cho * HS transmission 7509a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 7519a320415SYoungJun Cho * transmitting the Clock. 7529a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 7539a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 7549a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 7559a320415SYoungJun Cho * the beginning of T CLK-TRAIL 7569a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 7579a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 7589a320415SYoungJun Cho */ 759d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 760d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 761d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 762d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 763d668e8bfSHyungwon Hwang 764bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 7659a320415SYoungJun Cho 7669a320415SYoungJun Cho /* 7679a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 7689a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7699a320415SYoungJun Cho * HS transmission 7709a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 7719a320415SYoungJun Cho * transmitting the Sync sequence. 7729a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 7739a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 7749a320415SYoungJun Cho */ 775d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 776d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 777bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 7789a320415SYoungJun Cho } 7799a320415SYoungJun Cho 7807eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 7817eb8f069SAndrzej Hajda { 7827eb8f069SAndrzej Hajda u32 reg; 7837eb8f069SAndrzej Hajda 784bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 7857eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 7867eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 787bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 7887eb8f069SAndrzej Hajda 789bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 7907eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 791bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 7927eb8f069SAndrzej Hajda } 7937eb8f069SAndrzej Hajda 794e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 795e6f988a4SHyungwon Hwang { 796bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 797e6f988a4SHyungwon Hwang reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 798e6f988a4SHyungwon Hwang DSIM_LANE_EN(lane)); 799bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 800e6f988a4SHyungwon Hwang } 801e6f988a4SHyungwon Hwang 8027eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 8037eb8f069SAndrzej Hajda { 8042154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 8057eb8f069SAndrzej Hajda int timeout; 8067eb8f069SAndrzej Hajda u32 reg; 8077eb8f069SAndrzej Hajda u32 lanes_mask; 8087eb8f069SAndrzej Hajda 8097eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 810bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 8117eb8f069SAndrzej Hajda reg &= ~0x1f; 812bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 8137eb8f069SAndrzej Hajda 8147eb8f069SAndrzej Hajda usleep_range(9000, 11000); 8157eb8f069SAndrzej Hajda 8167eb8f069SAndrzej Hajda reg |= 0x1f; 817bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 8187eb8f069SAndrzej Hajda usleep_range(9000, 11000); 8197eb8f069SAndrzej Hajda 8207eb8f069SAndrzej Hajda /* DSI configuration */ 8217eb8f069SAndrzej Hajda reg = 0; 8227eb8f069SAndrzej Hajda 8232f36e33aSYoungJun Cho /* 8242f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 8252f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 8262f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 8272f36e33aSYoungJun Cho */ 8287eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8297eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 8307eb8f069SAndrzej Hajda 8312f36e33aSYoungJun Cho /* 8322f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 8332f36e33aSYoungJun Cho * command mode. 8342f36e33aSYoungJun Cho */ 8357eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 8367eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 8377eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 8387eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 8397eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 8407eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 8417eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 8427eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 8437eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 8442e337a8dSJagan Teki reg |= DSIM_HSE_DISABLE_MODE; 845996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 8462e337a8dSJagan Teki reg |= DSIM_HFP_DISABLE_MODE; 847996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 8482e337a8dSJagan Teki reg |= DSIM_HBP_DISABLE_MODE; 849996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 8502e337a8dSJagan Teki reg |= DSIM_HSA_DISABLE_MODE; 8517eb8f069SAndrzej Hajda } 8527eb8f069SAndrzej Hajda 853996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 8542f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 8552f36e33aSYoungJun Cho 8567eb8f069SAndrzej Hajda switch (dsi->format) { 8577eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 8587eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 8597eb8f069SAndrzej Hajda break; 8607eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 8617eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 8627eb8f069SAndrzej Hajda break; 8637eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 8647eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 8657eb8f069SAndrzej Hajda break; 8667eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 8677eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 8687eb8f069SAndrzej Hajda break; 8697eb8f069SAndrzej Hajda default: 8707eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 8717eb8f069SAndrzej Hajda return -EINVAL; 8727eb8f069SAndrzej Hajda } 8737eb8f069SAndrzej Hajda 87478d3a8c6SInki Dae /* 87578d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 87678d3a8c6SInki Dae * host controller supports 87778d3a8c6SInki Dae * 87878d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 87978d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 88078d3a8c6SInki Dae * power consumption. 88178d3a8c6SInki Dae */ 88278d3a8c6SInki Dae if (driver_data->has_clklane_stop && 88378d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 88478d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 88578d3a8c6SInki Dae } 886bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 887e6f988a4SHyungwon Hwang 888e6f988a4SHyungwon Hwang lanes_mask = BIT(dsi->lanes) - 1; 889e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, lanes_mask); 89078d3a8c6SInki Dae 8917eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 8927eb8f069SAndrzej Hajda timeout = 100; 8937eb8f069SAndrzej Hajda do { 8947eb8f069SAndrzej Hajda if (timeout-- == 0) { 8957eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 8967eb8f069SAndrzej Hajda return -EFAULT; 8977eb8f069SAndrzej Hajda } 8987eb8f069SAndrzej Hajda 899bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 9007eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 9017eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 9027eb8f069SAndrzej Hajda continue; 9037eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 9047eb8f069SAndrzej Hajda 905bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9067eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 907d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 908bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 9097eb8f069SAndrzej Hajda 9107eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 911bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 9127eb8f069SAndrzej Hajda 9137eb8f069SAndrzej Hajda return 0; 9147eb8f069SAndrzej Hajda } 9157eb8f069SAndrzej Hajda 9167eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 9177eb8f069SAndrzej Hajda { 918aee039e6SJagan Teki struct drm_display_mode *m = &dsi->mode; 919d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 9207eb8f069SAndrzej Hajda u32 reg; 9217eb8f069SAndrzej Hajda 9227eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 9237eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 924e8929999SAndrzej Hajda | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 925e8929999SAndrzej Hajda | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 926bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 9277eb8f069SAndrzej Hajda 928e8929999SAndrzej Hajda reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) 929e8929999SAndrzej Hajda | DSIM_MAIN_HBP(m->htotal - m->hsync_end); 930bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 9317eb8f069SAndrzej Hajda 932e8929999SAndrzej Hajda reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 933e8929999SAndrzej Hajda | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); 934bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 9357eb8f069SAndrzej Hajda } 936e8929999SAndrzej Hajda reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 937e8929999SAndrzej Hajda DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 9387eb8f069SAndrzej Hajda 939bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9407eb8f069SAndrzej Hajda 941e8929999SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 9427eb8f069SAndrzej Hajda } 9437eb8f069SAndrzej Hajda 9447eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 9457eb8f069SAndrzej Hajda { 9467eb8f069SAndrzej Hajda u32 reg; 9477eb8f069SAndrzej Hajda 948bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 9497eb8f069SAndrzej Hajda if (enable) 9507eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 9517eb8f069SAndrzej Hajda else 9527eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 953bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9547eb8f069SAndrzej Hajda } 9557eb8f069SAndrzej Hajda 9567eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 9577eb8f069SAndrzej Hajda { 9587eb8f069SAndrzej Hajda int timeout = 2000; 9597eb8f069SAndrzej Hajda 9607eb8f069SAndrzej Hajda do { 961bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 9627eb8f069SAndrzej Hajda 9637eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 9647eb8f069SAndrzej Hajda return 0; 9657eb8f069SAndrzej Hajda 9667eb8f069SAndrzej Hajda if (!cond_resched()) 9677eb8f069SAndrzej Hajda usleep_range(950, 1050); 9687eb8f069SAndrzej Hajda } while (--timeout); 9697eb8f069SAndrzej Hajda 9707eb8f069SAndrzej Hajda return -ETIMEDOUT; 9717eb8f069SAndrzej Hajda } 9727eb8f069SAndrzej Hajda 9737eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 9747eb8f069SAndrzej Hajda { 975bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9767eb8f069SAndrzej Hajda 9777eb8f069SAndrzej Hajda if (lpm) 9787eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 9797eb8f069SAndrzej Hajda else 9807eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 9817eb8f069SAndrzej Hajda 982bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9837eb8f069SAndrzej Hajda } 9847eb8f069SAndrzej Hajda 9857eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 9867eb8f069SAndrzej Hajda { 987bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9887eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 989bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9907eb8f069SAndrzej Hajda } 9917eb8f069SAndrzej Hajda 9927eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 9937eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9947eb8f069SAndrzej Hajda { 9957eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9966c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 9976c81e96dSAndrzej Hajda const u8 *payload = pkt->payload + xfer->tx_done; 9986c81e96dSAndrzej Hajda u16 length = pkt->payload_length - xfer->tx_done; 9997eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 10007eb8f069SAndrzej Hajda u32 reg; 10017eb8f069SAndrzej Hajda 10029cdf0ed2SKrzysztof Kozlowski dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 10036c81e96dSAndrzej Hajda xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 10047eb8f069SAndrzej Hajda 10057eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 10067eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 10077eb8f069SAndrzej Hajda 10087eb8f069SAndrzej Hajda xfer->tx_done += length; 10097eb8f069SAndrzej Hajda 10107eb8f069SAndrzej Hajda /* Send payload */ 10117eb8f069SAndrzej Hajda while (length >= 4) { 10126c81e96dSAndrzej Hajda reg = get_unaligned_le32(payload); 1013bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 10147eb8f069SAndrzej Hajda payload += 4; 10157eb8f069SAndrzej Hajda length -= 4; 10167eb8f069SAndrzej Hajda } 10177eb8f069SAndrzej Hajda 10187eb8f069SAndrzej Hajda reg = 0; 10197eb8f069SAndrzej Hajda switch (length) { 10207eb8f069SAndrzej Hajda case 3: 10217eb8f069SAndrzej Hajda reg |= payload[2] << 16; 1022df561f66SGustavo A. R. Silva fallthrough; 10237eb8f069SAndrzej Hajda case 2: 10247eb8f069SAndrzej Hajda reg |= payload[1] << 8; 1025df561f66SGustavo A. R. Silva fallthrough; 10267eb8f069SAndrzej Hajda case 1: 10277eb8f069SAndrzej Hajda reg |= payload[0]; 1028bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 10297eb8f069SAndrzej Hajda break; 10307eb8f069SAndrzej Hajda } 10317eb8f069SAndrzej Hajda 10327eb8f069SAndrzej Hajda /* Send packet header */ 10337eb8f069SAndrzej Hajda if (!first) 10347eb8f069SAndrzej Hajda return; 10357eb8f069SAndrzej Hajda 10366c81e96dSAndrzej Hajda reg = get_unaligned_le32(pkt->header); 10377eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 10387eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 10397eb8f069SAndrzej Hajda return; 10407eb8f069SAndrzej Hajda } 10417eb8f069SAndrzej Hajda 10427eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 10437eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 10447eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 10457eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 10467eb8f069SAndrzej Hajda } 10477eb8f069SAndrzej Hajda 1048bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 10497eb8f069SAndrzej Hajda 10507eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 10517eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 10527eb8f069SAndrzej Hajda } 10537eb8f069SAndrzej Hajda 10547eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 10557eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 10567eb8f069SAndrzej Hajda { 10577eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 10587eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 10597eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 10607eb8f069SAndrzej Hajda u16 length; 10617eb8f069SAndrzej Hajda u32 reg; 10627eb8f069SAndrzej Hajda 10637eb8f069SAndrzej Hajda if (first) { 1064bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10657eb8f069SAndrzej Hajda 10667eb8f069SAndrzej Hajda switch (reg & 0x3f) { 10677eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 10687eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 10697eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 10707eb8f069SAndrzej Hajda payload[1] = reg >> 16; 10717eb8f069SAndrzej Hajda ++xfer->rx_done; 10727eb8f069SAndrzej Hajda } 1073df561f66SGustavo A. R. Silva fallthrough; 10747eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 10757eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 10767eb8f069SAndrzej Hajda payload[0] = reg >> 8; 10777eb8f069SAndrzej Hajda ++xfer->rx_done; 10787eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 10797eb8f069SAndrzej Hajda xfer->result = 0; 10807eb8f069SAndrzej Hajda goto clear_fifo; 10817eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 10827eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 10837eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 10847eb8f069SAndrzej Hajda xfer->result = 0; 10857eb8f069SAndrzej Hajda goto clear_fifo; 10867eb8f069SAndrzej Hajda } 10877eb8f069SAndrzej Hajda 10887eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 10897eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 10907eb8f069SAndrzej Hajda dev_err(dev, 10917eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 10927eb8f069SAndrzej Hajda xfer->rx_len, length); 10937eb8f069SAndrzej Hajda length = xfer->rx_len; 10947eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 10957eb8f069SAndrzej Hajda xfer->rx_len = length; 10967eb8f069SAndrzej Hajda } 10977eb8f069SAndrzej Hajda 10987eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 10997eb8f069SAndrzej Hajda xfer->rx_done += length; 11007eb8f069SAndrzej Hajda 11017eb8f069SAndrzej Hajda /* Receive payload */ 11027eb8f069SAndrzej Hajda while (length >= 4) { 1103bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11047eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 11057eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 11067eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 11077eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 11087eb8f069SAndrzej Hajda payload += 4; 11097eb8f069SAndrzej Hajda length -= 4; 11107eb8f069SAndrzej Hajda } 11117eb8f069SAndrzej Hajda 11127eb8f069SAndrzej Hajda if (length) { 1113bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11147eb8f069SAndrzej Hajda switch (length) { 11157eb8f069SAndrzej Hajda case 3: 11167eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 1117df561f66SGustavo A. R. Silva fallthrough; 11187eb8f069SAndrzej Hajda case 2: 11197eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 1120df561f66SGustavo A. R. Silva fallthrough; 11217eb8f069SAndrzej Hajda case 1: 11227eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 11237eb8f069SAndrzej Hajda } 11247eb8f069SAndrzej Hajda } 11257eb8f069SAndrzej Hajda 11267eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 11277eb8f069SAndrzej Hajda xfer->result = 0; 11287eb8f069SAndrzej Hajda 11297eb8f069SAndrzej Hajda clear_fifo: 11307eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 11317eb8f069SAndrzej Hajda do { 1132bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11337eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 11347eb8f069SAndrzej Hajda break; 11357eb8f069SAndrzej Hajda } while (--length); 11367eb8f069SAndrzej Hajda } 11377eb8f069SAndrzej Hajda 11387eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 11397eb8f069SAndrzej Hajda { 11407eb8f069SAndrzej Hajda unsigned long flags; 11417eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11427eb8f069SAndrzej Hajda bool start = false; 11437eb8f069SAndrzej Hajda 11447eb8f069SAndrzej Hajda again: 11457eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11467eb8f069SAndrzej Hajda 11477eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11487eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11497eb8f069SAndrzej Hajda return; 11507eb8f069SAndrzej Hajda } 11517eb8f069SAndrzej Hajda 11527eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11537eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11547eb8f069SAndrzej Hajda 11557eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11567eb8f069SAndrzej Hajda 11576c81e96dSAndrzej Hajda if (xfer->packet.payload_length && 11586c81e96dSAndrzej Hajda xfer->tx_done == xfer->packet.payload_length) 11597eb8f069SAndrzej Hajda /* waiting for RX */ 11607eb8f069SAndrzej Hajda return; 11617eb8f069SAndrzej Hajda 11627eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 11637eb8f069SAndrzej Hajda 11646c81e96dSAndrzej Hajda if (xfer->packet.payload_length || xfer->rx_len) 11657eb8f069SAndrzej Hajda return; 11667eb8f069SAndrzej Hajda 11677eb8f069SAndrzej Hajda xfer->result = 0; 11687eb8f069SAndrzej Hajda complete(&xfer->completed); 11697eb8f069SAndrzej Hajda 11707eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11717eb8f069SAndrzej Hajda 11727eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11737eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11747eb8f069SAndrzej Hajda 11757eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11767eb8f069SAndrzej Hajda 11777eb8f069SAndrzej Hajda if (start) 11787eb8f069SAndrzej Hajda goto again; 11797eb8f069SAndrzej Hajda } 11807eb8f069SAndrzej Hajda 11817eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 11827eb8f069SAndrzej Hajda { 11837eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11847eb8f069SAndrzej Hajda unsigned long flags; 11857eb8f069SAndrzej Hajda bool start = true; 11867eb8f069SAndrzej Hajda 11877eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11887eb8f069SAndrzej Hajda 11897eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11907eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11917eb8f069SAndrzej Hajda return false; 11927eb8f069SAndrzej Hajda } 11937eb8f069SAndrzej Hajda 11947eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11957eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11967eb8f069SAndrzej Hajda 11977eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11987eb8f069SAndrzej Hajda 11997eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 12009cdf0ed2SKrzysztof Kozlowski "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 12016c81e96dSAndrzej Hajda xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 12026c81e96dSAndrzej Hajda xfer->rx_done); 12037eb8f069SAndrzej Hajda 12046c81e96dSAndrzej Hajda if (xfer->tx_done != xfer->packet.payload_length) 12057eb8f069SAndrzej Hajda return true; 12067eb8f069SAndrzej Hajda 12077eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 12087eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 12097eb8f069SAndrzej Hajda 12107eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 12117eb8f069SAndrzej Hajda return true; 12127eb8f069SAndrzej Hajda 12137eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12147eb8f069SAndrzej Hajda 12157eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12167eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12177eb8f069SAndrzej Hajda 12187eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12197eb8f069SAndrzej Hajda 12207eb8f069SAndrzej Hajda if (!xfer->rx_len) 12217eb8f069SAndrzej Hajda xfer->result = 0; 12227eb8f069SAndrzej Hajda complete(&xfer->completed); 12237eb8f069SAndrzej Hajda 12247eb8f069SAndrzej Hajda return start; 12257eb8f069SAndrzej Hajda } 12267eb8f069SAndrzej Hajda 12277eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 12287eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12297eb8f069SAndrzej Hajda { 12307eb8f069SAndrzej Hajda unsigned long flags; 12317eb8f069SAndrzej Hajda bool start; 12327eb8f069SAndrzej Hajda 12337eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12347eb8f069SAndrzej Hajda 12357eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 12367eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 12377eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 12387eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12397eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12407eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12417eb8f069SAndrzej Hajda if (start) 12427eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12437eb8f069SAndrzej Hajda return; 12447eb8f069SAndrzej Hajda } 12457eb8f069SAndrzej Hajda 12467eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12477eb8f069SAndrzej Hajda 12487eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12497eb8f069SAndrzej Hajda } 12507eb8f069SAndrzej Hajda 12517eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 12527eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12537eb8f069SAndrzej Hajda { 12547eb8f069SAndrzej Hajda unsigned long flags; 12557eb8f069SAndrzej Hajda bool stopped; 12567eb8f069SAndrzej Hajda 12577eb8f069SAndrzej Hajda xfer->tx_done = 0; 12587eb8f069SAndrzej Hajda xfer->rx_done = 0; 12597eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 12607eb8f069SAndrzej Hajda init_completion(&xfer->completed); 12617eb8f069SAndrzej Hajda 12627eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12637eb8f069SAndrzej Hajda 12647eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 12657eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 12667eb8f069SAndrzej Hajda 12677eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12687eb8f069SAndrzej Hajda 12697eb8f069SAndrzej Hajda if (stopped) 12707eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12717eb8f069SAndrzej Hajda 12727eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 12737eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 12747eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 12756c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 12767eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 12776c81e96dSAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 12786c81e96dSAndrzej Hajda (int)pkt->payload_length, pkt->payload); 12797eb8f069SAndrzej Hajda return -ETIMEDOUT; 12807eb8f069SAndrzej Hajda } 12817eb8f069SAndrzej Hajda 12827eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 12837eb8f069SAndrzej Hajda return xfer->result; 12847eb8f069SAndrzej Hajda } 12857eb8f069SAndrzej Hajda 12867eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 12877eb8f069SAndrzej Hajda { 12887eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 12897eb8f069SAndrzej Hajda u32 status; 12907eb8f069SAndrzej Hajda 1291bb32e408SAndrzej Hajda status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 12927eb8f069SAndrzej Hajda if (!status) { 12937eb8f069SAndrzej Hajda static unsigned long int j; 12947eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 12957eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 12967eb8f069SAndrzej Hajda return IRQ_HANDLED; 12977eb8f069SAndrzej Hajda } 1298bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 12997eb8f069SAndrzej Hajda 13007eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 1301e6f988a4SHyungwon Hwang u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1302ecf81ed9SAndrzej Hajda DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | 1303ecf81ed9SAndrzej Hajda DSIM_INT_SW_RST_RELEASE); 1304bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 13057eb8f069SAndrzej Hajda complete(&dsi->completed); 13067eb8f069SAndrzej Hajda return IRQ_HANDLED; 13077eb8f069SAndrzej Hajda } 13087eb8f069SAndrzej Hajda 1309e6f988a4SHyungwon Hwang if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1310ecf81ed9SAndrzej Hajda DSIM_INT_PLL_STABLE))) 13117eb8f069SAndrzej Hajda return IRQ_HANDLED; 13127eb8f069SAndrzej Hajda 13137eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 13147eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 13157eb8f069SAndrzej Hajda 13167eb8f069SAndrzej Hajda return IRQ_HANDLED; 13177eb8f069SAndrzej Hajda } 13187eb8f069SAndrzej Hajda 1319e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1320e17ddeccSYoungJun Cho { 1321e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 13222b8376c8SGustavo Padovan struct drm_encoder *encoder = &dsi->encoder; 1323e17ddeccSYoungJun Cho 13240e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1325e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1326e17ddeccSYoungJun Cho 1327e17ddeccSYoungJun Cho return IRQ_HANDLED; 1328e17ddeccSYoungJun Cho } 1329e17ddeccSYoungJun Cho 1330e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1331e17ddeccSYoungJun Cho { 1332e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1333e17ddeccSYoungJun Cho 1334ee6c8b5aSMaíra Canal if (dsi->te_gpio) 1335ee6c8b5aSMaíra Canal enable_irq(gpiod_to_irq(dsi->te_gpio)); 1336e17ddeccSYoungJun Cho } 1337e17ddeccSYoungJun Cho 1338e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1339e17ddeccSYoungJun Cho { 1340ee6c8b5aSMaíra Canal if (dsi->te_gpio) 1341ee6c8b5aSMaíra Canal disable_irq(gpiod_to_irq(dsi->te_gpio)); 1342e17ddeccSYoungJun Cho 1343e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1344e17ddeccSYoungJun Cho } 1345e17ddeccSYoungJun Cho 13467eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 13477eb8f069SAndrzej Hajda { 13482154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1349d668e8bfSHyungwon Hwang 1350bb57453dSMarek Szyprowski if (dsi->state & DSIM_STATE_INITIALIZED) 1351bb57453dSMarek Szyprowski return 0; 1352bb57453dSMarek Szyprowski 13537eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1354e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 1355e6f988a4SHyungwon Hwang 1356e6f988a4SHyungwon Hwang if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1357e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1358e6f988a4SHyungwon Hwang 13599a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1360d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 13617eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 13629a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 13637eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 13647eb8f069SAndrzej Hajda 1365bb57453dSMarek Szyprowski dsi->state |= DSIM_STATE_INITIALIZED; 1366bb57453dSMarek Szyprowski 13677eb8f069SAndrzej Hajda return 0; 13687eb8f069SAndrzej Hajda } 13697eb8f069SAndrzej Hajda 1370295e7954SAndrzej Hajda static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, 1371295e7954SAndrzej Hajda struct device *panel) 1372e17ddeccSYoungJun Cho { 1373e17ddeccSYoungJun Cho int ret; 13740cef83a5SYoungJun Cho int te_gpio_irq; 1375e17ddeccSYoungJun Cho 1376fedc8982SMarek Szyprowski dsi->te_gpio = gpiod_get_optional(panel, "te", GPIOD_IN); 13778e3fa9d8SMarek Szyprowski if (!dsi->te_gpio) { 13788e3fa9d8SMarek Szyprowski return 0; 13798e3fa9d8SMarek Szyprowski } else if (IS_ERR(dsi->te_gpio)) { 1380ee6c8b5aSMaíra Canal dev_err(dsi->dev, "gpio request failed with %ld\n", 1381ee6c8b5aSMaíra Canal PTR_ERR(dsi->te_gpio)); 1382760cceffSInki Dae return PTR_ERR(dsi->te_gpio); 1383e17ddeccSYoungJun Cho } 1384e17ddeccSYoungJun Cho 1385ee6c8b5aSMaíra Canal te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 138651d1decaSHyungwon Hwang 13870cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1388a4e5eed2STian Tao IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1389e17ddeccSYoungJun Cho if (ret) { 1390e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1391ee6c8b5aSMaíra Canal gpiod_put(dsi->te_gpio); 1392760cceffSInki Dae return ret; 1393e17ddeccSYoungJun Cho } 1394e17ddeccSYoungJun Cho 1395760cceffSInki Dae return 0; 1396e17ddeccSYoungJun Cho } 1397e17ddeccSYoungJun Cho 1398e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1399e17ddeccSYoungJun Cho { 1400ee6c8b5aSMaíra Canal if (dsi->te_gpio) { 1401ee6c8b5aSMaíra Canal free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1402ee6c8b5aSMaíra Canal gpiod_put(dsi->te_gpio); 1403e17ddeccSYoungJun Cho } 1404e17ddeccSYoungJun Cho } 1405e17ddeccSYoungJun Cho 140695a2441eSJagan Teki static void exynos_dsi_atomic_pre_enable(struct drm_bridge *bridge, 140795a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 14087eb8f069SAndrzej Hajda { 1409f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 14107eb8f069SAndrzej Hajda int ret; 14117eb8f069SAndrzej Hajda 14127eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 1413b6595dc7SGustavo Padovan return; 14147eb8f069SAndrzej Hajda 1415445d3bedSInki Dae ret = pm_runtime_resume_and_get(dsi->dev); 1416445d3bedSInki Dae if (ret < 0) { 1417445d3bedSInki Dae dev_err(dsi->dev, "failed to enable DSI device.\n"); 1418445d3bedSInki Dae return; 1419445d3bedSInki Dae } 1420445d3bedSInki Dae 14210e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 1422bb57453dSMarek Szyprowski 1423bb57453dSMarek Szyprowski /* 1424bb57453dSMarek Szyprowski * For Exynos-DSIM the downstream bridge, or panel are expecting 1425bb57453dSMarek Szyprowski * the host initialization during DSI transfer. 1426bb57453dSMarek Szyprowski */ 1427bb57453dSMarek Szyprowski if (!exynos_dsi_hw_is_exynos(dsi->plat_data->hw_type)) { 1428bb57453dSMarek Szyprowski ret = exynos_dsi_init(dsi); 1429bb57453dSMarek Szyprowski if (ret) 1430bb57453dSMarek Szyprowski return; 1431bb57453dSMarek Szyprowski } 1432f66ff55aSBoris Brezillon } 14337eb8f069SAndrzej Hajda 143495a2441eSJagan Teki static void exynos_dsi_atomic_enable(struct drm_bridge *bridge, 143595a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 1436f9bfd326SJagan Teki { 1437f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1438f9bfd326SJagan Teki 14397eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 14407eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 14417eb8f069SAndrzej Hajda 14420e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1443f9bfd326SJagan Teki 14448a08f671SMaciej Purski return; 14457eb8f069SAndrzej Hajda } 14467eb8f069SAndrzej Hajda 144795a2441eSJagan Teki static void exynos_dsi_atomic_disable(struct drm_bridge *bridge, 144895a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 14497eb8f069SAndrzej Hajda { 1450f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1451b6595dc7SGustavo Padovan 14527eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 14537eb8f069SAndrzej Hajda return; 14547eb8f069SAndrzej Hajda 14550e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1456f66ff55aSBoris Brezillon } 1457f66ff55aSBoris Brezillon 145895a2441eSJagan Teki static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, 145995a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 1460f9bfd326SJagan Teki { 1461f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1462f9bfd326SJagan Teki 1463cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1464f66ff55aSBoris Brezillon 14657eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 1466ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 14677eb8f069SAndrzej Hajda } 14687eb8f069SAndrzej Hajda 1469*88576e23SJagan Teki static int exynos_dsi_atomic_check(struct drm_bridge *bridge, 1470*88576e23SJagan Teki struct drm_bridge_state *bridge_state, 1471*88576e23SJagan Teki struct drm_crtc_state *crtc_state, 1472*88576e23SJagan Teki struct drm_connector_state *conn_state) 1473*88576e23SJagan Teki { 1474*88576e23SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1475*88576e23SJagan Teki struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1476*88576e23SJagan Teki 1477*88576e23SJagan Teki /* 1478*88576e23SJagan Teki * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM 1479*88576e23SJagan Teki * inverts HS/VS/DE sync signals polarity, therefore, while 1480*88576e23SJagan Teki * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 1481*88576e23SJagan Teki * 13.6.3.5.2 RGB interface 1482*88576e23SJagan Teki * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 1483*88576e23SJagan Teki * 13.6.2.7.2 RGB interface 1484*88576e23SJagan Teki * both claim "Vsync, Hsync, and VDEN are active high signals.", the 1485*88576e23SJagan Teki * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. 1486*88576e23SJagan Teki */ 1487*88576e23SJagan Teki if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { 1488*88576e23SJagan Teki adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1489*88576e23SJagan Teki adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1490*88576e23SJagan Teki } 1491*88576e23SJagan Teki 1492*88576e23SJagan Teki return 0; 1493*88576e23SJagan Teki } 1494*88576e23SJagan Teki 1495f9bfd326SJagan Teki static void exynos_dsi_mode_set(struct drm_bridge *bridge, 1496f9bfd326SJagan Teki const struct drm_display_mode *mode, 1497f9bfd326SJagan Teki const struct drm_display_mode *adjusted_mode) 1498bd29823eSJagan Teki { 1499f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1500bd29823eSJagan Teki 1501bd29823eSJagan Teki drm_mode_copy(&dsi->mode, adjusted_mode); 1502bd29823eSJagan Teki } 1503bd29823eSJagan Teki 1504f9bfd326SJagan Teki static int exynos_dsi_attach(struct drm_bridge *bridge, 1505f9bfd326SJagan Teki enum drm_bridge_attach_flags flags) 1506f9bfd326SJagan Teki { 1507f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1508f9bfd326SJagan Teki 15091a1ce789SJagan Teki return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge, 15101a1ce789SJagan Teki flags); 1511f9bfd326SJagan Teki } 1512f9bfd326SJagan Teki 1513f9bfd326SJagan Teki static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { 151495a2441eSJagan Teki .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 151595a2441eSJagan Teki .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 151695a2441eSJagan Teki .atomic_reset = drm_atomic_helper_bridge_reset, 1517*88576e23SJagan Teki .atomic_check = exynos_dsi_atomic_check, 151895a2441eSJagan Teki .atomic_pre_enable = exynos_dsi_atomic_pre_enable, 151995a2441eSJagan Teki .atomic_enable = exynos_dsi_atomic_enable, 152095a2441eSJagan Teki .atomic_disable = exynos_dsi_atomic_disable, 152195a2441eSJagan Teki .atomic_post_disable = exynos_dsi_atomic_post_disable, 1522aee039e6SJagan Teki .mode_set = exynos_dsi_mode_set, 1523f9bfd326SJagan Teki .attach = exynos_dsi_attach, 15247eb8f069SAndrzej Hajda }; 15257eb8f069SAndrzej Hajda 1526295e7954SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1527295e7954SAndrzej Hajda struct mipi_dsi_device *device) 1528295e7954SAndrzej Hajda { 1529295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 1530711c7adcSJagan Teki struct device *dev = dsi->dev; 15316afb7721SMaciej Purski struct drm_encoder *encoder = &dsi->encoder; 15326afb7721SMaciej Purski struct drm_device *drm = encoder->dev; 1533e39a82bfSJagan Teki struct device_node *np = dev->of_node; 1534e39a82bfSJagan Teki struct device_node *remote; 1535ea16c74cSJagan Teki struct drm_panel *panel; 1536711c7adcSJagan Teki int ret; 15376afb7721SMaciej Purski 1538e39a82bfSJagan Teki /* 1539e39a82bfSJagan Teki * Devices can also be child nodes when we also control that device 1540e39a82bfSJagan Teki * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). 1541e39a82bfSJagan Teki * 1542e39a82bfSJagan Teki * Lookup for a child node of the given parent that isn't either port 1543e39a82bfSJagan Teki * or ports. 1544e39a82bfSJagan Teki */ 1545e39a82bfSJagan Teki for_each_available_child_of_node(np, remote) { 1546e39a82bfSJagan Teki if (of_node_name_eq(remote, "port") || 1547e39a82bfSJagan Teki of_node_name_eq(remote, "ports")) 1548e39a82bfSJagan Teki continue; 1549e39a82bfSJagan Teki 1550e39a82bfSJagan Teki goto of_find_panel_or_bridge; 1551e39a82bfSJagan Teki } 1552e39a82bfSJagan Teki 1553e39a82bfSJagan Teki /* 1554e39a82bfSJagan Teki * of_graph_get_remote_node() produces a noisy error message if port 1555e39a82bfSJagan Teki * node isn't found and the absence of the port is a legit case here, 1556e39a82bfSJagan Teki * so at first we silently check whether graph presents in the 1557e39a82bfSJagan Teki * device-tree node. 1558e39a82bfSJagan Teki */ 1559e39a82bfSJagan Teki if (!of_graph_is_present(np)) 1560e39a82bfSJagan Teki return -ENODEV; 1561e39a82bfSJagan Teki 1562e39a82bfSJagan Teki remote = of_graph_get_remote_node(np, 1, 0); 1563e39a82bfSJagan Teki 1564e39a82bfSJagan Teki of_find_panel_or_bridge: 1565e39a82bfSJagan Teki if (!remote) 1566e39a82bfSJagan Teki return -ENODEV; 1567e39a82bfSJagan Teki 1568e39a82bfSJagan Teki panel = of_drm_find_panel(remote); 1569ea16c74cSJagan Teki if (!IS_ERR(panel)) { 1570ea16c74cSJagan Teki dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1571ea16c74cSJagan Teki } else { 1572e39a82bfSJagan Teki dsi->out_bridge = of_drm_find_bridge(remote); 1573ea16c74cSJagan Teki if (!dsi->out_bridge) 1574ea16c74cSJagan Teki dsi->out_bridge = ERR_PTR(-EINVAL); 1575ea16c74cSJagan Teki } 1576ea16c74cSJagan Teki 1577e39a82bfSJagan Teki of_node_put(remote); 1578e39a82bfSJagan Teki 1579711c7adcSJagan Teki if (IS_ERR(dsi->out_bridge)) { 1580711c7adcSJagan Teki ret = PTR_ERR(dsi->out_bridge); 1581711c7adcSJagan Teki DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 15826afb7721SMaciej Purski return ret; 15836afb7721SMaciej Purski } 15846afb7721SMaciej Purski 1585711c7adcSJagan Teki DRM_DEV_INFO(dev, "Attached %s device\n", device->name); 1586711c7adcSJagan Teki 1587f9bfd326SJagan Teki drm_bridge_add(&dsi->bridge); 1588f9bfd326SJagan Teki 15891a1ce789SJagan Teki drm_bridge_attach(encoder, &dsi->bridge, 15901a1ce789SJagan Teki list_first_entry_or_null(&encoder->bridge_chain, 15911a1ce789SJagan Teki struct drm_bridge, 15921a1ce789SJagan Teki chain_node), 0); 1593295e7954SAndrzej Hajda 1594295e7954SAndrzej Hajda /* 1595295e7954SAndrzej Hajda * This is a temporary solution and should be made by more generic way. 1596295e7954SAndrzej Hajda * 1597295e7954SAndrzej Hajda * If attached panel device is for command mode one, dsi should register 1598295e7954SAndrzej Hajda * TE interrupt handler. 1599295e7954SAndrzej Hajda */ 1600295e7954SAndrzej Hajda if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1601711c7adcSJagan Teki ret = exynos_dsi_register_te_irq(dsi, &device->dev); 1602295e7954SAndrzej Hajda if (ret) 1603295e7954SAndrzej Hajda return ret; 1604295e7954SAndrzej Hajda } 1605295e7954SAndrzej Hajda 1606295e7954SAndrzej Hajda mutex_lock(&drm->mode_config.mutex); 1607295e7954SAndrzej Hajda 1608295e7954SAndrzej Hajda dsi->lanes = device->lanes; 1609295e7954SAndrzej Hajda dsi->format = device->format; 1610295e7954SAndrzej Hajda dsi->mode_flags = device->mode_flags; 1611c038f538SAndrzej Hajda exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = 1612c038f538SAndrzej Hajda !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); 1613295e7954SAndrzej Hajda 1614295e7954SAndrzej Hajda mutex_unlock(&drm->mode_config.mutex); 1615295e7954SAndrzej Hajda 1616295e7954SAndrzej Hajda if (drm->mode_config.poll_enabled) 1617295e7954SAndrzej Hajda drm_kms_helper_hotplug_event(drm); 1618295e7954SAndrzej Hajda 1619295e7954SAndrzej Hajda return 0; 1620295e7954SAndrzej Hajda } 1621295e7954SAndrzej Hajda 1622295e7954SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1623295e7954SAndrzej Hajda struct mipi_dsi_device *device) 1624295e7954SAndrzej Hajda { 1625295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 16266afb7721SMaciej Purski struct drm_device *drm = dsi->encoder.dev; 1627295e7954SAndrzej Hajda 16286afb7721SMaciej Purski dsi->out_bridge = NULL; 1629295e7954SAndrzej Hajda 1630295e7954SAndrzej Hajda if (drm->mode_config.poll_enabled) 1631295e7954SAndrzej Hajda drm_kms_helper_hotplug_event(drm); 1632295e7954SAndrzej Hajda 1633295e7954SAndrzej Hajda exynos_dsi_unregister_te_irq(dsi); 1634295e7954SAndrzej Hajda 1635f9bfd326SJagan Teki drm_bridge_remove(&dsi->bridge); 1636f9bfd326SJagan Teki 1637295e7954SAndrzej Hajda return 0; 1638295e7954SAndrzej Hajda } 1639295e7954SAndrzej Hajda 1640295e7954SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1641295e7954SAndrzej Hajda const struct mipi_dsi_msg *msg) 1642295e7954SAndrzej Hajda { 1643295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 1644295e7954SAndrzej Hajda struct exynos_dsi_transfer xfer; 1645295e7954SAndrzej Hajda int ret; 1646295e7954SAndrzej Hajda 1647295e7954SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 1648295e7954SAndrzej Hajda return -EINVAL; 1649295e7954SAndrzej Hajda 1650295e7954SAndrzej Hajda ret = exynos_dsi_init(dsi); 1651295e7954SAndrzej Hajda if (ret) 1652295e7954SAndrzej Hajda return ret; 1653295e7954SAndrzej Hajda 1654295e7954SAndrzej Hajda ret = mipi_dsi_create_packet(&xfer.packet, msg); 1655295e7954SAndrzej Hajda if (ret < 0) 1656295e7954SAndrzej Hajda return ret; 1657295e7954SAndrzej Hajda 1658295e7954SAndrzej Hajda xfer.rx_len = msg->rx_len; 1659295e7954SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 1660295e7954SAndrzej Hajda xfer.flags = msg->flags; 1661295e7954SAndrzej Hajda 1662295e7954SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 1663295e7954SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 1664295e7954SAndrzej Hajda } 1665295e7954SAndrzej Hajda 1666295e7954SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1667295e7954SAndrzej Hajda .attach = exynos_dsi_host_attach, 1668295e7954SAndrzej Hajda .detach = exynos_dsi_host_detach, 1669295e7954SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 1670295e7954SAndrzej Hajda }; 1671295e7954SAndrzej Hajda 16727eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 16737eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 16747eb8f069SAndrzej Hajda { 16757eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 16767eb8f069SAndrzej Hajda 16777eb8f069SAndrzej Hajda if (ret < 0) 16784bf99144SRob Herring pr_err("%pOF: failed to get '%s' property\n", np, propname); 16797eb8f069SAndrzej Hajda 16807eb8f069SAndrzej Hajda return ret; 16817eb8f069SAndrzej Hajda } 16827eb8f069SAndrzej Hajda 16837eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 16847eb8f069SAndrzej Hajda { 16857eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 16867eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 16877eb8f069SAndrzej Hajda int ret; 16887eb8f069SAndrzej Hajda 16897eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 16907eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 16917eb8f069SAndrzej Hajda if (ret < 0) 16927eb8f069SAndrzej Hajda return ret; 16937eb8f069SAndrzej Hajda 1694f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 16957eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 16967eb8f069SAndrzej Hajda if (ret < 0) 1697f2921d8cSHoegeun Kwon return ret; 16987eb8f069SAndrzej Hajda 1699f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 17007eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 1701f5f3b9baSHyungwon Hwang if (ret < 0) 1702f2921d8cSHoegeun Kwon return ret; 1703f5f3b9baSHyungwon Hwang 1704f2921d8cSHoegeun Kwon return 0; 17057eb8f069SAndrzej Hajda } 17067eb8f069SAndrzej Hajda 1707f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1708f37cd5e8SInki Dae void *data) 1709f37cd5e8SInki Dae { 1710e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 1711e11e6df2SMichael Tretter struct drm_encoder *encoder = &dsi->encoder; 1712f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1713f37cd5e8SInki Dae int ret; 1714f37cd5e8SInki Dae 17153e1fe32dSThomas Zimmermann drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS); 17162b8376c8SGustavo Padovan 17171ca582f1SAndrzej Hajda ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); 17181ca582f1SAndrzej Hajda if (ret < 0) 17191ca582f1SAndrzej Hajda return ret; 17201ca582f1SAndrzej Hajda 1721f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1722f37cd5e8SInki Dae } 1723f37cd5e8SInki Dae 1724f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1725f37cd5e8SInki Dae void *data) 1726f37cd5e8SInki Dae { 1727e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 1728f37cd5e8SInki Dae 172995a2441eSJagan Teki exynos_dsi_atomic_disable(&dsi->bridge, NULL); 1730f37cd5e8SInki Dae 17310ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1732f37cd5e8SInki Dae } 1733f37cd5e8SInki Dae 1734f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1735f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1736f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1737f37cd5e8SInki Dae }; 1738f37cd5e8SInki Dae 17397eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 17407eb8f069SAndrzej Hajda { 17412900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 17427eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 17430ff03fd1SHyungwon Hwang int ret, i; 17447eb8f069SAndrzej Hajda 17452900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 17462900c69cSAndrzej Hajda if (!dsi) 17472900c69cSAndrzej Hajda return -ENOMEM; 17482900c69cSAndrzej Hajda 17497eb8f069SAndrzej Hajda init_completion(&dsi->completed); 17507eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 17517eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 17527eb8f069SAndrzej Hajda 17537eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1754e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 17557eb8f069SAndrzej Hajda 1756e2d2a1e0SAndrzej Hajda dsi->dev = dev; 17577e9f0d32SJagan Teki dsi->plat_data = of_device_get_match_data(dev); 17587e9f0d32SJagan Teki dsi->driver_data = exynos_dsi_types[dsi->plat_data->hw_type]; 17597eb8f069SAndrzej Hajda 17607eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 17617eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1762e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 17637eb8f069SAndrzej Hajda dsi->supplies); 176473bb394cSKrzysztof Kozlowski if (ret) 176573bb394cSKrzysztof Kozlowski return dev_err_probe(dev, ret, "failed to get regulators\n"); 17667eb8f069SAndrzej Hajda 1767a86854d0SKees Cook dsi->clks = devm_kcalloc(dev, 1768a86854d0SKees Cook dsi->driver_data->num_clks, sizeof(*dsi->clks), 17690ff03fd1SHyungwon Hwang GFP_KERNEL); 1770e6f988a4SHyungwon Hwang if (!dsi->clks) 1771e6f988a4SHyungwon Hwang return -ENOMEM; 1772e6f988a4SHyungwon Hwang 17730ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 17740ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 17750ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 17760ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1777c0fd99d6SMarek Szyprowski dsi->clks[i] = devm_clk_get(dev, 1778c0fd99d6SMarek Szyprowski OLD_SCLK_MIPI_CLK_NAME); 1779c0fd99d6SMarek Szyprowski if (!IS_ERR(dsi->clks[i])) 17800ff03fd1SHyungwon Hwang continue; 17817eb8f069SAndrzej Hajda } 17827eb8f069SAndrzej Hajda 17830ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 17840ff03fd1SHyungwon Hwang clk_names[i]); 17850ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 17860ff03fd1SHyungwon Hwang } 17877eb8f069SAndrzej Hajda } 17887eb8f069SAndrzej Hajda 178917ac76e0SCai Huoqing dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 179004562956SZhen Lei if (IS_ERR(dsi->reg_base)) 179186650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 17927eb8f069SAndrzej Hajda 17939528af4aSJagan Teki dsi->phy = devm_phy_optional_get(dev, "dsim"); 17947eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1795e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 179686650408SAndrzej Hajda return PTR_ERR(dsi->phy); 17977eb8f069SAndrzej Hajda } 17987eb8f069SAndrzej Hajda 17997eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 1800fdd79b0dSMarkus Elfring if (dsi->irq < 0) 180186650408SAndrzej Hajda return dsi->irq; 18027eb8f069SAndrzej Hajda 1803e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1804a4e5eed2STian Tao exynos_dsi_irq, 1805a4e5eed2STian Tao IRQF_ONESHOT | IRQF_NO_AUTOEN, 1806e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 18077eb8f069SAndrzej Hajda if (ret) { 1808e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 180986650408SAndrzej Hajda return ret; 18107eb8f069SAndrzej Hajda } 18117eb8f069SAndrzej Hajda 1812547a7348SChristophe JAILLET ret = exynos_dsi_parse_dt(dsi); 1813547a7348SChristophe JAILLET if (ret) 1814547a7348SChristophe JAILLET return ret; 1815547a7348SChristophe JAILLET 1816e11e6df2SMichael Tretter platform_set_drvdata(pdev, dsi); 18177eb8f069SAndrzej Hajda 1818ba6e4779SInki Dae pm_runtime_enable(dev); 1819ba6e4779SInki Dae 1820f9bfd326SJagan Teki dsi->bridge.funcs = &exynos_dsi_bridge_funcs; 1821f9bfd326SJagan Teki dsi->bridge.of_node = dev->of_node; 1822f9bfd326SJagan Teki dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 18231a1ce789SJagan Teki dsi->bridge.pre_enable_prev_first = true; 1824f9bfd326SJagan Teki 1825547a7348SChristophe JAILLET ret = component_add(dev, &exynos_dsi_component_ops); 1826547a7348SChristophe JAILLET if (ret) 1827547a7348SChristophe JAILLET goto err_disable_runtime; 1828547a7348SChristophe JAILLET 1829547a7348SChristophe JAILLET return 0; 1830547a7348SChristophe JAILLET 1831547a7348SChristophe JAILLET err_disable_runtime: 1832547a7348SChristophe JAILLET pm_runtime_disable(dev); 1833547a7348SChristophe JAILLET 1834547a7348SChristophe JAILLET return ret; 18357eb8f069SAndrzej Hajda } 18367eb8f069SAndrzej Hajda 18377eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 18387eb8f069SAndrzej Hajda { 1839ba6e4779SInki Dae pm_runtime_disable(&pdev->dev); 1840ba6e4779SInki Dae 1841df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1842df5225bcSInki Dae 18437eb8f069SAndrzej Hajda return 0; 18447eb8f069SAndrzej Hajda } 18457eb8f069SAndrzej Hajda 1846010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1847ba6e4779SInki Dae { 1848e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 18492154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1850ba6e4779SInki Dae int ret, i; 1851ba6e4779SInki Dae 1852ba6e4779SInki Dae usleep_range(10000, 20000); 1853ba6e4779SInki Dae 1854ba6e4779SInki Dae if (dsi->state & DSIM_STATE_INITIALIZED) { 1855ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_INITIALIZED; 1856ba6e4779SInki Dae 1857ba6e4779SInki Dae exynos_dsi_disable_clock(dsi); 1858ba6e4779SInki Dae 1859ba6e4779SInki Dae exynos_dsi_disable_irq(dsi); 1860ba6e4779SInki Dae } 1861ba6e4779SInki Dae 1862ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_CMD_LPM; 1863ba6e4779SInki Dae 1864ba6e4779SInki Dae phy_power_off(dsi->phy); 1865ba6e4779SInki Dae 1866ba6e4779SInki Dae for (i = driver_data->num_clks - 1; i > -1; i--) 1867ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1868ba6e4779SInki Dae 1869ba6e4779SInki Dae ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1870ba6e4779SInki Dae if (ret < 0) 1871ba6e4779SInki Dae dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1872ba6e4779SInki Dae 1873ba6e4779SInki Dae return 0; 1874ba6e4779SInki Dae } 1875ba6e4779SInki Dae 1876010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_resume(struct device *dev) 1877ba6e4779SInki Dae { 1878e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 18792154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1880ba6e4779SInki Dae int ret, i; 1881ba6e4779SInki Dae 1882ba6e4779SInki Dae ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1883ba6e4779SInki Dae if (ret < 0) { 1884ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1885ba6e4779SInki Dae return ret; 1886ba6e4779SInki Dae } 1887ba6e4779SInki Dae 1888ba6e4779SInki Dae for (i = 0; i < driver_data->num_clks; i++) { 1889ba6e4779SInki Dae ret = clk_prepare_enable(dsi->clks[i]); 1890ba6e4779SInki Dae if (ret < 0) 1891ba6e4779SInki Dae goto err_clk; 1892ba6e4779SInki Dae } 1893ba6e4779SInki Dae 1894ba6e4779SInki Dae ret = phy_power_on(dsi->phy); 1895ba6e4779SInki Dae if (ret < 0) { 1896ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1897ba6e4779SInki Dae goto err_clk; 1898ba6e4779SInki Dae } 1899ba6e4779SInki Dae 1900ba6e4779SInki Dae return 0; 1901ba6e4779SInki Dae 1902ba6e4779SInki Dae err_clk: 1903ba6e4779SInki Dae while (--i > -1) 1904ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1905ba6e4779SInki Dae regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1906ba6e4779SInki Dae 1907ba6e4779SInki Dae return ret; 1908ba6e4779SInki Dae } 1909ba6e4779SInki Dae 1910ba6e4779SInki Dae static const struct dev_pm_ops exynos_dsi_pm_ops = { 1911ba6e4779SInki Dae SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 19127e915746SMarek Szyprowski SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 19137e915746SMarek Szyprowski pm_runtime_force_resume) 1914ba6e4779SInki Dae }; 1915ba6e4779SInki Dae 19167e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos3250_dsi_pdata = { 19177e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS3250, 19187e9f0d32SJagan Teki }; 19197e9f0d32SJagan Teki 19207e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos4210_dsi_pdata = { 19217e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS4210, 19227e9f0d32SJagan Teki }; 19237e9f0d32SJagan Teki 19247e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos5410_dsi_pdata = { 19257e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS5410, 19267e9f0d32SJagan Teki }; 19277e9f0d32SJagan Teki 19287e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos5422_dsi_pdata = { 19297e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS5422, 19307e9f0d32SJagan Teki }; 19317e9f0d32SJagan Teki 19327e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos5433_dsi_pdata = { 19337e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS5433, 19347e9f0d32SJagan Teki }; 19357e9f0d32SJagan Teki 19367e9f0d32SJagan Teki static const struct of_device_id exynos_dsi_of_match[] = { 19377e9f0d32SJagan Teki { 19387e9f0d32SJagan Teki .compatible = "samsung,exynos3250-mipi-dsi", 19397e9f0d32SJagan Teki .data = &exynos3250_dsi_pdata, 19407e9f0d32SJagan Teki }, 19417e9f0d32SJagan Teki { 19427e9f0d32SJagan Teki .compatible = "samsung,exynos4210-mipi-dsi", 19437e9f0d32SJagan Teki .data = &exynos4210_dsi_pdata, 19447e9f0d32SJagan Teki }, 19457e9f0d32SJagan Teki { 19467e9f0d32SJagan Teki .compatible = "samsung,exynos5410-mipi-dsi", 19477e9f0d32SJagan Teki .data = &exynos5410_dsi_pdata, 19487e9f0d32SJagan Teki }, 19497e9f0d32SJagan Teki { 19507e9f0d32SJagan Teki .compatible = "samsung,exynos5422-mipi-dsi", 19517e9f0d32SJagan Teki .data = &exynos5422_dsi_pdata, 19527e9f0d32SJagan Teki }, 19537e9f0d32SJagan Teki { 19547e9f0d32SJagan Teki .compatible = "samsung,exynos5433-mipi-dsi", 19557e9f0d32SJagan Teki .data = &exynos5433_dsi_pdata, 19567e9f0d32SJagan Teki }, 19577e9f0d32SJagan Teki { /* sentinel. */ } 19587e9f0d32SJagan Teki }; 19597e9f0d32SJagan Teki MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 19607e9f0d32SJagan Teki 19617eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 19627eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 19637eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 19647eb8f069SAndrzej Hajda .driver = { 19657eb8f069SAndrzej Hajda .name = "exynos-dsi", 19667eb8f069SAndrzej Hajda .owner = THIS_MODULE, 1967ba6e4779SInki Dae .pm = &exynos_dsi_pm_ops, 19687eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 19697eb8f069SAndrzej Hajda }, 19707eb8f069SAndrzej Hajda }; 19717eb8f069SAndrzej Hajda 19727eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 19737eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 19747eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 19757eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 1976