1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 27eb8f069SAndrzej Hajda /* 37eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 47eb8f069SAndrzej Hajda * 57eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 67eb8f069SAndrzej Hajda * 77eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 87eb8f069SAndrzej Hajda */ 97eb8f069SAndrzej Hajda 107eb8f069SAndrzej Hajda #include <linux/clk.h> 112bda34d7SSam Ravnborg #include <linux/delay.h> 122bda34d7SSam Ravnborg #include <linux/component.h> 13e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 147eb8f069SAndrzej Hajda #include <linux/irq.h> 159a320415SYoungJun Cho #include <linux/of_device.h> 16f5f3b9baSHyungwon Hwang #include <linux/of_graph.h> 177eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 187eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 192bda34d7SSam Ravnborg 202bda34d7SSam Ravnborg #include <asm/unaligned.h> 217eb8f069SAndrzej Hajda 227eb8f069SAndrzej Hajda #include <video/mipi_display.h> 237eb8f069SAndrzej Hajda #include <video/videomode.h> 247eb8f069SAndrzej Hajda 252bda34d7SSam Ravnborg #include <drm/drm_atomic_helper.h> 26ee68c743SBoris Brezillon #include <drm/drm_bridge.h> 272bda34d7SSam Ravnborg #include <drm/drm_mipi_dsi.h> 28ea16c74cSJagan Teki #include <drm/drm_panel.h> 292bda34d7SSam Ravnborg #include <drm/drm_print.h> 302bda34d7SSam Ravnborg #include <drm/drm_probe_helper.h> 313e1fe32dSThomas Zimmermann #include <drm/drm_simple_kms_helper.h> 322bda34d7SSam Ravnborg 33e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 347eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 357eb8f069SAndrzej Hajda 367eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 377eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 387eb8f069SAndrzej Hajda 397eb8f069SAndrzej Hajda /* DSIM_STATUS */ 407eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 417eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 427eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 437eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 447eb8f069SAndrzej Hajda 457eb8f069SAndrzej Hajda /* DSIM_SWRST */ 467eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 477eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 487eb8f069SAndrzej Hajda 497eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 507eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 517eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 527eb8f069SAndrzej Hajda 537eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 547eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 557eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 567eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 587eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 597eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 617eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 627eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 637eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 647eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 657eb8f069SAndrzej Hajda 667eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 677eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 687eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 697eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 707eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 717eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 757eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 767eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 777eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 782e337a8dSJagan Teki #define DSIM_HSA_DISABLE_MODE (1 << 20) 792e337a8dSJagan Teki #define DSIM_HBP_DISABLE_MODE (1 << 21) 802e337a8dSJagan Teki #define DSIM_HFP_DISABLE_MODE (1 << 22) 812e337a8dSJagan Teki /* 822e337a8dSJagan Teki * The i.MX 8M Mini Applications Processor Reference Manual, 832e337a8dSJagan Teki * Rev. 3, 11/2020 Page 4091 842e337a8dSJagan Teki * The i.MX 8M Nano Applications Processor Reference Manual, 852e337a8dSJagan Teki * Rev. 2, 07/2022 Page 3058 862e337a8dSJagan Teki * The i.MX 8M Plus Applications Processor Reference Manual, 872e337a8dSJagan Teki * Rev. 1, 06/2021 Page 5436 882e337a8dSJagan Teki * named this bit as 'HseDisableMode' but the bit definition 892e337a8dSJagan Teki * is quite opposite like 902e337a8dSJagan Teki * 0 = Disables transfer 912e337a8dSJagan Teki * 1 = Enables transfer 922e337a8dSJagan Teki * which clearly states that HSE is not a disable bit. 932e337a8dSJagan Teki * 942e337a8dSJagan Teki * This bit is named as per the manual even though it is not 952e337a8dSJagan Teki * a disable bit however the driver logic for handling HSE 962e337a8dSJagan Teki * is based on the MIPI_DSI_MODE_VIDEO_HSE flag itself. 972e337a8dSJagan Teki */ 982e337a8dSJagan Teki #define DSIM_HSE_DISABLE_MODE (1 << 23) 997eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 1007eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 1017eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 1027eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 1037eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 1047eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 1056bdc92eeSKrzysztof Kozlowski /* This flag is valid only for exynos3250/3472/5260/5430 */ 10678d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 1077eb8f069SAndrzej Hajda 1087eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 1097eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 1107eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 1117eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 1127eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 1137eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 1147eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 1157eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 1167eb8f069SAndrzej Hajda 1177eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 1187eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 119d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 120d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1217eb8f069SAndrzej Hajda 1227eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1237eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1247eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1257eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1267eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1277eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1287eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1297eb8f069SAndrzej Hajda 1307eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1317eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1327eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1337eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1347eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1357eb8f069SAndrzej Hajda 1367eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1377eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1387eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1397eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1407eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1417eb8f069SAndrzej Hajda 1427eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1437eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1447eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1457eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1467eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1477eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1487eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1497eb8f069SAndrzej Hajda 1507eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1517eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1527eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1537eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 154e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 1557eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1567eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1577eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1587eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1597eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1607eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1617eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1627eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1637eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1647eb8f069SAndrzej Hajda 1657eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1667eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1677eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1687eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1697eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1707eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1717eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1727eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1737eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1747eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1757eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1767eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1777eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1787eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1797eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1807eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1817eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1827eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1837eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1847eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1857eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1867eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1877eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1887eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1897eb8f069SAndrzej Hajda 1907eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1917eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1927eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1937eb8f069SAndrzej Hajda 1947eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1957eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1967eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 197c4f8bdadSJagan Teki #define DSIM_PLL_P(x, offset) ((x) << (offset)) 1987eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1997eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 2007eb8f069SAndrzej Hajda 2019a320415SYoungJun Cho /* DSIM_PHYCTRL */ 2029a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 203e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 204e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 2059a320415SYoungJun Cho 2069a320415SYoungJun Cho /* DSIM_PHYTIMING */ 2079a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 2089a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 2099a320415SYoungJun Cho 2109a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 2119a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 2129a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 2139a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 2149a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 2159a320415SYoungJun Cho 2169a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 2179a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 2189a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 2199a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 2209a320415SYoungJun Cho 2217eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2227eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2237eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2247eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2257eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2267eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2277eb8f069SAndrzej Hajda 22826269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 22926269af9SHyungwon Hwang 230a046e7bfSBernard Zhao static const char *const clk_names[5] = { "bus_clk", "sclk_mipi", 231e6f988a4SHyungwon Hwang "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 232e6f988a4SHyungwon Hwang "sclk_rgb_vclk_to_dsim0" }; 2330ff03fd1SHyungwon Hwang 2347eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2357eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2367eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2377eb8f069SAndrzej Hajda }; 2387eb8f069SAndrzej Hajda 2397eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2407eb8f069SAndrzej Hajda struct list_head list; 2417eb8f069SAndrzej Hajda struct completion completed; 2427eb8f069SAndrzej Hajda int result; 2436c81e96dSAndrzej Hajda struct mipi_dsi_packet packet; 2447eb8f069SAndrzej Hajda u16 flags; 2457eb8f069SAndrzej Hajda u16 tx_done; 2467eb8f069SAndrzej Hajda 2477eb8f069SAndrzej Hajda u8 *rx_payload; 2487eb8f069SAndrzej Hajda u16 rx_len; 2497eb8f069SAndrzej Hajda u16 rx_done; 2507eb8f069SAndrzej Hajda }; 2517eb8f069SAndrzej Hajda 2527eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2537eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2547eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2550e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2567eb8f069SAndrzej Hajda 257*7e9f0d32SJagan Teki enum exynos_dsi_type { 258*7e9f0d32SJagan Teki DSIM_TYPE_EXYNOS3250, 259*7e9f0d32SJagan Teki DSIM_TYPE_EXYNOS4210, 260*7e9f0d32SJagan Teki DSIM_TYPE_EXYNOS5410, 261*7e9f0d32SJagan Teki DSIM_TYPE_EXYNOS5422, 262*7e9f0d32SJagan Teki DSIM_TYPE_EXYNOS5433, 263*7e9f0d32SJagan Teki DSIM_TYPE_COUNT, 264*7e9f0d32SJagan Teki }; 265*7e9f0d32SJagan Teki 2669a320415SYoungJun Cho struct exynos_dsi_driver_data { 267b115361eSAndrzej Hajda const unsigned int *reg_ofs; 2689a320415SYoungJun Cho unsigned int plltmr_reg; 2699a320415SYoungJun Cho unsigned int has_freqband:1; 27078d3a8c6SInki Dae unsigned int has_clklane_stop:1; 271d668e8bfSHyungwon Hwang unsigned int num_clks; 272d668e8bfSHyungwon Hwang unsigned int max_freq; 273d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 274d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 275c4f8bdadSJagan Teki unsigned int pll_p_offset; 276b115361eSAndrzej Hajda const unsigned int *reg_values; 2779a320415SYoungJun Cho }; 2789a320415SYoungJun Cho 279*7e9f0d32SJagan Teki struct exynos_dsi_plat_data { 280*7e9f0d32SJagan Teki enum exynos_dsi_type hw_type; 281*7e9f0d32SJagan Teki }; 282*7e9f0d32SJagan Teki 2837eb8f069SAndrzej Hajda struct exynos_dsi { 2842b8376c8SGustavo Padovan struct drm_encoder encoder; 2857eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 286f9bfd326SJagan Teki struct drm_bridge bridge; 2876afb7721SMaciej Purski struct drm_bridge *out_bridge; 2887eb8f069SAndrzej Hajda struct device *dev; 289aee039e6SJagan Teki struct drm_display_mode mode; 2907eb8f069SAndrzej Hajda 2917eb8f069SAndrzej Hajda void __iomem *reg_base; 2927eb8f069SAndrzej Hajda struct phy *phy; 2930ff03fd1SHyungwon Hwang struct clk **clks; 2947eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2957eb8f069SAndrzej Hajda int irq; 296ee6c8b5aSMaíra Canal struct gpio_desc *te_gpio; 2977eb8f069SAndrzej Hajda 2987eb8f069SAndrzej Hajda u32 pll_clk_rate; 2997eb8f069SAndrzej Hajda u32 burst_clk_rate; 3007eb8f069SAndrzej Hajda u32 esc_clk_rate; 3017eb8f069SAndrzej Hajda u32 lanes; 3027eb8f069SAndrzej Hajda u32 mode_flags; 3037eb8f069SAndrzej Hajda u32 format; 3047eb8f069SAndrzej Hajda 3057eb8f069SAndrzej Hajda int state; 3067eb8f069SAndrzej Hajda struct drm_property *brightness; 3077eb8f069SAndrzej Hajda struct completion completed; 3087eb8f069SAndrzej Hajda 3097eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 3107eb8f069SAndrzej Hajda struct list_head transfer_list; 3119a320415SYoungJun Cho 3122154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data; 313*7e9f0d32SJagan Teki const struct exynos_dsi_plat_data *plat_data; 3147eb8f069SAndrzej Hajda }; 3157eb8f069SAndrzej Hajda 3167eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 3177eb8f069SAndrzej Hajda 318f9bfd326SJagan Teki static inline struct exynos_dsi *bridge_to_dsi(struct drm_bridge *b) 3195cd5db80SAndrzej Hajda { 320f9bfd326SJagan Teki return container_of(b, struct exynos_dsi, bridge); 3215cd5db80SAndrzej Hajda } 3225cd5db80SAndrzej Hajda 323d668e8bfSHyungwon Hwang enum reg_idx { 324d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 325d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 326d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 327d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 328d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 329d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 330d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 331d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 332d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 333d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 334d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 335d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 336d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 337d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 338d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 339d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 340d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 341d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 342d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 343d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 344d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 345d668e8bfSHyungwon Hwang NUM_REGS 346d668e8bfSHyungwon Hwang }; 347bb32e408SAndrzej Hajda 348bb32e408SAndrzej Hajda static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 349bb32e408SAndrzej Hajda u32 val) 350bb32e408SAndrzej Hajda { 3516c81e96dSAndrzej Hajda 352bb32e408SAndrzej Hajda writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 353bb32e408SAndrzej Hajda } 354bb32e408SAndrzej Hajda 355bb32e408SAndrzej Hajda static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 356bb32e408SAndrzej Hajda { 357bb32e408SAndrzej Hajda return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 358bb32e408SAndrzej Hajda } 359bb32e408SAndrzej Hajda 360b115361eSAndrzej Hajda static const unsigned int exynos_reg_ofs[] = { 361d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 362d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 363d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 364d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 365d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 366d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 367d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 368d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 369d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 370d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 371d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 372d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 373d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 374d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 375d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 376d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 377d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 378d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 379d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 380d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 381d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 382d668e8bfSHyungwon Hwang }; 383d668e8bfSHyungwon Hwang 384b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_ofs[] = { 385e6f988a4SHyungwon Hwang [DSIM_STATUS_REG] = 0x04, 386e6f988a4SHyungwon Hwang [DSIM_SWRST_REG] = 0x0C, 387e6f988a4SHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x10, 388e6f988a4SHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x14, 389e6f988a4SHyungwon Hwang [DSIM_CONFIG_REG] = 0x18, 390e6f988a4SHyungwon Hwang [DSIM_ESCMODE_REG] = 0x1C, 391e6f988a4SHyungwon Hwang [DSIM_MDRESOL_REG] = 0x20, 392e6f988a4SHyungwon Hwang [DSIM_MVPORCH_REG] = 0x24, 393e6f988a4SHyungwon Hwang [DSIM_MHPORCH_REG] = 0x28, 394e6f988a4SHyungwon Hwang [DSIM_MSYNC_REG] = 0x2C, 395e6f988a4SHyungwon Hwang [DSIM_INTSRC_REG] = 0x34, 396e6f988a4SHyungwon Hwang [DSIM_INTMSK_REG] = 0x38, 397e6f988a4SHyungwon Hwang [DSIM_PKTHDR_REG] = 0x3C, 398e6f988a4SHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x40, 399e6f988a4SHyungwon Hwang [DSIM_RXFIFO_REG] = 0x44, 400e6f988a4SHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x4C, 401e6f988a4SHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x94, 402e6f988a4SHyungwon Hwang [DSIM_PHYCTRL_REG] = 0xA4, 403e6f988a4SHyungwon Hwang [DSIM_PHYTIMING_REG] = 0xB4, 404e6f988a4SHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0xB8, 405e6f988a4SHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0xBC, 406e6f988a4SHyungwon Hwang }; 407e6f988a4SHyungwon Hwang 408d668e8bfSHyungwon Hwang enum reg_value_idx { 409d668e8bfSHyungwon Hwang RESET_TYPE, 410d668e8bfSHyungwon Hwang PLL_TIMER, 411d668e8bfSHyungwon Hwang STOP_STATE_CNT, 412d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 413d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 414d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 415d668e8bfSHyungwon Hwang PHYTIMING_LPX, 416d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 417d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 418d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 419d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 420d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 421d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 422d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 423d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 424d668e8bfSHyungwon Hwang }; 425d668e8bfSHyungwon Hwang 426b115361eSAndrzej Hajda static const unsigned int reg_values[] = { 427d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 428d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 429d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 430d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 431d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 432d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 433d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 434d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 435d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 436d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 437d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 438d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 439d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 440d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 441d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 442d668e8bfSHyungwon Hwang }; 443d668e8bfSHyungwon Hwang 444b115361eSAndrzej Hajda static const unsigned int exynos5422_reg_values[] = { 445fdc2e108SChanho Park [RESET_TYPE] = DSIM_SWRST, 446fdc2e108SChanho Park [PLL_TIMER] = 500, 447fdc2e108SChanho Park [STOP_STATE_CNT] = 0xf, 448fdc2e108SChanho Park [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 449fdc2e108SChanho Park [PHYCTRL_VREG_LP] = 0, 450fdc2e108SChanho Park [PHYCTRL_SLEW_UP] = 0, 451fdc2e108SChanho Park [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 452fdc2e108SChanho Park [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 453fdc2e108SChanho Park [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 454fdc2e108SChanho Park [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 455fdc2e108SChanho Park [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 456fdc2e108SChanho Park [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 457fdc2e108SChanho Park [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 458fdc2e108SChanho Park [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 459fdc2e108SChanho Park [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 460fdc2e108SChanho Park }; 461fdc2e108SChanho Park 462b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_values[] = { 463e6f988a4SHyungwon Hwang [RESET_TYPE] = DSIM_FUNCRST, 464e6f988a4SHyungwon Hwang [PLL_TIMER] = 22200, 465e6f988a4SHyungwon Hwang [STOP_STATE_CNT] = 0xa, 466e6f988a4SHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 467e6f988a4SHyungwon Hwang [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 468e6f988a4SHyungwon Hwang [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 469e6f988a4SHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 470e6f988a4SHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 471e6f988a4SHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 472e6f988a4SHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 473e6f988a4SHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 474e6f988a4SHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 475e6f988a4SHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 476e6f988a4SHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 477e6f988a4SHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 478e6f988a4SHyungwon Hwang }; 479e6f988a4SHyungwon Hwang 480b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 481d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 482473462a1SInki Dae .plltmr_reg = 0x50, 483473462a1SInki Dae .has_freqband = 1, 484473462a1SInki Dae .has_clklane_stop = 1, 485d668e8bfSHyungwon Hwang .num_clks = 2, 486d668e8bfSHyungwon Hwang .max_freq = 1000, 487d668e8bfSHyungwon Hwang .wait_for_reset = 1, 488d668e8bfSHyungwon Hwang .num_bits_resol = 11, 489c4f8bdadSJagan Teki .pll_p_offset = 13, 490d668e8bfSHyungwon Hwang .reg_values = reg_values, 491473462a1SInki Dae }; 492473462a1SInki Dae 493b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 494d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4959a320415SYoungJun Cho .plltmr_reg = 0x50, 4969a320415SYoungJun Cho .has_freqband = 1, 49778d3a8c6SInki Dae .has_clklane_stop = 1, 498d668e8bfSHyungwon Hwang .num_clks = 2, 499d668e8bfSHyungwon Hwang .max_freq = 1000, 500d668e8bfSHyungwon Hwang .wait_for_reset = 1, 501d668e8bfSHyungwon Hwang .num_bits_resol = 11, 502c4f8bdadSJagan Teki .pll_p_offset = 13, 503d668e8bfSHyungwon Hwang .reg_values = reg_values, 5049a320415SYoungJun Cho }; 5059a320415SYoungJun Cho 506b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 507d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 5089a320415SYoungJun Cho .plltmr_reg = 0x58, 509d668e8bfSHyungwon Hwang .num_clks = 2, 510d668e8bfSHyungwon Hwang .max_freq = 1000, 511d668e8bfSHyungwon Hwang .wait_for_reset = 1, 512d668e8bfSHyungwon Hwang .num_bits_resol = 11, 513c4f8bdadSJagan Teki .pll_p_offset = 13, 514d668e8bfSHyungwon Hwang .reg_values = reg_values, 5159a320415SYoungJun Cho }; 5169a320415SYoungJun Cho 517b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 518e6f988a4SHyungwon Hwang .reg_ofs = exynos5433_reg_ofs, 519e6f988a4SHyungwon Hwang .plltmr_reg = 0xa0, 520e6f988a4SHyungwon Hwang .has_clklane_stop = 1, 521e6f988a4SHyungwon Hwang .num_clks = 5, 522e6f988a4SHyungwon Hwang .max_freq = 1500, 523e6f988a4SHyungwon Hwang .wait_for_reset = 0, 524e6f988a4SHyungwon Hwang .num_bits_resol = 12, 525c4f8bdadSJagan Teki .pll_p_offset = 13, 526e6f988a4SHyungwon Hwang .reg_values = exynos5433_reg_values, 527e6f988a4SHyungwon Hwang }; 528e6f988a4SHyungwon Hwang 529b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 530fdc2e108SChanho Park .reg_ofs = exynos5433_reg_ofs, 531fdc2e108SChanho Park .plltmr_reg = 0xa0, 532fdc2e108SChanho Park .has_clklane_stop = 1, 533fdc2e108SChanho Park .num_clks = 2, 534fdc2e108SChanho Park .max_freq = 1500, 535fdc2e108SChanho Park .wait_for_reset = 1, 536fdc2e108SChanho Park .num_bits_resol = 12, 537c4f8bdadSJagan Teki .pll_p_offset = 13, 538fdc2e108SChanho Park .reg_values = exynos5422_reg_values, 539fdc2e108SChanho Park }; 540fdc2e108SChanho Park 541*7e9f0d32SJagan Teki static const struct exynos_dsi_driver_data * 542*7e9f0d32SJagan Teki exynos_dsi_types[DSIM_TYPE_COUNT] = { 543*7e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, 544*7e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, 545*7e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, 546*7e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, 547*7e9f0d32SJagan Teki [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, 5489a320415SYoungJun Cho }; 5499a320415SYoungJun Cho 5507eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 5517eb8f069SAndrzej Hajda { 5527eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 5537eb8f069SAndrzej Hajda return; 5547eb8f069SAndrzej Hajda 5557eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 5567eb8f069SAndrzej Hajda } 5577eb8f069SAndrzej Hajda 5587eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 5597eb8f069SAndrzej Hajda { 560bb32e408SAndrzej Hajda u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 561ba12ac2bSHyungwon Hwang 5627eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 563bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 5647eb8f069SAndrzej Hajda } 5657eb8f069SAndrzej Hajda 5667eb8f069SAndrzej Hajda #ifndef MHZ 5677eb8f069SAndrzej Hajda #define MHZ (1000*1000) 5687eb8f069SAndrzej Hajda #endif 5697eb8f069SAndrzej Hajda 5707eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 5717eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 5727eb8f069SAndrzej Hajda { 5732154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5747eb8f069SAndrzej Hajda unsigned long best_freq = 0; 5757eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 5767eb8f069SAndrzej Hajda u8 p_min, p_max; 5773f649ab7SKees Cook u8 _p, best_p; 5783f649ab7SKees Cook u16 _m, best_m; 5793f649ab7SKees Cook u8 _s, best_s; 5807eb8f069SAndrzej Hajda 5817eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 5827eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 5837eb8f069SAndrzej Hajda 5847eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 5857eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 5867eb8f069SAndrzej Hajda u64 tmp; 5877eb8f069SAndrzej Hajda u32 delta; 5887eb8f069SAndrzej Hajda 5897eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 5907eb8f069SAndrzej Hajda do_div(tmp, fin); 5917eb8f069SAndrzej Hajda _m = tmp; 5927eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 5937eb8f069SAndrzej Hajda continue; 5947eb8f069SAndrzej Hajda 5957eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5967eb8f069SAndrzej Hajda do_div(tmp, _p); 597d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 598d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 5997eb8f069SAndrzej Hajda continue; 6007eb8f069SAndrzej Hajda 6017eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 6027eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 6037eb8f069SAndrzej Hajda 6047eb8f069SAndrzej Hajda delta = abs(fout - tmp); 6057eb8f069SAndrzej Hajda if (delta < min_delta) { 6067eb8f069SAndrzej Hajda best_p = _p; 6077eb8f069SAndrzej Hajda best_m = _m; 6087eb8f069SAndrzej Hajda best_s = _s; 6097eb8f069SAndrzej Hajda min_delta = delta; 6107eb8f069SAndrzej Hajda best_freq = tmp; 6117eb8f069SAndrzej Hajda } 6127eb8f069SAndrzej Hajda } 6137eb8f069SAndrzej Hajda } 6147eb8f069SAndrzej Hajda 6157eb8f069SAndrzej Hajda if (best_freq) { 6167eb8f069SAndrzej Hajda *p = best_p; 6177eb8f069SAndrzej Hajda *m = best_m; 6187eb8f069SAndrzej Hajda *s = best_s; 6197eb8f069SAndrzej Hajda } 6207eb8f069SAndrzej Hajda 6217eb8f069SAndrzej Hajda return best_freq; 6227eb8f069SAndrzej Hajda } 6237eb8f069SAndrzej Hajda 6247eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 6257eb8f069SAndrzej Hajda unsigned long freq) 6267eb8f069SAndrzej Hajda { 6272154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 6287eb8f069SAndrzej Hajda unsigned long fin, fout; 6299a320415SYoungJun Cho int timeout; 6307eb8f069SAndrzej Hajda u8 p, s; 6317eb8f069SAndrzej Hajda u16 m; 6327eb8f069SAndrzej Hajda u32 reg; 6337eb8f069SAndrzej Hajda 63426269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 6357eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 6367eb8f069SAndrzej Hajda if (!fout) { 6377eb8f069SAndrzej Hajda dev_err(dsi->dev, 6387eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 6398525b5ecSYoungJun Cho return 0; 6407eb8f069SAndrzej Hajda } 6419a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 6429a320415SYoungJun Cho 643d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 644d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 6459a320415SYoungJun Cho 646c4f8bdadSJagan Teki reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | 647c4f8bdadSJagan Teki DSIM_PLL_M(m) | DSIM_PLL_S(s); 6489a320415SYoungJun Cho 6499a320415SYoungJun Cho if (driver_data->has_freqband) { 6509a320415SYoungJun Cho static const unsigned long freq_bands[] = { 6519a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 6529a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 6539a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 6549a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 6559a320415SYoungJun Cho }; 6569a320415SYoungJun Cho int band; 6577eb8f069SAndrzej Hajda 6587eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 6597eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 6607eb8f069SAndrzej Hajda break; 6617eb8f069SAndrzej Hajda 6629a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 6637eb8f069SAndrzej Hajda 6649a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 6659a320415SYoungJun Cho } 6667eb8f069SAndrzej Hajda 667bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 6687eb8f069SAndrzej Hajda 6697eb8f069SAndrzej Hajda timeout = 1000; 6707eb8f069SAndrzej Hajda do { 6717eb8f069SAndrzej Hajda if (timeout-- == 0) { 6727eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 6738525b5ecSYoungJun Cho return 0; 6747eb8f069SAndrzej Hajda } 675bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 6767eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 6777eb8f069SAndrzej Hajda 6787eb8f069SAndrzej Hajda return fout; 6797eb8f069SAndrzej Hajda } 6807eb8f069SAndrzej Hajda 6817eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 6827eb8f069SAndrzej Hajda { 6837eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 6847eb8f069SAndrzej Hajda unsigned long esc_div; 6857eb8f069SAndrzej Hajda u32 reg; 6867eb8f069SAndrzej Hajda 6877eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 6887eb8f069SAndrzej Hajda if (!hs_clk) { 6897eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 6907eb8f069SAndrzej Hajda return -EFAULT; 6917eb8f069SAndrzej Hajda } 6927eb8f069SAndrzej Hajda 6937eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 6947eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 6957eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6967eb8f069SAndrzej Hajda 6977eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 6987eb8f069SAndrzej Hajda ++esc_div; 6997eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 7007eb8f069SAndrzej Hajda } 7017eb8f069SAndrzej Hajda 7027eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 7037eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 7047eb8f069SAndrzej Hajda 705bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 7067eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 7077eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 7087eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 7097eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 7107eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 7117eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 7127eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 7137eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 7147eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 715bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 7167eb8f069SAndrzej Hajda 7177eb8f069SAndrzej Hajda return 0; 7187eb8f069SAndrzej Hajda } 7197eb8f069SAndrzej Hajda 7209a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 7219a320415SYoungJun Cho { 7222154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 723b115361eSAndrzej Hajda const unsigned int *reg_values = driver_data->reg_values; 7249a320415SYoungJun Cho u32 reg; 7259a320415SYoungJun Cho 7269a320415SYoungJun Cho if (driver_data->has_freqband) 7279a320415SYoungJun Cho return; 7289a320415SYoungJun Cho 7299a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 730d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 731d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 732bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 7339a320415SYoungJun Cho 7349a320415SYoungJun Cho /* 7359a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 7369a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 7379a320415SYoungJun Cho * burst 7389a320415SYoungJun Cho */ 739d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 740bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 7419a320415SYoungJun Cho 7429a320415SYoungJun Cho /* 7439a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 7449a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7459a320415SYoungJun Cho * HS transmission 7469a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 7479a320415SYoungJun Cho * transmitting the Clock. 7489a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 7499a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 7509a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 7519a320415SYoungJun Cho * the beginning of T CLK-TRAIL 7529a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 7539a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 7549a320415SYoungJun Cho */ 755d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 756d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 757d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 758d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 759d668e8bfSHyungwon Hwang 760bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 7619a320415SYoungJun Cho 7629a320415SYoungJun Cho /* 7639a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 7649a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7659a320415SYoungJun Cho * HS transmission 7669a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 7679a320415SYoungJun Cho * transmitting the Sync sequence. 7689a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 7699a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 7709a320415SYoungJun Cho */ 771d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 772d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 773bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 7749a320415SYoungJun Cho } 7759a320415SYoungJun Cho 7767eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 7777eb8f069SAndrzej Hajda { 7787eb8f069SAndrzej Hajda u32 reg; 7797eb8f069SAndrzej Hajda 780bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 7817eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 7827eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 783bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 7847eb8f069SAndrzej Hajda 785bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 7867eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 787bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 7887eb8f069SAndrzej Hajda } 7897eb8f069SAndrzej Hajda 790e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 791e6f988a4SHyungwon Hwang { 792bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 793e6f988a4SHyungwon Hwang reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 794e6f988a4SHyungwon Hwang DSIM_LANE_EN(lane)); 795bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 796e6f988a4SHyungwon Hwang } 797e6f988a4SHyungwon Hwang 7987eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 7997eb8f069SAndrzej Hajda { 8002154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 8017eb8f069SAndrzej Hajda int timeout; 8027eb8f069SAndrzej Hajda u32 reg; 8037eb8f069SAndrzej Hajda u32 lanes_mask; 8047eb8f069SAndrzej Hajda 8057eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 806bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 8077eb8f069SAndrzej Hajda reg &= ~0x1f; 808bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 8097eb8f069SAndrzej Hajda 8107eb8f069SAndrzej Hajda usleep_range(9000, 11000); 8117eb8f069SAndrzej Hajda 8127eb8f069SAndrzej Hajda reg |= 0x1f; 813bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 8147eb8f069SAndrzej Hajda usleep_range(9000, 11000); 8157eb8f069SAndrzej Hajda 8167eb8f069SAndrzej Hajda /* DSI configuration */ 8177eb8f069SAndrzej Hajda reg = 0; 8187eb8f069SAndrzej Hajda 8192f36e33aSYoungJun Cho /* 8202f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 8212f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 8222f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 8232f36e33aSYoungJun Cho */ 8247eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8257eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 8267eb8f069SAndrzej Hajda 8272f36e33aSYoungJun Cho /* 8282f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 8292f36e33aSYoungJun Cho * command mode. 8302f36e33aSYoungJun Cho */ 8317eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 8327eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 8337eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 8347eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 8357eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 8367eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 8377eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 8387eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 8397eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 8402e337a8dSJagan Teki reg |= DSIM_HSE_DISABLE_MODE; 841996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 8422e337a8dSJagan Teki reg |= DSIM_HFP_DISABLE_MODE; 843996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 8442e337a8dSJagan Teki reg |= DSIM_HBP_DISABLE_MODE; 845996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 8462e337a8dSJagan Teki reg |= DSIM_HSA_DISABLE_MODE; 8477eb8f069SAndrzej Hajda } 8487eb8f069SAndrzej Hajda 849996e1defSJagan Teki if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 8502f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 8512f36e33aSYoungJun Cho 8527eb8f069SAndrzej Hajda switch (dsi->format) { 8537eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 8547eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 8557eb8f069SAndrzej Hajda break; 8567eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 8577eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 8587eb8f069SAndrzej Hajda break; 8597eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 8607eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 8617eb8f069SAndrzej Hajda break; 8627eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 8637eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 8647eb8f069SAndrzej Hajda break; 8657eb8f069SAndrzej Hajda default: 8667eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 8677eb8f069SAndrzej Hajda return -EINVAL; 8687eb8f069SAndrzej Hajda } 8697eb8f069SAndrzej Hajda 87078d3a8c6SInki Dae /* 87178d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 87278d3a8c6SInki Dae * host controller supports 87378d3a8c6SInki Dae * 87478d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 87578d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 87678d3a8c6SInki Dae * power consumption. 87778d3a8c6SInki Dae */ 87878d3a8c6SInki Dae if (driver_data->has_clklane_stop && 87978d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 88078d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 88178d3a8c6SInki Dae } 882bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 883e6f988a4SHyungwon Hwang 884e6f988a4SHyungwon Hwang lanes_mask = BIT(dsi->lanes) - 1; 885e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, lanes_mask); 88678d3a8c6SInki Dae 8877eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 8887eb8f069SAndrzej Hajda timeout = 100; 8897eb8f069SAndrzej Hajda do { 8907eb8f069SAndrzej Hajda if (timeout-- == 0) { 8917eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 8927eb8f069SAndrzej Hajda return -EFAULT; 8937eb8f069SAndrzej Hajda } 8947eb8f069SAndrzej Hajda 895bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 8967eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 8977eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 8987eb8f069SAndrzej Hajda continue; 8997eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 9007eb8f069SAndrzej Hajda 901bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9027eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 903d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 904bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 9057eb8f069SAndrzej Hajda 9067eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 907bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 9087eb8f069SAndrzej Hajda 9097eb8f069SAndrzej Hajda return 0; 9107eb8f069SAndrzej Hajda } 9117eb8f069SAndrzej Hajda 9127eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 9137eb8f069SAndrzej Hajda { 914aee039e6SJagan Teki struct drm_display_mode *m = &dsi->mode; 915d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 9167eb8f069SAndrzej Hajda u32 reg; 9177eb8f069SAndrzej Hajda 9187eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 9197eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 920e8929999SAndrzej Hajda | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 921e8929999SAndrzej Hajda | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 922bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 9237eb8f069SAndrzej Hajda 924e8929999SAndrzej Hajda reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) 925e8929999SAndrzej Hajda | DSIM_MAIN_HBP(m->htotal - m->hsync_end); 926bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 9277eb8f069SAndrzej Hajda 928e8929999SAndrzej Hajda reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 929e8929999SAndrzej Hajda | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); 930bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 9317eb8f069SAndrzej Hajda } 932e8929999SAndrzej Hajda reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 933e8929999SAndrzej Hajda DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 9347eb8f069SAndrzej Hajda 935bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9367eb8f069SAndrzej Hajda 937e8929999SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 9387eb8f069SAndrzej Hajda } 9397eb8f069SAndrzej Hajda 9407eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 9417eb8f069SAndrzej Hajda { 9427eb8f069SAndrzej Hajda u32 reg; 9437eb8f069SAndrzej Hajda 944bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 9457eb8f069SAndrzej Hajda if (enable) 9467eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 9477eb8f069SAndrzej Hajda else 9487eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 949bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9507eb8f069SAndrzej Hajda } 9517eb8f069SAndrzej Hajda 9527eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 9537eb8f069SAndrzej Hajda { 9547eb8f069SAndrzej Hajda int timeout = 2000; 9557eb8f069SAndrzej Hajda 9567eb8f069SAndrzej Hajda do { 957bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 9587eb8f069SAndrzej Hajda 9597eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 9607eb8f069SAndrzej Hajda return 0; 9617eb8f069SAndrzej Hajda 9627eb8f069SAndrzej Hajda if (!cond_resched()) 9637eb8f069SAndrzej Hajda usleep_range(950, 1050); 9647eb8f069SAndrzej Hajda } while (--timeout); 9657eb8f069SAndrzej Hajda 9667eb8f069SAndrzej Hajda return -ETIMEDOUT; 9677eb8f069SAndrzej Hajda } 9687eb8f069SAndrzej Hajda 9697eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 9707eb8f069SAndrzej Hajda { 971bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9727eb8f069SAndrzej Hajda 9737eb8f069SAndrzej Hajda if (lpm) 9747eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 9757eb8f069SAndrzej Hajda else 9767eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 9777eb8f069SAndrzej Hajda 978bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9797eb8f069SAndrzej Hajda } 9807eb8f069SAndrzej Hajda 9817eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 9827eb8f069SAndrzej Hajda { 983bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9847eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 985bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9867eb8f069SAndrzej Hajda } 9877eb8f069SAndrzej Hajda 9887eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 9897eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9907eb8f069SAndrzej Hajda { 9917eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9926c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 9936c81e96dSAndrzej Hajda const u8 *payload = pkt->payload + xfer->tx_done; 9946c81e96dSAndrzej Hajda u16 length = pkt->payload_length - xfer->tx_done; 9957eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 9967eb8f069SAndrzej Hajda u32 reg; 9977eb8f069SAndrzej Hajda 9989cdf0ed2SKrzysztof Kozlowski dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 9996c81e96dSAndrzej Hajda xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 10007eb8f069SAndrzej Hajda 10017eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 10027eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 10037eb8f069SAndrzej Hajda 10047eb8f069SAndrzej Hajda xfer->tx_done += length; 10057eb8f069SAndrzej Hajda 10067eb8f069SAndrzej Hajda /* Send payload */ 10077eb8f069SAndrzej Hajda while (length >= 4) { 10086c81e96dSAndrzej Hajda reg = get_unaligned_le32(payload); 1009bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 10107eb8f069SAndrzej Hajda payload += 4; 10117eb8f069SAndrzej Hajda length -= 4; 10127eb8f069SAndrzej Hajda } 10137eb8f069SAndrzej Hajda 10147eb8f069SAndrzej Hajda reg = 0; 10157eb8f069SAndrzej Hajda switch (length) { 10167eb8f069SAndrzej Hajda case 3: 10177eb8f069SAndrzej Hajda reg |= payload[2] << 16; 1018df561f66SGustavo A. R. Silva fallthrough; 10197eb8f069SAndrzej Hajda case 2: 10207eb8f069SAndrzej Hajda reg |= payload[1] << 8; 1021df561f66SGustavo A. R. Silva fallthrough; 10227eb8f069SAndrzej Hajda case 1: 10237eb8f069SAndrzej Hajda reg |= payload[0]; 1024bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 10257eb8f069SAndrzej Hajda break; 10267eb8f069SAndrzej Hajda } 10277eb8f069SAndrzej Hajda 10287eb8f069SAndrzej Hajda /* Send packet header */ 10297eb8f069SAndrzej Hajda if (!first) 10307eb8f069SAndrzej Hajda return; 10317eb8f069SAndrzej Hajda 10326c81e96dSAndrzej Hajda reg = get_unaligned_le32(pkt->header); 10337eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 10347eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 10357eb8f069SAndrzej Hajda return; 10367eb8f069SAndrzej Hajda } 10377eb8f069SAndrzej Hajda 10387eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 10397eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 10407eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 10417eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 10427eb8f069SAndrzej Hajda } 10437eb8f069SAndrzej Hajda 1044bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 10457eb8f069SAndrzej Hajda 10467eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 10477eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 10487eb8f069SAndrzej Hajda } 10497eb8f069SAndrzej Hajda 10507eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 10517eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 10527eb8f069SAndrzej Hajda { 10537eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 10547eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 10557eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 10567eb8f069SAndrzej Hajda u16 length; 10577eb8f069SAndrzej Hajda u32 reg; 10587eb8f069SAndrzej Hajda 10597eb8f069SAndrzej Hajda if (first) { 1060bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10617eb8f069SAndrzej Hajda 10627eb8f069SAndrzej Hajda switch (reg & 0x3f) { 10637eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 10647eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 10657eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 10667eb8f069SAndrzej Hajda payload[1] = reg >> 16; 10677eb8f069SAndrzej Hajda ++xfer->rx_done; 10687eb8f069SAndrzej Hajda } 1069df561f66SGustavo A. R. Silva fallthrough; 10707eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 10717eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 10727eb8f069SAndrzej Hajda payload[0] = reg >> 8; 10737eb8f069SAndrzej Hajda ++xfer->rx_done; 10747eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 10757eb8f069SAndrzej Hajda xfer->result = 0; 10767eb8f069SAndrzej Hajda goto clear_fifo; 10777eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 10787eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 10797eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 10807eb8f069SAndrzej Hajda xfer->result = 0; 10817eb8f069SAndrzej Hajda goto clear_fifo; 10827eb8f069SAndrzej Hajda } 10837eb8f069SAndrzej Hajda 10847eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 10857eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 10867eb8f069SAndrzej Hajda dev_err(dev, 10877eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 10887eb8f069SAndrzej Hajda xfer->rx_len, length); 10897eb8f069SAndrzej Hajda length = xfer->rx_len; 10907eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 10917eb8f069SAndrzej Hajda xfer->rx_len = length; 10927eb8f069SAndrzej Hajda } 10937eb8f069SAndrzej Hajda 10947eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 10957eb8f069SAndrzej Hajda xfer->rx_done += length; 10967eb8f069SAndrzej Hajda 10977eb8f069SAndrzej Hajda /* Receive payload */ 10987eb8f069SAndrzej Hajda while (length >= 4) { 1099bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11007eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 11017eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 11027eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 11037eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 11047eb8f069SAndrzej Hajda payload += 4; 11057eb8f069SAndrzej Hajda length -= 4; 11067eb8f069SAndrzej Hajda } 11077eb8f069SAndrzej Hajda 11087eb8f069SAndrzej Hajda if (length) { 1109bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11107eb8f069SAndrzej Hajda switch (length) { 11117eb8f069SAndrzej Hajda case 3: 11127eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 1113df561f66SGustavo A. R. Silva fallthrough; 11147eb8f069SAndrzej Hajda case 2: 11157eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 1116df561f66SGustavo A. R. Silva fallthrough; 11177eb8f069SAndrzej Hajda case 1: 11187eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 11197eb8f069SAndrzej Hajda } 11207eb8f069SAndrzej Hajda } 11217eb8f069SAndrzej Hajda 11227eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 11237eb8f069SAndrzej Hajda xfer->result = 0; 11247eb8f069SAndrzej Hajda 11257eb8f069SAndrzej Hajda clear_fifo: 11267eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 11277eb8f069SAndrzej Hajda do { 1128bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11297eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 11307eb8f069SAndrzej Hajda break; 11317eb8f069SAndrzej Hajda } while (--length); 11327eb8f069SAndrzej Hajda } 11337eb8f069SAndrzej Hajda 11347eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 11357eb8f069SAndrzej Hajda { 11367eb8f069SAndrzej Hajda unsigned long flags; 11377eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11387eb8f069SAndrzej Hajda bool start = false; 11397eb8f069SAndrzej Hajda 11407eb8f069SAndrzej Hajda again: 11417eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11427eb8f069SAndrzej Hajda 11437eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11447eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11457eb8f069SAndrzej Hajda return; 11467eb8f069SAndrzej Hajda } 11477eb8f069SAndrzej Hajda 11487eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11497eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11507eb8f069SAndrzej Hajda 11517eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11527eb8f069SAndrzej Hajda 11536c81e96dSAndrzej Hajda if (xfer->packet.payload_length && 11546c81e96dSAndrzej Hajda xfer->tx_done == xfer->packet.payload_length) 11557eb8f069SAndrzej Hajda /* waiting for RX */ 11567eb8f069SAndrzej Hajda return; 11577eb8f069SAndrzej Hajda 11587eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 11597eb8f069SAndrzej Hajda 11606c81e96dSAndrzej Hajda if (xfer->packet.payload_length || xfer->rx_len) 11617eb8f069SAndrzej Hajda return; 11627eb8f069SAndrzej Hajda 11637eb8f069SAndrzej Hajda xfer->result = 0; 11647eb8f069SAndrzej Hajda complete(&xfer->completed); 11657eb8f069SAndrzej Hajda 11667eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11677eb8f069SAndrzej Hajda 11687eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11697eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11707eb8f069SAndrzej Hajda 11717eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11727eb8f069SAndrzej Hajda 11737eb8f069SAndrzej Hajda if (start) 11747eb8f069SAndrzej Hajda goto again; 11757eb8f069SAndrzej Hajda } 11767eb8f069SAndrzej Hajda 11777eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 11787eb8f069SAndrzej Hajda { 11797eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11807eb8f069SAndrzej Hajda unsigned long flags; 11817eb8f069SAndrzej Hajda bool start = true; 11827eb8f069SAndrzej Hajda 11837eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11847eb8f069SAndrzej Hajda 11857eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11867eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11877eb8f069SAndrzej Hajda return false; 11887eb8f069SAndrzej Hajda } 11897eb8f069SAndrzej Hajda 11907eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11917eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11927eb8f069SAndrzej Hajda 11937eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11947eb8f069SAndrzej Hajda 11957eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 11969cdf0ed2SKrzysztof Kozlowski "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 11976c81e96dSAndrzej Hajda xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 11986c81e96dSAndrzej Hajda xfer->rx_done); 11997eb8f069SAndrzej Hajda 12006c81e96dSAndrzej Hajda if (xfer->tx_done != xfer->packet.payload_length) 12017eb8f069SAndrzej Hajda return true; 12027eb8f069SAndrzej Hajda 12037eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 12047eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 12057eb8f069SAndrzej Hajda 12067eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 12077eb8f069SAndrzej Hajda return true; 12087eb8f069SAndrzej Hajda 12097eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12107eb8f069SAndrzej Hajda 12117eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12127eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12137eb8f069SAndrzej Hajda 12147eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12157eb8f069SAndrzej Hajda 12167eb8f069SAndrzej Hajda if (!xfer->rx_len) 12177eb8f069SAndrzej Hajda xfer->result = 0; 12187eb8f069SAndrzej Hajda complete(&xfer->completed); 12197eb8f069SAndrzej Hajda 12207eb8f069SAndrzej Hajda return start; 12217eb8f069SAndrzej Hajda } 12227eb8f069SAndrzej Hajda 12237eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 12247eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12257eb8f069SAndrzej Hajda { 12267eb8f069SAndrzej Hajda unsigned long flags; 12277eb8f069SAndrzej Hajda bool start; 12287eb8f069SAndrzej Hajda 12297eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12307eb8f069SAndrzej Hajda 12317eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 12327eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 12337eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 12347eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12357eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12367eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12377eb8f069SAndrzej Hajda if (start) 12387eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12397eb8f069SAndrzej Hajda return; 12407eb8f069SAndrzej Hajda } 12417eb8f069SAndrzej Hajda 12427eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12437eb8f069SAndrzej Hajda 12447eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12457eb8f069SAndrzej Hajda } 12467eb8f069SAndrzej Hajda 12477eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 12487eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12497eb8f069SAndrzej Hajda { 12507eb8f069SAndrzej Hajda unsigned long flags; 12517eb8f069SAndrzej Hajda bool stopped; 12527eb8f069SAndrzej Hajda 12537eb8f069SAndrzej Hajda xfer->tx_done = 0; 12547eb8f069SAndrzej Hajda xfer->rx_done = 0; 12557eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 12567eb8f069SAndrzej Hajda init_completion(&xfer->completed); 12577eb8f069SAndrzej Hajda 12587eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12597eb8f069SAndrzej Hajda 12607eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 12617eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 12627eb8f069SAndrzej Hajda 12637eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12647eb8f069SAndrzej Hajda 12657eb8f069SAndrzej Hajda if (stopped) 12667eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12677eb8f069SAndrzej Hajda 12687eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 12697eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 12707eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 12716c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 12727eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 12736c81e96dSAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 12746c81e96dSAndrzej Hajda (int)pkt->payload_length, pkt->payload); 12757eb8f069SAndrzej Hajda return -ETIMEDOUT; 12767eb8f069SAndrzej Hajda } 12777eb8f069SAndrzej Hajda 12787eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 12797eb8f069SAndrzej Hajda return xfer->result; 12807eb8f069SAndrzej Hajda } 12817eb8f069SAndrzej Hajda 12827eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 12837eb8f069SAndrzej Hajda { 12847eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 12857eb8f069SAndrzej Hajda u32 status; 12867eb8f069SAndrzej Hajda 1287bb32e408SAndrzej Hajda status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 12887eb8f069SAndrzej Hajda if (!status) { 12897eb8f069SAndrzej Hajda static unsigned long int j; 12907eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 12917eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 12927eb8f069SAndrzej Hajda return IRQ_HANDLED; 12937eb8f069SAndrzej Hajda } 1294bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 12957eb8f069SAndrzej Hajda 12967eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 1297e6f988a4SHyungwon Hwang u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1298ecf81ed9SAndrzej Hajda DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_RX_ECC_ERR | 1299ecf81ed9SAndrzej Hajda DSIM_INT_SW_RST_RELEASE); 1300bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 13017eb8f069SAndrzej Hajda complete(&dsi->completed); 13027eb8f069SAndrzej Hajda return IRQ_HANDLED; 13037eb8f069SAndrzej Hajda } 13047eb8f069SAndrzej Hajda 1305e6f988a4SHyungwon Hwang if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1306ecf81ed9SAndrzej Hajda DSIM_INT_PLL_STABLE))) 13077eb8f069SAndrzej Hajda return IRQ_HANDLED; 13087eb8f069SAndrzej Hajda 13097eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 13107eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 13117eb8f069SAndrzej Hajda 13127eb8f069SAndrzej Hajda return IRQ_HANDLED; 13137eb8f069SAndrzej Hajda } 13147eb8f069SAndrzej Hajda 1315e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1316e17ddeccSYoungJun Cho { 1317e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 13182b8376c8SGustavo Padovan struct drm_encoder *encoder = &dsi->encoder; 1319e17ddeccSYoungJun Cho 13200e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1321e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1322e17ddeccSYoungJun Cho 1323e17ddeccSYoungJun Cho return IRQ_HANDLED; 1324e17ddeccSYoungJun Cho } 1325e17ddeccSYoungJun Cho 1326e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1327e17ddeccSYoungJun Cho { 1328e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1329e17ddeccSYoungJun Cho 1330ee6c8b5aSMaíra Canal if (dsi->te_gpio) 1331ee6c8b5aSMaíra Canal enable_irq(gpiod_to_irq(dsi->te_gpio)); 1332e17ddeccSYoungJun Cho } 1333e17ddeccSYoungJun Cho 1334e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1335e17ddeccSYoungJun Cho { 1336ee6c8b5aSMaíra Canal if (dsi->te_gpio) 1337ee6c8b5aSMaíra Canal disable_irq(gpiod_to_irq(dsi->te_gpio)); 1338e17ddeccSYoungJun Cho 1339e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1340e17ddeccSYoungJun Cho } 1341e17ddeccSYoungJun Cho 13427eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 13437eb8f069SAndrzej Hajda { 13442154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1345d668e8bfSHyungwon Hwang 13467eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1347e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 1348e6f988a4SHyungwon Hwang 1349e6f988a4SHyungwon Hwang if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1350e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1351e6f988a4SHyungwon Hwang 13529a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1353d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 13547eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 13559a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 13567eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 13577eb8f069SAndrzej Hajda 13587eb8f069SAndrzej Hajda return 0; 13597eb8f069SAndrzej Hajda } 13607eb8f069SAndrzej Hajda 1361295e7954SAndrzej Hajda static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi, 1362295e7954SAndrzej Hajda struct device *panel) 1363e17ddeccSYoungJun Cho { 1364e17ddeccSYoungJun Cho int ret; 13650cef83a5SYoungJun Cho int te_gpio_irq; 1366e17ddeccSYoungJun Cho 1367fedc8982SMarek Szyprowski dsi->te_gpio = gpiod_get_optional(panel, "te", GPIOD_IN); 13688e3fa9d8SMarek Szyprowski if (!dsi->te_gpio) { 13698e3fa9d8SMarek Szyprowski return 0; 13708e3fa9d8SMarek Szyprowski } else if (IS_ERR(dsi->te_gpio)) { 1371ee6c8b5aSMaíra Canal dev_err(dsi->dev, "gpio request failed with %ld\n", 1372ee6c8b5aSMaíra Canal PTR_ERR(dsi->te_gpio)); 1373760cceffSInki Dae return PTR_ERR(dsi->te_gpio); 1374e17ddeccSYoungJun Cho } 1375e17ddeccSYoungJun Cho 1376ee6c8b5aSMaíra Canal te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 137751d1decaSHyungwon Hwang 13780cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1379a4e5eed2STian Tao IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1380e17ddeccSYoungJun Cho if (ret) { 1381e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1382ee6c8b5aSMaíra Canal gpiod_put(dsi->te_gpio); 1383760cceffSInki Dae return ret; 1384e17ddeccSYoungJun Cho } 1385e17ddeccSYoungJun Cho 1386760cceffSInki Dae return 0; 1387e17ddeccSYoungJun Cho } 1388e17ddeccSYoungJun Cho 1389e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1390e17ddeccSYoungJun Cho { 1391ee6c8b5aSMaíra Canal if (dsi->te_gpio) { 1392ee6c8b5aSMaíra Canal free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1393ee6c8b5aSMaíra Canal gpiod_put(dsi->te_gpio); 1394e17ddeccSYoungJun Cho } 1395e17ddeccSYoungJun Cho } 1396e17ddeccSYoungJun Cho 139795a2441eSJagan Teki static void exynos_dsi_atomic_pre_enable(struct drm_bridge *bridge, 139895a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 13997eb8f069SAndrzej Hajda { 1400f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 14017eb8f069SAndrzej Hajda int ret; 14027eb8f069SAndrzej Hajda 14037eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 1404b6595dc7SGustavo Padovan return; 14057eb8f069SAndrzej Hajda 1406445d3bedSInki Dae ret = pm_runtime_resume_and_get(dsi->dev); 1407445d3bedSInki Dae if (ret < 0) { 1408445d3bedSInki Dae dev_err(dsi->dev, "failed to enable DSI device.\n"); 1409445d3bedSInki Dae return; 1410445d3bedSInki Dae } 1411445d3bedSInki Dae 14120e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 1413f66ff55aSBoris Brezillon } 14147eb8f069SAndrzej Hajda 141595a2441eSJagan Teki static void exynos_dsi_atomic_enable(struct drm_bridge *bridge, 141695a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 1417f9bfd326SJagan Teki { 1418f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1419f9bfd326SJagan Teki 14207eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 14217eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 14227eb8f069SAndrzej Hajda 14230e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1424f9bfd326SJagan Teki 14258a08f671SMaciej Purski return; 14267eb8f069SAndrzej Hajda } 14277eb8f069SAndrzej Hajda 142895a2441eSJagan Teki static void exynos_dsi_atomic_disable(struct drm_bridge *bridge, 142995a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 14307eb8f069SAndrzej Hajda { 1431f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1432b6595dc7SGustavo Padovan 14337eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 14347eb8f069SAndrzej Hajda return; 14357eb8f069SAndrzej Hajda 14360e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1437f66ff55aSBoris Brezillon } 1438f66ff55aSBoris Brezillon 143995a2441eSJagan Teki static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, 144095a2441eSJagan Teki struct drm_bridge_state *old_bridge_state) 1441f9bfd326SJagan Teki { 1442f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1443f9bfd326SJagan Teki 1444cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1445f66ff55aSBoris Brezillon 14467eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 1447ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 14487eb8f069SAndrzej Hajda } 14497eb8f069SAndrzej Hajda 1450f9bfd326SJagan Teki static void exynos_dsi_mode_set(struct drm_bridge *bridge, 1451f9bfd326SJagan Teki const struct drm_display_mode *mode, 1452f9bfd326SJagan Teki const struct drm_display_mode *adjusted_mode) 1453bd29823eSJagan Teki { 1454f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1455bd29823eSJagan Teki 1456bd29823eSJagan Teki drm_mode_copy(&dsi->mode, adjusted_mode); 1457bd29823eSJagan Teki } 1458bd29823eSJagan Teki 1459f9bfd326SJagan Teki static int exynos_dsi_attach(struct drm_bridge *bridge, 1460f9bfd326SJagan Teki enum drm_bridge_attach_flags flags) 1461f9bfd326SJagan Teki { 1462f9bfd326SJagan Teki struct exynos_dsi *dsi = bridge_to_dsi(bridge); 1463f9bfd326SJagan Teki 14641a1ce789SJagan Teki return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge, 14651a1ce789SJagan Teki flags); 1466f9bfd326SJagan Teki } 1467f9bfd326SJagan Teki 1468f9bfd326SJagan Teki static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { 146995a2441eSJagan Teki .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 147095a2441eSJagan Teki .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 147195a2441eSJagan Teki .atomic_reset = drm_atomic_helper_bridge_reset, 147295a2441eSJagan Teki .atomic_pre_enable = exynos_dsi_atomic_pre_enable, 147395a2441eSJagan Teki .atomic_enable = exynos_dsi_atomic_enable, 147495a2441eSJagan Teki .atomic_disable = exynos_dsi_atomic_disable, 147595a2441eSJagan Teki .atomic_post_disable = exynos_dsi_atomic_post_disable, 1476aee039e6SJagan Teki .mode_set = exynos_dsi_mode_set, 1477f9bfd326SJagan Teki .attach = exynos_dsi_attach, 14787eb8f069SAndrzej Hajda }; 14797eb8f069SAndrzej Hajda 1480295e7954SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 1481295e7954SAndrzej Hajda struct mipi_dsi_device *device) 1482295e7954SAndrzej Hajda { 1483295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 1484711c7adcSJagan Teki struct device *dev = dsi->dev; 14856afb7721SMaciej Purski struct drm_encoder *encoder = &dsi->encoder; 14866afb7721SMaciej Purski struct drm_device *drm = encoder->dev; 1487e39a82bfSJagan Teki struct device_node *np = dev->of_node; 1488e39a82bfSJagan Teki struct device_node *remote; 1489ea16c74cSJagan Teki struct drm_panel *panel; 1490711c7adcSJagan Teki int ret; 14916afb7721SMaciej Purski 1492e39a82bfSJagan Teki /* 1493e39a82bfSJagan Teki * Devices can also be child nodes when we also control that device 1494e39a82bfSJagan Teki * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). 1495e39a82bfSJagan Teki * 1496e39a82bfSJagan Teki * Lookup for a child node of the given parent that isn't either port 1497e39a82bfSJagan Teki * or ports. 1498e39a82bfSJagan Teki */ 1499e39a82bfSJagan Teki for_each_available_child_of_node(np, remote) { 1500e39a82bfSJagan Teki if (of_node_name_eq(remote, "port") || 1501e39a82bfSJagan Teki of_node_name_eq(remote, "ports")) 1502e39a82bfSJagan Teki continue; 1503e39a82bfSJagan Teki 1504e39a82bfSJagan Teki goto of_find_panel_or_bridge; 1505e39a82bfSJagan Teki } 1506e39a82bfSJagan Teki 1507e39a82bfSJagan Teki /* 1508e39a82bfSJagan Teki * of_graph_get_remote_node() produces a noisy error message if port 1509e39a82bfSJagan Teki * node isn't found and the absence of the port is a legit case here, 1510e39a82bfSJagan Teki * so at first we silently check whether graph presents in the 1511e39a82bfSJagan Teki * device-tree node. 1512e39a82bfSJagan Teki */ 1513e39a82bfSJagan Teki if (!of_graph_is_present(np)) 1514e39a82bfSJagan Teki return -ENODEV; 1515e39a82bfSJagan Teki 1516e39a82bfSJagan Teki remote = of_graph_get_remote_node(np, 1, 0); 1517e39a82bfSJagan Teki 1518e39a82bfSJagan Teki of_find_panel_or_bridge: 1519e39a82bfSJagan Teki if (!remote) 1520e39a82bfSJagan Teki return -ENODEV; 1521e39a82bfSJagan Teki 1522e39a82bfSJagan Teki panel = of_drm_find_panel(remote); 1523ea16c74cSJagan Teki if (!IS_ERR(panel)) { 1524ea16c74cSJagan Teki dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1525ea16c74cSJagan Teki } else { 1526e39a82bfSJagan Teki dsi->out_bridge = of_drm_find_bridge(remote); 1527ea16c74cSJagan Teki if (!dsi->out_bridge) 1528ea16c74cSJagan Teki dsi->out_bridge = ERR_PTR(-EINVAL); 1529ea16c74cSJagan Teki } 1530ea16c74cSJagan Teki 1531e39a82bfSJagan Teki of_node_put(remote); 1532e39a82bfSJagan Teki 1533711c7adcSJagan Teki if (IS_ERR(dsi->out_bridge)) { 1534711c7adcSJagan Teki ret = PTR_ERR(dsi->out_bridge); 1535711c7adcSJagan Teki DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 15366afb7721SMaciej Purski return ret; 15376afb7721SMaciej Purski } 15386afb7721SMaciej Purski 1539711c7adcSJagan Teki DRM_DEV_INFO(dev, "Attached %s device\n", device->name); 1540711c7adcSJagan Teki 1541f9bfd326SJagan Teki drm_bridge_add(&dsi->bridge); 1542f9bfd326SJagan Teki 15431a1ce789SJagan Teki drm_bridge_attach(encoder, &dsi->bridge, 15441a1ce789SJagan Teki list_first_entry_or_null(&encoder->bridge_chain, 15451a1ce789SJagan Teki struct drm_bridge, 15461a1ce789SJagan Teki chain_node), 0); 1547295e7954SAndrzej Hajda 1548295e7954SAndrzej Hajda /* 1549295e7954SAndrzej Hajda * This is a temporary solution and should be made by more generic way. 1550295e7954SAndrzej Hajda * 1551295e7954SAndrzej Hajda * If attached panel device is for command mode one, dsi should register 1552295e7954SAndrzej Hajda * TE interrupt handler. 1553295e7954SAndrzej Hajda */ 1554295e7954SAndrzej Hajda if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1555711c7adcSJagan Teki ret = exynos_dsi_register_te_irq(dsi, &device->dev); 1556295e7954SAndrzej Hajda if (ret) 1557295e7954SAndrzej Hajda return ret; 1558295e7954SAndrzej Hajda } 1559295e7954SAndrzej Hajda 1560295e7954SAndrzej Hajda mutex_lock(&drm->mode_config.mutex); 1561295e7954SAndrzej Hajda 1562295e7954SAndrzej Hajda dsi->lanes = device->lanes; 1563295e7954SAndrzej Hajda dsi->format = device->format; 1564295e7954SAndrzej Hajda dsi->mode_flags = device->mode_flags; 1565c038f538SAndrzej Hajda exynos_drm_crtc_get_by_type(drm, EXYNOS_DISPLAY_TYPE_LCD)->i80_mode = 1566c038f538SAndrzej Hajda !(dsi->mode_flags & MIPI_DSI_MODE_VIDEO); 1567295e7954SAndrzej Hajda 1568295e7954SAndrzej Hajda mutex_unlock(&drm->mode_config.mutex); 1569295e7954SAndrzej Hajda 1570295e7954SAndrzej Hajda if (drm->mode_config.poll_enabled) 1571295e7954SAndrzej Hajda drm_kms_helper_hotplug_event(drm); 1572295e7954SAndrzej Hajda 1573295e7954SAndrzej Hajda return 0; 1574295e7954SAndrzej Hajda } 1575295e7954SAndrzej Hajda 1576295e7954SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 1577295e7954SAndrzej Hajda struct mipi_dsi_device *device) 1578295e7954SAndrzej Hajda { 1579295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 15806afb7721SMaciej Purski struct drm_device *drm = dsi->encoder.dev; 1581295e7954SAndrzej Hajda 15826afb7721SMaciej Purski dsi->out_bridge = NULL; 1583295e7954SAndrzej Hajda 1584295e7954SAndrzej Hajda if (drm->mode_config.poll_enabled) 1585295e7954SAndrzej Hajda drm_kms_helper_hotplug_event(drm); 1586295e7954SAndrzej Hajda 1587295e7954SAndrzej Hajda exynos_dsi_unregister_te_irq(dsi); 1588295e7954SAndrzej Hajda 1589f9bfd326SJagan Teki drm_bridge_remove(&dsi->bridge); 1590f9bfd326SJagan Teki 1591295e7954SAndrzej Hajda return 0; 1592295e7954SAndrzej Hajda } 1593295e7954SAndrzej Hajda 1594295e7954SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1595295e7954SAndrzej Hajda const struct mipi_dsi_msg *msg) 1596295e7954SAndrzej Hajda { 1597295e7954SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 1598295e7954SAndrzej Hajda struct exynos_dsi_transfer xfer; 1599295e7954SAndrzej Hajda int ret; 1600295e7954SAndrzej Hajda 1601295e7954SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 1602295e7954SAndrzej Hajda return -EINVAL; 1603295e7954SAndrzej Hajda 1604295e7954SAndrzej Hajda if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 1605295e7954SAndrzej Hajda ret = exynos_dsi_init(dsi); 1606295e7954SAndrzej Hajda if (ret) 1607295e7954SAndrzej Hajda return ret; 1608295e7954SAndrzej Hajda dsi->state |= DSIM_STATE_INITIALIZED; 1609295e7954SAndrzej Hajda } 1610295e7954SAndrzej Hajda 1611295e7954SAndrzej Hajda ret = mipi_dsi_create_packet(&xfer.packet, msg); 1612295e7954SAndrzej Hajda if (ret < 0) 1613295e7954SAndrzej Hajda return ret; 1614295e7954SAndrzej Hajda 1615295e7954SAndrzej Hajda xfer.rx_len = msg->rx_len; 1616295e7954SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 1617295e7954SAndrzej Hajda xfer.flags = msg->flags; 1618295e7954SAndrzej Hajda 1619295e7954SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 1620295e7954SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 1621295e7954SAndrzej Hajda } 1622295e7954SAndrzej Hajda 1623295e7954SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 1624295e7954SAndrzej Hajda .attach = exynos_dsi_host_attach, 1625295e7954SAndrzej Hajda .detach = exynos_dsi_host_detach, 1626295e7954SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 1627295e7954SAndrzej Hajda }; 1628295e7954SAndrzej Hajda 16297eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 16307eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 16317eb8f069SAndrzej Hajda { 16327eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 16337eb8f069SAndrzej Hajda 16347eb8f069SAndrzej Hajda if (ret < 0) 16354bf99144SRob Herring pr_err("%pOF: failed to get '%s' property\n", np, propname); 16367eb8f069SAndrzej Hajda 16377eb8f069SAndrzej Hajda return ret; 16387eb8f069SAndrzej Hajda } 16397eb8f069SAndrzej Hajda 16407eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 16417eb8f069SAndrzej Hajda { 16427eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 16437eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 16447eb8f069SAndrzej Hajda int ret; 16457eb8f069SAndrzej Hajda 16467eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 16477eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 16487eb8f069SAndrzej Hajda if (ret < 0) 16497eb8f069SAndrzej Hajda return ret; 16507eb8f069SAndrzej Hajda 1651f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 16527eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 16537eb8f069SAndrzej Hajda if (ret < 0) 1654f2921d8cSHoegeun Kwon return ret; 16557eb8f069SAndrzej Hajda 1656f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 16577eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 1658f5f3b9baSHyungwon Hwang if (ret < 0) 1659f2921d8cSHoegeun Kwon return ret; 1660f5f3b9baSHyungwon Hwang 1661f2921d8cSHoegeun Kwon return 0; 16627eb8f069SAndrzej Hajda } 16637eb8f069SAndrzej Hajda 1664f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1665f37cd5e8SInki Dae void *data) 1666f37cd5e8SInki Dae { 1667e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 1668e11e6df2SMichael Tretter struct drm_encoder *encoder = &dsi->encoder; 1669f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1670f37cd5e8SInki Dae int ret; 1671f37cd5e8SInki Dae 16723e1fe32dSThomas Zimmermann drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_TMDS); 16732b8376c8SGustavo Padovan 16741ca582f1SAndrzej Hajda ret = exynos_drm_set_possible_crtcs(encoder, EXYNOS_DISPLAY_TYPE_LCD); 16751ca582f1SAndrzej Hajda if (ret < 0) 16761ca582f1SAndrzej Hajda return ret; 16771ca582f1SAndrzej Hajda 1678f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1679f37cd5e8SInki Dae } 1680f37cd5e8SInki Dae 1681f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1682f37cd5e8SInki Dae void *data) 1683f37cd5e8SInki Dae { 1684e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 1685f37cd5e8SInki Dae 168695a2441eSJagan Teki exynos_dsi_atomic_disable(&dsi->bridge, NULL); 1687f37cd5e8SInki Dae 16880ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1689f37cd5e8SInki Dae } 1690f37cd5e8SInki Dae 1691f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1692f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1693f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1694f37cd5e8SInki Dae }; 1695f37cd5e8SInki Dae 16967eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 16977eb8f069SAndrzej Hajda { 16982900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 16997eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 17000ff03fd1SHyungwon Hwang int ret, i; 17017eb8f069SAndrzej Hajda 17022900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 17032900c69cSAndrzej Hajda if (!dsi) 17042900c69cSAndrzej Hajda return -ENOMEM; 17052900c69cSAndrzej Hajda 17067eb8f069SAndrzej Hajda init_completion(&dsi->completed); 17077eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 17087eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 17097eb8f069SAndrzej Hajda 17107eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1711e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 17127eb8f069SAndrzej Hajda 1713e2d2a1e0SAndrzej Hajda dsi->dev = dev; 1714*7e9f0d32SJagan Teki dsi->plat_data = of_device_get_match_data(dev); 1715*7e9f0d32SJagan Teki dsi->driver_data = exynos_dsi_types[dsi->plat_data->hw_type]; 17167eb8f069SAndrzej Hajda 17177eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 17187eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1719e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 17207eb8f069SAndrzej Hajda dsi->supplies); 172173bb394cSKrzysztof Kozlowski if (ret) 172273bb394cSKrzysztof Kozlowski return dev_err_probe(dev, ret, "failed to get regulators\n"); 17237eb8f069SAndrzej Hajda 1724a86854d0SKees Cook dsi->clks = devm_kcalloc(dev, 1725a86854d0SKees Cook dsi->driver_data->num_clks, sizeof(*dsi->clks), 17260ff03fd1SHyungwon Hwang GFP_KERNEL); 1727e6f988a4SHyungwon Hwang if (!dsi->clks) 1728e6f988a4SHyungwon Hwang return -ENOMEM; 1729e6f988a4SHyungwon Hwang 17300ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 17310ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 17320ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 17330ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1734c0fd99d6SMarek Szyprowski dsi->clks[i] = devm_clk_get(dev, 1735c0fd99d6SMarek Szyprowski OLD_SCLK_MIPI_CLK_NAME); 1736c0fd99d6SMarek Szyprowski if (!IS_ERR(dsi->clks[i])) 17370ff03fd1SHyungwon Hwang continue; 17387eb8f069SAndrzej Hajda } 17397eb8f069SAndrzej Hajda 17400ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 17410ff03fd1SHyungwon Hwang clk_names[i]); 17420ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 17430ff03fd1SHyungwon Hwang } 17447eb8f069SAndrzej Hajda } 17457eb8f069SAndrzej Hajda 174617ac76e0SCai Huoqing dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 174704562956SZhen Lei if (IS_ERR(dsi->reg_base)) 174886650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 17497eb8f069SAndrzej Hajda 17509528af4aSJagan Teki dsi->phy = devm_phy_optional_get(dev, "dsim"); 17517eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1752e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 175386650408SAndrzej Hajda return PTR_ERR(dsi->phy); 17547eb8f069SAndrzej Hajda } 17557eb8f069SAndrzej Hajda 17567eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 1757fdd79b0dSMarkus Elfring if (dsi->irq < 0) 175886650408SAndrzej Hajda return dsi->irq; 17597eb8f069SAndrzej Hajda 1760e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1761a4e5eed2STian Tao exynos_dsi_irq, 1762a4e5eed2STian Tao IRQF_ONESHOT | IRQF_NO_AUTOEN, 1763e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 17647eb8f069SAndrzej Hajda if (ret) { 1765e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 176686650408SAndrzej Hajda return ret; 17677eb8f069SAndrzej Hajda } 17687eb8f069SAndrzej Hajda 1769547a7348SChristophe JAILLET ret = exynos_dsi_parse_dt(dsi); 1770547a7348SChristophe JAILLET if (ret) 1771547a7348SChristophe JAILLET return ret; 1772547a7348SChristophe JAILLET 1773e11e6df2SMichael Tretter platform_set_drvdata(pdev, dsi); 17747eb8f069SAndrzej Hajda 1775ba6e4779SInki Dae pm_runtime_enable(dev); 1776ba6e4779SInki Dae 1777f9bfd326SJagan Teki dsi->bridge.funcs = &exynos_dsi_bridge_funcs; 1778f9bfd326SJagan Teki dsi->bridge.of_node = dev->of_node; 1779f9bfd326SJagan Teki dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 17801a1ce789SJagan Teki dsi->bridge.pre_enable_prev_first = true; 1781f9bfd326SJagan Teki 1782547a7348SChristophe JAILLET ret = component_add(dev, &exynos_dsi_component_ops); 1783547a7348SChristophe JAILLET if (ret) 1784547a7348SChristophe JAILLET goto err_disable_runtime; 1785547a7348SChristophe JAILLET 1786547a7348SChristophe JAILLET return 0; 1787547a7348SChristophe JAILLET 1788547a7348SChristophe JAILLET err_disable_runtime: 1789547a7348SChristophe JAILLET pm_runtime_disable(dev); 1790547a7348SChristophe JAILLET 1791547a7348SChristophe JAILLET return ret; 17927eb8f069SAndrzej Hajda } 17937eb8f069SAndrzej Hajda 17947eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 17957eb8f069SAndrzej Hajda { 1796ba6e4779SInki Dae pm_runtime_disable(&pdev->dev); 1797ba6e4779SInki Dae 1798df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1799df5225bcSInki Dae 18007eb8f069SAndrzej Hajda return 0; 18017eb8f069SAndrzej Hajda } 18027eb8f069SAndrzej Hajda 1803010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1804ba6e4779SInki Dae { 1805e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 18062154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1807ba6e4779SInki Dae int ret, i; 1808ba6e4779SInki Dae 1809ba6e4779SInki Dae usleep_range(10000, 20000); 1810ba6e4779SInki Dae 1811ba6e4779SInki Dae if (dsi->state & DSIM_STATE_INITIALIZED) { 1812ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_INITIALIZED; 1813ba6e4779SInki Dae 1814ba6e4779SInki Dae exynos_dsi_disable_clock(dsi); 1815ba6e4779SInki Dae 1816ba6e4779SInki Dae exynos_dsi_disable_irq(dsi); 1817ba6e4779SInki Dae } 1818ba6e4779SInki Dae 1819ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_CMD_LPM; 1820ba6e4779SInki Dae 1821ba6e4779SInki Dae phy_power_off(dsi->phy); 1822ba6e4779SInki Dae 1823ba6e4779SInki Dae for (i = driver_data->num_clks - 1; i > -1; i--) 1824ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1825ba6e4779SInki Dae 1826ba6e4779SInki Dae ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1827ba6e4779SInki Dae if (ret < 0) 1828ba6e4779SInki Dae dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1829ba6e4779SInki Dae 1830ba6e4779SInki Dae return 0; 1831ba6e4779SInki Dae } 1832ba6e4779SInki Dae 1833010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_resume(struct device *dev) 1834ba6e4779SInki Dae { 1835e11e6df2SMichael Tretter struct exynos_dsi *dsi = dev_get_drvdata(dev); 18362154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1837ba6e4779SInki Dae int ret, i; 1838ba6e4779SInki Dae 1839ba6e4779SInki Dae ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1840ba6e4779SInki Dae if (ret < 0) { 1841ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1842ba6e4779SInki Dae return ret; 1843ba6e4779SInki Dae } 1844ba6e4779SInki Dae 1845ba6e4779SInki Dae for (i = 0; i < driver_data->num_clks; i++) { 1846ba6e4779SInki Dae ret = clk_prepare_enable(dsi->clks[i]); 1847ba6e4779SInki Dae if (ret < 0) 1848ba6e4779SInki Dae goto err_clk; 1849ba6e4779SInki Dae } 1850ba6e4779SInki Dae 1851ba6e4779SInki Dae ret = phy_power_on(dsi->phy); 1852ba6e4779SInki Dae if (ret < 0) { 1853ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1854ba6e4779SInki Dae goto err_clk; 1855ba6e4779SInki Dae } 1856ba6e4779SInki Dae 1857ba6e4779SInki Dae return 0; 1858ba6e4779SInki Dae 1859ba6e4779SInki Dae err_clk: 1860ba6e4779SInki Dae while (--i > -1) 1861ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1862ba6e4779SInki Dae regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1863ba6e4779SInki Dae 1864ba6e4779SInki Dae return ret; 1865ba6e4779SInki Dae } 1866ba6e4779SInki Dae 1867ba6e4779SInki Dae static const struct dev_pm_ops exynos_dsi_pm_ops = { 1868ba6e4779SInki Dae SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 18697e915746SMarek Szyprowski SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 18707e915746SMarek Szyprowski pm_runtime_force_resume) 1871ba6e4779SInki Dae }; 1872ba6e4779SInki Dae 1873*7e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos3250_dsi_pdata = { 1874*7e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS3250, 1875*7e9f0d32SJagan Teki }; 1876*7e9f0d32SJagan Teki 1877*7e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos4210_dsi_pdata = { 1878*7e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS4210, 1879*7e9f0d32SJagan Teki }; 1880*7e9f0d32SJagan Teki 1881*7e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos5410_dsi_pdata = { 1882*7e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS5410, 1883*7e9f0d32SJagan Teki }; 1884*7e9f0d32SJagan Teki 1885*7e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos5422_dsi_pdata = { 1886*7e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS5422, 1887*7e9f0d32SJagan Teki }; 1888*7e9f0d32SJagan Teki 1889*7e9f0d32SJagan Teki static const struct exynos_dsi_plat_data exynos5433_dsi_pdata = { 1890*7e9f0d32SJagan Teki .hw_type = DSIM_TYPE_EXYNOS5433, 1891*7e9f0d32SJagan Teki }; 1892*7e9f0d32SJagan Teki 1893*7e9f0d32SJagan Teki static const struct of_device_id exynos_dsi_of_match[] = { 1894*7e9f0d32SJagan Teki { 1895*7e9f0d32SJagan Teki .compatible = "samsung,exynos3250-mipi-dsi", 1896*7e9f0d32SJagan Teki .data = &exynos3250_dsi_pdata, 1897*7e9f0d32SJagan Teki }, 1898*7e9f0d32SJagan Teki { 1899*7e9f0d32SJagan Teki .compatible = "samsung,exynos4210-mipi-dsi", 1900*7e9f0d32SJagan Teki .data = &exynos4210_dsi_pdata, 1901*7e9f0d32SJagan Teki }, 1902*7e9f0d32SJagan Teki { 1903*7e9f0d32SJagan Teki .compatible = "samsung,exynos5410-mipi-dsi", 1904*7e9f0d32SJagan Teki .data = &exynos5410_dsi_pdata, 1905*7e9f0d32SJagan Teki }, 1906*7e9f0d32SJagan Teki { 1907*7e9f0d32SJagan Teki .compatible = "samsung,exynos5422-mipi-dsi", 1908*7e9f0d32SJagan Teki .data = &exynos5422_dsi_pdata, 1909*7e9f0d32SJagan Teki }, 1910*7e9f0d32SJagan Teki { 1911*7e9f0d32SJagan Teki .compatible = "samsung,exynos5433-mipi-dsi", 1912*7e9f0d32SJagan Teki .data = &exynos5433_dsi_pdata, 1913*7e9f0d32SJagan Teki }, 1914*7e9f0d32SJagan Teki { /* sentinel. */ } 1915*7e9f0d32SJagan Teki }; 1916*7e9f0d32SJagan Teki MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 1917*7e9f0d32SJagan Teki 19187eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 19197eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 19207eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 19217eb8f069SAndrzej Hajda .driver = { 19227eb8f069SAndrzej Hajda .name = "exynos-dsi", 19237eb8f069SAndrzej Hajda .owner = THIS_MODULE, 1924ba6e4779SInki Dae .pm = &exynos_dsi_pm_ops, 19257eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 19267eb8f069SAndrzej Hajda }, 19277eb8f069SAndrzej Hajda }; 19287eb8f069SAndrzej Hajda 19297eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 19307eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 19317eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 19327eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 1933