17eb8f069SAndrzej Hajda /* 27eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 37eb8f069SAndrzej Hajda * 47eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 57eb8f069SAndrzej Hajda * 67eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 77eb8f069SAndrzej Hajda * 87eb8f069SAndrzej Hajda * This program is free software; you can redistribute it and/or modify 97eb8f069SAndrzej Hajda * it under the terms of the GNU General Public License version 2 as 107eb8f069SAndrzej Hajda * published by the Free Software Foundation. 117eb8f069SAndrzej Hajda */ 127eb8f069SAndrzej Hajda 136c81e96dSAndrzej Hajda #include <asm/unaligned.h> 146c81e96dSAndrzej Hajda 157eb8f069SAndrzej Hajda #include <drm/drmP.h> 167eb8f069SAndrzej Hajda #include <drm/drm_crtc_helper.h> 177eb8f069SAndrzej Hajda #include <drm/drm_mipi_dsi.h> 187eb8f069SAndrzej Hajda #include <drm/drm_panel.h> 194ea9526bSGustavo Padovan #include <drm/drm_atomic_helper.h> 207eb8f069SAndrzej Hajda 217eb8f069SAndrzej Hajda #include <linux/clk.h> 22e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 237eb8f069SAndrzej Hajda #include <linux/irq.h> 249a320415SYoungJun Cho #include <linux/of_device.h> 25e17ddeccSYoungJun Cho #include <linux/of_gpio.h> 26f5f3b9baSHyungwon Hwang #include <linux/of_graph.h> 277eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 287eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 29f37cd5e8SInki Dae #include <linux/component.h> 307eb8f069SAndrzej Hajda 317eb8f069SAndrzej Hajda #include <video/mipi_display.h> 327eb8f069SAndrzej Hajda #include <video/videomode.h> 337eb8f069SAndrzej Hajda 34e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 357eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 367eb8f069SAndrzej Hajda 377eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 387eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 397eb8f069SAndrzej Hajda 407eb8f069SAndrzej Hajda /* DSIM_STATUS */ 417eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 427eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 437eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 447eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 457eb8f069SAndrzej Hajda 467eb8f069SAndrzej Hajda /* DSIM_SWRST */ 477eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 487eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 497eb8f069SAndrzej Hajda 507eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 517eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 527eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 537eb8f069SAndrzej Hajda 547eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 557eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 567eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 587eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 597eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 617eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 627eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 637eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 647eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 657eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 667eb8f069SAndrzej Hajda 677eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 687eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 697eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 707eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 717eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 757eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 767eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 777eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 787eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 797eb8f069SAndrzej Hajda #define DSIM_HSA_MODE (1 << 20) 807eb8f069SAndrzej Hajda #define DSIM_HBP_MODE (1 << 21) 817eb8f069SAndrzej Hajda #define DSIM_HFP_MODE (1 << 22) 827eb8f069SAndrzej Hajda #define DSIM_HSE_MODE (1 << 23) 837eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 847eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 857eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 867eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 877eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 887eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 896bdc92eeSKrzysztof Kozlowski /* This flag is valid only for exynos3250/3472/5260/5430 */ 9078d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 917eb8f069SAndrzej Hajda 927eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 937eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 947eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 957eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 967eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 977eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 987eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 997eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 1007eb8f069SAndrzej Hajda 1017eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 1027eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 103d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 104d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1057eb8f069SAndrzej Hajda 1067eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1077eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1087eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1097eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1107eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1117eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1127eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1137eb8f069SAndrzej Hajda 1147eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1157eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1167eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1177eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1187eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1197eb8f069SAndrzej Hajda 1207eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1217eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1227eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1237eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1247eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1257eb8f069SAndrzej Hajda 1267eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1277eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1287eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1297eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1307eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1317eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1327eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1337eb8f069SAndrzej Hajda 1347eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1357eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1367eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1377eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 138e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 1397eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1407eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1417eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1427eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1437eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1447eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1457eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1467eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1477eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1487eb8f069SAndrzej Hajda 1497eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1507eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1517eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1527eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1537eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1547eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1557eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1567eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1577eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1587eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1597eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1607eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1617eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1627eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1637eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1647eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1657eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1667eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1677eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1687eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1697eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1707eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1717eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1727eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1737eb8f069SAndrzej Hajda 1747eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1757eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1767eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1777eb8f069SAndrzej Hajda 1787eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1797eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1807eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 1817eb8f069SAndrzej Hajda #define DSIM_PLL_P(x) ((x) << 13) 1827eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1837eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 1847eb8f069SAndrzej Hajda 1859a320415SYoungJun Cho /* DSIM_PHYCTRL */ 1869a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 187e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 188e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 1899a320415SYoungJun Cho 1909a320415SYoungJun Cho /* DSIM_PHYTIMING */ 1919a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 1929a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 1939a320415SYoungJun Cho 1949a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 1959a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 1969a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 1979a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 1989a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 1999a320415SYoungJun Cho 2009a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 2019a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 2029a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 2039a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 2049a320415SYoungJun Cho 2057eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2067eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2077eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2087eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2097eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2107eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2117eb8f069SAndrzej Hajda 21226269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 21326269af9SHyungwon Hwang 214e6f988a4SHyungwon Hwang static char *clk_names[5] = { "bus_clk", "sclk_mipi", 215e6f988a4SHyungwon Hwang "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 216e6f988a4SHyungwon Hwang "sclk_rgb_vclk_to_dsim0" }; 2170ff03fd1SHyungwon Hwang 2187eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2197eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2207eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2217eb8f069SAndrzej Hajda }; 2227eb8f069SAndrzej Hajda 2237eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2247eb8f069SAndrzej Hajda struct list_head list; 2257eb8f069SAndrzej Hajda struct completion completed; 2267eb8f069SAndrzej Hajda int result; 2276c81e96dSAndrzej Hajda struct mipi_dsi_packet packet; 2287eb8f069SAndrzej Hajda u16 flags; 2297eb8f069SAndrzej Hajda u16 tx_done; 2307eb8f069SAndrzej Hajda 2317eb8f069SAndrzej Hajda u8 *rx_payload; 2327eb8f069SAndrzej Hajda u16 rx_len; 2337eb8f069SAndrzej Hajda u16 rx_done; 2347eb8f069SAndrzej Hajda }; 2357eb8f069SAndrzej Hajda 2367eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2377eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2387eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2390e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2407eb8f069SAndrzej Hajda 2419a320415SYoungJun Cho struct exynos_dsi_driver_data { 242b115361eSAndrzej Hajda const unsigned int *reg_ofs; 2439a320415SYoungJun Cho unsigned int plltmr_reg; 2449a320415SYoungJun Cho unsigned int has_freqband:1; 24578d3a8c6SInki Dae unsigned int has_clklane_stop:1; 246d668e8bfSHyungwon Hwang unsigned int num_clks; 247d668e8bfSHyungwon Hwang unsigned int max_freq; 248d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 249d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 250b115361eSAndrzej Hajda const unsigned int *reg_values; 2519a320415SYoungJun Cho }; 2529a320415SYoungJun Cho 2537eb8f069SAndrzej Hajda struct exynos_dsi { 2542b8376c8SGustavo Padovan struct drm_encoder encoder; 2557eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 2567eb8f069SAndrzej Hajda struct drm_connector connector; 2577eb8f069SAndrzej Hajda struct device_node *panel_node; 2587eb8f069SAndrzej Hajda struct drm_panel *panel; 2597eb8f069SAndrzej Hajda struct device *dev; 2607eb8f069SAndrzej Hajda 2617eb8f069SAndrzej Hajda void __iomem *reg_base; 2627eb8f069SAndrzej Hajda struct phy *phy; 2630ff03fd1SHyungwon Hwang struct clk **clks; 2647eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2657eb8f069SAndrzej Hajda int irq; 266e17ddeccSYoungJun Cho int te_gpio; 2677eb8f069SAndrzej Hajda 2687eb8f069SAndrzej Hajda u32 pll_clk_rate; 2697eb8f069SAndrzej Hajda u32 burst_clk_rate; 2707eb8f069SAndrzej Hajda u32 esc_clk_rate; 2717eb8f069SAndrzej Hajda u32 lanes; 2727eb8f069SAndrzej Hajda u32 mode_flags; 2737eb8f069SAndrzej Hajda u32 format; 2747eb8f069SAndrzej Hajda struct videomode vm; 2757eb8f069SAndrzej Hajda 2767eb8f069SAndrzej Hajda int state; 2777eb8f069SAndrzej Hajda struct drm_property *brightness; 2787eb8f069SAndrzej Hajda struct completion completed; 2797eb8f069SAndrzej Hajda 2807eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 2817eb8f069SAndrzej Hajda struct list_head transfer_list; 2829a320415SYoungJun Cho 2832154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data; 284f5f3b9baSHyungwon Hwang struct device_node *bridge_node; 2857eb8f069SAndrzej Hajda }; 2867eb8f069SAndrzej Hajda 2877eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 2887eb8f069SAndrzej Hajda #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 2897eb8f069SAndrzej Hajda 2902b8376c8SGustavo Padovan static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) 2915cd5db80SAndrzej Hajda { 292cf67cc9aSGustavo Padovan return container_of(e, struct exynos_dsi, encoder); 2935cd5db80SAndrzej Hajda } 2945cd5db80SAndrzej Hajda 295d668e8bfSHyungwon Hwang enum reg_idx { 296d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 297d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 298d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 299d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 300d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 301d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 302d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 303d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 304d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 305d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 306d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 307d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 308d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 309d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 310d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 311d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 312d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 313d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 314d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 315d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 316d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 317d668e8bfSHyungwon Hwang NUM_REGS 318d668e8bfSHyungwon Hwang }; 319bb32e408SAndrzej Hajda 320bb32e408SAndrzej Hajda static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, 321bb32e408SAndrzej Hajda u32 val) 322bb32e408SAndrzej Hajda { 3236c81e96dSAndrzej Hajda 324bb32e408SAndrzej Hajda writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 325bb32e408SAndrzej Hajda } 326bb32e408SAndrzej Hajda 327bb32e408SAndrzej Hajda static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) 328bb32e408SAndrzej Hajda { 329bb32e408SAndrzej Hajda return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 330bb32e408SAndrzej Hajda } 331bb32e408SAndrzej Hajda 332b115361eSAndrzej Hajda static const unsigned int exynos_reg_ofs[] = { 333d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 334d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 335d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 336d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 337d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 338d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 339d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 340d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 341d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 342d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 343d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 344d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 345d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 346d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 347d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 348d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 349d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 350d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 351d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 352d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 353d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 354d668e8bfSHyungwon Hwang }; 355d668e8bfSHyungwon Hwang 356b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_ofs[] = { 357e6f988a4SHyungwon Hwang [DSIM_STATUS_REG] = 0x04, 358e6f988a4SHyungwon Hwang [DSIM_SWRST_REG] = 0x0C, 359e6f988a4SHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x10, 360e6f988a4SHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x14, 361e6f988a4SHyungwon Hwang [DSIM_CONFIG_REG] = 0x18, 362e6f988a4SHyungwon Hwang [DSIM_ESCMODE_REG] = 0x1C, 363e6f988a4SHyungwon Hwang [DSIM_MDRESOL_REG] = 0x20, 364e6f988a4SHyungwon Hwang [DSIM_MVPORCH_REG] = 0x24, 365e6f988a4SHyungwon Hwang [DSIM_MHPORCH_REG] = 0x28, 366e6f988a4SHyungwon Hwang [DSIM_MSYNC_REG] = 0x2C, 367e6f988a4SHyungwon Hwang [DSIM_INTSRC_REG] = 0x34, 368e6f988a4SHyungwon Hwang [DSIM_INTMSK_REG] = 0x38, 369e6f988a4SHyungwon Hwang [DSIM_PKTHDR_REG] = 0x3C, 370e6f988a4SHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x40, 371e6f988a4SHyungwon Hwang [DSIM_RXFIFO_REG] = 0x44, 372e6f988a4SHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x4C, 373e6f988a4SHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x94, 374e6f988a4SHyungwon Hwang [DSIM_PHYCTRL_REG] = 0xA4, 375e6f988a4SHyungwon Hwang [DSIM_PHYTIMING_REG] = 0xB4, 376e6f988a4SHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0xB8, 377e6f988a4SHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0xBC, 378e6f988a4SHyungwon Hwang }; 379e6f988a4SHyungwon Hwang 380d668e8bfSHyungwon Hwang enum reg_value_idx { 381d668e8bfSHyungwon Hwang RESET_TYPE, 382d668e8bfSHyungwon Hwang PLL_TIMER, 383d668e8bfSHyungwon Hwang STOP_STATE_CNT, 384d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 385d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 386d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 387d668e8bfSHyungwon Hwang PHYTIMING_LPX, 388d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 389d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 390d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 391d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 392d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 393d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 394d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 395d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 396d668e8bfSHyungwon Hwang }; 397d668e8bfSHyungwon Hwang 398b115361eSAndrzej Hajda static const unsigned int reg_values[] = { 399d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 400d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 401d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 402d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 403d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 404d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 405d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 406d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 407d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 408d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 409d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 410d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 411d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 412d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 413d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 414d668e8bfSHyungwon Hwang }; 415d668e8bfSHyungwon Hwang 416b115361eSAndrzej Hajda static const unsigned int exynos5422_reg_values[] = { 417fdc2e108SChanho Park [RESET_TYPE] = DSIM_SWRST, 418fdc2e108SChanho Park [PLL_TIMER] = 500, 419fdc2e108SChanho Park [STOP_STATE_CNT] = 0xf, 420fdc2e108SChanho Park [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 421fdc2e108SChanho Park [PHYCTRL_VREG_LP] = 0, 422fdc2e108SChanho Park [PHYCTRL_SLEW_UP] = 0, 423fdc2e108SChanho Park [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 424fdc2e108SChanho Park [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 425fdc2e108SChanho Park [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 426fdc2e108SChanho Park [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 427fdc2e108SChanho Park [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 428fdc2e108SChanho Park [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 429fdc2e108SChanho Park [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 430fdc2e108SChanho Park [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 431fdc2e108SChanho Park [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 432fdc2e108SChanho Park }; 433fdc2e108SChanho Park 434b115361eSAndrzej Hajda static const unsigned int exynos5433_reg_values[] = { 435e6f988a4SHyungwon Hwang [RESET_TYPE] = DSIM_FUNCRST, 436e6f988a4SHyungwon Hwang [PLL_TIMER] = 22200, 437e6f988a4SHyungwon Hwang [STOP_STATE_CNT] = 0xa, 438e6f988a4SHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 439e6f988a4SHyungwon Hwang [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 440e6f988a4SHyungwon Hwang [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 441e6f988a4SHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 442e6f988a4SHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 443e6f988a4SHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 444e6f988a4SHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 445e6f988a4SHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 446e6f988a4SHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 447e6f988a4SHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 448e6f988a4SHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 449e6f988a4SHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 450e6f988a4SHyungwon Hwang }; 451e6f988a4SHyungwon Hwang 452b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 453d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 454473462a1SInki Dae .plltmr_reg = 0x50, 455473462a1SInki Dae .has_freqband = 1, 456473462a1SInki Dae .has_clklane_stop = 1, 457d668e8bfSHyungwon Hwang .num_clks = 2, 458d668e8bfSHyungwon Hwang .max_freq = 1000, 459d668e8bfSHyungwon Hwang .wait_for_reset = 1, 460d668e8bfSHyungwon Hwang .num_bits_resol = 11, 461d668e8bfSHyungwon Hwang .reg_values = reg_values, 462473462a1SInki Dae }; 463473462a1SInki Dae 464b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 465d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4669a320415SYoungJun Cho .plltmr_reg = 0x50, 4679a320415SYoungJun Cho .has_freqband = 1, 46878d3a8c6SInki Dae .has_clklane_stop = 1, 469d668e8bfSHyungwon Hwang .num_clks = 2, 470d668e8bfSHyungwon Hwang .max_freq = 1000, 471d668e8bfSHyungwon Hwang .wait_for_reset = 1, 472d668e8bfSHyungwon Hwang .num_bits_resol = 11, 473d668e8bfSHyungwon Hwang .reg_values = reg_values, 4749a320415SYoungJun Cho }; 4759a320415SYoungJun Cho 476b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 477d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4789a320415SYoungJun Cho .plltmr_reg = 0x58, 479d668e8bfSHyungwon Hwang .num_clks = 2, 480d668e8bfSHyungwon Hwang .max_freq = 1000, 481d668e8bfSHyungwon Hwang .wait_for_reset = 1, 482d668e8bfSHyungwon Hwang .num_bits_resol = 11, 483d668e8bfSHyungwon Hwang .reg_values = reg_values, 4849a320415SYoungJun Cho }; 4859a320415SYoungJun Cho 486b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 487e6f988a4SHyungwon Hwang .reg_ofs = exynos5433_reg_ofs, 488e6f988a4SHyungwon Hwang .plltmr_reg = 0xa0, 489e6f988a4SHyungwon Hwang .has_clklane_stop = 1, 490e6f988a4SHyungwon Hwang .num_clks = 5, 491e6f988a4SHyungwon Hwang .max_freq = 1500, 492e6f988a4SHyungwon Hwang .wait_for_reset = 0, 493e6f988a4SHyungwon Hwang .num_bits_resol = 12, 494e6f988a4SHyungwon Hwang .reg_values = exynos5433_reg_values, 495e6f988a4SHyungwon Hwang }; 496e6f988a4SHyungwon Hwang 497b115361eSAndrzej Hajda static const struct exynos_dsi_driver_data exynos5422_dsi_driver_data = { 498fdc2e108SChanho Park .reg_ofs = exynos5433_reg_ofs, 499fdc2e108SChanho Park .plltmr_reg = 0xa0, 500fdc2e108SChanho Park .has_clklane_stop = 1, 501fdc2e108SChanho Park .num_clks = 2, 502fdc2e108SChanho Park .max_freq = 1500, 503fdc2e108SChanho Park .wait_for_reset = 1, 504fdc2e108SChanho Park .num_bits_resol = 12, 505fdc2e108SChanho Park .reg_values = exynos5422_reg_values, 506fdc2e108SChanho Park }; 507fdc2e108SChanho Park 508b115361eSAndrzej Hajda static const struct of_device_id exynos_dsi_of_match[] = { 509473462a1SInki Dae { .compatible = "samsung,exynos3250-mipi-dsi", 510473462a1SInki Dae .data = &exynos3_dsi_driver_data }, 5119a320415SYoungJun Cho { .compatible = "samsung,exynos4210-mipi-dsi", 5129a320415SYoungJun Cho .data = &exynos4_dsi_driver_data }, 5139a320415SYoungJun Cho { .compatible = "samsung,exynos5410-mipi-dsi", 5149a320415SYoungJun Cho .data = &exynos5_dsi_driver_data }, 515fdc2e108SChanho Park { .compatible = "samsung,exynos5422-mipi-dsi", 516fdc2e108SChanho Park .data = &exynos5422_dsi_driver_data }, 517e6f988a4SHyungwon Hwang { .compatible = "samsung,exynos5433-mipi-dsi", 518e6f988a4SHyungwon Hwang .data = &exynos5433_dsi_driver_data }, 5199a320415SYoungJun Cho { } 5209a320415SYoungJun Cho }; 5219a320415SYoungJun Cho 5227eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 5237eb8f069SAndrzej Hajda { 5247eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 5257eb8f069SAndrzej Hajda return; 5267eb8f069SAndrzej Hajda 5277eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 5287eb8f069SAndrzej Hajda } 5297eb8f069SAndrzej Hajda 5307eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 5317eb8f069SAndrzej Hajda { 532bb32e408SAndrzej Hajda u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 533ba12ac2bSHyungwon Hwang 5347eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 535bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_SWRST_REG, reset_val); 5367eb8f069SAndrzej Hajda } 5377eb8f069SAndrzej Hajda 5387eb8f069SAndrzej Hajda #ifndef MHZ 5397eb8f069SAndrzej Hajda #define MHZ (1000*1000) 5407eb8f069SAndrzej Hajda #endif 5417eb8f069SAndrzej Hajda 5427eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 5437eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 5447eb8f069SAndrzej Hajda { 5452154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5467eb8f069SAndrzej Hajda unsigned long best_freq = 0; 5477eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 5487eb8f069SAndrzej Hajda u8 p_min, p_max; 5497eb8f069SAndrzej Hajda u8 _p, uninitialized_var(best_p); 5507eb8f069SAndrzej Hajda u16 _m, uninitialized_var(best_m); 5517eb8f069SAndrzej Hajda u8 _s, uninitialized_var(best_s); 5527eb8f069SAndrzej Hajda 5537eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 5547eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 5557eb8f069SAndrzej Hajda 5567eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 5577eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 5587eb8f069SAndrzej Hajda u64 tmp; 5597eb8f069SAndrzej Hajda u32 delta; 5607eb8f069SAndrzej Hajda 5617eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 5627eb8f069SAndrzej Hajda do_div(tmp, fin); 5637eb8f069SAndrzej Hajda _m = tmp; 5647eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 5657eb8f069SAndrzej Hajda continue; 5667eb8f069SAndrzej Hajda 5677eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5687eb8f069SAndrzej Hajda do_div(tmp, _p); 569d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 570d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 5717eb8f069SAndrzej Hajda continue; 5727eb8f069SAndrzej Hajda 5737eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5747eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 5757eb8f069SAndrzej Hajda 5767eb8f069SAndrzej Hajda delta = abs(fout - tmp); 5777eb8f069SAndrzej Hajda if (delta < min_delta) { 5787eb8f069SAndrzej Hajda best_p = _p; 5797eb8f069SAndrzej Hajda best_m = _m; 5807eb8f069SAndrzej Hajda best_s = _s; 5817eb8f069SAndrzej Hajda min_delta = delta; 5827eb8f069SAndrzej Hajda best_freq = tmp; 5837eb8f069SAndrzej Hajda } 5847eb8f069SAndrzej Hajda } 5857eb8f069SAndrzej Hajda } 5867eb8f069SAndrzej Hajda 5877eb8f069SAndrzej Hajda if (best_freq) { 5887eb8f069SAndrzej Hajda *p = best_p; 5897eb8f069SAndrzej Hajda *m = best_m; 5907eb8f069SAndrzej Hajda *s = best_s; 5917eb8f069SAndrzej Hajda } 5927eb8f069SAndrzej Hajda 5937eb8f069SAndrzej Hajda return best_freq; 5947eb8f069SAndrzej Hajda } 5957eb8f069SAndrzej Hajda 5967eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 5977eb8f069SAndrzej Hajda unsigned long freq) 5987eb8f069SAndrzej Hajda { 5992154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 6007eb8f069SAndrzej Hajda unsigned long fin, fout; 6019a320415SYoungJun Cho int timeout; 6027eb8f069SAndrzej Hajda u8 p, s; 6037eb8f069SAndrzej Hajda u16 m; 6047eb8f069SAndrzej Hajda u32 reg; 6057eb8f069SAndrzej Hajda 60626269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 6077eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 6087eb8f069SAndrzej Hajda if (!fout) { 6097eb8f069SAndrzej Hajda dev_err(dsi->dev, 6107eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 6118525b5ecSYoungJun Cho return 0; 6127eb8f069SAndrzej Hajda } 6139a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 6149a320415SYoungJun Cho 615d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 616d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 6179a320415SYoungJun Cho 6189a320415SYoungJun Cho reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 6199a320415SYoungJun Cho 6209a320415SYoungJun Cho if (driver_data->has_freqband) { 6219a320415SYoungJun Cho static const unsigned long freq_bands[] = { 6229a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 6239a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 6249a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 6259a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 6269a320415SYoungJun Cho }; 6279a320415SYoungJun Cho int band; 6287eb8f069SAndrzej Hajda 6297eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 6307eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 6317eb8f069SAndrzej Hajda break; 6327eb8f069SAndrzej Hajda 6339a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 6347eb8f069SAndrzej Hajda 6359a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 6369a320415SYoungJun Cho } 6377eb8f069SAndrzej Hajda 638bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 6397eb8f069SAndrzej Hajda 6407eb8f069SAndrzej Hajda timeout = 1000; 6417eb8f069SAndrzej Hajda do { 6427eb8f069SAndrzej Hajda if (timeout-- == 0) { 6437eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 6448525b5ecSYoungJun Cho return 0; 6457eb8f069SAndrzej Hajda } 646bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 6477eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 6487eb8f069SAndrzej Hajda 6497eb8f069SAndrzej Hajda return fout; 6507eb8f069SAndrzej Hajda } 6517eb8f069SAndrzej Hajda 6527eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 6537eb8f069SAndrzej Hajda { 6547eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 6557eb8f069SAndrzej Hajda unsigned long esc_div; 6567eb8f069SAndrzej Hajda u32 reg; 6577eb8f069SAndrzej Hajda 6587eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 6597eb8f069SAndrzej Hajda if (!hs_clk) { 6607eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 6617eb8f069SAndrzej Hajda return -EFAULT; 6627eb8f069SAndrzej Hajda } 6637eb8f069SAndrzej Hajda 6647eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 6657eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 6667eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6677eb8f069SAndrzej Hajda 6687eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 6697eb8f069SAndrzej Hajda ++esc_div; 6707eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6717eb8f069SAndrzej Hajda } 6727eb8f069SAndrzej Hajda 6737eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 6747eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 6757eb8f069SAndrzej Hajda 676bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 6777eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 6787eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 6797eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 6807eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 6817eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 6827eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 6837eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 6847eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 6857eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 686bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 6877eb8f069SAndrzej Hajda 6887eb8f069SAndrzej Hajda return 0; 6897eb8f069SAndrzej Hajda } 6907eb8f069SAndrzej Hajda 6919a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 6929a320415SYoungJun Cho { 6932154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 694b115361eSAndrzej Hajda const unsigned int *reg_values = driver_data->reg_values; 6959a320415SYoungJun Cho u32 reg; 6969a320415SYoungJun Cho 6979a320415SYoungJun Cho if (driver_data->has_freqband) 6989a320415SYoungJun Cho return; 6999a320415SYoungJun Cho 7009a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 701d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 702d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 703bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYCTRL_REG, reg); 7049a320415SYoungJun Cho 7059a320415SYoungJun Cho /* 7069a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 7079a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 7089a320415SYoungJun Cho * burst 7099a320415SYoungJun Cho */ 710d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 711bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING_REG, reg); 7129a320415SYoungJun Cho 7139a320415SYoungJun Cho /* 7149a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 7159a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7169a320415SYoungJun Cho * HS transmission 7179a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 7189a320415SYoungJun Cho * transmitting the Clock. 7199a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 7209a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 7219a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 7229a320415SYoungJun Cho * the beginning of T CLK-TRAIL 7239a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 7249a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 7259a320415SYoungJun Cho */ 726d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 727d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 728d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 729d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 730d668e8bfSHyungwon Hwang 731bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING1_REG, reg); 7329a320415SYoungJun Cho 7339a320415SYoungJun Cho /* 7349a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 7359a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7369a320415SYoungJun Cho * HS transmission 7379a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 7389a320415SYoungJun Cho * transmitting the Sync sequence. 7399a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 7409a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 7419a320415SYoungJun Cho */ 742d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 743d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 744bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PHYTIMING2_REG, reg); 7459a320415SYoungJun Cho } 7469a320415SYoungJun Cho 7477eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 7487eb8f069SAndrzej Hajda { 7497eb8f069SAndrzej Hajda u32 reg; 7507eb8f069SAndrzej Hajda 751bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_CLKCTRL_REG); 7527eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 7537eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 754bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CLKCTRL_REG, reg); 7557eb8f069SAndrzej Hajda 756bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_PLLCTRL_REG); 7577eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 758bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PLLCTRL_REG, reg); 7597eb8f069SAndrzej Hajda } 7607eb8f069SAndrzej Hajda 761e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 762e6f988a4SHyungwon Hwang { 763bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_CONFIG_REG); 764e6f988a4SHyungwon Hwang reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 765e6f988a4SHyungwon Hwang DSIM_LANE_EN(lane)); 766bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 767e6f988a4SHyungwon Hwang } 768e6f988a4SHyungwon Hwang 7697eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 7707eb8f069SAndrzej Hajda { 7712154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 7727eb8f069SAndrzej Hajda int timeout; 7737eb8f069SAndrzej Hajda u32 reg; 7747eb8f069SAndrzej Hajda u32 lanes_mask; 7757eb8f069SAndrzej Hajda 7767eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 777bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 7787eb8f069SAndrzej Hajda reg &= ~0x1f; 779bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 7807eb8f069SAndrzej Hajda 7817eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7827eb8f069SAndrzej Hajda 7837eb8f069SAndrzej Hajda reg |= 0x1f; 784bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_FIFOCTRL_REG, reg); 7857eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7867eb8f069SAndrzej Hajda 7877eb8f069SAndrzej Hajda /* DSI configuration */ 7887eb8f069SAndrzej Hajda reg = 0; 7897eb8f069SAndrzej Hajda 7902f36e33aSYoungJun Cho /* 7912f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 7922f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 7932f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 7942f36e33aSYoungJun Cho */ 7957eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 7967eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 7977eb8f069SAndrzej Hajda 7982f36e33aSYoungJun Cho /* 7992f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 8002f36e33aSYoungJun Cho * command mode. 8012f36e33aSYoungJun Cho */ 8027eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 8037eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 8047eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 8057eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 8067eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 8077eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 8087eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 8097eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 8107eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 8117eb8f069SAndrzej Hajda reg |= DSIM_HSE_MODE; 8127eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 8137eb8f069SAndrzej Hajda reg |= DSIM_HFP_MODE; 8147eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 8157eb8f069SAndrzej Hajda reg |= DSIM_HBP_MODE; 8167eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 8177eb8f069SAndrzej Hajda reg |= DSIM_HSA_MODE; 8187eb8f069SAndrzej Hajda } 8197eb8f069SAndrzej Hajda 8202f36e33aSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 8212f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 8222f36e33aSYoungJun Cho 8237eb8f069SAndrzej Hajda switch (dsi->format) { 8247eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 8257eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 8267eb8f069SAndrzej Hajda break; 8277eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 8287eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 8297eb8f069SAndrzej Hajda break; 8307eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 8317eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 8327eb8f069SAndrzej Hajda break; 8337eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 8347eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 8357eb8f069SAndrzej Hajda break; 8367eb8f069SAndrzej Hajda default: 8377eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 8387eb8f069SAndrzej Hajda return -EINVAL; 8397eb8f069SAndrzej Hajda } 8407eb8f069SAndrzej Hajda 84178d3a8c6SInki Dae /* 84278d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 84378d3a8c6SInki Dae * host controller supports 84478d3a8c6SInki Dae * 84578d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 84678d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 84778d3a8c6SInki Dae * power consumption. 84878d3a8c6SInki Dae */ 84978d3a8c6SInki Dae if (driver_data->has_clklane_stop && 85078d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 85178d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 85278d3a8c6SInki Dae } 853bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_CONFIG_REG, reg); 854e6f988a4SHyungwon Hwang 855e6f988a4SHyungwon Hwang lanes_mask = BIT(dsi->lanes) - 1; 856e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, lanes_mask); 85778d3a8c6SInki Dae 8587eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 8597eb8f069SAndrzej Hajda timeout = 100; 8607eb8f069SAndrzej Hajda do { 8617eb8f069SAndrzej Hajda if (timeout-- == 0) { 8627eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 8637eb8f069SAndrzej Hajda return -EFAULT; 8647eb8f069SAndrzej Hajda } 8657eb8f069SAndrzej Hajda 866bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_STATUS_REG); 8677eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 8687eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 8697eb8f069SAndrzej Hajda continue; 8707eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 8717eb8f069SAndrzej Hajda 872bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 8737eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 874d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 875bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, reg); 8767eb8f069SAndrzej Hajda 8777eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 878bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_TIMEOUT_REG, reg); 8797eb8f069SAndrzej Hajda 8807eb8f069SAndrzej Hajda return 0; 8817eb8f069SAndrzej Hajda } 8827eb8f069SAndrzej Hajda 8837eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 8847eb8f069SAndrzej Hajda { 8857eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 886d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 8877eb8f069SAndrzej Hajda u32 reg; 8887eb8f069SAndrzej Hajda 8897eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8907eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 8917eb8f069SAndrzej Hajda | DSIM_STABLE_VFP(vm->vfront_porch) 8927eb8f069SAndrzej Hajda | DSIM_MAIN_VBP(vm->vback_porch); 893bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MVPORCH_REG, reg); 8947eb8f069SAndrzej Hajda 8957eb8f069SAndrzej Hajda reg = DSIM_MAIN_HFP(vm->hfront_porch) 8967eb8f069SAndrzej Hajda | DSIM_MAIN_HBP(vm->hback_porch); 897bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MHPORCH_REG, reg); 8987eb8f069SAndrzej Hajda 8997eb8f069SAndrzej Hajda reg = DSIM_MAIN_VSA(vm->vsync_len) 9007eb8f069SAndrzej Hajda | DSIM_MAIN_HSA(vm->hsync_len); 901bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MSYNC_REG, reg); 9027eb8f069SAndrzej Hajda } 903d668e8bfSHyungwon Hwang reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | 904d668e8bfSHyungwon Hwang DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); 9057eb8f069SAndrzej Hajda 906bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9077eb8f069SAndrzej Hajda 9087eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 9097eb8f069SAndrzej Hajda } 9107eb8f069SAndrzej Hajda 9117eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 9127eb8f069SAndrzej Hajda { 9137eb8f069SAndrzej Hajda u32 reg; 9147eb8f069SAndrzej Hajda 915bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_MDRESOL_REG); 9167eb8f069SAndrzej Hajda if (enable) 9177eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 9187eb8f069SAndrzej Hajda else 9197eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 920bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_MDRESOL_REG, reg); 9217eb8f069SAndrzej Hajda } 9227eb8f069SAndrzej Hajda 9237eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 9247eb8f069SAndrzej Hajda { 9257eb8f069SAndrzej Hajda int timeout = 2000; 9267eb8f069SAndrzej Hajda 9277eb8f069SAndrzej Hajda do { 928bb32e408SAndrzej Hajda u32 reg = exynos_dsi_read(dsi, DSIM_FIFOCTRL_REG); 9297eb8f069SAndrzej Hajda 9307eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 9317eb8f069SAndrzej Hajda return 0; 9327eb8f069SAndrzej Hajda 9337eb8f069SAndrzej Hajda if (!cond_resched()) 9347eb8f069SAndrzej Hajda usleep_range(950, 1050); 9357eb8f069SAndrzej Hajda } while (--timeout); 9367eb8f069SAndrzej Hajda 9377eb8f069SAndrzej Hajda return -ETIMEDOUT; 9387eb8f069SAndrzej Hajda } 9397eb8f069SAndrzej Hajda 9407eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 9417eb8f069SAndrzej Hajda { 942bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9437eb8f069SAndrzej Hajda 9447eb8f069SAndrzej Hajda if (lpm) 9457eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 9467eb8f069SAndrzej Hajda else 9477eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 9487eb8f069SAndrzej Hajda 949bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9507eb8f069SAndrzej Hajda } 9517eb8f069SAndrzej Hajda 9527eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 9537eb8f069SAndrzej Hajda { 954bb32e408SAndrzej Hajda u32 v = exynos_dsi_read(dsi, DSIM_ESCMODE_REG); 9557eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 956bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_ESCMODE_REG, v); 9577eb8f069SAndrzej Hajda } 9587eb8f069SAndrzej Hajda 9597eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 9607eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9617eb8f069SAndrzej Hajda { 9627eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9636c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 9646c81e96dSAndrzej Hajda const u8 *payload = pkt->payload + xfer->tx_done; 9656c81e96dSAndrzej Hajda u16 length = pkt->payload_length - xfer->tx_done; 9667eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 9677eb8f069SAndrzej Hajda u32 reg; 9687eb8f069SAndrzej Hajda 9699cdf0ed2SKrzysztof Kozlowski dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 9706c81e96dSAndrzej Hajda xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 9717eb8f069SAndrzej Hajda 9727eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 9737eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 9747eb8f069SAndrzej Hajda 9757eb8f069SAndrzej Hajda xfer->tx_done += length; 9767eb8f069SAndrzej Hajda 9777eb8f069SAndrzej Hajda /* Send payload */ 9787eb8f069SAndrzej Hajda while (length >= 4) { 9796c81e96dSAndrzej Hajda reg = get_unaligned_le32(payload); 980bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 9817eb8f069SAndrzej Hajda payload += 4; 9827eb8f069SAndrzej Hajda length -= 4; 9837eb8f069SAndrzej Hajda } 9847eb8f069SAndrzej Hajda 9857eb8f069SAndrzej Hajda reg = 0; 9867eb8f069SAndrzej Hajda switch (length) { 9877eb8f069SAndrzej Hajda case 3: 9887eb8f069SAndrzej Hajda reg |= payload[2] << 16; 9897eb8f069SAndrzej Hajda /* Fall through */ 9907eb8f069SAndrzej Hajda case 2: 9917eb8f069SAndrzej Hajda reg |= payload[1] << 8; 9927eb8f069SAndrzej Hajda /* Fall through */ 9937eb8f069SAndrzej Hajda case 1: 9947eb8f069SAndrzej Hajda reg |= payload[0]; 995bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PAYLOAD_REG, reg); 9967eb8f069SAndrzej Hajda break; 9977eb8f069SAndrzej Hajda } 9987eb8f069SAndrzej Hajda 9997eb8f069SAndrzej Hajda /* Send packet header */ 10007eb8f069SAndrzej Hajda if (!first) 10017eb8f069SAndrzej Hajda return; 10027eb8f069SAndrzej Hajda 10036c81e96dSAndrzej Hajda reg = get_unaligned_le32(pkt->header); 10047eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 10057eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 10067eb8f069SAndrzej Hajda return; 10077eb8f069SAndrzej Hajda } 10087eb8f069SAndrzej Hajda 10097eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 10107eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 10117eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 10127eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 10137eb8f069SAndrzej Hajda } 10147eb8f069SAndrzej Hajda 1015bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_PKTHDR_REG, reg); 10167eb8f069SAndrzej Hajda 10177eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 10187eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 10197eb8f069SAndrzej Hajda } 10207eb8f069SAndrzej Hajda 10217eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 10227eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 10237eb8f069SAndrzej Hajda { 10247eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 10257eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 10267eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 10277eb8f069SAndrzej Hajda u16 length; 10287eb8f069SAndrzej Hajda u32 reg; 10297eb8f069SAndrzej Hajda 10307eb8f069SAndrzej Hajda if (first) { 1031bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10327eb8f069SAndrzej Hajda 10337eb8f069SAndrzej Hajda switch (reg & 0x3f) { 10347eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 10357eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 10367eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 10377eb8f069SAndrzej Hajda payload[1] = reg >> 16; 10387eb8f069SAndrzej Hajda ++xfer->rx_done; 10397eb8f069SAndrzej Hajda } 10407eb8f069SAndrzej Hajda /* Fall through */ 10417eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 10427eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 10437eb8f069SAndrzej Hajda payload[0] = reg >> 8; 10447eb8f069SAndrzej Hajda ++xfer->rx_done; 10457eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 10467eb8f069SAndrzej Hajda xfer->result = 0; 10477eb8f069SAndrzej Hajda goto clear_fifo; 10487eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 10497eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 10507eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 10517eb8f069SAndrzej Hajda xfer->result = 0; 10527eb8f069SAndrzej Hajda goto clear_fifo; 10537eb8f069SAndrzej Hajda } 10547eb8f069SAndrzej Hajda 10557eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 10567eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 10577eb8f069SAndrzej Hajda dev_err(dev, 10587eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 10597eb8f069SAndrzej Hajda xfer->rx_len, length); 10607eb8f069SAndrzej Hajda length = xfer->rx_len; 10617eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 10627eb8f069SAndrzej Hajda xfer->rx_len = length; 10637eb8f069SAndrzej Hajda } 10647eb8f069SAndrzej Hajda 10657eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 10667eb8f069SAndrzej Hajda xfer->rx_done += length; 10677eb8f069SAndrzej Hajda 10687eb8f069SAndrzej Hajda /* Receive payload */ 10697eb8f069SAndrzej Hajda while (length >= 4) { 1070bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10717eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 10727eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10737eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10747eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 10757eb8f069SAndrzej Hajda payload += 4; 10767eb8f069SAndrzej Hajda length -= 4; 10777eb8f069SAndrzej Hajda } 10787eb8f069SAndrzej Hajda 10797eb8f069SAndrzej Hajda if (length) { 1080bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 10817eb8f069SAndrzej Hajda switch (length) { 10827eb8f069SAndrzej Hajda case 3: 10837eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10847eb8f069SAndrzej Hajda /* Fall through */ 10857eb8f069SAndrzej Hajda case 2: 10867eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10877eb8f069SAndrzej Hajda /* Fall through */ 10887eb8f069SAndrzej Hajda case 1: 10897eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 10907eb8f069SAndrzej Hajda } 10917eb8f069SAndrzej Hajda } 10927eb8f069SAndrzej Hajda 10937eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 10947eb8f069SAndrzej Hajda xfer->result = 0; 10957eb8f069SAndrzej Hajda 10967eb8f069SAndrzej Hajda clear_fifo: 10977eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 10987eb8f069SAndrzej Hajda do { 1099bb32e408SAndrzej Hajda reg = exynos_dsi_read(dsi, DSIM_RXFIFO_REG); 11007eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 11017eb8f069SAndrzej Hajda break; 11027eb8f069SAndrzej Hajda } while (--length); 11037eb8f069SAndrzej Hajda } 11047eb8f069SAndrzej Hajda 11057eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 11067eb8f069SAndrzej Hajda { 11077eb8f069SAndrzej Hajda unsigned long flags; 11087eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11097eb8f069SAndrzej Hajda bool start = false; 11107eb8f069SAndrzej Hajda 11117eb8f069SAndrzej Hajda again: 11127eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11137eb8f069SAndrzej Hajda 11147eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11157eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11167eb8f069SAndrzej Hajda return; 11177eb8f069SAndrzej Hajda } 11187eb8f069SAndrzej Hajda 11197eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11207eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11217eb8f069SAndrzej Hajda 11227eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11237eb8f069SAndrzej Hajda 11246c81e96dSAndrzej Hajda if (xfer->packet.payload_length && 11256c81e96dSAndrzej Hajda xfer->tx_done == xfer->packet.payload_length) 11267eb8f069SAndrzej Hajda /* waiting for RX */ 11277eb8f069SAndrzej Hajda return; 11287eb8f069SAndrzej Hajda 11297eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 11307eb8f069SAndrzej Hajda 11316c81e96dSAndrzej Hajda if (xfer->packet.payload_length || xfer->rx_len) 11327eb8f069SAndrzej Hajda return; 11337eb8f069SAndrzej Hajda 11347eb8f069SAndrzej Hajda xfer->result = 0; 11357eb8f069SAndrzej Hajda complete(&xfer->completed); 11367eb8f069SAndrzej Hajda 11377eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11387eb8f069SAndrzej Hajda 11397eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11407eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11417eb8f069SAndrzej Hajda 11427eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11437eb8f069SAndrzej Hajda 11447eb8f069SAndrzej Hajda if (start) 11457eb8f069SAndrzej Hajda goto again; 11467eb8f069SAndrzej Hajda } 11477eb8f069SAndrzej Hajda 11487eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 11497eb8f069SAndrzej Hajda { 11507eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11517eb8f069SAndrzej Hajda unsigned long flags; 11527eb8f069SAndrzej Hajda bool start = true; 11537eb8f069SAndrzej Hajda 11547eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11557eb8f069SAndrzej Hajda 11567eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11577eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11587eb8f069SAndrzej Hajda return false; 11597eb8f069SAndrzej Hajda } 11607eb8f069SAndrzej Hajda 11617eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11627eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11637eb8f069SAndrzej Hajda 11647eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11657eb8f069SAndrzej Hajda 11667eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 11679cdf0ed2SKrzysztof Kozlowski "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 11686c81e96dSAndrzej Hajda xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 11696c81e96dSAndrzej Hajda xfer->rx_done); 11707eb8f069SAndrzej Hajda 11716c81e96dSAndrzej Hajda if (xfer->tx_done != xfer->packet.payload_length) 11727eb8f069SAndrzej Hajda return true; 11737eb8f069SAndrzej Hajda 11747eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11757eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 11767eb8f069SAndrzej Hajda 11777eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11787eb8f069SAndrzej Hajda return true; 11797eb8f069SAndrzej Hajda 11807eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11817eb8f069SAndrzej Hajda 11827eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11837eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11847eb8f069SAndrzej Hajda 11857eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11867eb8f069SAndrzej Hajda 11877eb8f069SAndrzej Hajda if (!xfer->rx_len) 11887eb8f069SAndrzej Hajda xfer->result = 0; 11897eb8f069SAndrzej Hajda complete(&xfer->completed); 11907eb8f069SAndrzej Hajda 11917eb8f069SAndrzej Hajda return start; 11927eb8f069SAndrzej Hajda } 11937eb8f069SAndrzej Hajda 11947eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 11957eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 11967eb8f069SAndrzej Hajda { 11977eb8f069SAndrzej Hajda unsigned long flags; 11987eb8f069SAndrzej Hajda bool start; 11997eb8f069SAndrzej Hajda 12007eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12017eb8f069SAndrzej Hajda 12027eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 12037eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 12047eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 12057eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12067eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 12077eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12087eb8f069SAndrzej Hajda if (start) 12097eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12107eb8f069SAndrzej Hajda return; 12117eb8f069SAndrzej Hajda } 12127eb8f069SAndrzej Hajda 12137eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12147eb8f069SAndrzej Hajda 12157eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12167eb8f069SAndrzej Hajda } 12177eb8f069SAndrzej Hajda 12187eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 12197eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12207eb8f069SAndrzej Hajda { 12217eb8f069SAndrzej Hajda unsigned long flags; 12227eb8f069SAndrzej Hajda bool stopped; 12237eb8f069SAndrzej Hajda 12247eb8f069SAndrzej Hajda xfer->tx_done = 0; 12257eb8f069SAndrzej Hajda xfer->rx_done = 0; 12267eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 12277eb8f069SAndrzej Hajda init_completion(&xfer->completed); 12287eb8f069SAndrzej Hajda 12297eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12307eb8f069SAndrzej Hajda 12317eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 12327eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 12337eb8f069SAndrzej Hajda 12347eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12357eb8f069SAndrzej Hajda 12367eb8f069SAndrzej Hajda if (stopped) 12377eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12387eb8f069SAndrzej Hajda 12397eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 12407eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 12417eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 12426c81e96dSAndrzej Hajda struct mipi_dsi_packet *pkt = &xfer->packet; 12437eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 12446c81e96dSAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 12456c81e96dSAndrzej Hajda (int)pkt->payload_length, pkt->payload); 12467eb8f069SAndrzej Hajda return -ETIMEDOUT; 12477eb8f069SAndrzej Hajda } 12487eb8f069SAndrzej Hajda 12497eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 12507eb8f069SAndrzej Hajda return xfer->result; 12517eb8f069SAndrzej Hajda } 12527eb8f069SAndrzej Hajda 12537eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 12547eb8f069SAndrzej Hajda { 12557eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 12567eb8f069SAndrzej Hajda u32 status; 12577eb8f069SAndrzej Hajda 1258bb32e408SAndrzej Hajda status = exynos_dsi_read(dsi, DSIM_INTSRC_REG); 12597eb8f069SAndrzej Hajda if (!status) { 12607eb8f069SAndrzej Hajda static unsigned long int j; 12617eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 12627eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 12637eb8f069SAndrzej Hajda return IRQ_HANDLED; 12647eb8f069SAndrzej Hajda } 1265bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTSRC_REG, status); 12667eb8f069SAndrzej Hajda 12677eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 1268e6f988a4SHyungwon Hwang u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1269e6f988a4SHyungwon Hwang DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | 1270e6f988a4SHyungwon Hwang DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); 1271bb32e408SAndrzej Hajda exynos_dsi_write(dsi, DSIM_INTMSK_REG, mask); 12727eb8f069SAndrzej Hajda complete(&dsi->completed); 12737eb8f069SAndrzej Hajda return IRQ_HANDLED; 12747eb8f069SAndrzej Hajda } 12757eb8f069SAndrzej Hajda 1276e6f988a4SHyungwon Hwang if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1277e6f988a4SHyungwon Hwang DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) 12787eb8f069SAndrzej Hajda return IRQ_HANDLED; 12797eb8f069SAndrzej Hajda 12807eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 12817eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12827eb8f069SAndrzej Hajda 12837eb8f069SAndrzej Hajda return IRQ_HANDLED; 12847eb8f069SAndrzej Hajda } 12857eb8f069SAndrzej Hajda 1286e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1287e17ddeccSYoungJun Cho { 1288e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 12892b8376c8SGustavo Padovan struct drm_encoder *encoder = &dsi->encoder; 1290e17ddeccSYoungJun Cho 12910e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1292e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1293e17ddeccSYoungJun Cho 1294e17ddeccSYoungJun Cho return IRQ_HANDLED; 1295e17ddeccSYoungJun Cho } 1296e17ddeccSYoungJun Cho 1297e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1298e17ddeccSYoungJun Cho { 1299e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1300e17ddeccSYoungJun Cho 1301e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1302e17ddeccSYoungJun Cho enable_irq(gpio_to_irq(dsi->te_gpio)); 1303e17ddeccSYoungJun Cho } 1304e17ddeccSYoungJun Cho 1305e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1306e17ddeccSYoungJun Cho { 1307e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1308e17ddeccSYoungJun Cho disable_irq(gpio_to_irq(dsi->te_gpio)); 1309e17ddeccSYoungJun Cho 1310e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1311e17ddeccSYoungJun Cho } 1312e17ddeccSYoungJun Cho 13137eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 13147eb8f069SAndrzej Hajda { 13152154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1316d668e8bfSHyungwon Hwang 13177eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1318e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 1319e6f988a4SHyungwon Hwang 1320e6f988a4SHyungwon Hwang if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1321e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1322e6f988a4SHyungwon Hwang 13239a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1324d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 13257eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 13269a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 13277eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 13287eb8f069SAndrzej Hajda 13297eb8f069SAndrzej Hajda return 0; 13307eb8f069SAndrzej Hajda } 13317eb8f069SAndrzej Hajda 1332e17ddeccSYoungJun Cho static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1333e17ddeccSYoungJun Cho { 1334e17ddeccSYoungJun Cho int ret; 13350cef83a5SYoungJun Cho int te_gpio_irq; 1336e17ddeccSYoungJun Cho 1337e17ddeccSYoungJun Cho dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 133822e098daSAndrzej Hajda if (dsi->te_gpio == -ENOENT) 133922e098daSAndrzej Hajda return 0; 134022e098daSAndrzej Hajda 1341e17ddeccSYoungJun Cho if (!gpio_is_valid(dsi->te_gpio)) { 1342e17ddeccSYoungJun Cho ret = dsi->te_gpio; 134322e098daSAndrzej Hajda dev_err(dsi->dev, "cannot get te-gpios, %d\n", ret); 1344e17ddeccSYoungJun Cho goto out; 1345e17ddeccSYoungJun Cho } 1346e17ddeccSYoungJun Cho 134751d1decaSHyungwon Hwang ret = gpio_request(dsi->te_gpio, "te_gpio"); 1348e17ddeccSYoungJun Cho if (ret) { 1349e17ddeccSYoungJun Cho dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1350e17ddeccSYoungJun Cho goto out; 1351e17ddeccSYoungJun Cho } 1352e17ddeccSYoungJun Cho 13530cef83a5SYoungJun Cho te_gpio_irq = gpio_to_irq(dsi->te_gpio); 13540cef83a5SYoungJun Cho irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 135551d1decaSHyungwon Hwang 13560cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1357e17ddeccSYoungJun Cho IRQF_TRIGGER_RISING, "TE", dsi); 1358e17ddeccSYoungJun Cho if (ret) { 1359e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1360e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1361e17ddeccSYoungJun Cho goto out; 1362e17ddeccSYoungJun Cho } 1363e17ddeccSYoungJun Cho 1364e17ddeccSYoungJun Cho out: 1365e17ddeccSYoungJun Cho return ret; 1366e17ddeccSYoungJun Cho } 1367e17ddeccSYoungJun Cho 1368e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1369e17ddeccSYoungJun Cho { 1370e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) { 1371e17ddeccSYoungJun Cho free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1372e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1373e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1374e17ddeccSYoungJun Cho } 1375e17ddeccSYoungJun Cho } 1376e17ddeccSYoungJun Cho 13777eb8f069SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 13787eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 13797eb8f069SAndrzej Hajda { 13807eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 13817eb8f069SAndrzej Hajda 13827eb8f069SAndrzej Hajda dsi->lanes = device->lanes; 13837eb8f069SAndrzej Hajda dsi->format = device->format; 13847eb8f069SAndrzej Hajda dsi->mode_flags = device->mode_flags; 13857eb8f069SAndrzej Hajda dsi->panel_node = device->dev.of_node; 13867eb8f069SAndrzej Hajda 1387e17ddeccSYoungJun Cho /* 1388e17ddeccSYoungJun Cho * This is a temporary solution and should be made by more generic way. 1389e17ddeccSYoungJun Cho * 1390e17ddeccSYoungJun Cho * If attached panel device is for command mode one, dsi should register 1391e17ddeccSYoungJun Cho * TE interrupt handler. 1392e17ddeccSYoungJun Cho */ 1393e17ddeccSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1394e17ddeccSYoungJun Cho int ret = exynos_dsi_register_te_irq(dsi); 1395e17ddeccSYoungJun Cho 1396e17ddeccSYoungJun Cho if (ret) 1397e17ddeccSYoungJun Cho return ret; 1398e17ddeccSYoungJun Cho } 1399e17ddeccSYoungJun Cho 1400ecb84157SYoungJun Cho if (dsi->connector.dev) 1401ecb84157SYoungJun Cho drm_helper_hpd_irq_event(dsi->connector.dev); 1402ecb84157SYoungJun Cho 14037eb8f069SAndrzej Hajda return 0; 14047eb8f069SAndrzej Hajda } 14057eb8f069SAndrzej Hajda 14067eb8f069SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 14077eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 14087eb8f069SAndrzej Hajda { 14097eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 14107eb8f069SAndrzej Hajda 1411e17ddeccSYoungJun Cho exynos_dsi_unregister_te_irq(dsi); 1412e17ddeccSYoungJun Cho 14137eb8f069SAndrzej Hajda dsi->panel_node = NULL; 14147eb8f069SAndrzej Hajda 14157eb8f069SAndrzej Hajda if (dsi->connector.dev) 14167eb8f069SAndrzej Hajda drm_helper_hpd_irq_event(dsi->connector.dev); 14177eb8f069SAndrzej Hajda 14187eb8f069SAndrzej Hajda return 0; 14197eb8f069SAndrzej Hajda } 14207eb8f069SAndrzej Hajda 14217eb8f069SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1422ed6ff40eSThierry Reding const struct mipi_dsi_msg *msg) 14237eb8f069SAndrzej Hajda { 14247eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 14257eb8f069SAndrzej Hajda struct exynos_dsi_transfer xfer; 14267eb8f069SAndrzej Hajda int ret; 14277eb8f069SAndrzej Hajda 14280e480f6fSHyungwon Hwang if (!(dsi->state & DSIM_STATE_ENABLED)) 14290e480f6fSHyungwon Hwang return -EINVAL; 14300e480f6fSHyungwon Hwang 14317eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 14327eb8f069SAndrzej Hajda ret = exynos_dsi_init(dsi); 14337eb8f069SAndrzej Hajda if (ret) 14347eb8f069SAndrzej Hajda return ret; 14357eb8f069SAndrzej Hajda dsi->state |= DSIM_STATE_INITIALIZED; 14367eb8f069SAndrzej Hajda } 14377eb8f069SAndrzej Hajda 14386c81e96dSAndrzej Hajda ret = mipi_dsi_create_packet(&xfer.packet, msg); 14396c81e96dSAndrzej Hajda if (ret < 0) 14406c81e96dSAndrzej Hajda return ret; 14417eb8f069SAndrzej Hajda 14427eb8f069SAndrzej Hajda xfer.rx_len = msg->rx_len; 14437eb8f069SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 14447eb8f069SAndrzej Hajda xfer.flags = msg->flags; 14457eb8f069SAndrzej Hajda 14467eb8f069SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 14477eb8f069SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 14487eb8f069SAndrzej Hajda } 14497eb8f069SAndrzej Hajda 14507eb8f069SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 14517eb8f069SAndrzej Hajda .attach = exynos_dsi_host_attach, 14527eb8f069SAndrzej Hajda .detach = exynos_dsi_host_detach, 14537eb8f069SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 14547eb8f069SAndrzej Hajda }; 14557eb8f069SAndrzej Hajda 14562b8376c8SGustavo Padovan static void exynos_dsi_enable(struct drm_encoder *encoder) 14577eb8f069SAndrzej Hajda { 1458cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 14597eb8f069SAndrzej Hajda int ret; 14607eb8f069SAndrzej Hajda 14617eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 1462b6595dc7SGustavo Padovan return; 14637eb8f069SAndrzej Hajda 1464ba6e4779SInki Dae pm_runtime_get_sync(dsi->dev); 14657eb8f069SAndrzej Hajda 14660e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 14670e480f6fSHyungwon Hwang 1468cdfb8694SAjay Kumar ret = drm_panel_prepare(dsi->panel); 14697eb8f069SAndrzej Hajda if (ret < 0) { 14700e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_ENABLED; 1471ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 1472b6595dc7SGustavo Padovan return; 14737eb8f069SAndrzej Hajda } 14747eb8f069SAndrzej Hajda 14757eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 14767eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 14777eb8f069SAndrzej Hajda 1478cdfb8694SAjay Kumar ret = drm_panel_enable(dsi->panel); 1479cdfb8694SAjay Kumar if (ret < 0) { 1480d41bb38fSYoungJun Cho dsi->state &= ~DSIM_STATE_ENABLED; 1481cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1482cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 1483ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 1484b6595dc7SGustavo Padovan return; 1485cdfb8694SAjay Kumar } 1486cdfb8694SAjay Kumar 14870e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 14887eb8f069SAndrzej Hajda } 14897eb8f069SAndrzej Hajda 14902b8376c8SGustavo Padovan static void exynos_dsi_disable(struct drm_encoder *encoder) 14917eb8f069SAndrzej Hajda { 1492cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1493b6595dc7SGustavo Padovan 14947eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 14957eb8f069SAndrzej Hajda return; 14967eb8f069SAndrzej Hajda 14970e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 14980e480f6fSHyungwon Hwang 14997eb8f069SAndrzej Hajda drm_panel_disable(dsi->panel); 1500cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1501cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 15027eb8f069SAndrzej Hajda 15037eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 15040e480f6fSHyungwon Hwang 1505ba6e4779SInki Dae pm_runtime_put_sync(dsi->dev); 15067eb8f069SAndrzej Hajda } 15077eb8f069SAndrzej Hajda 15087eb8f069SAndrzej Hajda static enum drm_connector_status 15097eb8f069SAndrzej Hajda exynos_dsi_detect(struct drm_connector *connector, bool force) 15107eb8f069SAndrzej Hajda { 15117eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15127eb8f069SAndrzej Hajda 15137eb8f069SAndrzej Hajda if (!dsi->panel) { 15147eb8f069SAndrzej Hajda dsi->panel = of_drm_find_panel(dsi->panel_node); 15157eb8f069SAndrzej Hajda if (dsi->panel) 15167eb8f069SAndrzej Hajda drm_panel_attach(dsi->panel, &dsi->connector); 15177eb8f069SAndrzej Hajda } else if (!dsi->panel_node) { 15182b8376c8SGustavo Padovan struct drm_encoder *encoder; 15197eb8f069SAndrzej Hajda 1520cf67cc9aSGustavo Padovan encoder = platform_get_drvdata(to_platform_device(dsi->dev)); 1521cf67cc9aSGustavo Padovan exynos_dsi_disable(encoder); 15227eb8f069SAndrzej Hajda drm_panel_detach(dsi->panel); 15237eb8f069SAndrzej Hajda dsi->panel = NULL; 15247eb8f069SAndrzej Hajda } 15257eb8f069SAndrzej Hajda 15267eb8f069SAndrzej Hajda if (dsi->panel) 15277eb8f069SAndrzej Hajda return connector_status_connected; 15287eb8f069SAndrzej Hajda 15297eb8f069SAndrzej Hajda return connector_status_disconnected; 15307eb8f069SAndrzej Hajda } 15317eb8f069SAndrzej Hajda 15327eb8f069SAndrzej Hajda static void exynos_dsi_connector_destroy(struct drm_connector *connector) 15337eb8f069SAndrzej Hajda { 15340ae46015SAndrzej Hajda drm_connector_unregister(connector); 15350ae46015SAndrzej Hajda drm_connector_cleanup(connector); 15360ae46015SAndrzej Hajda connector->dev = NULL; 15377eb8f069SAndrzej Hajda } 15387eb8f069SAndrzej Hajda 1539800ba2b5SVille Syrjälä static const struct drm_connector_funcs exynos_dsi_connector_funcs = { 154063498e30SGustavo Padovan .dpms = drm_atomic_helper_connector_dpms, 15417eb8f069SAndrzej Hajda .detect = exynos_dsi_detect, 15427eb8f069SAndrzej Hajda .fill_modes = drm_helper_probe_single_connector_modes, 15437eb8f069SAndrzej Hajda .destroy = exynos_dsi_connector_destroy, 15444ea9526bSGustavo Padovan .reset = drm_atomic_helper_connector_reset, 15454ea9526bSGustavo Padovan .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 15464ea9526bSGustavo Padovan .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 15477eb8f069SAndrzej Hajda }; 15487eb8f069SAndrzej Hajda 15497eb8f069SAndrzej Hajda static int exynos_dsi_get_modes(struct drm_connector *connector) 15507eb8f069SAndrzej Hajda { 15517eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15527eb8f069SAndrzej Hajda 15537eb8f069SAndrzej Hajda if (dsi->panel) 15547eb8f069SAndrzej Hajda return dsi->panel->funcs->get_modes(dsi->panel); 15557eb8f069SAndrzej Hajda 15567eb8f069SAndrzej Hajda return 0; 15577eb8f069SAndrzej Hajda } 15587eb8f069SAndrzej Hajda 1559800ba2b5SVille Syrjälä static const struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 15607eb8f069SAndrzej Hajda .get_modes = exynos_dsi_get_modes, 15617eb8f069SAndrzej Hajda }; 15627eb8f069SAndrzej Hajda 15632b8376c8SGustavo Padovan static int exynos_dsi_create_connector(struct drm_encoder *encoder) 15647eb8f069SAndrzej Hajda { 15652b8376c8SGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 15667eb8f069SAndrzej Hajda struct drm_connector *connector = &dsi->connector; 15677eb8f069SAndrzej Hajda int ret; 15687eb8f069SAndrzej Hajda 15697eb8f069SAndrzej Hajda connector->polled = DRM_CONNECTOR_POLL_HPD; 15707eb8f069SAndrzej Hajda 15717eb8f069SAndrzej Hajda ret = drm_connector_init(encoder->dev, connector, 15727eb8f069SAndrzej Hajda &exynos_dsi_connector_funcs, 15737eb8f069SAndrzej Hajda DRM_MODE_CONNECTOR_DSI); 15747eb8f069SAndrzej Hajda if (ret) { 15757eb8f069SAndrzej Hajda DRM_ERROR("Failed to initialize connector with drm\n"); 15767eb8f069SAndrzej Hajda return ret; 15777eb8f069SAndrzej Hajda } 15787eb8f069SAndrzej Hajda 15797eb8f069SAndrzej Hajda drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 15807eb8f069SAndrzej Hajda drm_mode_connector_attach_encoder(connector, encoder); 15817eb8f069SAndrzej Hajda 15827eb8f069SAndrzej Hajda return 0; 15837eb8f069SAndrzej Hajda } 15847eb8f069SAndrzej Hajda 15852b8376c8SGustavo Padovan static void exynos_dsi_mode_set(struct drm_encoder *encoder, 15862b8376c8SGustavo Padovan struct drm_display_mode *mode, 15872b8376c8SGustavo Padovan struct drm_display_mode *adjusted_mode) 15887eb8f069SAndrzej Hajda { 1589cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 15907eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 15912b8376c8SGustavo Padovan struct drm_display_mode *m = adjusted_mode; 15927eb8f069SAndrzej Hajda 15932b8376c8SGustavo Padovan vm->hactive = m->hdisplay; 15942b8376c8SGustavo Padovan vm->vactive = m->vdisplay; 15952b8376c8SGustavo Padovan vm->vfront_porch = m->vsync_start - m->vdisplay; 15962b8376c8SGustavo Padovan vm->vback_porch = m->vtotal - m->vsync_end; 15972b8376c8SGustavo Padovan vm->vsync_len = m->vsync_end - m->vsync_start; 15982b8376c8SGustavo Padovan vm->hfront_porch = m->hsync_start - m->hdisplay; 15992b8376c8SGustavo Padovan vm->hback_porch = m->htotal - m->hsync_end; 16002b8376c8SGustavo Padovan vm->hsync_len = m->hsync_end - m->hsync_start; 16017eb8f069SAndrzej Hajda } 16027eb8f069SAndrzej Hajda 1603800ba2b5SVille Syrjälä static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { 16047eb8f069SAndrzej Hajda .mode_set = exynos_dsi_mode_set, 1605b6595dc7SGustavo Padovan .enable = exynos_dsi_enable, 1606b6595dc7SGustavo Padovan .disable = exynos_dsi_disable, 16077eb8f069SAndrzej Hajda }; 16087eb8f069SAndrzej Hajda 1609800ba2b5SVille Syrjälä static const struct drm_encoder_funcs exynos_dsi_encoder_funcs = { 16102b8376c8SGustavo Padovan .destroy = drm_encoder_cleanup, 16112b8376c8SGustavo Padovan }; 16122b8376c8SGustavo Padovan 1613bd024b86SSjoerd Simons MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 16147eb8f069SAndrzej Hajda 16157eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 16167eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 16177eb8f069SAndrzej Hajda { 16187eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 16197eb8f069SAndrzej Hajda 16207eb8f069SAndrzej Hajda if (ret < 0) 16217eb8f069SAndrzej Hajda pr_err("%s: failed to get '%s' property\n", np->full_name, 16227eb8f069SAndrzej Hajda propname); 16237eb8f069SAndrzej Hajda 16247eb8f069SAndrzej Hajda return ret; 16257eb8f069SAndrzej Hajda } 16267eb8f069SAndrzej Hajda 16277eb8f069SAndrzej Hajda enum { 16287eb8f069SAndrzej Hajda DSI_PORT_IN, 16297eb8f069SAndrzej Hajda DSI_PORT_OUT 16307eb8f069SAndrzej Hajda }; 16317eb8f069SAndrzej Hajda 16327eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 16337eb8f069SAndrzej Hajda { 16347eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 16357eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 16367eb8f069SAndrzej Hajda int ret; 16377eb8f069SAndrzej Hajda 16387eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 16397eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 16407eb8f069SAndrzej Hajda if (ret < 0) 16417eb8f069SAndrzej Hajda return ret; 16427eb8f069SAndrzej Hajda 1643f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,burst-clock-frequency", 16447eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 16457eb8f069SAndrzej Hajda if (ret < 0) 1646f2921d8cSHoegeun Kwon return ret; 16477eb8f069SAndrzej Hajda 1648f2921d8cSHoegeun Kwon ret = exynos_dsi_of_read_u32(node, "samsung,esc-clock-frequency", 16497eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 1650f5f3b9baSHyungwon Hwang if (ret < 0) 1651f2921d8cSHoegeun Kwon return ret; 1652f5f3b9baSHyungwon Hwang 165386418f90SRob Herring dsi->bridge_node = of_graph_get_remote_node(node, DSI_PORT_OUT, 0); 165486418f90SRob Herring if (!dsi->bridge_node) 165586418f90SRob Herring return -EINVAL; 1656f5f3b9baSHyungwon Hwang 1657f2921d8cSHoegeun Kwon return 0; 16587eb8f069SAndrzej Hajda } 16597eb8f069SAndrzej Hajda 1660f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1661f37cd5e8SInki Dae void *data) 1662f37cd5e8SInki Dae { 16632b8376c8SGustavo Padovan struct drm_encoder *encoder = dev_get_drvdata(dev); 16642b8376c8SGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1665f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1666f5f3b9baSHyungwon Hwang struct drm_bridge *bridge; 1667f37cd5e8SInki Dae int ret; 1668f37cd5e8SInki Dae 16692b8376c8SGustavo Padovan ret = exynos_drm_crtc_get_pipe_from_type(drm_dev, 1670cf67cc9aSGustavo Padovan EXYNOS_DISPLAY_TYPE_LCD); 16712b8376c8SGustavo Padovan if (ret < 0) 1672a2986e80SGustavo Padovan return ret; 1673a2986e80SGustavo Padovan 16742b8376c8SGustavo Padovan encoder->possible_crtcs = 1 << ret; 16752b8376c8SGustavo Padovan 16762b8376c8SGustavo Padovan DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 16772b8376c8SGustavo Padovan 16782b8376c8SGustavo Padovan drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, 167913a3d91fSVille Syrjälä DRM_MODE_ENCODER_TMDS, NULL); 16802b8376c8SGustavo Padovan 16812b8376c8SGustavo Padovan drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); 16822b8376c8SGustavo Padovan 16832b8376c8SGustavo Padovan ret = exynos_dsi_create_connector(encoder); 1684a2986e80SGustavo Padovan if (ret) { 1685a2986e80SGustavo Padovan DRM_ERROR("failed to create connector ret = %d\n", ret); 16862b8376c8SGustavo Padovan drm_encoder_cleanup(encoder); 1687f37cd5e8SInki Dae return ret; 1688f37cd5e8SInki Dae } 1689f37cd5e8SInki Dae 1690f5f3b9baSHyungwon Hwang bridge = of_drm_find_bridge(dsi->bridge_node); 16913bb80f24SLaurent Pinchart if (bridge) 16923bb80f24SLaurent Pinchart drm_bridge_attach(encoder, bridge, NULL); 1693f5f3b9baSHyungwon Hwang 1694f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1695f37cd5e8SInki Dae } 1696f37cd5e8SInki Dae 1697f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1698f37cd5e8SInki Dae void *data) 1699f37cd5e8SInki Dae { 17002b8376c8SGustavo Padovan struct drm_encoder *encoder = dev_get_drvdata(dev); 1701cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1702f37cd5e8SInki Dae 1703cf67cc9aSGustavo Padovan exynos_dsi_disable(encoder); 1704f37cd5e8SInki Dae 17050ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1706f37cd5e8SInki Dae } 1707f37cd5e8SInki Dae 1708f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1709f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1710f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1711f37cd5e8SInki Dae }; 1712f37cd5e8SInki Dae 17137eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 17147eb8f069SAndrzej Hajda { 17152900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 17167eb8f069SAndrzej Hajda struct resource *res; 17177eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 17180ff03fd1SHyungwon Hwang int ret, i; 17197eb8f069SAndrzej Hajda 17202900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 17212900c69cSAndrzej Hajda if (!dsi) 17222900c69cSAndrzej Hajda return -ENOMEM; 17232900c69cSAndrzej Hajda 1724e17ddeccSYoungJun Cho /* To be checked as invalid one */ 1725e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1726e17ddeccSYoungJun Cho 17277eb8f069SAndrzej Hajda init_completion(&dsi->completed); 17287eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 17297eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 17307eb8f069SAndrzej Hajda 17317eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1732e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 17337eb8f069SAndrzej Hajda 1734e2d2a1e0SAndrzej Hajda dsi->dev = dev; 17352154ac92SMarek Szyprowski dsi->driver_data = of_device_get_match_data(dev); 17367eb8f069SAndrzej Hajda 17377eb8f069SAndrzej Hajda ret = exynos_dsi_parse_dt(dsi); 17387eb8f069SAndrzej Hajda if (ret) 173986650408SAndrzej Hajda return ret; 17407eb8f069SAndrzej Hajda 17417eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 17427eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1743e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 17447eb8f069SAndrzej Hajda dsi->supplies); 17457eb8f069SAndrzej Hajda if (ret) { 1746e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get regulators: %d\n", ret); 17477eb8f069SAndrzej Hajda return -EPROBE_DEFER; 17487eb8f069SAndrzej Hajda } 17497eb8f069SAndrzej Hajda 17500ff03fd1SHyungwon Hwang dsi->clks = devm_kzalloc(dev, 17510ff03fd1SHyungwon Hwang sizeof(*dsi->clks) * dsi->driver_data->num_clks, 17520ff03fd1SHyungwon Hwang GFP_KERNEL); 1753e6f988a4SHyungwon Hwang if (!dsi->clks) 1754e6f988a4SHyungwon Hwang return -ENOMEM; 1755e6f988a4SHyungwon Hwang 17560ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 17570ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 17580ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 17590ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 17600ff03fd1SHyungwon Hwang strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 17610ff03fd1SHyungwon Hwang i--; 17620ff03fd1SHyungwon Hwang continue; 17637eb8f069SAndrzej Hajda } 17647eb8f069SAndrzej Hajda 17650ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 17660ff03fd1SHyungwon Hwang clk_names[i]); 17670ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 17680ff03fd1SHyungwon Hwang } 17697eb8f069SAndrzej Hajda } 17707eb8f069SAndrzej Hajda 17717eb8f069SAndrzej Hajda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1772e2d2a1e0SAndrzej Hajda dsi->reg_base = devm_ioremap_resource(dev, res); 1773293d3f6aSJingoo Han if (IS_ERR(dsi->reg_base)) { 1774e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to remap io region\n"); 177586650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 17767eb8f069SAndrzej Hajda } 17777eb8f069SAndrzej Hajda 1778e2d2a1e0SAndrzej Hajda dsi->phy = devm_phy_get(dev, "dsim"); 17797eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1780e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 178186650408SAndrzej Hajda return PTR_ERR(dsi->phy); 17827eb8f069SAndrzej Hajda } 17837eb8f069SAndrzej Hajda 17847eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 17857eb8f069SAndrzej Hajda if (dsi->irq < 0) { 1786e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq resource\n"); 178786650408SAndrzej Hajda return dsi->irq; 17887eb8f069SAndrzej Hajda } 17897eb8f069SAndrzej Hajda 17907eb8f069SAndrzej Hajda irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1791e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 17927eb8f069SAndrzej Hajda exynos_dsi_irq, IRQF_ONESHOT, 1793e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 17947eb8f069SAndrzej Hajda if (ret) { 1795e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 179686650408SAndrzej Hajda return ret; 17977eb8f069SAndrzej Hajda } 17987eb8f069SAndrzej Hajda 1799cf67cc9aSGustavo Padovan platform_set_drvdata(pdev, &dsi->encoder); 18007eb8f069SAndrzej Hajda 1801ba6e4779SInki Dae pm_runtime_enable(dev); 1802ba6e4779SInki Dae 180386650408SAndrzej Hajda return component_add(dev, &exynos_dsi_component_ops); 18047eb8f069SAndrzej Hajda } 18057eb8f069SAndrzej Hajda 18067eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 18077eb8f069SAndrzej Hajda { 180870505c2eSHoegeun Kwon struct exynos_dsi *dsi = platform_get_drvdata(pdev); 180970505c2eSHoegeun Kwon 181070505c2eSHoegeun Kwon of_node_put(dsi->bridge_node); 181170505c2eSHoegeun Kwon 1812ba6e4779SInki Dae pm_runtime_disable(&pdev->dev); 1813ba6e4779SInki Dae 1814df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1815df5225bcSInki Dae 18167eb8f069SAndrzej Hajda return 0; 18177eb8f069SAndrzej Hajda } 18187eb8f069SAndrzej Hajda 1819010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_suspend(struct device *dev) 1820ba6e4779SInki Dae { 1821ba6e4779SInki Dae struct drm_encoder *encoder = dev_get_drvdata(dev); 1822ba6e4779SInki Dae struct exynos_dsi *dsi = encoder_to_dsi(encoder); 18232154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1824ba6e4779SInki Dae int ret, i; 1825ba6e4779SInki Dae 1826ba6e4779SInki Dae usleep_range(10000, 20000); 1827ba6e4779SInki Dae 1828ba6e4779SInki Dae if (dsi->state & DSIM_STATE_INITIALIZED) { 1829ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_INITIALIZED; 1830ba6e4779SInki Dae 1831ba6e4779SInki Dae exynos_dsi_disable_clock(dsi); 1832ba6e4779SInki Dae 1833ba6e4779SInki Dae exynos_dsi_disable_irq(dsi); 1834ba6e4779SInki Dae } 1835ba6e4779SInki Dae 1836ba6e4779SInki Dae dsi->state &= ~DSIM_STATE_CMD_LPM; 1837ba6e4779SInki Dae 1838ba6e4779SInki Dae phy_power_off(dsi->phy); 1839ba6e4779SInki Dae 1840ba6e4779SInki Dae for (i = driver_data->num_clks - 1; i > -1; i--) 1841ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1842ba6e4779SInki Dae 1843ba6e4779SInki Dae ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1844ba6e4779SInki Dae if (ret < 0) 1845ba6e4779SInki Dae dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 1846ba6e4779SInki Dae 1847ba6e4779SInki Dae return 0; 1848ba6e4779SInki Dae } 1849ba6e4779SInki Dae 1850010848a7SArnd Bergmann static int __maybe_unused exynos_dsi_resume(struct device *dev) 1851ba6e4779SInki Dae { 1852ba6e4779SInki Dae struct drm_encoder *encoder = dev_get_drvdata(dev); 1853ba6e4779SInki Dae struct exynos_dsi *dsi = encoder_to_dsi(encoder); 18542154ac92SMarek Szyprowski const struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1855ba6e4779SInki Dae int ret, i; 1856ba6e4779SInki Dae 1857ba6e4779SInki Dae ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1858ba6e4779SInki Dae if (ret < 0) { 1859ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 1860ba6e4779SInki Dae return ret; 1861ba6e4779SInki Dae } 1862ba6e4779SInki Dae 1863ba6e4779SInki Dae for (i = 0; i < driver_data->num_clks; i++) { 1864ba6e4779SInki Dae ret = clk_prepare_enable(dsi->clks[i]); 1865ba6e4779SInki Dae if (ret < 0) 1866ba6e4779SInki Dae goto err_clk; 1867ba6e4779SInki Dae } 1868ba6e4779SInki Dae 1869ba6e4779SInki Dae ret = phy_power_on(dsi->phy); 1870ba6e4779SInki Dae if (ret < 0) { 1871ba6e4779SInki Dae dev_err(dsi->dev, "cannot enable phy %d\n", ret); 1872ba6e4779SInki Dae goto err_clk; 1873ba6e4779SInki Dae } 1874ba6e4779SInki Dae 1875ba6e4779SInki Dae return 0; 1876ba6e4779SInki Dae 1877ba6e4779SInki Dae err_clk: 1878ba6e4779SInki Dae while (--i > -1) 1879ba6e4779SInki Dae clk_disable_unprepare(dsi->clks[i]); 1880ba6e4779SInki Dae regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 1881ba6e4779SInki Dae 1882ba6e4779SInki Dae return ret; 1883ba6e4779SInki Dae } 1884ba6e4779SInki Dae 1885ba6e4779SInki Dae static const struct dev_pm_ops exynos_dsi_pm_ops = { 1886ba6e4779SInki Dae SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL) 1887ba6e4779SInki Dae }; 1888ba6e4779SInki Dae 18897eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 18907eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 18917eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 18927eb8f069SAndrzej Hajda .driver = { 18937eb8f069SAndrzej Hajda .name = "exynos-dsi", 18947eb8f069SAndrzej Hajda .owner = THIS_MODULE, 1895ba6e4779SInki Dae .pm = &exynos_dsi_pm_ops, 18967eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 18977eb8f069SAndrzej Hajda }, 18987eb8f069SAndrzej Hajda }; 18997eb8f069SAndrzej Hajda 19007eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 19017eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 19027eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 19037eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 1904