17eb8f069SAndrzej Hajda /* 27eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 37eb8f069SAndrzej Hajda * 47eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 57eb8f069SAndrzej Hajda * 67eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 77eb8f069SAndrzej Hajda * 87eb8f069SAndrzej Hajda * This program is free software; you can redistribute it and/or modify 97eb8f069SAndrzej Hajda * it under the terms of the GNU General Public License version 2 as 107eb8f069SAndrzej Hajda * published by the Free Software Foundation. 117eb8f069SAndrzej Hajda */ 127eb8f069SAndrzej Hajda 137eb8f069SAndrzej Hajda #include <drm/drmP.h> 147eb8f069SAndrzej Hajda #include <drm/drm_crtc_helper.h> 157eb8f069SAndrzej Hajda #include <drm/drm_mipi_dsi.h> 167eb8f069SAndrzej Hajda #include <drm/drm_panel.h> 174ea9526bSGustavo Padovan #include <drm/drm_atomic_helper.h> 187eb8f069SAndrzej Hajda 197eb8f069SAndrzej Hajda #include <linux/clk.h> 20e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 217eb8f069SAndrzej Hajda #include <linux/irq.h> 229a320415SYoungJun Cho #include <linux/of_device.h> 23e17ddeccSYoungJun Cho #include <linux/of_gpio.h> 24f5f3b9baSHyungwon Hwang #include <linux/of_graph.h> 257eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 267eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 27f37cd5e8SInki Dae #include <linux/component.h> 287eb8f069SAndrzej Hajda 297eb8f069SAndrzej Hajda #include <video/mipi_display.h> 307eb8f069SAndrzej Hajda #include <video/videomode.h> 317eb8f069SAndrzej Hajda 32e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 337eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 347eb8f069SAndrzej Hajda 357eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 367eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 377eb8f069SAndrzej Hajda 387eb8f069SAndrzej Hajda /* DSIM_STATUS */ 397eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 407eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 417eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 427eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 437eb8f069SAndrzej Hajda 447eb8f069SAndrzej Hajda /* DSIM_SWRST */ 457eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 467eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 477eb8f069SAndrzej Hajda 487eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 497eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 507eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 517eb8f069SAndrzej Hajda 527eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 537eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 547eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 557eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 567eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 577eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 587eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 597eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 607eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 617eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 627eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 637eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 647eb8f069SAndrzej Hajda 657eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 667eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 677eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 687eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 697eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 707eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 717eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 747eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 757eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 767eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 777eb8f069SAndrzej Hajda #define DSIM_HSA_MODE (1 << 20) 787eb8f069SAndrzej Hajda #define DSIM_HBP_MODE (1 << 21) 797eb8f069SAndrzej Hajda #define DSIM_HFP_MODE (1 << 22) 807eb8f069SAndrzej Hajda #define DSIM_HSE_MODE (1 << 23) 817eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 827eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 837eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 847eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 857eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 867eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 8778d3a8c6SInki Dae /* This flag is valid only for exynos3250/3472/4415/5260/5430 */ 8878d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 897eb8f069SAndrzej Hajda 907eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 917eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 927eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 937eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 947eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 957eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 967eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 977eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 987eb8f069SAndrzej Hajda 997eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 1007eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 101d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 102d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1037eb8f069SAndrzej Hajda 1047eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1057eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1067eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1077eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1087eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1097eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1107eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1117eb8f069SAndrzej Hajda 1127eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1137eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1147eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1157eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1167eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1177eb8f069SAndrzej Hajda 1187eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1197eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1207eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1217eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1227eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1237eb8f069SAndrzej Hajda 1247eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1257eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1267eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1277eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1287eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1297eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1307eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1317eb8f069SAndrzej Hajda 1327eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1337eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1347eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1357eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 136e6f988a4SHyungwon Hwang #define DSIM_INT_SFR_HDR_FIFO_EMPTY (1 << 28) 1377eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1387eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1397eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1407eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1417eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1427eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1437eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1447eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1457eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1467eb8f069SAndrzej Hajda 1477eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1487eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1497eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1507eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1517eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1527eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1537eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1547eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1557eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1567eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1577eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1587eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1597eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1607eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1617eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1627eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1637eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1647eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1657eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1667eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1677eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1687eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1697eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1707eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1717eb8f069SAndrzej Hajda 1727eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1737eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1747eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1757eb8f069SAndrzej Hajda 1767eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1777eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1787eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 1797eb8f069SAndrzej Hajda #define DSIM_PLL_P(x) ((x) << 13) 1807eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1817eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 1827eb8f069SAndrzej Hajda 1839a320415SYoungJun Cho /* DSIM_PHYCTRL */ 1849a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 185e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP (1 << 30) 186e6f988a4SHyungwon Hwang #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP (1 << 14) 1879a320415SYoungJun Cho 1889a320415SYoungJun Cho /* DSIM_PHYTIMING */ 1899a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 1909a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 1919a320415SYoungJun Cho 1929a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 1939a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 1949a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 1959a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 1969a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 1979a320415SYoungJun Cho 1989a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 1999a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 2009a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 2019a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 2029a320415SYoungJun Cho 2037eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2047eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2057eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2067eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2077eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2087eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2097eb8f069SAndrzej Hajda 21026269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 21126269af9SHyungwon Hwang 212d668e8bfSHyungwon Hwang #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \ 213d668e8bfSHyungwon Hwang dsi->driver_data->reg_ofs[(reg_idx)]) 214d668e8bfSHyungwon Hwang #define DSI_WRITE(dsi, reg_idx, val) writel((val), \ 215d668e8bfSHyungwon Hwang REG_ADDR((dsi), (reg_idx))) 216d668e8bfSHyungwon Hwang #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) 217ba12ac2bSHyungwon Hwang 218e6f988a4SHyungwon Hwang static char *clk_names[5] = { "bus_clk", "sclk_mipi", 219e6f988a4SHyungwon Hwang "phyclk_mipidphy0_bitclkdiv8", "phyclk_mipidphy0_rxclkesc0", 220e6f988a4SHyungwon Hwang "sclk_rgb_vclk_to_dsim0" }; 2210ff03fd1SHyungwon Hwang 2227eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2237eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2247eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2257eb8f069SAndrzej Hajda }; 2267eb8f069SAndrzej Hajda 2277eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2287eb8f069SAndrzej Hajda struct list_head list; 2297eb8f069SAndrzej Hajda struct completion completed; 2307eb8f069SAndrzej Hajda int result; 2317eb8f069SAndrzej Hajda u8 data_id; 2327eb8f069SAndrzej Hajda u8 data[2]; 2337eb8f069SAndrzej Hajda u16 flags; 2347eb8f069SAndrzej Hajda 2357eb8f069SAndrzej Hajda const u8 *tx_payload; 2367eb8f069SAndrzej Hajda u16 tx_len; 2377eb8f069SAndrzej Hajda u16 tx_done; 2387eb8f069SAndrzej Hajda 2397eb8f069SAndrzej Hajda u8 *rx_payload; 2407eb8f069SAndrzej Hajda u16 rx_len; 2417eb8f069SAndrzej Hajda u16 rx_done; 2427eb8f069SAndrzej Hajda }; 2437eb8f069SAndrzej Hajda 2447eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2457eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2467eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2470e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2487eb8f069SAndrzej Hajda 2499a320415SYoungJun Cho struct exynos_dsi_driver_data { 250d668e8bfSHyungwon Hwang unsigned int *reg_ofs; 2519a320415SYoungJun Cho unsigned int plltmr_reg; 2529a320415SYoungJun Cho unsigned int has_freqband:1; 25378d3a8c6SInki Dae unsigned int has_clklane_stop:1; 254d668e8bfSHyungwon Hwang unsigned int num_clks; 255d668e8bfSHyungwon Hwang unsigned int max_freq; 256d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 257d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 258d668e8bfSHyungwon Hwang unsigned int *reg_values; 2599a320415SYoungJun Cho }; 2609a320415SYoungJun Cho 2617eb8f069SAndrzej Hajda struct exynos_dsi { 2622b8376c8SGustavo Padovan struct drm_encoder encoder; 2637eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 2647eb8f069SAndrzej Hajda struct drm_connector connector; 2657eb8f069SAndrzej Hajda struct device_node *panel_node; 2667eb8f069SAndrzej Hajda struct drm_panel *panel; 2677eb8f069SAndrzej Hajda struct device *dev; 2687eb8f069SAndrzej Hajda 2697eb8f069SAndrzej Hajda void __iomem *reg_base; 2707eb8f069SAndrzej Hajda struct phy *phy; 2710ff03fd1SHyungwon Hwang struct clk **clks; 2727eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2737eb8f069SAndrzej Hajda int irq; 274e17ddeccSYoungJun Cho int te_gpio; 2757eb8f069SAndrzej Hajda 2767eb8f069SAndrzej Hajda u32 pll_clk_rate; 2777eb8f069SAndrzej Hajda u32 burst_clk_rate; 2787eb8f069SAndrzej Hajda u32 esc_clk_rate; 2797eb8f069SAndrzej Hajda u32 lanes; 2807eb8f069SAndrzej Hajda u32 mode_flags; 2817eb8f069SAndrzej Hajda u32 format; 2827eb8f069SAndrzej Hajda struct videomode vm; 2837eb8f069SAndrzej Hajda 2847eb8f069SAndrzej Hajda int state; 2857eb8f069SAndrzej Hajda struct drm_property *brightness; 2867eb8f069SAndrzej Hajda struct completion completed; 2877eb8f069SAndrzej Hajda 2887eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 2897eb8f069SAndrzej Hajda struct list_head transfer_list; 2909a320415SYoungJun Cho 2919a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data; 292f5f3b9baSHyungwon Hwang struct device_node *bridge_node; 2937eb8f069SAndrzej Hajda }; 2947eb8f069SAndrzej Hajda 2957eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 2967eb8f069SAndrzej Hajda #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 2977eb8f069SAndrzej Hajda 2982b8376c8SGustavo Padovan static inline struct exynos_dsi *encoder_to_dsi(struct drm_encoder *e) 2995cd5db80SAndrzej Hajda { 300cf67cc9aSGustavo Padovan return container_of(e, struct exynos_dsi, encoder); 3015cd5db80SAndrzej Hajda } 3025cd5db80SAndrzej Hajda 303d668e8bfSHyungwon Hwang enum reg_idx { 304d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 305d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 306d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 307d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 308d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 309d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 310d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 311d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 312d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 313d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 314d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 315d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 316d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 317d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 318d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 319d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 320d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 321d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 322d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 323d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 324d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 325d668e8bfSHyungwon Hwang NUM_REGS 326d668e8bfSHyungwon Hwang }; 327d668e8bfSHyungwon Hwang static unsigned int exynos_reg_ofs[] = { 328d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 329d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 330d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 331d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 332d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 333d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 334d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 335d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 336d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 337d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 338d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 339d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 340d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 341d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 342d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 343d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 344d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 345d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 346d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 347d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 348d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 349d668e8bfSHyungwon Hwang }; 350d668e8bfSHyungwon Hwang 351e6f988a4SHyungwon Hwang static unsigned int exynos5433_reg_ofs[] = { 352e6f988a4SHyungwon Hwang [DSIM_STATUS_REG] = 0x04, 353e6f988a4SHyungwon Hwang [DSIM_SWRST_REG] = 0x0C, 354e6f988a4SHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x10, 355e6f988a4SHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x14, 356e6f988a4SHyungwon Hwang [DSIM_CONFIG_REG] = 0x18, 357e6f988a4SHyungwon Hwang [DSIM_ESCMODE_REG] = 0x1C, 358e6f988a4SHyungwon Hwang [DSIM_MDRESOL_REG] = 0x20, 359e6f988a4SHyungwon Hwang [DSIM_MVPORCH_REG] = 0x24, 360e6f988a4SHyungwon Hwang [DSIM_MHPORCH_REG] = 0x28, 361e6f988a4SHyungwon Hwang [DSIM_MSYNC_REG] = 0x2C, 362e6f988a4SHyungwon Hwang [DSIM_INTSRC_REG] = 0x34, 363e6f988a4SHyungwon Hwang [DSIM_INTMSK_REG] = 0x38, 364e6f988a4SHyungwon Hwang [DSIM_PKTHDR_REG] = 0x3C, 365e6f988a4SHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x40, 366e6f988a4SHyungwon Hwang [DSIM_RXFIFO_REG] = 0x44, 367e6f988a4SHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x4C, 368e6f988a4SHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x94, 369e6f988a4SHyungwon Hwang [DSIM_PHYCTRL_REG] = 0xA4, 370e6f988a4SHyungwon Hwang [DSIM_PHYTIMING_REG] = 0xB4, 371e6f988a4SHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0xB8, 372e6f988a4SHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0xBC, 373e6f988a4SHyungwon Hwang }; 374e6f988a4SHyungwon Hwang 375d668e8bfSHyungwon Hwang enum reg_value_idx { 376d668e8bfSHyungwon Hwang RESET_TYPE, 377d668e8bfSHyungwon Hwang PLL_TIMER, 378d668e8bfSHyungwon Hwang STOP_STATE_CNT, 379d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 380d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 381d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 382d668e8bfSHyungwon Hwang PHYTIMING_LPX, 383d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 384d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 385d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 386d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 387d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 388d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 389d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 390d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 391d668e8bfSHyungwon Hwang }; 392d668e8bfSHyungwon Hwang 393d668e8bfSHyungwon Hwang static unsigned int reg_values[] = { 394d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 395d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 396d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 397d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 398d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 399d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 400d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 401d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 402d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 403d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 404d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 405d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 406d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 407d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 408d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 409d668e8bfSHyungwon Hwang }; 410d668e8bfSHyungwon Hwang 411e6f988a4SHyungwon Hwang static unsigned int exynos5433_reg_values[] = { 412e6f988a4SHyungwon Hwang [RESET_TYPE] = DSIM_FUNCRST, 413e6f988a4SHyungwon Hwang [PLL_TIMER] = 22200, 414e6f988a4SHyungwon Hwang [STOP_STATE_CNT] = 0xa, 415e6f988a4SHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 416e6f988a4SHyungwon Hwang [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 417e6f988a4SHyungwon Hwang [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 418e6f988a4SHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 419e6f988a4SHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 420e6f988a4SHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 421e6f988a4SHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 422e6f988a4SHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 423e6f988a4SHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 424e6f988a4SHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 425e6f988a4SHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 426e6f988a4SHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 427e6f988a4SHyungwon Hwang }; 428e6f988a4SHyungwon Hwang 429473462a1SInki Dae static struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 430d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 431473462a1SInki Dae .plltmr_reg = 0x50, 432473462a1SInki Dae .has_freqband = 1, 433473462a1SInki Dae .has_clklane_stop = 1, 434d668e8bfSHyungwon Hwang .num_clks = 2, 435d668e8bfSHyungwon Hwang .max_freq = 1000, 436d668e8bfSHyungwon Hwang .wait_for_reset = 1, 437d668e8bfSHyungwon Hwang .num_bits_resol = 11, 438d668e8bfSHyungwon Hwang .reg_values = reg_values, 439473462a1SInki Dae }; 440473462a1SInki Dae 4419a320415SYoungJun Cho static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 442d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4439a320415SYoungJun Cho .plltmr_reg = 0x50, 4449a320415SYoungJun Cho .has_freqband = 1, 44578d3a8c6SInki Dae .has_clklane_stop = 1, 446d668e8bfSHyungwon Hwang .num_clks = 2, 447d668e8bfSHyungwon Hwang .max_freq = 1000, 448d668e8bfSHyungwon Hwang .wait_for_reset = 1, 449d668e8bfSHyungwon Hwang .num_bits_resol = 11, 450d668e8bfSHyungwon Hwang .reg_values = reg_values, 4519a320415SYoungJun Cho }; 4529a320415SYoungJun Cho 4534bc6d644SYoungJun Cho static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = { 454d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4554bc6d644SYoungJun Cho .plltmr_reg = 0x58, 4564bc6d644SYoungJun Cho .has_clklane_stop = 1, 457d668e8bfSHyungwon Hwang .num_clks = 2, 458d668e8bfSHyungwon Hwang .max_freq = 1000, 459d668e8bfSHyungwon Hwang .wait_for_reset = 1, 460d668e8bfSHyungwon Hwang .num_bits_resol = 11, 461d668e8bfSHyungwon Hwang .reg_values = reg_values, 4624bc6d644SYoungJun Cho }; 4634bc6d644SYoungJun Cho 4649a320415SYoungJun Cho static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 465d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4669a320415SYoungJun Cho .plltmr_reg = 0x58, 467d668e8bfSHyungwon Hwang .num_clks = 2, 468d668e8bfSHyungwon Hwang .max_freq = 1000, 469d668e8bfSHyungwon Hwang .wait_for_reset = 1, 470d668e8bfSHyungwon Hwang .num_bits_resol = 11, 471d668e8bfSHyungwon Hwang .reg_values = reg_values, 4729a320415SYoungJun Cho }; 4739a320415SYoungJun Cho 474e6f988a4SHyungwon Hwang static struct exynos_dsi_driver_data exynos5433_dsi_driver_data = { 475e6f988a4SHyungwon Hwang .reg_ofs = exynos5433_reg_ofs, 476e6f988a4SHyungwon Hwang .plltmr_reg = 0xa0, 477e6f988a4SHyungwon Hwang .has_clklane_stop = 1, 478e6f988a4SHyungwon Hwang .num_clks = 5, 479e6f988a4SHyungwon Hwang .max_freq = 1500, 480e6f988a4SHyungwon Hwang .wait_for_reset = 0, 481e6f988a4SHyungwon Hwang .num_bits_resol = 12, 482e6f988a4SHyungwon Hwang .reg_values = exynos5433_reg_values, 483e6f988a4SHyungwon Hwang }; 484e6f988a4SHyungwon Hwang 4859a320415SYoungJun Cho static struct of_device_id exynos_dsi_of_match[] = { 486473462a1SInki Dae { .compatible = "samsung,exynos3250-mipi-dsi", 487473462a1SInki Dae .data = &exynos3_dsi_driver_data }, 4889a320415SYoungJun Cho { .compatible = "samsung,exynos4210-mipi-dsi", 4899a320415SYoungJun Cho .data = &exynos4_dsi_driver_data }, 4904bc6d644SYoungJun Cho { .compatible = "samsung,exynos4415-mipi-dsi", 4914bc6d644SYoungJun Cho .data = &exynos4415_dsi_driver_data }, 4929a320415SYoungJun Cho { .compatible = "samsung,exynos5410-mipi-dsi", 4939a320415SYoungJun Cho .data = &exynos5_dsi_driver_data }, 494e6f988a4SHyungwon Hwang { .compatible = "samsung,exynos5433-mipi-dsi", 495e6f988a4SHyungwon Hwang .data = &exynos5433_dsi_driver_data }, 4969a320415SYoungJun Cho { } 4979a320415SYoungJun Cho }; 4989a320415SYoungJun Cho 4999a320415SYoungJun Cho static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( 5009a320415SYoungJun Cho struct platform_device *pdev) 5019a320415SYoungJun Cho { 5029a320415SYoungJun Cho const struct of_device_id *of_id = 5039a320415SYoungJun Cho of_match_device(exynos_dsi_of_match, &pdev->dev); 5049a320415SYoungJun Cho 5059a320415SYoungJun Cho return (struct exynos_dsi_driver_data *)of_id->data; 5069a320415SYoungJun Cho } 5079a320415SYoungJun Cho 5087eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 5097eb8f069SAndrzej Hajda { 5107eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 5117eb8f069SAndrzej Hajda return; 5127eb8f069SAndrzej Hajda 5137eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 5147eb8f069SAndrzej Hajda } 5157eb8f069SAndrzej Hajda 5167eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 5177eb8f069SAndrzej Hajda { 518ba12ac2bSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 519ba12ac2bSHyungwon Hwang 5207eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 521d668e8bfSHyungwon Hwang DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); 5227eb8f069SAndrzej Hajda } 5237eb8f069SAndrzej Hajda 5247eb8f069SAndrzej Hajda #ifndef MHZ 5257eb8f069SAndrzej Hajda #define MHZ (1000*1000) 5267eb8f069SAndrzej Hajda #endif 5277eb8f069SAndrzej Hajda 5287eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 5297eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 5307eb8f069SAndrzej Hajda { 531ba12ac2bSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5327eb8f069SAndrzej Hajda unsigned long best_freq = 0; 5337eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 5347eb8f069SAndrzej Hajda u8 p_min, p_max; 5357eb8f069SAndrzej Hajda u8 _p, uninitialized_var(best_p); 5367eb8f069SAndrzej Hajda u16 _m, uninitialized_var(best_m); 5377eb8f069SAndrzej Hajda u8 _s, uninitialized_var(best_s); 5387eb8f069SAndrzej Hajda 5397eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 5407eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 5417eb8f069SAndrzej Hajda 5427eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 5437eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 5447eb8f069SAndrzej Hajda u64 tmp; 5457eb8f069SAndrzej Hajda u32 delta; 5467eb8f069SAndrzej Hajda 5477eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 5487eb8f069SAndrzej Hajda do_div(tmp, fin); 5497eb8f069SAndrzej Hajda _m = tmp; 5507eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 5517eb8f069SAndrzej Hajda continue; 5527eb8f069SAndrzej Hajda 5537eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5547eb8f069SAndrzej Hajda do_div(tmp, _p); 555d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 556d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 5577eb8f069SAndrzej Hajda continue; 5587eb8f069SAndrzej Hajda 5597eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 5607eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 5617eb8f069SAndrzej Hajda 5627eb8f069SAndrzej Hajda delta = abs(fout - tmp); 5637eb8f069SAndrzej Hajda if (delta < min_delta) { 5647eb8f069SAndrzej Hajda best_p = _p; 5657eb8f069SAndrzej Hajda best_m = _m; 5667eb8f069SAndrzej Hajda best_s = _s; 5677eb8f069SAndrzej Hajda min_delta = delta; 5687eb8f069SAndrzej Hajda best_freq = tmp; 5697eb8f069SAndrzej Hajda } 5707eb8f069SAndrzej Hajda } 5717eb8f069SAndrzej Hajda } 5727eb8f069SAndrzej Hajda 5737eb8f069SAndrzej Hajda if (best_freq) { 5747eb8f069SAndrzej Hajda *p = best_p; 5757eb8f069SAndrzej Hajda *m = best_m; 5767eb8f069SAndrzej Hajda *s = best_s; 5777eb8f069SAndrzej Hajda } 5787eb8f069SAndrzej Hajda 5797eb8f069SAndrzej Hajda return best_freq; 5807eb8f069SAndrzej Hajda } 5817eb8f069SAndrzej Hajda 5827eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 5837eb8f069SAndrzej Hajda unsigned long freq) 5847eb8f069SAndrzej Hajda { 5859a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5867eb8f069SAndrzej Hajda unsigned long fin, fout; 5879a320415SYoungJun Cho int timeout; 5887eb8f069SAndrzej Hajda u8 p, s; 5897eb8f069SAndrzej Hajda u16 m; 5907eb8f069SAndrzej Hajda u32 reg; 5917eb8f069SAndrzej Hajda 59226269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 5937eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 5947eb8f069SAndrzej Hajda if (!fout) { 5957eb8f069SAndrzej Hajda dev_err(dsi->dev, 5967eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 5978525b5ecSYoungJun Cho return 0; 5987eb8f069SAndrzej Hajda } 5999a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 6009a320415SYoungJun Cho 601d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 602d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 6039a320415SYoungJun Cho 6049a320415SYoungJun Cho reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 6059a320415SYoungJun Cho 6069a320415SYoungJun Cho if (driver_data->has_freqband) { 6079a320415SYoungJun Cho static const unsigned long freq_bands[] = { 6089a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 6099a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 6109a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 6119a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 6129a320415SYoungJun Cho }; 6139a320415SYoungJun Cho int band; 6147eb8f069SAndrzej Hajda 6157eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 6167eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 6177eb8f069SAndrzej Hajda break; 6187eb8f069SAndrzej Hajda 6199a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 6207eb8f069SAndrzej Hajda 6219a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 6229a320415SYoungJun Cho } 6237eb8f069SAndrzej Hajda 624ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 6257eb8f069SAndrzej Hajda 6267eb8f069SAndrzej Hajda timeout = 1000; 6277eb8f069SAndrzej Hajda do { 6287eb8f069SAndrzej Hajda if (timeout-- == 0) { 6297eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 6308525b5ecSYoungJun Cho return 0; 6317eb8f069SAndrzej Hajda } 632ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_STATUS_REG); 6337eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 6347eb8f069SAndrzej Hajda 6357eb8f069SAndrzej Hajda return fout; 6367eb8f069SAndrzej Hajda } 6377eb8f069SAndrzej Hajda 6387eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 6397eb8f069SAndrzej Hajda { 6407eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 6417eb8f069SAndrzej Hajda unsigned long esc_div; 6427eb8f069SAndrzej Hajda u32 reg; 6437eb8f069SAndrzej Hajda 6447eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 6457eb8f069SAndrzej Hajda if (!hs_clk) { 6467eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 6477eb8f069SAndrzej Hajda return -EFAULT; 6487eb8f069SAndrzej Hajda } 6497eb8f069SAndrzej Hajda 6507eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 6517eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 6527eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6537eb8f069SAndrzej Hajda 6547eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 6557eb8f069SAndrzej Hajda ++esc_div; 6567eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 6577eb8f069SAndrzej Hajda } 6587eb8f069SAndrzej Hajda 6597eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 6607eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 6617eb8f069SAndrzej Hajda 662ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 6637eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 6647eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 6657eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 6667eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 6677eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 6687eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 6697eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 6707eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 6717eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 672ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 6737eb8f069SAndrzej Hajda 6747eb8f069SAndrzej Hajda return 0; 6757eb8f069SAndrzej Hajda } 6767eb8f069SAndrzej Hajda 6779a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 6789a320415SYoungJun Cho { 6799a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 680d668e8bfSHyungwon Hwang unsigned int *reg_values = driver_data->reg_values; 6819a320415SYoungJun Cho u32 reg; 6829a320415SYoungJun Cho 6839a320415SYoungJun Cho if (driver_data->has_freqband) 6849a320415SYoungJun Cho return; 6859a320415SYoungJun Cho 6869a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 687d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 688d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 689ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg); 6909a320415SYoungJun Cho 6919a320415SYoungJun Cho /* 6929a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 6939a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 6949a320415SYoungJun Cho * burst 6959a320415SYoungJun Cho */ 696d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 697ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg); 6989a320415SYoungJun Cho 6999a320415SYoungJun Cho /* 7009a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 7019a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7029a320415SYoungJun Cho * HS transmission 7039a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 7049a320415SYoungJun Cho * transmitting the Clock. 7059a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 7069a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 7079a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 7089a320415SYoungJun Cho * the beginning of T CLK-TRAIL 7099a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 7109a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 7119a320415SYoungJun Cho */ 712d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 713d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 714d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 715d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 716d668e8bfSHyungwon Hwang 717ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg); 7189a320415SYoungJun Cho 7199a320415SYoungJun Cho /* 7209a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 7219a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 7229a320415SYoungJun Cho * HS transmission 7239a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 7249a320415SYoungJun Cho * transmitting the Sync sequence. 7259a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 7269a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 7279a320415SYoungJun Cho */ 728d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 729d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 730ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg); 7319a320415SYoungJun Cho } 7329a320415SYoungJun Cho 7337eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 7347eb8f069SAndrzej Hajda { 7357eb8f069SAndrzej Hajda u32 reg; 7367eb8f069SAndrzej Hajda 737ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 7387eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 7397eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 740ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 7417eb8f069SAndrzej Hajda 742ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_PLLCTRL_REG); 7437eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 744ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 7457eb8f069SAndrzej Hajda } 7467eb8f069SAndrzej Hajda 747e6f988a4SHyungwon Hwang static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) 748e6f988a4SHyungwon Hwang { 749e6f988a4SHyungwon Hwang u32 reg = DSI_READ(dsi, DSIM_CONFIG_REG); 750e6f988a4SHyungwon Hwang reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 751e6f988a4SHyungwon Hwang DSIM_LANE_EN(lane)); 752e6f988a4SHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 753e6f988a4SHyungwon Hwang } 754e6f988a4SHyungwon Hwang 7557eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 7567eb8f069SAndrzej Hajda { 75778d3a8c6SInki Dae struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 7587eb8f069SAndrzej Hajda int timeout; 7597eb8f069SAndrzej Hajda u32 reg; 7607eb8f069SAndrzej Hajda u32 lanes_mask; 7617eb8f069SAndrzej Hajda 7627eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 763ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 7647eb8f069SAndrzej Hajda reg &= ~0x1f; 765ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 7667eb8f069SAndrzej Hajda 7677eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7687eb8f069SAndrzej Hajda 7697eb8f069SAndrzej Hajda reg |= 0x1f; 770ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 7717eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7727eb8f069SAndrzej Hajda 7737eb8f069SAndrzej Hajda /* DSI configuration */ 7747eb8f069SAndrzej Hajda reg = 0; 7757eb8f069SAndrzej Hajda 7762f36e33aSYoungJun Cho /* 7772f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 7782f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 7792f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 7802f36e33aSYoungJun Cho */ 7817eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 7827eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 7837eb8f069SAndrzej Hajda 7842f36e33aSYoungJun Cho /* 7852f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 7862f36e33aSYoungJun Cho * command mode. 7872f36e33aSYoungJun Cho */ 7887eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 7897eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 7907eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 7917eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 7927eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 7937eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 7947eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 7957eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 7967eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 7977eb8f069SAndrzej Hajda reg |= DSIM_HSE_MODE; 7987eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 7997eb8f069SAndrzej Hajda reg |= DSIM_HFP_MODE; 8007eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 8017eb8f069SAndrzej Hajda reg |= DSIM_HBP_MODE; 8027eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 8037eb8f069SAndrzej Hajda reg |= DSIM_HSA_MODE; 8047eb8f069SAndrzej Hajda } 8057eb8f069SAndrzej Hajda 8062f36e33aSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 8072f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 8082f36e33aSYoungJun Cho 8097eb8f069SAndrzej Hajda switch (dsi->format) { 8107eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 8117eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 8127eb8f069SAndrzej Hajda break; 8137eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 8147eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 8157eb8f069SAndrzej Hajda break; 8167eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 8177eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 8187eb8f069SAndrzej Hajda break; 8197eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 8207eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 8217eb8f069SAndrzej Hajda break; 8227eb8f069SAndrzej Hajda default: 8237eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 8247eb8f069SAndrzej Hajda return -EINVAL; 8257eb8f069SAndrzej Hajda } 8267eb8f069SAndrzej Hajda 82778d3a8c6SInki Dae /* 82878d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 82978d3a8c6SInki Dae * host controller supports 83078d3a8c6SInki Dae * 83178d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 83278d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 83378d3a8c6SInki Dae * power consumption. 83478d3a8c6SInki Dae */ 83578d3a8c6SInki Dae if (driver_data->has_clklane_stop && 83678d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 83778d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 83878d3a8c6SInki Dae } 839e6f988a4SHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 840e6f988a4SHyungwon Hwang 841e6f988a4SHyungwon Hwang lanes_mask = BIT(dsi->lanes) - 1; 842e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, lanes_mask); 84378d3a8c6SInki Dae 8447eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 8457eb8f069SAndrzej Hajda timeout = 100; 8467eb8f069SAndrzej Hajda do { 8477eb8f069SAndrzej Hajda if (timeout-- == 0) { 8487eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 8497eb8f069SAndrzej Hajda return -EFAULT; 8507eb8f069SAndrzej Hajda } 8517eb8f069SAndrzej Hajda 852ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_STATUS_REG); 8537eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 8547eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 8557eb8f069SAndrzej Hajda continue; 8567eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 8577eb8f069SAndrzej Hajda 858ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_ESCMODE_REG); 8597eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 860d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 861ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg); 8627eb8f069SAndrzej Hajda 8637eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 864ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg); 8657eb8f069SAndrzej Hajda 8667eb8f069SAndrzej Hajda return 0; 8677eb8f069SAndrzej Hajda } 8687eb8f069SAndrzej Hajda 8697eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 8707eb8f069SAndrzej Hajda { 8717eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 872d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 8737eb8f069SAndrzej Hajda u32 reg; 8747eb8f069SAndrzej Hajda 8757eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8767eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 8777eb8f069SAndrzej Hajda | DSIM_STABLE_VFP(vm->vfront_porch) 8787eb8f069SAndrzej Hajda | DSIM_MAIN_VBP(vm->vback_porch); 879ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg); 8807eb8f069SAndrzej Hajda 8817eb8f069SAndrzej Hajda reg = DSIM_MAIN_HFP(vm->hfront_porch) 8827eb8f069SAndrzej Hajda | DSIM_MAIN_HBP(vm->hback_porch); 883ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg); 8847eb8f069SAndrzej Hajda 8857eb8f069SAndrzej Hajda reg = DSIM_MAIN_VSA(vm->vsync_len) 8867eb8f069SAndrzej Hajda | DSIM_MAIN_HSA(vm->hsync_len); 887ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MSYNC_REG, reg); 8887eb8f069SAndrzej Hajda } 889d668e8bfSHyungwon Hwang reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | 890d668e8bfSHyungwon Hwang DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); 8917eb8f069SAndrzej Hajda 892ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 8937eb8f069SAndrzej Hajda 8947eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 8957eb8f069SAndrzej Hajda } 8967eb8f069SAndrzej Hajda 8977eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 8987eb8f069SAndrzej Hajda { 8997eb8f069SAndrzej Hajda u32 reg; 9007eb8f069SAndrzej Hajda 901ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_MDRESOL_REG); 9027eb8f069SAndrzej Hajda if (enable) 9037eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 9047eb8f069SAndrzej Hajda else 9057eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 906ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 9077eb8f069SAndrzej Hajda } 9087eb8f069SAndrzej Hajda 9097eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 9107eb8f069SAndrzej Hajda { 9117eb8f069SAndrzej Hajda int timeout = 2000; 9127eb8f069SAndrzej Hajda 9137eb8f069SAndrzej Hajda do { 914ba12ac2bSHyungwon Hwang u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 9157eb8f069SAndrzej Hajda 9167eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 9177eb8f069SAndrzej Hajda return 0; 9187eb8f069SAndrzej Hajda 9197eb8f069SAndrzej Hajda if (!cond_resched()) 9207eb8f069SAndrzej Hajda usleep_range(950, 1050); 9217eb8f069SAndrzej Hajda } while (--timeout); 9227eb8f069SAndrzej Hajda 9237eb8f069SAndrzej Hajda return -ETIMEDOUT; 9247eb8f069SAndrzej Hajda } 9257eb8f069SAndrzej Hajda 9267eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 9277eb8f069SAndrzej Hajda { 928ba12ac2bSHyungwon Hwang u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 9297eb8f069SAndrzej Hajda 9307eb8f069SAndrzej Hajda if (lpm) 9317eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 9327eb8f069SAndrzej Hajda else 9337eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 9347eb8f069SAndrzej Hajda 935ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 9367eb8f069SAndrzej Hajda } 9377eb8f069SAndrzej Hajda 9387eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 9397eb8f069SAndrzej Hajda { 940ba12ac2bSHyungwon Hwang u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 9417eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 942ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 9437eb8f069SAndrzej Hajda } 9447eb8f069SAndrzej Hajda 9457eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 9467eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9477eb8f069SAndrzej Hajda { 9487eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9497eb8f069SAndrzej Hajda const u8 *payload = xfer->tx_payload + xfer->tx_done; 9507eb8f069SAndrzej Hajda u16 length = xfer->tx_len - xfer->tx_done; 9517eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 9527eb8f069SAndrzej Hajda u32 reg; 9537eb8f069SAndrzej Hajda 9547eb8f069SAndrzej Hajda dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 9557eb8f069SAndrzej Hajda xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 9567eb8f069SAndrzej Hajda 9577eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 9587eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 9597eb8f069SAndrzej Hajda 9607eb8f069SAndrzej Hajda xfer->tx_done += length; 9617eb8f069SAndrzej Hajda 9627eb8f069SAndrzej Hajda /* Send payload */ 9637eb8f069SAndrzej Hajda while (length >= 4) { 9647eb8f069SAndrzej Hajda reg = (payload[3] << 24) | (payload[2] << 16) 9657eb8f069SAndrzej Hajda | (payload[1] << 8) | payload[0]; 966ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 9677eb8f069SAndrzej Hajda payload += 4; 9687eb8f069SAndrzej Hajda length -= 4; 9697eb8f069SAndrzej Hajda } 9707eb8f069SAndrzej Hajda 9717eb8f069SAndrzej Hajda reg = 0; 9727eb8f069SAndrzej Hajda switch (length) { 9737eb8f069SAndrzej Hajda case 3: 9747eb8f069SAndrzej Hajda reg |= payload[2] << 16; 9757eb8f069SAndrzej Hajda /* Fall through */ 9767eb8f069SAndrzej Hajda case 2: 9777eb8f069SAndrzej Hajda reg |= payload[1] << 8; 9787eb8f069SAndrzej Hajda /* Fall through */ 9797eb8f069SAndrzej Hajda case 1: 9807eb8f069SAndrzej Hajda reg |= payload[0]; 981ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 9827eb8f069SAndrzej Hajda break; 9837eb8f069SAndrzej Hajda case 0: 9847eb8f069SAndrzej Hajda /* Do nothing */ 9857eb8f069SAndrzej Hajda break; 9867eb8f069SAndrzej Hajda } 9877eb8f069SAndrzej Hajda 9887eb8f069SAndrzej Hajda /* Send packet header */ 9897eb8f069SAndrzej Hajda if (!first) 9907eb8f069SAndrzej Hajda return; 9917eb8f069SAndrzej Hajda 9927eb8f069SAndrzej Hajda reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; 9937eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 9947eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 9957eb8f069SAndrzej Hajda return; 9967eb8f069SAndrzej Hajda } 9977eb8f069SAndrzej Hajda 9987eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 9997eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 10007eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 10017eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 10027eb8f069SAndrzej Hajda } 10037eb8f069SAndrzej Hajda 1004ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg); 10057eb8f069SAndrzej Hajda 10067eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 10077eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 10087eb8f069SAndrzej Hajda } 10097eb8f069SAndrzej Hajda 10107eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 10117eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 10127eb8f069SAndrzej Hajda { 10137eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 10147eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 10157eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 10167eb8f069SAndrzej Hajda u16 length; 10177eb8f069SAndrzej Hajda u32 reg; 10187eb8f069SAndrzej Hajda 10197eb8f069SAndrzej Hajda if (first) { 1020ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10217eb8f069SAndrzej Hajda 10227eb8f069SAndrzej Hajda switch (reg & 0x3f) { 10237eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 10247eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 10257eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 10267eb8f069SAndrzej Hajda payload[1] = reg >> 16; 10277eb8f069SAndrzej Hajda ++xfer->rx_done; 10287eb8f069SAndrzej Hajda } 10297eb8f069SAndrzej Hajda /* Fall through */ 10307eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 10317eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 10327eb8f069SAndrzej Hajda payload[0] = reg >> 8; 10337eb8f069SAndrzej Hajda ++xfer->rx_done; 10347eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 10357eb8f069SAndrzej Hajda xfer->result = 0; 10367eb8f069SAndrzej Hajda goto clear_fifo; 10377eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 10387eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 10397eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 10407eb8f069SAndrzej Hajda xfer->result = 0; 10417eb8f069SAndrzej Hajda goto clear_fifo; 10427eb8f069SAndrzej Hajda } 10437eb8f069SAndrzej Hajda 10447eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 10457eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 10467eb8f069SAndrzej Hajda dev_err(dev, 10477eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 10487eb8f069SAndrzej Hajda xfer->rx_len, length); 10497eb8f069SAndrzej Hajda length = xfer->rx_len; 10507eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 10517eb8f069SAndrzej Hajda xfer->rx_len = length; 10527eb8f069SAndrzej Hajda } 10537eb8f069SAndrzej Hajda 10547eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 10557eb8f069SAndrzej Hajda xfer->rx_done += length; 10567eb8f069SAndrzej Hajda 10577eb8f069SAndrzej Hajda /* Receive payload */ 10587eb8f069SAndrzej Hajda while (length >= 4) { 1059ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10607eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 10617eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10627eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10637eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 10647eb8f069SAndrzej Hajda payload += 4; 10657eb8f069SAndrzej Hajda length -= 4; 10667eb8f069SAndrzej Hajda } 10677eb8f069SAndrzej Hajda 10687eb8f069SAndrzej Hajda if (length) { 1069ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10707eb8f069SAndrzej Hajda switch (length) { 10717eb8f069SAndrzej Hajda case 3: 10727eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10737eb8f069SAndrzej Hajda /* Fall through */ 10747eb8f069SAndrzej Hajda case 2: 10757eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10767eb8f069SAndrzej Hajda /* Fall through */ 10777eb8f069SAndrzej Hajda case 1: 10787eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 10797eb8f069SAndrzej Hajda } 10807eb8f069SAndrzej Hajda } 10817eb8f069SAndrzej Hajda 10827eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 10837eb8f069SAndrzej Hajda xfer->result = 0; 10847eb8f069SAndrzej Hajda 10857eb8f069SAndrzej Hajda clear_fifo: 10867eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 10877eb8f069SAndrzej Hajda do { 1088ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10897eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 10907eb8f069SAndrzej Hajda break; 10917eb8f069SAndrzej Hajda } while (--length); 10927eb8f069SAndrzej Hajda } 10937eb8f069SAndrzej Hajda 10947eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 10957eb8f069SAndrzej Hajda { 10967eb8f069SAndrzej Hajda unsigned long flags; 10977eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 10987eb8f069SAndrzej Hajda bool start = false; 10997eb8f069SAndrzej Hajda 11007eb8f069SAndrzej Hajda again: 11017eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11027eb8f069SAndrzej Hajda 11037eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11047eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11057eb8f069SAndrzej Hajda return; 11067eb8f069SAndrzej Hajda } 11077eb8f069SAndrzej Hajda 11087eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11097eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11107eb8f069SAndrzej Hajda 11117eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11127eb8f069SAndrzej Hajda 11137eb8f069SAndrzej Hajda if (xfer->tx_len && xfer->tx_done == xfer->tx_len) 11147eb8f069SAndrzej Hajda /* waiting for RX */ 11157eb8f069SAndrzej Hajda return; 11167eb8f069SAndrzej Hajda 11177eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 11187eb8f069SAndrzej Hajda 11197eb8f069SAndrzej Hajda if (xfer->tx_len || xfer->rx_len) 11207eb8f069SAndrzej Hajda return; 11217eb8f069SAndrzej Hajda 11227eb8f069SAndrzej Hajda xfer->result = 0; 11237eb8f069SAndrzej Hajda complete(&xfer->completed); 11247eb8f069SAndrzej Hajda 11257eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11267eb8f069SAndrzej Hajda 11277eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11287eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11297eb8f069SAndrzej Hajda 11307eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11317eb8f069SAndrzej Hajda 11327eb8f069SAndrzej Hajda if (start) 11337eb8f069SAndrzej Hajda goto again; 11347eb8f069SAndrzej Hajda } 11357eb8f069SAndrzej Hajda 11367eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 11377eb8f069SAndrzej Hajda { 11387eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 11397eb8f069SAndrzej Hajda unsigned long flags; 11407eb8f069SAndrzej Hajda bool start = true; 11417eb8f069SAndrzej Hajda 11427eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11437eb8f069SAndrzej Hajda 11447eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 11457eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11467eb8f069SAndrzej Hajda return false; 11477eb8f069SAndrzej Hajda } 11487eb8f069SAndrzej Hajda 11497eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 11507eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 11517eb8f069SAndrzej Hajda 11527eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11537eb8f069SAndrzej Hajda 11547eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 11557eb8f069SAndrzej Hajda "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", 11567eb8f069SAndrzej Hajda xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 11577eb8f069SAndrzej Hajda 11587eb8f069SAndrzej Hajda if (xfer->tx_done != xfer->tx_len) 11597eb8f069SAndrzej Hajda return true; 11607eb8f069SAndrzej Hajda 11617eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11627eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 11637eb8f069SAndrzej Hajda 11647eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11657eb8f069SAndrzej Hajda return true; 11667eb8f069SAndrzej Hajda 11677eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11687eb8f069SAndrzej Hajda 11697eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11707eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11717eb8f069SAndrzej Hajda 11727eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11737eb8f069SAndrzej Hajda 11747eb8f069SAndrzej Hajda if (!xfer->rx_len) 11757eb8f069SAndrzej Hajda xfer->result = 0; 11767eb8f069SAndrzej Hajda complete(&xfer->completed); 11777eb8f069SAndrzej Hajda 11787eb8f069SAndrzej Hajda return start; 11797eb8f069SAndrzej Hajda } 11807eb8f069SAndrzej Hajda 11817eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 11827eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 11837eb8f069SAndrzej Hajda { 11847eb8f069SAndrzej Hajda unsigned long flags; 11857eb8f069SAndrzej Hajda bool start; 11867eb8f069SAndrzej Hajda 11877eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11887eb8f069SAndrzej Hajda 11897eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 11907eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 11917eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 11927eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11937eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11947eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11957eb8f069SAndrzej Hajda if (start) 11967eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 11977eb8f069SAndrzej Hajda return; 11987eb8f069SAndrzej Hajda } 11997eb8f069SAndrzej Hajda 12007eb8f069SAndrzej Hajda list_del_init(&xfer->list); 12017eb8f069SAndrzej Hajda 12027eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12037eb8f069SAndrzej Hajda } 12047eb8f069SAndrzej Hajda 12057eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 12067eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 12077eb8f069SAndrzej Hajda { 12087eb8f069SAndrzej Hajda unsigned long flags; 12097eb8f069SAndrzej Hajda bool stopped; 12107eb8f069SAndrzej Hajda 12117eb8f069SAndrzej Hajda xfer->tx_done = 0; 12127eb8f069SAndrzej Hajda xfer->rx_done = 0; 12137eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 12147eb8f069SAndrzej Hajda init_completion(&xfer->completed); 12157eb8f069SAndrzej Hajda 12167eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 12177eb8f069SAndrzej Hajda 12187eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 12197eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 12207eb8f069SAndrzej Hajda 12217eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 12227eb8f069SAndrzej Hajda 12237eb8f069SAndrzej Hajda if (stopped) 12247eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12257eb8f069SAndrzej Hajda 12267eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 12277eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 12287eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 12297eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 12307eb8f069SAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, 12317eb8f069SAndrzej Hajda xfer->tx_len, xfer->tx_payload); 12327eb8f069SAndrzej Hajda return -ETIMEDOUT; 12337eb8f069SAndrzej Hajda } 12347eb8f069SAndrzej Hajda 12357eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 12367eb8f069SAndrzej Hajda return xfer->result; 12377eb8f069SAndrzej Hajda } 12387eb8f069SAndrzej Hajda 12397eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 12407eb8f069SAndrzej Hajda { 12417eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 12427eb8f069SAndrzej Hajda u32 status; 12437eb8f069SAndrzej Hajda 1244ba12ac2bSHyungwon Hwang status = DSI_READ(dsi, DSIM_INTSRC_REG); 12457eb8f069SAndrzej Hajda if (!status) { 12467eb8f069SAndrzej Hajda static unsigned long int j; 12477eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 12487eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 12497eb8f069SAndrzej Hajda return IRQ_HANDLED; 12507eb8f069SAndrzej Hajda } 1251ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_INTSRC_REG, status); 12527eb8f069SAndrzej Hajda 12537eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 1254e6f988a4SHyungwon Hwang u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1255e6f988a4SHyungwon Hwang DSIM_INT_SFR_HDR_FIFO_EMPTY | DSIM_INT_FRAME_DONE | 1256e6f988a4SHyungwon Hwang DSIM_INT_RX_ECC_ERR | DSIM_INT_SW_RST_RELEASE); 1257ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); 12587eb8f069SAndrzej Hajda complete(&dsi->completed); 12597eb8f069SAndrzej Hajda return IRQ_HANDLED; 12607eb8f069SAndrzej Hajda } 12617eb8f069SAndrzej Hajda 1262e6f988a4SHyungwon Hwang if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1263e6f988a4SHyungwon Hwang DSIM_INT_FRAME_DONE | DSIM_INT_PLL_STABLE))) 12647eb8f069SAndrzej Hajda return IRQ_HANDLED; 12657eb8f069SAndrzej Hajda 12667eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 12677eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12687eb8f069SAndrzej Hajda 12697eb8f069SAndrzej Hajda return IRQ_HANDLED; 12707eb8f069SAndrzej Hajda } 12717eb8f069SAndrzej Hajda 1272e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1273e17ddeccSYoungJun Cho { 1274e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 12752b8376c8SGustavo Padovan struct drm_encoder *encoder = &dsi->encoder; 1276e17ddeccSYoungJun Cho 12770e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1278e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1279e17ddeccSYoungJun Cho 1280e17ddeccSYoungJun Cho return IRQ_HANDLED; 1281e17ddeccSYoungJun Cho } 1282e17ddeccSYoungJun Cho 1283e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1284e17ddeccSYoungJun Cho { 1285e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1286e17ddeccSYoungJun Cho 1287e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1288e17ddeccSYoungJun Cho enable_irq(gpio_to_irq(dsi->te_gpio)); 1289e17ddeccSYoungJun Cho } 1290e17ddeccSYoungJun Cho 1291e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1292e17ddeccSYoungJun Cho { 1293e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1294e17ddeccSYoungJun Cho disable_irq(gpio_to_irq(dsi->te_gpio)); 1295e17ddeccSYoungJun Cho 1296e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1297e17ddeccSYoungJun Cho } 1298e17ddeccSYoungJun Cho 12997eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 13007eb8f069SAndrzej Hajda { 1301d668e8bfSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1302d668e8bfSHyungwon Hwang 13037eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1304e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 1305e6f988a4SHyungwon Hwang 1306e6f988a4SHyungwon Hwang if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1307e6f988a4SHyungwon Hwang exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); 1308e6f988a4SHyungwon Hwang 13099a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1310d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 13117eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 13129a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 13137eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 13147eb8f069SAndrzej Hajda 13157eb8f069SAndrzej Hajda return 0; 13167eb8f069SAndrzej Hajda } 13177eb8f069SAndrzej Hajda 1318e17ddeccSYoungJun Cho static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1319e17ddeccSYoungJun Cho { 1320e17ddeccSYoungJun Cho int ret; 13210cef83a5SYoungJun Cho int te_gpio_irq; 1322e17ddeccSYoungJun Cho 1323e17ddeccSYoungJun Cho dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 1324e17ddeccSYoungJun Cho if (!gpio_is_valid(dsi->te_gpio)) { 1325e17ddeccSYoungJun Cho dev_err(dsi->dev, "no te-gpios specified\n"); 1326e17ddeccSYoungJun Cho ret = dsi->te_gpio; 1327e17ddeccSYoungJun Cho goto out; 1328e17ddeccSYoungJun Cho } 1329e17ddeccSYoungJun Cho 133051d1decaSHyungwon Hwang ret = gpio_request(dsi->te_gpio, "te_gpio"); 1331e17ddeccSYoungJun Cho if (ret) { 1332e17ddeccSYoungJun Cho dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1333e17ddeccSYoungJun Cho goto out; 1334e17ddeccSYoungJun Cho } 1335e17ddeccSYoungJun Cho 13360cef83a5SYoungJun Cho te_gpio_irq = gpio_to_irq(dsi->te_gpio); 13370cef83a5SYoungJun Cho irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 133851d1decaSHyungwon Hwang 13390cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1340e17ddeccSYoungJun Cho IRQF_TRIGGER_RISING, "TE", dsi); 1341e17ddeccSYoungJun Cho if (ret) { 1342e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1343e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1344e17ddeccSYoungJun Cho goto out; 1345e17ddeccSYoungJun Cho } 1346e17ddeccSYoungJun Cho 1347e17ddeccSYoungJun Cho out: 1348e17ddeccSYoungJun Cho return ret; 1349e17ddeccSYoungJun Cho } 1350e17ddeccSYoungJun Cho 1351e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1352e17ddeccSYoungJun Cho { 1353e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) { 1354e17ddeccSYoungJun Cho free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1355e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1356e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1357e17ddeccSYoungJun Cho } 1358e17ddeccSYoungJun Cho } 1359e17ddeccSYoungJun Cho 13607eb8f069SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 13617eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 13627eb8f069SAndrzej Hajda { 13637eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 13647eb8f069SAndrzej Hajda 13657eb8f069SAndrzej Hajda dsi->lanes = device->lanes; 13667eb8f069SAndrzej Hajda dsi->format = device->format; 13677eb8f069SAndrzej Hajda dsi->mode_flags = device->mode_flags; 13687eb8f069SAndrzej Hajda dsi->panel_node = device->dev.of_node; 13697eb8f069SAndrzej Hajda 1370e17ddeccSYoungJun Cho /* 1371e17ddeccSYoungJun Cho * This is a temporary solution and should be made by more generic way. 1372e17ddeccSYoungJun Cho * 1373e17ddeccSYoungJun Cho * If attached panel device is for command mode one, dsi should register 1374e17ddeccSYoungJun Cho * TE interrupt handler. 1375e17ddeccSYoungJun Cho */ 1376e17ddeccSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1377e17ddeccSYoungJun Cho int ret = exynos_dsi_register_te_irq(dsi); 1378e17ddeccSYoungJun Cho 1379e17ddeccSYoungJun Cho if (ret) 1380e17ddeccSYoungJun Cho return ret; 1381e17ddeccSYoungJun Cho } 1382e17ddeccSYoungJun Cho 1383ecb84157SYoungJun Cho if (dsi->connector.dev) 1384ecb84157SYoungJun Cho drm_helper_hpd_irq_event(dsi->connector.dev); 1385ecb84157SYoungJun Cho 13867eb8f069SAndrzej Hajda return 0; 13877eb8f069SAndrzej Hajda } 13887eb8f069SAndrzej Hajda 13897eb8f069SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 13907eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 13917eb8f069SAndrzej Hajda { 13927eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 13937eb8f069SAndrzej Hajda 1394e17ddeccSYoungJun Cho exynos_dsi_unregister_te_irq(dsi); 1395e17ddeccSYoungJun Cho 13967eb8f069SAndrzej Hajda dsi->panel_node = NULL; 13977eb8f069SAndrzej Hajda 13987eb8f069SAndrzej Hajda if (dsi->connector.dev) 13997eb8f069SAndrzej Hajda drm_helper_hpd_irq_event(dsi->connector.dev); 14007eb8f069SAndrzej Hajda 14017eb8f069SAndrzej Hajda return 0; 14027eb8f069SAndrzej Hajda } 14037eb8f069SAndrzej Hajda 14047eb8f069SAndrzej Hajda /* distinguish between short and long DSI packet types */ 14057eb8f069SAndrzej Hajda static bool exynos_dsi_is_short_dsi_type(u8 type) 14067eb8f069SAndrzej Hajda { 14077eb8f069SAndrzej Hajda return (type & 0x0f) <= 8; 14087eb8f069SAndrzej Hajda } 14097eb8f069SAndrzej Hajda 14107eb8f069SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1411ed6ff40eSThierry Reding const struct mipi_dsi_msg *msg) 14127eb8f069SAndrzej Hajda { 14137eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 14147eb8f069SAndrzej Hajda struct exynos_dsi_transfer xfer; 14157eb8f069SAndrzej Hajda int ret; 14167eb8f069SAndrzej Hajda 14170e480f6fSHyungwon Hwang if (!(dsi->state & DSIM_STATE_ENABLED)) 14180e480f6fSHyungwon Hwang return -EINVAL; 14190e480f6fSHyungwon Hwang 14207eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 14217eb8f069SAndrzej Hajda ret = exynos_dsi_init(dsi); 14227eb8f069SAndrzej Hajda if (ret) 14237eb8f069SAndrzej Hajda return ret; 14247eb8f069SAndrzej Hajda dsi->state |= DSIM_STATE_INITIALIZED; 14257eb8f069SAndrzej Hajda } 14267eb8f069SAndrzej Hajda 14277eb8f069SAndrzej Hajda if (msg->tx_len == 0) 14287eb8f069SAndrzej Hajda return -EINVAL; 14297eb8f069SAndrzej Hajda 14307eb8f069SAndrzej Hajda xfer.data_id = msg->type | (msg->channel << 6); 14317eb8f069SAndrzej Hajda 14327eb8f069SAndrzej Hajda if (exynos_dsi_is_short_dsi_type(msg->type)) { 14337eb8f069SAndrzej Hajda const char *tx_buf = msg->tx_buf; 14347eb8f069SAndrzej Hajda 14357eb8f069SAndrzej Hajda if (msg->tx_len > 2) 14367eb8f069SAndrzej Hajda return -EINVAL; 14377eb8f069SAndrzej Hajda xfer.tx_len = 0; 14387eb8f069SAndrzej Hajda xfer.data[0] = tx_buf[0]; 14397eb8f069SAndrzej Hajda xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; 14407eb8f069SAndrzej Hajda } else { 14417eb8f069SAndrzej Hajda xfer.tx_len = msg->tx_len; 14427eb8f069SAndrzej Hajda xfer.data[0] = msg->tx_len & 0xff; 14437eb8f069SAndrzej Hajda xfer.data[1] = msg->tx_len >> 8; 14447eb8f069SAndrzej Hajda xfer.tx_payload = msg->tx_buf; 14457eb8f069SAndrzej Hajda } 14467eb8f069SAndrzej Hajda 14477eb8f069SAndrzej Hajda xfer.rx_len = msg->rx_len; 14487eb8f069SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 14497eb8f069SAndrzej Hajda xfer.flags = msg->flags; 14507eb8f069SAndrzej Hajda 14517eb8f069SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 14527eb8f069SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 14537eb8f069SAndrzej Hajda } 14547eb8f069SAndrzej Hajda 14557eb8f069SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 14567eb8f069SAndrzej Hajda .attach = exynos_dsi_host_attach, 14577eb8f069SAndrzej Hajda .detach = exynos_dsi_host_detach, 14587eb8f069SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 14597eb8f069SAndrzej Hajda }; 14607eb8f069SAndrzej Hajda 14617eb8f069SAndrzej Hajda static int exynos_dsi_poweron(struct exynos_dsi *dsi) 14627eb8f069SAndrzej Hajda { 14630ff03fd1SHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 14640ff03fd1SHyungwon Hwang int ret, i; 14657eb8f069SAndrzej Hajda 14667eb8f069SAndrzej Hajda ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 14677eb8f069SAndrzej Hajda if (ret < 0) { 14687eb8f069SAndrzej Hajda dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 14697eb8f069SAndrzej Hajda return ret; 14707eb8f069SAndrzej Hajda } 14717eb8f069SAndrzej Hajda 14720ff03fd1SHyungwon Hwang for (i = 0; i < driver_data->num_clks; i++) { 14730ff03fd1SHyungwon Hwang ret = clk_prepare_enable(dsi->clks[i]); 14740ff03fd1SHyungwon Hwang if (ret < 0) 14750ff03fd1SHyungwon Hwang goto err_clk; 14767eb8f069SAndrzej Hajda } 14777eb8f069SAndrzej Hajda 14787eb8f069SAndrzej Hajda ret = phy_power_on(dsi->phy); 14797eb8f069SAndrzej Hajda if (ret < 0) { 14807eb8f069SAndrzej Hajda dev_err(dsi->dev, "cannot enable phy %d\n", ret); 14810ff03fd1SHyungwon Hwang goto err_clk; 14827eb8f069SAndrzej Hajda } 14837eb8f069SAndrzej Hajda 14847eb8f069SAndrzej Hajda return 0; 14857eb8f069SAndrzej Hajda 14860ff03fd1SHyungwon Hwang err_clk: 14870ff03fd1SHyungwon Hwang while (--i > -1) 14880ff03fd1SHyungwon Hwang clk_disable_unprepare(dsi->clks[i]); 14897eb8f069SAndrzej Hajda regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 14907eb8f069SAndrzej Hajda 14917eb8f069SAndrzej Hajda return ret; 14927eb8f069SAndrzej Hajda } 14937eb8f069SAndrzej Hajda 14947eb8f069SAndrzej Hajda static void exynos_dsi_poweroff(struct exynos_dsi *dsi) 14957eb8f069SAndrzej Hajda { 14960ff03fd1SHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 14970ff03fd1SHyungwon Hwang int ret, i; 14987eb8f069SAndrzej Hajda 14997eb8f069SAndrzej Hajda usleep_range(10000, 20000); 15007eb8f069SAndrzej Hajda 15017eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_INITIALIZED) { 15027eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_INITIALIZED; 15037eb8f069SAndrzej Hajda 15047eb8f069SAndrzej Hajda exynos_dsi_disable_clock(dsi); 15057eb8f069SAndrzej Hajda 1506e17ddeccSYoungJun Cho exynos_dsi_disable_irq(dsi); 15077eb8f069SAndrzej Hajda } 15087eb8f069SAndrzej Hajda 15097eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_CMD_LPM; 15107eb8f069SAndrzej Hajda 15117eb8f069SAndrzej Hajda phy_power_off(dsi->phy); 15127eb8f069SAndrzej Hajda 15130ff03fd1SHyungwon Hwang for (i = driver_data->num_clks - 1; i > -1; i--) 15140ff03fd1SHyungwon Hwang clk_disable_unprepare(dsi->clks[i]); 15157eb8f069SAndrzej Hajda 15167eb8f069SAndrzej Hajda ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 15177eb8f069SAndrzej Hajda if (ret < 0) 15187eb8f069SAndrzej Hajda dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 15197eb8f069SAndrzej Hajda } 15207eb8f069SAndrzej Hajda 15212b8376c8SGustavo Padovan static void exynos_dsi_enable(struct drm_encoder *encoder) 15227eb8f069SAndrzej Hajda { 1523cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 15247eb8f069SAndrzej Hajda int ret; 15257eb8f069SAndrzej Hajda 15267eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 1527b6595dc7SGustavo Padovan return; 15287eb8f069SAndrzej Hajda 15297eb8f069SAndrzej Hajda ret = exynos_dsi_poweron(dsi); 15307eb8f069SAndrzej Hajda if (ret < 0) 1531b6595dc7SGustavo Padovan return; 15327eb8f069SAndrzej Hajda 15330e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 15340e480f6fSHyungwon Hwang 1535cdfb8694SAjay Kumar ret = drm_panel_prepare(dsi->panel); 15367eb8f069SAndrzej Hajda if (ret < 0) { 15370e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_ENABLED; 15387eb8f069SAndrzej Hajda exynos_dsi_poweroff(dsi); 1539b6595dc7SGustavo Padovan return; 15407eb8f069SAndrzej Hajda } 15417eb8f069SAndrzej Hajda 15427eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 15437eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 15447eb8f069SAndrzej Hajda 1545cdfb8694SAjay Kumar ret = drm_panel_enable(dsi->panel); 1546cdfb8694SAjay Kumar if (ret < 0) { 1547d41bb38fSYoungJun Cho dsi->state &= ~DSIM_STATE_ENABLED; 1548cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1549cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 1550cdfb8694SAjay Kumar exynos_dsi_poweroff(dsi); 1551b6595dc7SGustavo Padovan return; 1552cdfb8694SAjay Kumar } 1553cdfb8694SAjay Kumar 15540e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 15557eb8f069SAndrzej Hajda } 15567eb8f069SAndrzej Hajda 15572b8376c8SGustavo Padovan static void exynos_dsi_disable(struct drm_encoder *encoder) 15587eb8f069SAndrzej Hajda { 1559cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1560b6595dc7SGustavo Padovan 15617eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 15627eb8f069SAndrzej Hajda return; 15637eb8f069SAndrzej Hajda 15640e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 15650e480f6fSHyungwon Hwang 15667eb8f069SAndrzej Hajda drm_panel_disable(dsi->panel); 1567cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1568cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 15697eb8f069SAndrzej Hajda 15707eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 15710e480f6fSHyungwon Hwang 15720e480f6fSHyungwon Hwang exynos_dsi_poweroff(dsi); 15737eb8f069SAndrzej Hajda } 15747eb8f069SAndrzej Hajda 15757eb8f069SAndrzej Hajda static enum drm_connector_status 15767eb8f069SAndrzej Hajda exynos_dsi_detect(struct drm_connector *connector, bool force) 15777eb8f069SAndrzej Hajda { 15787eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15797eb8f069SAndrzej Hajda 15807eb8f069SAndrzej Hajda if (!dsi->panel) { 15817eb8f069SAndrzej Hajda dsi->panel = of_drm_find_panel(dsi->panel_node); 15827eb8f069SAndrzej Hajda if (dsi->panel) 15837eb8f069SAndrzej Hajda drm_panel_attach(dsi->panel, &dsi->connector); 15847eb8f069SAndrzej Hajda } else if (!dsi->panel_node) { 15852b8376c8SGustavo Padovan struct drm_encoder *encoder; 15867eb8f069SAndrzej Hajda 1587cf67cc9aSGustavo Padovan encoder = platform_get_drvdata(to_platform_device(dsi->dev)); 1588cf67cc9aSGustavo Padovan exynos_dsi_disable(encoder); 15897eb8f069SAndrzej Hajda drm_panel_detach(dsi->panel); 15907eb8f069SAndrzej Hajda dsi->panel = NULL; 15917eb8f069SAndrzej Hajda } 15927eb8f069SAndrzej Hajda 15937eb8f069SAndrzej Hajda if (dsi->panel) 15947eb8f069SAndrzej Hajda return connector_status_connected; 15957eb8f069SAndrzej Hajda 15967eb8f069SAndrzej Hajda return connector_status_disconnected; 15977eb8f069SAndrzej Hajda } 15987eb8f069SAndrzej Hajda 15997eb8f069SAndrzej Hajda static void exynos_dsi_connector_destroy(struct drm_connector *connector) 16007eb8f069SAndrzej Hajda { 16010ae46015SAndrzej Hajda drm_connector_unregister(connector); 16020ae46015SAndrzej Hajda drm_connector_cleanup(connector); 16030ae46015SAndrzej Hajda connector->dev = NULL; 16047eb8f069SAndrzej Hajda } 16057eb8f069SAndrzej Hajda 16067eb8f069SAndrzej Hajda static struct drm_connector_funcs exynos_dsi_connector_funcs = { 160763498e30SGustavo Padovan .dpms = drm_atomic_helper_connector_dpms, 16087eb8f069SAndrzej Hajda .detect = exynos_dsi_detect, 16097eb8f069SAndrzej Hajda .fill_modes = drm_helper_probe_single_connector_modes, 16107eb8f069SAndrzej Hajda .destroy = exynos_dsi_connector_destroy, 16114ea9526bSGustavo Padovan .reset = drm_atomic_helper_connector_reset, 16124ea9526bSGustavo Padovan .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 16134ea9526bSGustavo Padovan .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 16147eb8f069SAndrzej Hajda }; 16157eb8f069SAndrzej Hajda 16167eb8f069SAndrzej Hajda static int exynos_dsi_get_modes(struct drm_connector *connector) 16177eb8f069SAndrzej Hajda { 16187eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 16197eb8f069SAndrzej Hajda 16207eb8f069SAndrzej Hajda if (dsi->panel) 16217eb8f069SAndrzej Hajda return dsi->panel->funcs->get_modes(dsi->panel); 16227eb8f069SAndrzej Hajda 16237eb8f069SAndrzej Hajda return 0; 16247eb8f069SAndrzej Hajda } 16257eb8f069SAndrzej Hajda 16267eb8f069SAndrzej Hajda static struct drm_encoder * 16277eb8f069SAndrzej Hajda exynos_dsi_best_encoder(struct drm_connector *connector) 16287eb8f069SAndrzej Hajda { 16297eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 16307eb8f069SAndrzej Hajda 16312b8376c8SGustavo Padovan return &dsi->encoder; 16327eb8f069SAndrzej Hajda } 16337eb8f069SAndrzej Hajda 16347eb8f069SAndrzej Hajda static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 16357eb8f069SAndrzej Hajda .get_modes = exynos_dsi_get_modes, 16367eb8f069SAndrzej Hajda .best_encoder = exynos_dsi_best_encoder, 16377eb8f069SAndrzej Hajda }; 16387eb8f069SAndrzej Hajda 16392b8376c8SGustavo Padovan static int exynos_dsi_create_connector(struct drm_encoder *encoder) 16407eb8f069SAndrzej Hajda { 16412b8376c8SGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 16427eb8f069SAndrzej Hajda struct drm_connector *connector = &dsi->connector; 16437eb8f069SAndrzej Hajda int ret; 16447eb8f069SAndrzej Hajda 16457eb8f069SAndrzej Hajda connector->polled = DRM_CONNECTOR_POLL_HPD; 16467eb8f069SAndrzej Hajda 16477eb8f069SAndrzej Hajda ret = drm_connector_init(encoder->dev, connector, 16487eb8f069SAndrzej Hajda &exynos_dsi_connector_funcs, 16497eb8f069SAndrzej Hajda DRM_MODE_CONNECTOR_DSI); 16507eb8f069SAndrzej Hajda if (ret) { 16517eb8f069SAndrzej Hajda DRM_ERROR("Failed to initialize connector with drm\n"); 16527eb8f069SAndrzej Hajda return ret; 16537eb8f069SAndrzej Hajda } 16547eb8f069SAndrzej Hajda 16557eb8f069SAndrzej Hajda drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 165634ea3d38SThomas Wood drm_connector_register(connector); 16577eb8f069SAndrzej Hajda drm_mode_connector_attach_encoder(connector, encoder); 16587eb8f069SAndrzej Hajda 16597eb8f069SAndrzej Hajda return 0; 16607eb8f069SAndrzej Hajda } 16617eb8f069SAndrzej Hajda 16622b8376c8SGustavo Padovan static bool exynos_dsi_mode_fixup(struct drm_encoder *encoder, 16632b8376c8SGustavo Padovan const struct drm_display_mode *mode, 16642b8376c8SGustavo Padovan struct drm_display_mode *adjusted_mode) 16652b8376c8SGustavo Padovan { 16662b8376c8SGustavo Padovan return true; 16672b8376c8SGustavo Padovan } 16682b8376c8SGustavo Padovan 16692b8376c8SGustavo Padovan static void exynos_dsi_mode_set(struct drm_encoder *encoder, 16702b8376c8SGustavo Padovan struct drm_display_mode *mode, 16712b8376c8SGustavo Padovan struct drm_display_mode *adjusted_mode) 16727eb8f069SAndrzej Hajda { 1673cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 16747eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 16752b8376c8SGustavo Padovan struct drm_display_mode *m = adjusted_mode; 16767eb8f069SAndrzej Hajda 16772b8376c8SGustavo Padovan vm->hactive = m->hdisplay; 16782b8376c8SGustavo Padovan vm->vactive = m->vdisplay; 16792b8376c8SGustavo Padovan vm->vfront_porch = m->vsync_start - m->vdisplay; 16802b8376c8SGustavo Padovan vm->vback_porch = m->vtotal - m->vsync_end; 16812b8376c8SGustavo Padovan vm->vsync_len = m->vsync_end - m->vsync_start; 16822b8376c8SGustavo Padovan vm->hfront_porch = m->hsync_start - m->hdisplay; 16832b8376c8SGustavo Padovan vm->hback_porch = m->htotal - m->hsync_end; 16842b8376c8SGustavo Padovan vm->hsync_len = m->hsync_end - m->hsync_start; 16857eb8f069SAndrzej Hajda } 16867eb8f069SAndrzej Hajda 16872b8376c8SGustavo Padovan static struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = { 16882b8376c8SGustavo Padovan .mode_fixup = exynos_dsi_mode_fixup, 16897eb8f069SAndrzej Hajda .mode_set = exynos_dsi_mode_set, 1690b6595dc7SGustavo Padovan .enable = exynos_dsi_enable, 1691b6595dc7SGustavo Padovan .disable = exynos_dsi_disable, 16927eb8f069SAndrzej Hajda }; 16937eb8f069SAndrzej Hajda 16942b8376c8SGustavo Padovan static struct drm_encoder_funcs exynos_dsi_encoder_funcs = { 16952b8376c8SGustavo Padovan .destroy = drm_encoder_cleanup, 16962b8376c8SGustavo Padovan }; 16972b8376c8SGustavo Padovan 1698bd024b86SSjoerd Simons MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 16997eb8f069SAndrzej Hajda 17007eb8f069SAndrzej Hajda /* of_* functions will be removed after merge of of_graph patches */ 17017eb8f069SAndrzej Hajda static struct device_node * 17027eb8f069SAndrzej Hajda of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) 17037eb8f069SAndrzej Hajda { 17047eb8f069SAndrzej Hajda struct device_node *np; 17057eb8f069SAndrzej Hajda 17067eb8f069SAndrzej Hajda for_each_child_of_node(parent, np) { 17077eb8f069SAndrzej Hajda u32 r; 17087eb8f069SAndrzej Hajda 17097eb8f069SAndrzej Hajda if (!np->name || of_node_cmp(np->name, name)) 17107eb8f069SAndrzej Hajda continue; 17117eb8f069SAndrzej Hajda 17127eb8f069SAndrzej Hajda if (of_property_read_u32(np, "reg", &r) < 0) 17137eb8f069SAndrzej Hajda r = 0; 17147eb8f069SAndrzej Hajda 17157eb8f069SAndrzej Hajda if (reg == r) 17167eb8f069SAndrzej Hajda break; 17177eb8f069SAndrzej Hajda } 17187eb8f069SAndrzej Hajda 17197eb8f069SAndrzej Hajda return np; 17207eb8f069SAndrzej Hajda } 17217eb8f069SAndrzej Hajda 17227eb8f069SAndrzej Hajda static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, 17237eb8f069SAndrzej Hajda u32 reg) 17247eb8f069SAndrzej Hajda { 17257eb8f069SAndrzej Hajda struct device_node *ports, *port; 17267eb8f069SAndrzej Hajda 17277eb8f069SAndrzej Hajda ports = of_get_child_by_name(parent, "ports"); 17287eb8f069SAndrzej Hajda if (ports) 17297eb8f069SAndrzej Hajda parent = ports; 17307eb8f069SAndrzej Hajda 17317eb8f069SAndrzej Hajda port = of_get_child_by_name_reg(parent, "port", reg); 17327eb8f069SAndrzej Hajda 17337eb8f069SAndrzej Hajda of_node_put(ports); 17347eb8f069SAndrzej Hajda 17357eb8f069SAndrzej Hajda return port; 17367eb8f069SAndrzej Hajda } 17377eb8f069SAndrzej Hajda 17387eb8f069SAndrzej Hajda static struct device_node * 17397eb8f069SAndrzej Hajda of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) 17407eb8f069SAndrzej Hajda { 17417eb8f069SAndrzej Hajda return of_get_child_by_name_reg(port, "endpoint", reg); 17427eb8f069SAndrzej Hajda } 17437eb8f069SAndrzej Hajda 17447eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 17457eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 17467eb8f069SAndrzej Hajda { 17477eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 17487eb8f069SAndrzej Hajda 17497eb8f069SAndrzej Hajda if (ret < 0) 17507eb8f069SAndrzej Hajda pr_err("%s: failed to get '%s' property\n", np->full_name, 17517eb8f069SAndrzej Hajda propname); 17527eb8f069SAndrzej Hajda 17537eb8f069SAndrzej Hajda return ret; 17547eb8f069SAndrzej Hajda } 17557eb8f069SAndrzej Hajda 17567eb8f069SAndrzej Hajda enum { 17577eb8f069SAndrzej Hajda DSI_PORT_IN, 17587eb8f069SAndrzej Hajda DSI_PORT_OUT 17597eb8f069SAndrzej Hajda }; 17607eb8f069SAndrzej Hajda 17617eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 17627eb8f069SAndrzej Hajda { 17637eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 17647eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 17657eb8f069SAndrzej Hajda struct device_node *port, *ep; 17667eb8f069SAndrzej Hajda int ret; 17677eb8f069SAndrzej Hajda 17687eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 17697eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 17707eb8f069SAndrzej Hajda if (ret < 0) 17717eb8f069SAndrzej Hajda return ret; 17727eb8f069SAndrzej Hajda 17737eb8f069SAndrzej Hajda port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); 17747eb8f069SAndrzej Hajda if (!port) { 17757eb8f069SAndrzej Hajda dev_err(dev, "no output port specified\n"); 17767eb8f069SAndrzej Hajda return -EINVAL; 17777eb8f069SAndrzej Hajda } 17787eb8f069SAndrzej Hajda 17797eb8f069SAndrzej Hajda ep = of_graph_get_endpoint_by_reg(port, 0); 17807eb8f069SAndrzej Hajda of_node_put(port); 17817eb8f069SAndrzej Hajda if (!ep) { 17827eb8f069SAndrzej Hajda dev_err(dev, "no endpoint specified in output port\n"); 17837eb8f069SAndrzej Hajda return -EINVAL; 17847eb8f069SAndrzej Hajda } 17857eb8f069SAndrzej Hajda 17867eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", 17877eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 17887eb8f069SAndrzej Hajda if (ret < 0) 17897eb8f069SAndrzej Hajda goto end; 17907eb8f069SAndrzej Hajda 17917eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", 17927eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 1793f5f3b9baSHyungwon Hwang if (ret < 0) 1794f5f3b9baSHyungwon Hwang goto end; 17957eb8f069SAndrzej Hajda 1796f5f3b9baSHyungwon Hwang of_node_put(ep); 1797f5f3b9baSHyungwon Hwang 1798f5f3b9baSHyungwon Hwang ep = of_graph_get_next_endpoint(node, NULL); 1799f5f3b9baSHyungwon Hwang if (!ep) { 1800f5f3b9baSHyungwon Hwang ret = -ENXIO; 1801f5f3b9baSHyungwon Hwang goto end; 1802f5f3b9baSHyungwon Hwang } 1803f5f3b9baSHyungwon Hwang 1804f5f3b9baSHyungwon Hwang dsi->bridge_node = of_graph_get_remote_port_parent(ep); 1805f5f3b9baSHyungwon Hwang if (!dsi->bridge_node) { 1806f5f3b9baSHyungwon Hwang ret = -ENXIO; 1807f5f3b9baSHyungwon Hwang goto end; 1808f5f3b9baSHyungwon Hwang } 18097eb8f069SAndrzej Hajda end: 18107eb8f069SAndrzej Hajda of_node_put(ep); 18117eb8f069SAndrzej Hajda 18127eb8f069SAndrzej Hajda return ret; 18137eb8f069SAndrzej Hajda } 18147eb8f069SAndrzej Hajda 1815f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1816f37cd5e8SInki Dae void *data) 1817f37cd5e8SInki Dae { 18182b8376c8SGustavo Padovan struct drm_encoder *encoder = dev_get_drvdata(dev); 18192b8376c8SGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1820f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1821f5f3b9baSHyungwon Hwang struct drm_bridge *bridge; 1822f37cd5e8SInki Dae int ret; 1823f37cd5e8SInki Dae 18242b8376c8SGustavo Padovan ret = exynos_drm_crtc_get_pipe_from_type(drm_dev, 1825cf67cc9aSGustavo Padovan EXYNOS_DISPLAY_TYPE_LCD); 18262b8376c8SGustavo Padovan if (ret < 0) 1827a2986e80SGustavo Padovan return ret; 1828a2986e80SGustavo Padovan 18292b8376c8SGustavo Padovan encoder->possible_crtcs = 1 << ret; 18302b8376c8SGustavo Padovan 18312b8376c8SGustavo Padovan DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs); 18322b8376c8SGustavo Padovan 18332b8376c8SGustavo Padovan drm_encoder_init(drm_dev, encoder, &exynos_dsi_encoder_funcs, 183413a3d91fSVille Syrjälä DRM_MODE_ENCODER_TMDS, NULL); 18352b8376c8SGustavo Padovan 18362b8376c8SGustavo Padovan drm_encoder_helper_add(encoder, &exynos_dsi_encoder_helper_funcs); 18372b8376c8SGustavo Padovan 18382b8376c8SGustavo Padovan ret = exynos_dsi_create_connector(encoder); 1839a2986e80SGustavo Padovan if (ret) { 1840a2986e80SGustavo Padovan DRM_ERROR("failed to create connector ret = %d\n", ret); 18412b8376c8SGustavo Padovan drm_encoder_cleanup(encoder); 1842f37cd5e8SInki Dae return ret; 1843f37cd5e8SInki Dae } 1844f37cd5e8SInki Dae 1845f5f3b9baSHyungwon Hwang bridge = of_drm_find_bridge(dsi->bridge_node); 1846f5f3b9baSHyungwon Hwang if (bridge) { 1847f5f3b9baSHyungwon Hwang drm_bridge_attach(drm_dev, bridge); 1848f5f3b9baSHyungwon Hwang } 1849f5f3b9baSHyungwon Hwang 1850f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1851f37cd5e8SInki Dae } 1852f37cd5e8SInki Dae 1853f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1854f37cd5e8SInki Dae void *data) 1855f37cd5e8SInki Dae { 18562b8376c8SGustavo Padovan struct drm_encoder *encoder = dev_get_drvdata(dev); 1857cf67cc9aSGustavo Padovan struct exynos_dsi *dsi = encoder_to_dsi(encoder); 1858f37cd5e8SInki Dae 1859cf67cc9aSGustavo Padovan exynos_dsi_disable(encoder); 1860f37cd5e8SInki Dae 18610ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1862f37cd5e8SInki Dae } 1863f37cd5e8SInki Dae 1864f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1865f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1866f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1867f37cd5e8SInki Dae }; 1868f37cd5e8SInki Dae 18697eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 18707eb8f069SAndrzej Hajda { 18712900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 18727eb8f069SAndrzej Hajda struct resource *res; 18737eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 18740ff03fd1SHyungwon Hwang int ret, i; 18757eb8f069SAndrzej Hajda 18762900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 18772900c69cSAndrzej Hajda if (!dsi) 18782900c69cSAndrzej Hajda return -ENOMEM; 18792900c69cSAndrzej Hajda 1880e17ddeccSYoungJun Cho /* To be checked as invalid one */ 1881e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1882e17ddeccSYoungJun Cho 18837eb8f069SAndrzej Hajda init_completion(&dsi->completed); 18847eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 18857eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 18867eb8f069SAndrzej Hajda 18877eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1888e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 18897eb8f069SAndrzej Hajda 1890e2d2a1e0SAndrzej Hajda dsi->dev = dev; 18919a320415SYoungJun Cho dsi->driver_data = exynos_dsi_get_driver_data(pdev); 18927eb8f069SAndrzej Hajda 18937eb8f069SAndrzej Hajda ret = exynos_dsi_parse_dt(dsi); 18947eb8f069SAndrzej Hajda if (ret) 189586650408SAndrzej Hajda return ret; 18967eb8f069SAndrzej Hajda 18977eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 18987eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1899e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 19007eb8f069SAndrzej Hajda dsi->supplies); 19017eb8f069SAndrzej Hajda if (ret) { 1902e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get regulators: %d\n", ret); 19037eb8f069SAndrzej Hajda return -EPROBE_DEFER; 19047eb8f069SAndrzej Hajda } 19057eb8f069SAndrzej Hajda 19060ff03fd1SHyungwon Hwang dsi->clks = devm_kzalloc(dev, 19070ff03fd1SHyungwon Hwang sizeof(*dsi->clks) * dsi->driver_data->num_clks, 19080ff03fd1SHyungwon Hwang GFP_KERNEL); 1909e6f988a4SHyungwon Hwang if (!dsi->clks) 1910e6f988a4SHyungwon Hwang return -ENOMEM; 1911e6f988a4SHyungwon Hwang 19120ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 19130ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 19140ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 19150ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 19160ff03fd1SHyungwon Hwang strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 19170ff03fd1SHyungwon Hwang i--; 19180ff03fd1SHyungwon Hwang continue; 19197eb8f069SAndrzej Hajda } 19207eb8f069SAndrzej Hajda 19210ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 19220ff03fd1SHyungwon Hwang clk_names[i]); 19230ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 19240ff03fd1SHyungwon Hwang } 19257eb8f069SAndrzej Hajda } 19267eb8f069SAndrzej Hajda 19277eb8f069SAndrzej Hajda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1928e2d2a1e0SAndrzej Hajda dsi->reg_base = devm_ioremap_resource(dev, res); 1929293d3f6aSJingoo Han if (IS_ERR(dsi->reg_base)) { 1930e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to remap io region\n"); 193186650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 19327eb8f069SAndrzej Hajda } 19337eb8f069SAndrzej Hajda 1934e2d2a1e0SAndrzej Hajda dsi->phy = devm_phy_get(dev, "dsim"); 19357eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1936e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 193786650408SAndrzej Hajda return PTR_ERR(dsi->phy); 19387eb8f069SAndrzej Hajda } 19397eb8f069SAndrzej Hajda 19407eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 19417eb8f069SAndrzej Hajda if (dsi->irq < 0) { 1942e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq resource\n"); 194386650408SAndrzej Hajda return dsi->irq; 19447eb8f069SAndrzej Hajda } 19457eb8f069SAndrzej Hajda 19467eb8f069SAndrzej Hajda irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1947e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 19487eb8f069SAndrzej Hajda exynos_dsi_irq, IRQF_ONESHOT, 1949e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 19507eb8f069SAndrzej Hajda if (ret) { 1951e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 195286650408SAndrzej Hajda return ret; 19537eb8f069SAndrzej Hajda } 19547eb8f069SAndrzej Hajda 1955cf67cc9aSGustavo Padovan platform_set_drvdata(pdev, &dsi->encoder); 19567eb8f069SAndrzej Hajda 195786650408SAndrzej Hajda return component_add(dev, &exynos_dsi_component_ops); 19587eb8f069SAndrzej Hajda } 19597eb8f069SAndrzej Hajda 19607eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 19617eb8f069SAndrzej Hajda { 1962df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1963df5225bcSInki Dae 19647eb8f069SAndrzej Hajda return 0; 19657eb8f069SAndrzej Hajda } 19667eb8f069SAndrzej Hajda 19677eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 19687eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 19697eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 19707eb8f069SAndrzej Hajda .driver = { 19717eb8f069SAndrzej Hajda .name = "exynos-dsi", 19727eb8f069SAndrzej Hajda .owner = THIS_MODULE, 19737eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 19747eb8f069SAndrzej Hajda }, 19757eb8f069SAndrzej Hajda }; 19767eb8f069SAndrzej Hajda 19777eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 19787eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 19797eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 19807eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 1981