17eb8f069SAndrzej Hajda /* 27eb8f069SAndrzej Hajda * Samsung SoC MIPI DSI Master driver. 37eb8f069SAndrzej Hajda * 47eb8f069SAndrzej Hajda * Copyright (c) 2014 Samsung Electronics Co., Ltd 57eb8f069SAndrzej Hajda * 67eb8f069SAndrzej Hajda * Contacts: Tomasz Figa <t.figa@samsung.com> 77eb8f069SAndrzej Hajda * 87eb8f069SAndrzej Hajda * This program is free software; you can redistribute it and/or modify 97eb8f069SAndrzej Hajda * it under the terms of the GNU General Public License version 2 as 107eb8f069SAndrzej Hajda * published by the Free Software Foundation. 117eb8f069SAndrzej Hajda */ 127eb8f069SAndrzej Hajda 137eb8f069SAndrzej Hajda #include <drm/drmP.h> 147eb8f069SAndrzej Hajda #include <drm/drm_crtc_helper.h> 157eb8f069SAndrzej Hajda #include <drm/drm_mipi_dsi.h> 167eb8f069SAndrzej Hajda #include <drm/drm_panel.h> 174ea9526bSGustavo Padovan #include <drm/drm_atomic_helper.h> 187eb8f069SAndrzej Hajda 197eb8f069SAndrzej Hajda #include <linux/clk.h> 20e17ddeccSYoungJun Cho #include <linux/gpio/consumer.h> 217eb8f069SAndrzej Hajda #include <linux/irq.h> 229a320415SYoungJun Cho #include <linux/of_device.h> 23e17ddeccSYoungJun Cho #include <linux/of_gpio.h> 247eb8f069SAndrzej Hajda #include <linux/phy/phy.h> 257eb8f069SAndrzej Hajda #include <linux/regulator/consumer.h> 26f37cd5e8SInki Dae #include <linux/component.h> 277eb8f069SAndrzej Hajda 287eb8f069SAndrzej Hajda #include <video/mipi_display.h> 297eb8f069SAndrzej Hajda #include <video/videomode.h> 307eb8f069SAndrzej Hajda 31e17ddeccSYoungJun Cho #include "exynos_drm_crtc.h" 327eb8f069SAndrzej Hajda #include "exynos_drm_drv.h" 337eb8f069SAndrzej Hajda 347eb8f069SAndrzej Hajda /* returns true iff both arguments logically differs */ 357eb8f069SAndrzej Hajda #define NEQV(a, b) (!(a) ^ !(b)) 367eb8f069SAndrzej Hajda 377eb8f069SAndrzej Hajda /* DSIM_STATUS */ 387eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 397eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CLK (1 << 8) 407eb8f069SAndrzej Hajda #define DSIM_TX_READY_HS_CLK (1 << 10) 417eb8f069SAndrzej Hajda #define DSIM_PLL_STABLE (1 << 31) 427eb8f069SAndrzej Hajda 437eb8f069SAndrzej Hajda /* DSIM_SWRST */ 447eb8f069SAndrzej Hajda #define DSIM_FUNCRST (1 << 16) 457eb8f069SAndrzej Hajda #define DSIM_SWRST (1 << 0) 467eb8f069SAndrzej Hajda 477eb8f069SAndrzej Hajda /* DSIM_TIMEOUT */ 487eb8f069SAndrzej Hajda #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 497eb8f069SAndrzej Hajda #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 507eb8f069SAndrzej Hajda 517eb8f069SAndrzej Hajda /* DSIM_CLKCTRL */ 527eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 537eb8f069SAndrzej Hajda #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 547eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19) 557eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 567eb8f069SAndrzej Hajda #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 577eb8f069SAndrzej Hajda #define DSIM_BYTE_CLKEN (1 << 24) 587eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 597eb8f069SAndrzej Hajda #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 607eb8f069SAndrzej Hajda #define DSIM_PLL_BYPASS (1 << 27) 617eb8f069SAndrzej Hajda #define DSIM_ESC_CLKEN (1 << 28) 627eb8f069SAndrzej Hajda #define DSIM_TX_REQUEST_HSCLK (1 << 31) 637eb8f069SAndrzej Hajda 647eb8f069SAndrzej Hajda /* DSIM_CONFIG */ 657eb8f069SAndrzej Hajda #define DSIM_LANE_EN_CLK (1 << 0) 667eb8f069SAndrzej Hajda #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 677eb8f069SAndrzej Hajda #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 687eb8f069SAndrzej Hajda #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 697eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 707eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 717eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 727eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 737eb8f069SAndrzej Hajda #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 747eb8f069SAndrzej Hajda #define DSIM_SUB_VC (((x) & 0x3) << 16) 757eb8f069SAndrzej Hajda #define DSIM_MAIN_VC (((x) & 0x3) << 18) 767eb8f069SAndrzej Hajda #define DSIM_HSA_MODE (1 << 20) 777eb8f069SAndrzej Hajda #define DSIM_HBP_MODE (1 << 21) 787eb8f069SAndrzej Hajda #define DSIM_HFP_MODE (1 << 22) 797eb8f069SAndrzej Hajda #define DSIM_HSE_MODE (1 << 23) 807eb8f069SAndrzej Hajda #define DSIM_AUTO_MODE (1 << 24) 817eb8f069SAndrzej Hajda #define DSIM_VIDEO_MODE (1 << 25) 827eb8f069SAndrzej Hajda #define DSIM_BURST_MODE (1 << 26) 837eb8f069SAndrzej Hajda #define DSIM_SYNC_INFORM (1 << 27) 847eb8f069SAndrzej Hajda #define DSIM_EOT_DISABLE (1 << 28) 857eb8f069SAndrzej Hajda #define DSIM_MFLUSH_VS (1 << 29) 8678d3a8c6SInki Dae /* This flag is valid only for exynos3250/3472/4415/5260/5430 */ 8778d3a8c6SInki Dae #define DSIM_CLKLANE_STOP (1 << 30) 887eb8f069SAndrzej Hajda 897eb8f069SAndrzej Hajda /* DSIM_ESCMODE */ 907eb8f069SAndrzej Hajda #define DSIM_TX_TRIGGER_RST (1 << 4) 917eb8f069SAndrzej Hajda #define DSIM_TX_LPDT_LP (1 << 6) 927eb8f069SAndrzej Hajda #define DSIM_CMD_LPDT_LP (1 << 7) 937eb8f069SAndrzej Hajda #define DSIM_FORCE_BTA (1 << 16) 947eb8f069SAndrzej Hajda #define DSIM_FORCE_STOP_STATE (1 << 20) 957eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 967eb8f069SAndrzej Hajda #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 977eb8f069SAndrzej Hajda 987eb8f069SAndrzej Hajda /* DSIM_MDRESOL */ 997eb8f069SAndrzej Hajda #define DSIM_MAIN_STAND_BY (1 << 31) 100d668e8bfSHyungwon Hwang #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 101d668e8bfSHyungwon Hwang #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 1027eb8f069SAndrzej Hajda 1037eb8f069SAndrzej Hajda /* DSIM_MVPORCH */ 1047eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW(x) ((x) << 28) 1057eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP(x) ((x) << 16) 1067eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP(x) ((x) << 0) 1077eb8f069SAndrzej Hajda #define DSIM_CMD_ALLOW_MASK (0xf << 28) 1087eb8f069SAndrzej Hajda #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 1097eb8f069SAndrzej Hajda #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 1107eb8f069SAndrzej Hajda 1117eb8f069SAndrzej Hajda /* DSIM_MHPORCH */ 1127eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP(x) ((x) << 16) 1137eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP(x) ((x) << 0) 1147eb8f069SAndrzej Hajda #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 1157eb8f069SAndrzej Hajda #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 1167eb8f069SAndrzej Hajda 1177eb8f069SAndrzej Hajda /* DSIM_MSYNC */ 1187eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA(x) ((x) << 22) 1197eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA(x) ((x) << 0) 1207eb8f069SAndrzej Hajda #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 1217eb8f069SAndrzej Hajda #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 1227eb8f069SAndrzej Hajda 1237eb8f069SAndrzej Hajda /* DSIM_SDRESOL */ 1247eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY(x) ((x) << 31) 1257eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL(x) ((x) << 16) 1267eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL(x) ((x) << 0) 1277eb8f069SAndrzej Hajda #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 1287eb8f069SAndrzej Hajda #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 1297eb8f069SAndrzej Hajda #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 1307eb8f069SAndrzej Hajda 1317eb8f069SAndrzej Hajda /* DSIM_INTSRC */ 1327eb8f069SAndrzej Hajda #define DSIM_INT_PLL_STABLE (1 << 31) 1337eb8f069SAndrzej Hajda #define DSIM_INT_SW_RST_RELEASE (1 << 30) 1347eb8f069SAndrzej Hajda #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29) 1357eb8f069SAndrzej Hajda #define DSIM_INT_BTA (1 << 25) 1367eb8f069SAndrzej Hajda #define DSIM_INT_FRAME_DONE (1 << 24) 1377eb8f069SAndrzej Hajda #define DSIM_INT_RX_TIMEOUT (1 << 21) 1387eb8f069SAndrzej Hajda #define DSIM_INT_BTA_TIMEOUT (1 << 20) 1397eb8f069SAndrzej Hajda #define DSIM_INT_RX_DONE (1 << 18) 1407eb8f069SAndrzej Hajda #define DSIM_INT_RX_TE (1 << 17) 1417eb8f069SAndrzej Hajda #define DSIM_INT_RX_ACK (1 << 16) 1427eb8f069SAndrzej Hajda #define DSIM_INT_RX_ECC_ERR (1 << 15) 1437eb8f069SAndrzej Hajda #define DSIM_INT_RX_CRC_ERR (1 << 14) 1447eb8f069SAndrzej Hajda 1457eb8f069SAndrzej Hajda /* DSIM_FIFOCTRL */ 1467eb8f069SAndrzej Hajda #define DSIM_RX_DATA_FULL (1 << 25) 1477eb8f069SAndrzej Hajda #define DSIM_RX_DATA_EMPTY (1 << 24) 1487eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_FULL (1 << 23) 1497eb8f069SAndrzej Hajda #define DSIM_SFR_HEADER_EMPTY (1 << 22) 1507eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_FULL (1 << 21) 1517eb8f069SAndrzej Hajda #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20) 1527eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_FULL (1 << 19) 1537eb8f069SAndrzej Hajda #define DSIM_I80_HEADER_EMPTY (1 << 18) 1547eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_FULL (1 << 17) 1557eb8f069SAndrzej Hajda #define DSIM_I80_PAYLOAD_EMPTY (1 << 16) 1567eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_FULL (1 << 15) 1577eb8f069SAndrzej Hajda #define DSIM_SD_HEADER_EMPTY (1 << 14) 1587eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_FULL (1 << 13) 1597eb8f069SAndrzej Hajda #define DSIM_SD_PAYLOAD_EMPTY (1 << 12) 1607eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_FULL (1 << 11) 1617eb8f069SAndrzej Hajda #define DSIM_MD_HEADER_EMPTY (1 << 10) 1627eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_FULL (1 << 9) 1637eb8f069SAndrzej Hajda #define DSIM_MD_PAYLOAD_EMPTY (1 << 8) 1647eb8f069SAndrzej Hajda #define DSIM_RX_FIFO (1 << 4) 1657eb8f069SAndrzej Hajda #define DSIM_SFR_FIFO (1 << 3) 1667eb8f069SAndrzej Hajda #define DSIM_I80_FIFO (1 << 2) 1677eb8f069SAndrzej Hajda #define DSIM_SD_FIFO (1 << 1) 1687eb8f069SAndrzej Hajda #define DSIM_MD_FIFO (1 << 0) 1697eb8f069SAndrzej Hajda 1707eb8f069SAndrzej Hajda /* DSIM_PHYACCHR */ 1717eb8f069SAndrzej Hajda #define DSIM_AFC_EN (1 << 14) 1727eb8f069SAndrzej Hajda #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 1737eb8f069SAndrzej Hajda 1747eb8f069SAndrzej Hajda /* DSIM_PLLCTRL */ 1757eb8f069SAndrzej Hajda #define DSIM_FREQ_BAND(x) ((x) << 24) 1767eb8f069SAndrzej Hajda #define DSIM_PLL_EN (1 << 23) 1777eb8f069SAndrzej Hajda #define DSIM_PLL_P(x) ((x) << 13) 1787eb8f069SAndrzej Hajda #define DSIM_PLL_M(x) ((x) << 4) 1797eb8f069SAndrzej Hajda #define DSIM_PLL_S(x) ((x) << 1) 1807eb8f069SAndrzej Hajda 1819a320415SYoungJun Cho /* DSIM_PHYCTRL */ 1829a320415SYoungJun Cho #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 1839a320415SYoungJun Cho 1849a320415SYoungJun Cho /* DSIM_PHYTIMING */ 1859a320415SYoungJun Cho #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 1869a320415SYoungJun Cho #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 1879a320415SYoungJun Cho 1889a320415SYoungJun Cho /* DSIM_PHYTIMING1 */ 1899a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 1909a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 1919a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 1929a320415SYoungJun Cho #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 1939a320415SYoungJun Cho 1949a320415SYoungJun Cho /* DSIM_PHYTIMING2 */ 1959a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 1969a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 1979a320415SYoungJun Cho #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 1989a320415SYoungJun Cho 1997eb8f069SAndrzej Hajda #define DSI_MAX_BUS_WIDTH 4 2007eb8f069SAndrzej Hajda #define DSI_NUM_VIRTUAL_CHANNELS 4 2017eb8f069SAndrzej Hajda #define DSI_TX_FIFO_SIZE 2048 2027eb8f069SAndrzej Hajda #define DSI_RX_FIFO_SIZE 256 2037eb8f069SAndrzej Hajda #define DSI_XFER_TIMEOUT_MS 100 2047eb8f069SAndrzej Hajda #define DSI_RX_FIFO_EMPTY 0x30800002 2057eb8f069SAndrzej Hajda 20626269af9SHyungwon Hwang #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 20726269af9SHyungwon Hwang 208d668e8bfSHyungwon Hwang #define REG_ADDR(dsi, reg_idx) ((dsi)->reg_base + \ 209d668e8bfSHyungwon Hwang dsi->driver_data->reg_ofs[(reg_idx)]) 210d668e8bfSHyungwon Hwang #define DSI_WRITE(dsi, reg_idx, val) writel((val), \ 211d668e8bfSHyungwon Hwang REG_ADDR((dsi), (reg_idx))) 212d668e8bfSHyungwon Hwang #define DSI_READ(dsi, reg_idx) readl(REG_ADDR((dsi), (reg_idx))) 213ba12ac2bSHyungwon Hwang 2140ff03fd1SHyungwon Hwang static char *clk_names[2] = { "bus_clk", "sclk_mipi" }; 2150ff03fd1SHyungwon Hwang 2167eb8f069SAndrzej Hajda enum exynos_dsi_transfer_type { 2177eb8f069SAndrzej Hajda EXYNOS_DSI_TX, 2187eb8f069SAndrzej Hajda EXYNOS_DSI_RX, 2197eb8f069SAndrzej Hajda }; 2207eb8f069SAndrzej Hajda 2217eb8f069SAndrzej Hajda struct exynos_dsi_transfer { 2227eb8f069SAndrzej Hajda struct list_head list; 2237eb8f069SAndrzej Hajda struct completion completed; 2247eb8f069SAndrzej Hajda int result; 2257eb8f069SAndrzej Hajda u8 data_id; 2267eb8f069SAndrzej Hajda u8 data[2]; 2277eb8f069SAndrzej Hajda u16 flags; 2287eb8f069SAndrzej Hajda 2297eb8f069SAndrzej Hajda const u8 *tx_payload; 2307eb8f069SAndrzej Hajda u16 tx_len; 2317eb8f069SAndrzej Hajda u16 tx_done; 2327eb8f069SAndrzej Hajda 2337eb8f069SAndrzej Hajda u8 *rx_payload; 2347eb8f069SAndrzej Hajda u16 rx_len; 2357eb8f069SAndrzej Hajda u16 rx_done; 2367eb8f069SAndrzej Hajda }; 2377eb8f069SAndrzej Hajda 2387eb8f069SAndrzej Hajda #define DSIM_STATE_ENABLED BIT(0) 2397eb8f069SAndrzej Hajda #define DSIM_STATE_INITIALIZED BIT(1) 2407eb8f069SAndrzej Hajda #define DSIM_STATE_CMD_LPM BIT(2) 2410e480f6fSHyungwon Hwang #define DSIM_STATE_VIDOUT_AVAILABLE BIT(3) 2427eb8f069SAndrzej Hajda 2439a320415SYoungJun Cho struct exynos_dsi_driver_data { 244d668e8bfSHyungwon Hwang unsigned int *reg_ofs; 2459a320415SYoungJun Cho unsigned int plltmr_reg; 2469a320415SYoungJun Cho unsigned int has_freqband:1; 24778d3a8c6SInki Dae unsigned int has_clklane_stop:1; 248d668e8bfSHyungwon Hwang unsigned int num_clks; 249d668e8bfSHyungwon Hwang unsigned int max_freq; 250d668e8bfSHyungwon Hwang unsigned int wait_for_reset; 251d668e8bfSHyungwon Hwang unsigned int num_bits_resol; 252d668e8bfSHyungwon Hwang unsigned int *reg_values; 2539a320415SYoungJun Cho }; 2549a320415SYoungJun Cho 2557eb8f069SAndrzej Hajda struct exynos_dsi { 2562900c69cSAndrzej Hajda struct exynos_drm_display display; 2577eb8f069SAndrzej Hajda struct mipi_dsi_host dsi_host; 2587eb8f069SAndrzej Hajda struct drm_connector connector; 2597eb8f069SAndrzej Hajda struct device_node *panel_node; 2607eb8f069SAndrzej Hajda struct drm_panel *panel; 2617eb8f069SAndrzej Hajda struct device *dev; 2627eb8f069SAndrzej Hajda 2637eb8f069SAndrzej Hajda void __iomem *reg_base; 2647eb8f069SAndrzej Hajda struct phy *phy; 2650ff03fd1SHyungwon Hwang struct clk **clks; 2667eb8f069SAndrzej Hajda struct regulator_bulk_data supplies[2]; 2677eb8f069SAndrzej Hajda int irq; 268e17ddeccSYoungJun Cho int te_gpio; 2697eb8f069SAndrzej Hajda 2707eb8f069SAndrzej Hajda u32 pll_clk_rate; 2717eb8f069SAndrzej Hajda u32 burst_clk_rate; 2727eb8f069SAndrzej Hajda u32 esc_clk_rate; 2737eb8f069SAndrzej Hajda u32 lanes; 2747eb8f069SAndrzej Hajda u32 mode_flags; 2757eb8f069SAndrzej Hajda u32 format; 2767eb8f069SAndrzej Hajda struct videomode vm; 2777eb8f069SAndrzej Hajda 2787eb8f069SAndrzej Hajda int state; 2797eb8f069SAndrzej Hajda struct drm_property *brightness; 2807eb8f069SAndrzej Hajda struct completion completed; 2817eb8f069SAndrzej Hajda 2827eb8f069SAndrzej Hajda spinlock_t transfer_lock; /* protects transfer_list */ 2837eb8f069SAndrzej Hajda struct list_head transfer_list; 2849a320415SYoungJun Cho 2859a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data; 2867eb8f069SAndrzej Hajda }; 2877eb8f069SAndrzej Hajda 2887eb8f069SAndrzej Hajda #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host) 2897eb8f069SAndrzej Hajda #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector) 2907eb8f069SAndrzej Hajda 2915cd5db80SAndrzej Hajda static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d) 2925cd5db80SAndrzej Hajda { 2935cd5db80SAndrzej Hajda return container_of(d, struct exynos_dsi, display); 2945cd5db80SAndrzej Hajda } 2955cd5db80SAndrzej Hajda 296d668e8bfSHyungwon Hwang enum reg_idx { 297d668e8bfSHyungwon Hwang DSIM_STATUS_REG, /* Status register */ 298d668e8bfSHyungwon Hwang DSIM_SWRST_REG, /* Software reset register */ 299d668e8bfSHyungwon Hwang DSIM_CLKCTRL_REG, /* Clock control register */ 300d668e8bfSHyungwon Hwang DSIM_TIMEOUT_REG, /* Time out register */ 301d668e8bfSHyungwon Hwang DSIM_CONFIG_REG, /* Configuration register */ 302d668e8bfSHyungwon Hwang DSIM_ESCMODE_REG, /* Escape mode register */ 303d668e8bfSHyungwon Hwang DSIM_MDRESOL_REG, 304d668e8bfSHyungwon Hwang DSIM_MVPORCH_REG, /* Main display Vporch register */ 305d668e8bfSHyungwon Hwang DSIM_MHPORCH_REG, /* Main display Hporch register */ 306d668e8bfSHyungwon Hwang DSIM_MSYNC_REG, /* Main display sync area register */ 307d668e8bfSHyungwon Hwang DSIM_INTSRC_REG, /* Interrupt source register */ 308d668e8bfSHyungwon Hwang DSIM_INTMSK_REG, /* Interrupt mask register */ 309d668e8bfSHyungwon Hwang DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 310d668e8bfSHyungwon Hwang DSIM_PAYLOAD_REG, /* Payload FIFO register */ 311d668e8bfSHyungwon Hwang DSIM_RXFIFO_REG, /* Read FIFO register */ 312d668e8bfSHyungwon Hwang DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 313d668e8bfSHyungwon Hwang DSIM_PLLCTRL_REG, /* PLL control register */ 314d668e8bfSHyungwon Hwang DSIM_PHYCTRL_REG, 315d668e8bfSHyungwon Hwang DSIM_PHYTIMING_REG, 316d668e8bfSHyungwon Hwang DSIM_PHYTIMING1_REG, 317d668e8bfSHyungwon Hwang DSIM_PHYTIMING2_REG, 318d668e8bfSHyungwon Hwang NUM_REGS 319d668e8bfSHyungwon Hwang }; 320d668e8bfSHyungwon Hwang static unsigned int exynos_reg_ofs[] = { 321d668e8bfSHyungwon Hwang [DSIM_STATUS_REG] = 0x00, 322d668e8bfSHyungwon Hwang [DSIM_SWRST_REG] = 0x04, 323d668e8bfSHyungwon Hwang [DSIM_CLKCTRL_REG] = 0x08, 324d668e8bfSHyungwon Hwang [DSIM_TIMEOUT_REG] = 0x0c, 325d668e8bfSHyungwon Hwang [DSIM_CONFIG_REG] = 0x10, 326d668e8bfSHyungwon Hwang [DSIM_ESCMODE_REG] = 0x14, 327d668e8bfSHyungwon Hwang [DSIM_MDRESOL_REG] = 0x18, 328d668e8bfSHyungwon Hwang [DSIM_MVPORCH_REG] = 0x1c, 329d668e8bfSHyungwon Hwang [DSIM_MHPORCH_REG] = 0x20, 330d668e8bfSHyungwon Hwang [DSIM_MSYNC_REG] = 0x24, 331d668e8bfSHyungwon Hwang [DSIM_INTSRC_REG] = 0x2c, 332d668e8bfSHyungwon Hwang [DSIM_INTMSK_REG] = 0x30, 333d668e8bfSHyungwon Hwang [DSIM_PKTHDR_REG] = 0x34, 334d668e8bfSHyungwon Hwang [DSIM_PAYLOAD_REG] = 0x38, 335d668e8bfSHyungwon Hwang [DSIM_RXFIFO_REG] = 0x3c, 336d668e8bfSHyungwon Hwang [DSIM_FIFOCTRL_REG] = 0x44, 337d668e8bfSHyungwon Hwang [DSIM_PLLCTRL_REG] = 0x4c, 338d668e8bfSHyungwon Hwang [DSIM_PHYCTRL_REG] = 0x5c, 339d668e8bfSHyungwon Hwang [DSIM_PHYTIMING_REG] = 0x64, 340d668e8bfSHyungwon Hwang [DSIM_PHYTIMING1_REG] = 0x68, 341d668e8bfSHyungwon Hwang [DSIM_PHYTIMING2_REG] = 0x6c, 342d668e8bfSHyungwon Hwang }; 343d668e8bfSHyungwon Hwang 344d668e8bfSHyungwon Hwang enum reg_value_idx { 345d668e8bfSHyungwon Hwang RESET_TYPE, 346d668e8bfSHyungwon Hwang PLL_TIMER, 347d668e8bfSHyungwon Hwang STOP_STATE_CNT, 348d668e8bfSHyungwon Hwang PHYCTRL_ULPS_EXIT, 349d668e8bfSHyungwon Hwang PHYCTRL_VREG_LP, 350d668e8bfSHyungwon Hwang PHYCTRL_SLEW_UP, 351d668e8bfSHyungwon Hwang PHYTIMING_LPX, 352d668e8bfSHyungwon Hwang PHYTIMING_HS_EXIT, 353d668e8bfSHyungwon Hwang PHYTIMING_CLK_PREPARE, 354d668e8bfSHyungwon Hwang PHYTIMING_CLK_ZERO, 355d668e8bfSHyungwon Hwang PHYTIMING_CLK_POST, 356d668e8bfSHyungwon Hwang PHYTIMING_CLK_TRAIL, 357d668e8bfSHyungwon Hwang PHYTIMING_HS_PREPARE, 358d668e8bfSHyungwon Hwang PHYTIMING_HS_ZERO, 359d668e8bfSHyungwon Hwang PHYTIMING_HS_TRAIL 360d668e8bfSHyungwon Hwang }; 361d668e8bfSHyungwon Hwang 362d668e8bfSHyungwon Hwang static unsigned int reg_values[] = { 363d668e8bfSHyungwon Hwang [RESET_TYPE] = DSIM_SWRST, 364d668e8bfSHyungwon Hwang [PLL_TIMER] = 500, 365d668e8bfSHyungwon Hwang [STOP_STATE_CNT] = 0xf, 366d668e8bfSHyungwon Hwang [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 367d668e8bfSHyungwon Hwang [PHYCTRL_VREG_LP] = 0, 368d668e8bfSHyungwon Hwang [PHYCTRL_SLEW_UP] = 0, 369d668e8bfSHyungwon Hwang [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 370d668e8bfSHyungwon Hwang [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 371d668e8bfSHyungwon Hwang [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 372d668e8bfSHyungwon Hwang [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 373d668e8bfSHyungwon Hwang [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 374d668e8bfSHyungwon Hwang [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 375d668e8bfSHyungwon Hwang [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 376d668e8bfSHyungwon Hwang [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 377d668e8bfSHyungwon Hwang [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 378d668e8bfSHyungwon Hwang }; 379d668e8bfSHyungwon Hwang 380473462a1SInki Dae static struct exynos_dsi_driver_data exynos3_dsi_driver_data = { 381d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 382473462a1SInki Dae .plltmr_reg = 0x50, 383473462a1SInki Dae .has_freqband = 1, 384473462a1SInki Dae .has_clklane_stop = 1, 385d668e8bfSHyungwon Hwang .num_clks = 2, 386d668e8bfSHyungwon Hwang .max_freq = 1000, 387d668e8bfSHyungwon Hwang .wait_for_reset = 1, 388d668e8bfSHyungwon Hwang .num_bits_resol = 11, 389d668e8bfSHyungwon Hwang .reg_values = reg_values, 390473462a1SInki Dae }; 391473462a1SInki Dae 3929a320415SYoungJun Cho static struct exynos_dsi_driver_data exynos4_dsi_driver_data = { 393d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 3949a320415SYoungJun Cho .plltmr_reg = 0x50, 3959a320415SYoungJun Cho .has_freqband = 1, 39678d3a8c6SInki Dae .has_clklane_stop = 1, 397d668e8bfSHyungwon Hwang .num_clks = 2, 398d668e8bfSHyungwon Hwang .max_freq = 1000, 399d668e8bfSHyungwon Hwang .wait_for_reset = 1, 400d668e8bfSHyungwon Hwang .num_bits_resol = 11, 401d668e8bfSHyungwon Hwang .reg_values = reg_values, 4029a320415SYoungJun Cho }; 4039a320415SYoungJun Cho 4044bc6d644SYoungJun Cho static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = { 405d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4064bc6d644SYoungJun Cho .plltmr_reg = 0x58, 4074bc6d644SYoungJun Cho .has_clklane_stop = 1, 408d668e8bfSHyungwon Hwang .num_clks = 2, 409d668e8bfSHyungwon Hwang .max_freq = 1000, 410d668e8bfSHyungwon Hwang .wait_for_reset = 1, 411d668e8bfSHyungwon Hwang .num_bits_resol = 11, 412d668e8bfSHyungwon Hwang .reg_values = reg_values, 4134bc6d644SYoungJun Cho }; 4144bc6d644SYoungJun Cho 4159a320415SYoungJun Cho static struct exynos_dsi_driver_data exynos5_dsi_driver_data = { 416d668e8bfSHyungwon Hwang .reg_ofs = exynos_reg_ofs, 4179a320415SYoungJun Cho .plltmr_reg = 0x58, 418d668e8bfSHyungwon Hwang .num_clks = 2, 419d668e8bfSHyungwon Hwang .max_freq = 1000, 420d668e8bfSHyungwon Hwang .wait_for_reset = 1, 421d668e8bfSHyungwon Hwang .num_bits_resol = 11, 422d668e8bfSHyungwon Hwang .reg_values = reg_values, 4239a320415SYoungJun Cho }; 4249a320415SYoungJun Cho 4259a320415SYoungJun Cho static struct of_device_id exynos_dsi_of_match[] = { 426473462a1SInki Dae { .compatible = "samsung,exynos3250-mipi-dsi", 427473462a1SInki Dae .data = &exynos3_dsi_driver_data }, 4289a320415SYoungJun Cho { .compatible = "samsung,exynos4210-mipi-dsi", 4299a320415SYoungJun Cho .data = &exynos4_dsi_driver_data }, 4304bc6d644SYoungJun Cho { .compatible = "samsung,exynos4415-mipi-dsi", 4314bc6d644SYoungJun Cho .data = &exynos4415_dsi_driver_data }, 4329a320415SYoungJun Cho { .compatible = "samsung,exynos5410-mipi-dsi", 4339a320415SYoungJun Cho .data = &exynos5_dsi_driver_data }, 4349a320415SYoungJun Cho { } 4359a320415SYoungJun Cho }; 4369a320415SYoungJun Cho 4379a320415SYoungJun Cho static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data( 4389a320415SYoungJun Cho struct platform_device *pdev) 4399a320415SYoungJun Cho { 4409a320415SYoungJun Cho const struct of_device_id *of_id = 4419a320415SYoungJun Cho of_match_device(exynos_dsi_of_match, &pdev->dev); 4429a320415SYoungJun Cho 4439a320415SYoungJun Cho return (struct exynos_dsi_driver_data *)of_id->data; 4449a320415SYoungJun Cho } 4459a320415SYoungJun Cho 4467eb8f069SAndrzej Hajda static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi) 4477eb8f069SAndrzej Hajda { 4487eb8f069SAndrzej Hajda if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 4497eb8f069SAndrzej Hajda return; 4507eb8f069SAndrzej Hajda 4517eb8f069SAndrzej Hajda dev_err(dsi->dev, "timeout waiting for reset\n"); 4527eb8f069SAndrzej Hajda } 4537eb8f069SAndrzej Hajda 4547eb8f069SAndrzej Hajda static void exynos_dsi_reset(struct exynos_dsi *dsi) 4557eb8f069SAndrzej Hajda { 456ba12ac2bSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 457ba12ac2bSHyungwon Hwang 4587eb8f069SAndrzej Hajda reinit_completion(&dsi->completed); 459d668e8bfSHyungwon Hwang DSI_WRITE(dsi, DSIM_SWRST_REG, driver_data->reg_values[RESET_TYPE]); 4607eb8f069SAndrzej Hajda } 4617eb8f069SAndrzej Hajda 4627eb8f069SAndrzej Hajda #ifndef MHZ 4637eb8f069SAndrzej Hajda #define MHZ (1000*1000) 4647eb8f069SAndrzej Hajda #endif 4657eb8f069SAndrzej Hajda 4667eb8f069SAndrzej Hajda static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, 4677eb8f069SAndrzej Hajda unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s) 4687eb8f069SAndrzej Hajda { 469ba12ac2bSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 4707eb8f069SAndrzej Hajda unsigned long best_freq = 0; 4717eb8f069SAndrzej Hajda u32 min_delta = 0xffffffff; 4727eb8f069SAndrzej Hajda u8 p_min, p_max; 4737eb8f069SAndrzej Hajda u8 _p, uninitialized_var(best_p); 4747eb8f069SAndrzej Hajda u16 _m, uninitialized_var(best_m); 4757eb8f069SAndrzej Hajda u8 _s, uninitialized_var(best_s); 4767eb8f069SAndrzej Hajda 4777eb8f069SAndrzej Hajda p_min = DIV_ROUND_UP(fin, (12 * MHZ)); 4787eb8f069SAndrzej Hajda p_max = fin / (6 * MHZ); 4797eb8f069SAndrzej Hajda 4807eb8f069SAndrzej Hajda for (_p = p_min; _p <= p_max; ++_p) { 4817eb8f069SAndrzej Hajda for (_s = 0; _s <= 5; ++_s) { 4827eb8f069SAndrzej Hajda u64 tmp; 4837eb8f069SAndrzej Hajda u32 delta; 4847eb8f069SAndrzej Hajda 4857eb8f069SAndrzej Hajda tmp = (u64)fout * (_p << _s); 4867eb8f069SAndrzej Hajda do_div(tmp, fin); 4877eb8f069SAndrzej Hajda _m = tmp; 4887eb8f069SAndrzej Hajda if (_m < 41 || _m > 125) 4897eb8f069SAndrzej Hajda continue; 4907eb8f069SAndrzej Hajda 4917eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 4927eb8f069SAndrzej Hajda do_div(tmp, _p); 493d668e8bfSHyungwon Hwang if (tmp < 500 * MHZ || 494d668e8bfSHyungwon Hwang tmp > driver_data->max_freq * MHZ) 4957eb8f069SAndrzej Hajda continue; 4967eb8f069SAndrzej Hajda 4977eb8f069SAndrzej Hajda tmp = (u64)_m * fin; 4987eb8f069SAndrzej Hajda do_div(tmp, _p << _s); 4997eb8f069SAndrzej Hajda 5007eb8f069SAndrzej Hajda delta = abs(fout - tmp); 5017eb8f069SAndrzej Hajda if (delta < min_delta) { 5027eb8f069SAndrzej Hajda best_p = _p; 5037eb8f069SAndrzej Hajda best_m = _m; 5047eb8f069SAndrzej Hajda best_s = _s; 5057eb8f069SAndrzej Hajda min_delta = delta; 5067eb8f069SAndrzej Hajda best_freq = tmp; 5077eb8f069SAndrzej Hajda } 5087eb8f069SAndrzej Hajda } 5097eb8f069SAndrzej Hajda } 5107eb8f069SAndrzej Hajda 5117eb8f069SAndrzej Hajda if (best_freq) { 5127eb8f069SAndrzej Hajda *p = best_p; 5137eb8f069SAndrzej Hajda *m = best_m; 5147eb8f069SAndrzej Hajda *s = best_s; 5157eb8f069SAndrzej Hajda } 5167eb8f069SAndrzej Hajda 5177eb8f069SAndrzej Hajda return best_freq; 5187eb8f069SAndrzej Hajda } 5197eb8f069SAndrzej Hajda 5207eb8f069SAndrzej Hajda static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, 5217eb8f069SAndrzej Hajda unsigned long freq) 5227eb8f069SAndrzej Hajda { 5239a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 5247eb8f069SAndrzej Hajda unsigned long fin, fout; 5259a320415SYoungJun Cho int timeout; 5267eb8f069SAndrzej Hajda u8 p, s; 5277eb8f069SAndrzej Hajda u16 m; 5287eb8f069SAndrzej Hajda u32 reg; 5297eb8f069SAndrzej Hajda 53026269af9SHyungwon Hwang fin = dsi->pll_clk_rate; 5317eb8f069SAndrzej Hajda fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); 5327eb8f069SAndrzej Hajda if (!fout) { 5337eb8f069SAndrzej Hajda dev_err(dsi->dev, 5347eb8f069SAndrzej Hajda "failed to find PLL PMS for requested frequency\n"); 5358525b5ecSYoungJun Cho return 0; 5367eb8f069SAndrzej Hajda } 5379a320415SYoungJun Cho dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 5389a320415SYoungJun Cho 539d668e8bfSHyungwon Hwang writel(driver_data->reg_values[PLL_TIMER], 540d668e8bfSHyungwon Hwang dsi->reg_base + driver_data->plltmr_reg); 5419a320415SYoungJun Cho 5429a320415SYoungJun Cho reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s); 5439a320415SYoungJun Cho 5449a320415SYoungJun Cho if (driver_data->has_freqband) { 5459a320415SYoungJun Cho static const unsigned long freq_bands[] = { 5469a320415SYoungJun Cho 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 5479a320415SYoungJun Cho 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 5489a320415SYoungJun Cho 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 5499a320415SYoungJun Cho 770 * MHZ, 870 * MHZ, 950 * MHZ, 5509a320415SYoungJun Cho }; 5519a320415SYoungJun Cho int band; 5527eb8f069SAndrzej Hajda 5537eb8f069SAndrzej Hajda for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 5547eb8f069SAndrzej Hajda if (fout < freq_bands[band]) 5557eb8f069SAndrzej Hajda break; 5567eb8f069SAndrzej Hajda 5579a320415SYoungJun Cho dev_dbg(dsi->dev, "band %d\n", band); 5587eb8f069SAndrzej Hajda 5599a320415SYoungJun Cho reg |= DSIM_FREQ_BAND(band); 5609a320415SYoungJun Cho } 5617eb8f069SAndrzej Hajda 562ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 5637eb8f069SAndrzej Hajda 5647eb8f069SAndrzej Hajda timeout = 1000; 5657eb8f069SAndrzej Hajda do { 5667eb8f069SAndrzej Hajda if (timeout-- == 0) { 5677eb8f069SAndrzej Hajda dev_err(dsi->dev, "PLL failed to stabilize\n"); 5688525b5ecSYoungJun Cho return 0; 5697eb8f069SAndrzej Hajda } 570ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_STATUS_REG); 5717eb8f069SAndrzej Hajda } while ((reg & DSIM_PLL_STABLE) == 0); 5727eb8f069SAndrzej Hajda 5737eb8f069SAndrzej Hajda return fout; 5747eb8f069SAndrzej Hajda } 5757eb8f069SAndrzej Hajda 5767eb8f069SAndrzej Hajda static int exynos_dsi_enable_clock(struct exynos_dsi *dsi) 5777eb8f069SAndrzej Hajda { 5787eb8f069SAndrzej Hajda unsigned long hs_clk, byte_clk, esc_clk; 5797eb8f069SAndrzej Hajda unsigned long esc_div; 5807eb8f069SAndrzej Hajda u32 reg; 5817eb8f069SAndrzej Hajda 5827eb8f069SAndrzej Hajda hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate); 5837eb8f069SAndrzej Hajda if (!hs_clk) { 5847eb8f069SAndrzej Hajda dev_err(dsi->dev, "failed to configure DSI PLL\n"); 5857eb8f069SAndrzej Hajda return -EFAULT; 5867eb8f069SAndrzej Hajda } 5877eb8f069SAndrzej Hajda 5887eb8f069SAndrzej Hajda byte_clk = hs_clk / 8; 5897eb8f069SAndrzej Hajda esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 5907eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 5917eb8f069SAndrzej Hajda 5927eb8f069SAndrzej Hajda if (esc_clk > 20 * MHZ) { 5937eb8f069SAndrzej Hajda ++esc_div; 5947eb8f069SAndrzej Hajda esc_clk = byte_clk / esc_div; 5957eb8f069SAndrzej Hajda } 5967eb8f069SAndrzej Hajda 5977eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 5987eb8f069SAndrzej Hajda hs_clk, byte_clk, esc_clk); 5997eb8f069SAndrzej Hajda 600ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 6017eb8f069SAndrzej Hajda reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 6027eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 6037eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC_MASK); 6047eb8f069SAndrzej Hajda reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 6057eb8f069SAndrzej Hajda | DSIM_ESC_PRESCALER(esc_div) 6067eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_CLK 6077eb8f069SAndrzej Hajda | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 6087eb8f069SAndrzej Hajda | DSIM_BYTE_CLK_SRC(0) 6097eb8f069SAndrzej Hajda | DSIM_TX_REQUEST_HSCLK; 610ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 6117eb8f069SAndrzej Hajda 6127eb8f069SAndrzej Hajda return 0; 6137eb8f069SAndrzej Hajda } 6147eb8f069SAndrzej Hajda 6159a320415SYoungJun Cho static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi) 6169a320415SYoungJun Cho { 6179a320415SYoungJun Cho struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 618d668e8bfSHyungwon Hwang unsigned int *reg_values = driver_data->reg_values; 6199a320415SYoungJun Cho u32 reg; 6209a320415SYoungJun Cho 6219a320415SYoungJun Cho if (driver_data->has_freqband) 6229a320415SYoungJun Cho return; 6239a320415SYoungJun Cho 6249a320415SYoungJun Cho /* B D-PHY: D-PHY Master & Slave Analog Block control */ 625d668e8bfSHyungwon Hwang reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 626d668e8bfSHyungwon Hwang reg_values[PHYCTRL_SLEW_UP]; 627ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYCTRL_REG, reg); 6289a320415SYoungJun Cho 6299a320415SYoungJun Cho /* 6309a320415SYoungJun Cho * T LPX: Transmitted length of any Low-Power state period 6319a320415SYoungJun Cho * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 6329a320415SYoungJun Cho * burst 6339a320415SYoungJun Cho */ 634d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_LPX] | reg_values[PHYTIMING_HS_EXIT]; 635ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING_REG, reg); 6369a320415SYoungJun Cho 6379a320415SYoungJun Cho /* 6389a320415SYoungJun Cho * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 6399a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 6409a320415SYoungJun Cho * HS transmission 6419a320415SYoungJun Cho * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 6429a320415SYoungJun Cho * transmitting the Clock. 6439a320415SYoungJun Cho * T CLK_POST: Time that the transmitter continues to send HS clock 6449a320415SYoungJun Cho * after the last associated Data Lane has transitioned to LP Mode 6459a320415SYoungJun Cho * Interval is defined as the period from the end of T HS-TRAIL to 6469a320415SYoungJun Cho * the beginning of T CLK-TRAIL 6479a320415SYoungJun Cho * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 6489a320415SYoungJun Cho * the last payload clock bit of a HS transmission burst 6499a320415SYoungJun Cho */ 650d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_CLK_PREPARE] | 651d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_ZERO] | 652d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_POST] | 653d668e8bfSHyungwon Hwang reg_values[PHYTIMING_CLK_TRAIL]; 654d668e8bfSHyungwon Hwang 655ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING1_REG, reg); 6569a320415SYoungJun Cho 6579a320415SYoungJun Cho /* 6589a320415SYoungJun Cho * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 6599a320415SYoungJun Cho * Line state immediately before the HS-0 Line state starting the 6609a320415SYoungJun Cho * HS transmission 6619a320415SYoungJun Cho * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 6629a320415SYoungJun Cho * transmitting the Sync sequence. 6639a320415SYoungJun Cho * T HS-TRAIL: Time that the transmitter drives the flipped differential 6649a320415SYoungJun Cho * state after last payload data bit of a HS transmission burst 6659a320415SYoungJun Cho */ 666d668e8bfSHyungwon Hwang reg = reg_values[PHYTIMING_HS_PREPARE] | reg_values[PHYTIMING_HS_ZERO] | 667d668e8bfSHyungwon Hwang reg_values[PHYTIMING_HS_TRAIL]; 668ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PHYTIMING2_REG, reg); 6699a320415SYoungJun Cho } 6709a320415SYoungJun Cho 6717eb8f069SAndrzej Hajda static void exynos_dsi_disable_clock(struct exynos_dsi *dsi) 6727eb8f069SAndrzej Hajda { 6737eb8f069SAndrzej Hajda u32 reg; 6747eb8f069SAndrzej Hajda 675ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_CLKCTRL_REG); 6767eb8f069SAndrzej Hajda reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 6777eb8f069SAndrzej Hajda | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 678ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CLKCTRL_REG, reg); 6797eb8f069SAndrzej Hajda 680ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_PLLCTRL_REG); 6817eb8f069SAndrzej Hajda reg &= ~DSIM_PLL_EN; 682ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PLLCTRL_REG, reg); 6837eb8f069SAndrzej Hajda } 6847eb8f069SAndrzej Hajda 6857eb8f069SAndrzej Hajda static int exynos_dsi_init_link(struct exynos_dsi *dsi) 6867eb8f069SAndrzej Hajda { 68778d3a8c6SInki Dae struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 6887eb8f069SAndrzej Hajda int timeout; 6897eb8f069SAndrzej Hajda u32 reg; 6907eb8f069SAndrzej Hajda u32 lanes_mask; 6917eb8f069SAndrzej Hajda 6927eb8f069SAndrzej Hajda /* Initialize FIFO pointers */ 693ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 6947eb8f069SAndrzej Hajda reg &= ~0x1f; 695ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 6967eb8f069SAndrzej Hajda 6977eb8f069SAndrzej Hajda usleep_range(9000, 11000); 6987eb8f069SAndrzej Hajda 6997eb8f069SAndrzej Hajda reg |= 0x1f; 700ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_FIFOCTRL_REG, reg); 7017eb8f069SAndrzej Hajda usleep_range(9000, 11000); 7027eb8f069SAndrzej Hajda 7037eb8f069SAndrzej Hajda /* DSI configuration */ 7047eb8f069SAndrzej Hajda reg = 0; 7057eb8f069SAndrzej Hajda 7062f36e33aSYoungJun Cho /* 7072f36e33aSYoungJun Cho * The first bit of mode_flags specifies display configuration. 7082f36e33aSYoungJun Cho * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 7092f36e33aSYoungJun Cho * mode, otherwise it will support command mode. 7102f36e33aSYoungJun Cho */ 7117eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 7127eb8f069SAndrzej Hajda reg |= DSIM_VIDEO_MODE; 7137eb8f069SAndrzej Hajda 7142f36e33aSYoungJun Cho /* 7152f36e33aSYoungJun Cho * The user manual describes that following bits are ignored in 7162f36e33aSYoungJun Cho * command mode. 7172f36e33aSYoungJun Cho */ 7187eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 7197eb8f069SAndrzej Hajda reg |= DSIM_MFLUSH_VS; 7207eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 7217eb8f069SAndrzej Hajda reg |= DSIM_SYNC_INFORM; 7227eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 7237eb8f069SAndrzej Hajda reg |= DSIM_BURST_MODE; 7247eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 7257eb8f069SAndrzej Hajda reg |= DSIM_AUTO_MODE; 7267eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 7277eb8f069SAndrzej Hajda reg |= DSIM_HSE_MODE; 7287eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)) 7297eb8f069SAndrzej Hajda reg |= DSIM_HFP_MODE; 7307eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)) 7317eb8f069SAndrzej Hajda reg |= DSIM_HBP_MODE; 7327eb8f069SAndrzej Hajda if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)) 7337eb8f069SAndrzej Hajda reg |= DSIM_HSA_MODE; 7347eb8f069SAndrzej Hajda } 7357eb8f069SAndrzej Hajda 7362f36e33aSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET)) 7372f36e33aSYoungJun Cho reg |= DSIM_EOT_DISABLE; 7382f36e33aSYoungJun Cho 7397eb8f069SAndrzej Hajda switch (dsi->format) { 7407eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB888: 7417eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 7427eb8f069SAndrzej Hajda break; 7437eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666: 7447eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 7457eb8f069SAndrzej Hajda break; 7467eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB666_PACKED: 7477eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 7487eb8f069SAndrzej Hajda break; 7497eb8f069SAndrzej Hajda case MIPI_DSI_FMT_RGB565: 7507eb8f069SAndrzej Hajda reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 7517eb8f069SAndrzej Hajda break; 7527eb8f069SAndrzej Hajda default: 7537eb8f069SAndrzej Hajda dev_err(dsi->dev, "invalid pixel format\n"); 7547eb8f069SAndrzej Hajda return -EINVAL; 7557eb8f069SAndrzej Hajda } 7567eb8f069SAndrzej Hajda 7577eb8f069SAndrzej Hajda reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1); 7587eb8f069SAndrzej Hajda 759ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 7607eb8f069SAndrzej Hajda 7617eb8f069SAndrzej Hajda reg |= DSIM_LANE_EN_CLK; 762ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 7637eb8f069SAndrzej Hajda 7647eb8f069SAndrzej Hajda lanes_mask = BIT(dsi->lanes) - 1; 7657eb8f069SAndrzej Hajda reg |= DSIM_LANE_EN(lanes_mask); 766ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 7677eb8f069SAndrzej Hajda 76878d3a8c6SInki Dae /* 76978d3a8c6SInki Dae * Use non-continuous clock mode if the periparal wants and 77078d3a8c6SInki Dae * host controller supports 77178d3a8c6SInki Dae * 77278d3a8c6SInki Dae * In non-continous clock mode, host controller will turn off 77378d3a8c6SInki Dae * the HS clock between high-speed transmissions to reduce 77478d3a8c6SInki Dae * power consumption. 77578d3a8c6SInki Dae */ 77678d3a8c6SInki Dae if (driver_data->has_clklane_stop && 77778d3a8c6SInki Dae dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 77878d3a8c6SInki Dae reg |= DSIM_CLKLANE_STOP; 779ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_CONFIG_REG, reg); 78078d3a8c6SInki Dae } 78178d3a8c6SInki Dae 7827eb8f069SAndrzej Hajda /* Check clock and data lane state are stop state */ 7837eb8f069SAndrzej Hajda timeout = 100; 7847eb8f069SAndrzej Hajda do { 7857eb8f069SAndrzej Hajda if (timeout-- == 0) { 7867eb8f069SAndrzej Hajda dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 7877eb8f069SAndrzej Hajda return -EFAULT; 7887eb8f069SAndrzej Hajda } 7897eb8f069SAndrzej Hajda 790ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_STATUS_REG); 7917eb8f069SAndrzej Hajda if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 7927eb8f069SAndrzej Hajda != DSIM_STOP_STATE_DAT(lanes_mask)) 7937eb8f069SAndrzej Hajda continue; 7947eb8f069SAndrzej Hajda } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 7957eb8f069SAndrzej Hajda 796ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_ESCMODE_REG); 7977eb8f069SAndrzej Hajda reg &= ~DSIM_STOP_STATE_CNT_MASK; 798d668e8bfSHyungwon Hwang reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 799ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, reg); 8007eb8f069SAndrzej Hajda 8017eb8f069SAndrzej Hajda reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 802ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_TIMEOUT_REG, reg); 8037eb8f069SAndrzej Hajda 8047eb8f069SAndrzej Hajda return 0; 8057eb8f069SAndrzej Hajda } 8067eb8f069SAndrzej Hajda 8077eb8f069SAndrzej Hajda static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi) 8087eb8f069SAndrzej Hajda { 8097eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 810d668e8bfSHyungwon Hwang unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 8117eb8f069SAndrzej Hajda u32 reg; 8127eb8f069SAndrzej Hajda 8137eb8f069SAndrzej Hajda if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 8147eb8f069SAndrzej Hajda reg = DSIM_CMD_ALLOW(0xf) 8157eb8f069SAndrzej Hajda | DSIM_STABLE_VFP(vm->vfront_porch) 8167eb8f069SAndrzej Hajda | DSIM_MAIN_VBP(vm->vback_porch); 817ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MVPORCH_REG, reg); 8187eb8f069SAndrzej Hajda 8197eb8f069SAndrzej Hajda reg = DSIM_MAIN_HFP(vm->hfront_porch) 8207eb8f069SAndrzej Hajda | DSIM_MAIN_HBP(vm->hback_porch); 821ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MHPORCH_REG, reg); 8227eb8f069SAndrzej Hajda 8237eb8f069SAndrzej Hajda reg = DSIM_MAIN_VSA(vm->vsync_len) 8247eb8f069SAndrzej Hajda | DSIM_MAIN_HSA(vm->hsync_len); 825ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MSYNC_REG, reg); 8267eb8f069SAndrzej Hajda } 827d668e8bfSHyungwon Hwang reg = DSIM_MAIN_HRESOL(vm->hactive, num_bits_resol) | 828d668e8bfSHyungwon Hwang DSIM_MAIN_VRESOL(vm->vactive, num_bits_resol); 8297eb8f069SAndrzej Hajda 830ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 8317eb8f069SAndrzej Hajda 8327eb8f069SAndrzej Hajda dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive); 8337eb8f069SAndrzej Hajda } 8347eb8f069SAndrzej Hajda 8357eb8f069SAndrzej Hajda static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable) 8367eb8f069SAndrzej Hajda { 8377eb8f069SAndrzej Hajda u32 reg; 8387eb8f069SAndrzej Hajda 839ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_MDRESOL_REG); 8407eb8f069SAndrzej Hajda if (enable) 8417eb8f069SAndrzej Hajda reg |= DSIM_MAIN_STAND_BY; 8427eb8f069SAndrzej Hajda else 8437eb8f069SAndrzej Hajda reg &= ~DSIM_MAIN_STAND_BY; 844ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_MDRESOL_REG, reg); 8457eb8f069SAndrzej Hajda } 8467eb8f069SAndrzej Hajda 8477eb8f069SAndrzej Hajda static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi) 8487eb8f069SAndrzej Hajda { 8497eb8f069SAndrzej Hajda int timeout = 2000; 8507eb8f069SAndrzej Hajda 8517eb8f069SAndrzej Hajda do { 852ba12ac2bSHyungwon Hwang u32 reg = DSI_READ(dsi, DSIM_FIFOCTRL_REG); 8537eb8f069SAndrzej Hajda 8547eb8f069SAndrzej Hajda if (!(reg & DSIM_SFR_HEADER_FULL)) 8557eb8f069SAndrzej Hajda return 0; 8567eb8f069SAndrzej Hajda 8577eb8f069SAndrzej Hajda if (!cond_resched()) 8587eb8f069SAndrzej Hajda usleep_range(950, 1050); 8597eb8f069SAndrzej Hajda } while (--timeout); 8607eb8f069SAndrzej Hajda 8617eb8f069SAndrzej Hajda return -ETIMEDOUT; 8627eb8f069SAndrzej Hajda } 8637eb8f069SAndrzej Hajda 8647eb8f069SAndrzej Hajda static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm) 8657eb8f069SAndrzej Hajda { 866ba12ac2bSHyungwon Hwang u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 8677eb8f069SAndrzej Hajda 8687eb8f069SAndrzej Hajda if (lpm) 8697eb8f069SAndrzej Hajda v |= DSIM_CMD_LPDT_LP; 8707eb8f069SAndrzej Hajda else 8717eb8f069SAndrzej Hajda v &= ~DSIM_CMD_LPDT_LP; 8727eb8f069SAndrzej Hajda 873ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 8747eb8f069SAndrzej Hajda } 8757eb8f069SAndrzej Hajda 8767eb8f069SAndrzej Hajda static void exynos_dsi_force_bta(struct exynos_dsi *dsi) 8777eb8f069SAndrzej Hajda { 878ba12ac2bSHyungwon Hwang u32 v = DSI_READ(dsi, DSIM_ESCMODE_REG); 8797eb8f069SAndrzej Hajda v |= DSIM_FORCE_BTA; 880ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_ESCMODE_REG, v); 8817eb8f069SAndrzej Hajda } 8827eb8f069SAndrzej Hajda 8837eb8f069SAndrzej Hajda static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi, 8847eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 8857eb8f069SAndrzej Hajda { 8867eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 8877eb8f069SAndrzej Hajda const u8 *payload = xfer->tx_payload + xfer->tx_done; 8887eb8f069SAndrzej Hajda u16 length = xfer->tx_len - xfer->tx_done; 8897eb8f069SAndrzej Hajda bool first = !xfer->tx_done; 8907eb8f069SAndrzej Hajda u32 reg; 8917eb8f069SAndrzej Hajda 8927eb8f069SAndrzej Hajda dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 8937eb8f069SAndrzej Hajda xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 8947eb8f069SAndrzej Hajda 8957eb8f069SAndrzej Hajda if (length > DSI_TX_FIFO_SIZE) 8967eb8f069SAndrzej Hajda length = DSI_TX_FIFO_SIZE; 8977eb8f069SAndrzej Hajda 8987eb8f069SAndrzej Hajda xfer->tx_done += length; 8997eb8f069SAndrzej Hajda 9007eb8f069SAndrzej Hajda /* Send payload */ 9017eb8f069SAndrzej Hajda while (length >= 4) { 9027eb8f069SAndrzej Hajda reg = (payload[3] << 24) | (payload[2] << 16) 9037eb8f069SAndrzej Hajda | (payload[1] << 8) | payload[0]; 904ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 9057eb8f069SAndrzej Hajda payload += 4; 9067eb8f069SAndrzej Hajda length -= 4; 9077eb8f069SAndrzej Hajda } 9087eb8f069SAndrzej Hajda 9097eb8f069SAndrzej Hajda reg = 0; 9107eb8f069SAndrzej Hajda switch (length) { 9117eb8f069SAndrzej Hajda case 3: 9127eb8f069SAndrzej Hajda reg |= payload[2] << 16; 9137eb8f069SAndrzej Hajda /* Fall through */ 9147eb8f069SAndrzej Hajda case 2: 9157eb8f069SAndrzej Hajda reg |= payload[1] << 8; 9167eb8f069SAndrzej Hajda /* Fall through */ 9177eb8f069SAndrzej Hajda case 1: 9187eb8f069SAndrzej Hajda reg |= payload[0]; 919ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PAYLOAD_REG, reg); 9207eb8f069SAndrzej Hajda break; 9217eb8f069SAndrzej Hajda case 0: 9227eb8f069SAndrzej Hajda /* Do nothing */ 9237eb8f069SAndrzej Hajda break; 9247eb8f069SAndrzej Hajda } 9257eb8f069SAndrzej Hajda 9267eb8f069SAndrzej Hajda /* Send packet header */ 9277eb8f069SAndrzej Hajda if (!first) 9287eb8f069SAndrzej Hajda return; 9297eb8f069SAndrzej Hajda 9307eb8f069SAndrzej Hajda reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id; 9317eb8f069SAndrzej Hajda if (exynos_dsi_wait_for_hdr_fifo(dsi)) { 9327eb8f069SAndrzej Hajda dev_err(dev, "waiting for header FIFO timed out\n"); 9337eb8f069SAndrzej Hajda return; 9347eb8f069SAndrzej Hajda } 9357eb8f069SAndrzej Hajda 9367eb8f069SAndrzej Hajda if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 9377eb8f069SAndrzej Hajda dsi->state & DSIM_STATE_CMD_LPM)) { 9387eb8f069SAndrzej Hajda exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 9397eb8f069SAndrzej Hajda dsi->state ^= DSIM_STATE_CMD_LPM; 9407eb8f069SAndrzej Hajda } 9417eb8f069SAndrzej Hajda 942ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_PKTHDR_REG, reg); 9437eb8f069SAndrzej Hajda 9447eb8f069SAndrzej Hajda if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 9457eb8f069SAndrzej Hajda exynos_dsi_force_bta(dsi); 9467eb8f069SAndrzej Hajda } 9477eb8f069SAndrzej Hajda 9487eb8f069SAndrzej Hajda static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi, 9497eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 9507eb8f069SAndrzej Hajda { 9517eb8f069SAndrzej Hajda u8 *payload = xfer->rx_payload + xfer->rx_done; 9527eb8f069SAndrzej Hajda bool first = !xfer->rx_done; 9537eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 9547eb8f069SAndrzej Hajda u16 length; 9557eb8f069SAndrzej Hajda u32 reg; 9567eb8f069SAndrzej Hajda 9577eb8f069SAndrzej Hajda if (first) { 958ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 9597eb8f069SAndrzej Hajda 9607eb8f069SAndrzej Hajda switch (reg & 0x3f) { 9617eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 9627eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 9637eb8f069SAndrzej Hajda if (xfer->rx_len >= 2) { 9647eb8f069SAndrzej Hajda payload[1] = reg >> 16; 9657eb8f069SAndrzej Hajda ++xfer->rx_done; 9667eb8f069SAndrzej Hajda } 9677eb8f069SAndrzej Hajda /* Fall through */ 9687eb8f069SAndrzej Hajda case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 9697eb8f069SAndrzej Hajda case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 9707eb8f069SAndrzej Hajda payload[0] = reg >> 8; 9717eb8f069SAndrzej Hajda ++xfer->rx_done; 9727eb8f069SAndrzej Hajda xfer->rx_len = xfer->rx_done; 9737eb8f069SAndrzej Hajda xfer->result = 0; 9747eb8f069SAndrzej Hajda goto clear_fifo; 9757eb8f069SAndrzej Hajda case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 9767eb8f069SAndrzej Hajda dev_err(dev, "DSI Error Report: 0x%04x\n", 9777eb8f069SAndrzej Hajda (reg >> 8) & 0xffff); 9787eb8f069SAndrzej Hajda xfer->result = 0; 9797eb8f069SAndrzej Hajda goto clear_fifo; 9807eb8f069SAndrzej Hajda } 9817eb8f069SAndrzej Hajda 9827eb8f069SAndrzej Hajda length = (reg >> 8) & 0xffff; 9837eb8f069SAndrzej Hajda if (length > xfer->rx_len) { 9847eb8f069SAndrzej Hajda dev_err(dev, 9857eb8f069SAndrzej Hajda "response too long (%u > %u bytes), stripping\n", 9867eb8f069SAndrzej Hajda xfer->rx_len, length); 9877eb8f069SAndrzej Hajda length = xfer->rx_len; 9887eb8f069SAndrzej Hajda } else if (length < xfer->rx_len) 9897eb8f069SAndrzej Hajda xfer->rx_len = length; 9907eb8f069SAndrzej Hajda } 9917eb8f069SAndrzej Hajda 9927eb8f069SAndrzej Hajda length = xfer->rx_len - xfer->rx_done; 9937eb8f069SAndrzej Hajda xfer->rx_done += length; 9947eb8f069SAndrzej Hajda 9957eb8f069SAndrzej Hajda /* Receive payload */ 9967eb8f069SAndrzej Hajda while (length >= 4) { 997ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 9987eb8f069SAndrzej Hajda payload[0] = (reg >> 0) & 0xff; 9997eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10007eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10017eb8f069SAndrzej Hajda payload[3] = (reg >> 24) & 0xff; 10027eb8f069SAndrzej Hajda payload += 4; 10037eb8f069SAndrzej Hajda length -= 4; 10047eb8f069SAndrzej Hajda } 10057eb8f069SAndrzej Hajda 10067eb8f069SAndrzej Hajda if (length) { 1007ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10087eb8f069SAndrzej Hajda switch (length) { 10097eb8f069SAndrzej Hajda case 3: 10107eb8f069SAndrzej Hajda payload[2] = (reg >> 16) & 0xff; 10117eb8f069SAndrzej Hajda /* Fall through */ 10127eb8f069SAndrzej Hajda case 2: 10137eb8f069SAndrzej Hajda payload[1] = (reg >> 8) & 0xff; 10147eb8f069SAndrzej Hajda /* Fall through */ 10157eb8f069SAndrzej Hajda case 1: 10167eb8f069SAndrzej Hajda payload[0] = reg & 0xff; 10177eb8f069SAndrzej Hajda } 10187eb8f069SAndrzej Hajda } 10197eb8f069SAndrzej Hajda 10207eb8f069SAndrzej Hajda if (xfer->rx_done == xfer->rx_len) 10217eb8f069SAndrzej Hajda xfer->result = 0; 10227eb8f069SAndrzej Hajda 10237eb8f069SAndrzej Hajda clear_fifo: 10247eb8f069SAndrzej Hajda length = DSI_RX_FIFO_SIZE / 4; 10257eb8f069SAndrzej Hajda do { 1026ba12ac2bSHyungwon Hwang reg = DSI_READ(dsi, DSIM_RXFIFO_REG); 10277eb8f069SAndrzej Hajda if (reg == DSI_RX_FIFO_EMPTY) 10287eb8f069SAndrzej Hajda break; 10297eb8f069SAndrzej Hajda } while (--length); 10307eb8f069SAndrzej Hajda } 10317eb8f069SAndrzej Hajda 10327eb8f069SAndrzej Hajda static void exynos_dsi_transfer_start(struct exynos_dsi *dsi) 10337eb8f069SAndrzej Hajda { 10347eb8f069SAndrzej Hajda unsigned long flags; 10357eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 10367eb8f069SAndrzej Hajda bool start = false; 10377eb8f069SAndrzej Hajda 10387eb8f069SAndrzej Hajda again: 10397eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 10407eb8f069SAndrzej Hajda 10417eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 10427eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 10437eb8f069SAndrzej Hajda return; 10447eb8f069SAndrzej Hajda } 10457eb8f069SAndrzej Hajda 10467eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 10477eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 10487eb8f069SAndrzej Hajda 10497eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 10507eb8f069SAndrzej Hajda 10517eb8f069SAndrzej Hajda if (xfer->tx_len && xfer->tx_done == xfer->tx_len) 10527eb8f069SAndrzej Hajda /* waiting for RX */ 10537eb8f069SAndrzej Hajda return; 10547eb8f069SAndrzej Hajda 10557eb8f069SAndrzej Hajda exynos_dsi_send_to_fifo(dsi, xfer); 10567eb8f069SAndrzej Hajda 10577eb8f069SAndrzej Hajda if (xfer->tx_len || xfer->rx_len) 10587eb8f069SAndrzej Hajda return; 10597eb8f069SAndrzej Hajda 10607eb8f069SAndrzej Hajda xfer->result = 0; 10617eb8f069SAndrzej Hajda complete(&xfer->completed); 10627eb8f069SAndrzej Hajda 10637eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 10647eb8f069SAndrzej Hajda 10657eb8f069SAndrzej Hajda list_del_init(&xfer->list); 10667eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 10677eb8f069SAndrzej Hajda 10687eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 10697eb8f069SAndrzej Hajda 10707eb8f069SAndrzej Hajda if (start) 10717eb8f069SAndrzej Hajda goto again; 10727eb8f069SAndrzej Hajda } 10737eb8f069SAndrzej Hajda 10747eb8f069SAndrzej Hajda static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi) 10757eb8f069SAndrzej Hajda { 10767eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer; 10777eb8f069SAndrzej Hajda unsigned long flags; 10787eb8f069SAndrzej Hajda bool start = true; 10797eb8f069SAndrzej Hajda 10807eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 10817eb8f069SAndrzej Hajda 10827eb8f069SAndrzej Hajda if (list_empty(&dsi->transfer_list)) { 10837eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 10847eb8f069SAndrzej Hajda return false; 10857eb8f069SAndrzej Hajda } 10867eb8f069SAndrzej Hajda 10877eb8f069SAndrzej Hajda xfer = list_first_entry(&dsi->transfer_list, 10887eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list); 10897eb8f069SAndrzej Hajda 10907eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 10917eb8f069SAndrzej Hajda 10927eb8f069SAndrzej Hajda dev_dbg(dsi->dev, 10937eb8f069SAndrzej Hajda "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n", 10947eb8f069SAndrzej Hajda xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done); 10957eb8f069SAndrzej Hajda 10967eb8f069SAndrzej Hajda if (xfer->tx_done != xfer->tx_len) 10977eb8f069SAndrzej Hajda return true; 10987eb8f069SAndrzej Hajda 10997eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11007eb8f069SAndrzej Hajda exynos_dsi_read_from_fifo(dsi, xfer); 11017eb8f069SAndrzej Hajda 11027eb8f069SAndrzej Hajda if (xfer->rx_done != xfer->rx_len) 11037eb8f069SAndrzej Hajda return true; 11047eb8f069SAndrzej Hajda 11057eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11067eb8f069SAndrzej Hajda 11077eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11087eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11097eb8f069SAndrzej Hajda 11107eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11117eb8f069SAndrzej Hajda 11127eb8f069SAndrzej Hajda if (!xfer->rx_len) 11137eb8f069SAndrzej Hajda xfer->result = 0; 11147eb8f069SAndrzej Hajda complete(&xfer->completed); 11157eb8f069SAndrzej Hajda 11167eb8f069SAndrzej Hajda return start; 11177eb8f069SAndrzej Hajda } 11187eb8f069SAndrzej Hajda 11197eb8f069SAndrzej Hajda static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi, 11207eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 11217eb8f069SAndrzej Hajda { 11227eb8f069SAndrzej Hajda unsigned long flags; 11237eb8f069SAndrzej Hajda bool start; 11247eb8f069SAndrzej Hajda 11257eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11267eb8f069SAndrzej Hajda 11277eb8f069SAndrzej Hajda if (!list_empty(&dsi->transfer_list) && 11287eb8f069SAndrzej Hajda xfer == list_first_entry(&dsi->transfer_list, 11297eb8f069SAndrzej Hajda struct exynos_dsi_transfer, list)) { 11307eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11317eb8f069SAndrzej Hajda start = !list_empty(&dsi->transfer_list); 11327eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11337eb8f069SAndrzej Hajda if (start) 11347eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 11357eb8f069SAndrzej Hajda return; 11367eb8f069SAndrzej Hajda } 11377eb8f069SAndrzej Hajda 11387eb8f069SAndrzej Hajda list_del_init(&xfer->list); 11397eb8f069SAndrzej Hajda 11407eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11417eb8f069SAndrzej Hajda } 11427eb8f069SAndrzej Hajda 11437eb8f069SAndrzej Hajda static int exynos_dsi_transfer(struct exynos_dsi *dsi, 11447eb8f069SAndrzej Hajda struct exynos_dsi_transfer *xfer) 11457eb8f069SAndrzej Hajda { 11467eb8f069SAndrzej Hajda unsigned long flags; 11477eb8f069SAndrzej Hajda bool stopped; 11487eb8f069SAndrzej Hajda 11497eb8f069SAndrzej Hajda xfer->tx_done = 0; 11507eb8f069SAndrzej Hajda xfer->rx_done = 0; 11517eb8f069SAndrzej Hajda xfer->result = -ETIMEDOUT; 11527eb8f069SAndrzej Hajda init_completion(&xfer->completed); 11537eb8f069SAndrzej Hajda 11547eb8f069SAndrzej Hajda spin_lock_irqsave(&dsi->transfer_lock, flags); 11557eb8f069SAndrzej Hajda 11567eb8f069SAndrzej Hajda stopped = list_empty(&dsi->transfer_list); 11577eb8f069SAndrzej Hajda list_add_tail(&xfer->list, &dsi->transfer_list); 11587eb8f069SAndrzej Hajda 11597eb8f069SAndrzej Hajda spin_unlock_irqrestore(&dsi->transfer_lock, flags); 11607eb8f069SAndrzej Hajda 11617eb8f069SAndrzej Hajda if (stopped) 11627eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 11637eb8f069SAndrzej Hajda 11647eb8f069SAndrzej Hajda wait_for_completion_timeout(&xfer->completed, 11657eb8f069SAndrzej Hajda msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 11667eb8f069SAndrzej Hajda if (xfer->result == -ETIMEDOUT) { 11677eb8f069SAndrzej Hajda exynos_dsi_remove_transfer(dsi, xfer); 11687eb8f069SAndrzej Hajda dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data, 11697eb8f069SAndrzej Hajda xfer->tx_len, xfer->tx_payload); 11707eb8f069SAndrzej Hajda return -ETIMEDOUT; 11717eb8f069SAndrzej Hajda } 11727eb8f069SAndrzej Hajda 11737eb8f069SAndrzej Hajda /* Also covers hardware timeout condition */ 11747eb8f069SAndrzej Hajda return xfer->result; 11757eb8f069SAndrzej Hajda } 11767eb8f069SAndrzej Hajda 11777eb8f069SAndrzej Hajda static irqreturn_t exynos_dsi_irq(int irq, void *dev_id) 11787eb8f069SAndrzej Hajda { 11797eb8f069SAndrzej Hajda struct exynos_dsi *dsi = dev_id; 11807eb8f069SAndrzej Hajda u32 status; 11817eb8f069SAndrzej Hajda 1182ba12ac2bSHyungwon Hwang status = DSI_READ(dsi, DSIM_INTSRC_REG); 11837eb8f069SAndrzej Hajda if (!status) { 11847eb8f069SAndrzej Hajda static unsigned long int j; 11857eb8f069SAndrzej Hajda if (printk_timed_ratelimit(&j, 500)) 11867eb8f069SAndrzej Hajda dev_warn(dsi->dev, "spurious interrupt\n"); 11877eb8f069SAndrzej Hajda return IRQ_HANDLED; 11887eb8f069SAndrzej Hajda } 1189ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_INTSRC_REG, status); 11907eb8f069SAndrzej Hajda 11917eb8f069SAndrzej Hajda if (status & DSIM_INT_SW_RST_RELEASE) { 11927eb8f069SAndrzej Hajda u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY); 1193ba12ac2bSHyungwon Hwang DSI_WRITE(dsi, DSIM_INTMSK_REG, mask); 11947eb8f069SAndrzej Hajda complete(&dsi->completed); 11957eb8f069SAndrzej Hajda return IRQ_HANDLED; 11967eb8f069SAndrzej Hajda } 11977eb8f069SAndrzej Hajda 11987eb8f069SAndrzej Hajda if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY))) 11997eb8f069SAndrzej Hajda return IRQ_HANDLED; 12007eb8f069SAndrzej Hajda 12017eb8f069SAndrzej Hajda if (exynos_dsi_transfer_finish(dsi)) 12027eb8f069SAndrzej Hajda exynos_dsi_transfer_start(dsi); 12037eb8f069SAndrzej Hajda 12047eb8f069SAndrzej Hajda return IRQ_HANDLED; 12057eb8f069SAndrzej Hajda } 12067eb8f069SAndrzej Hajda 1207e17ddeccSYoungJun Cho static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id) 1208e17ddeccSYoungJun Cho { 1209e17ddeccSYoungJun Cho struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id; 1210e5169723SAndrzej Hajda struct drm_encoder *encoder = dsi->display.encoder; 1211e17ddeccSYoungJun Cho 12120e480f6fSHyungwon Hwang if (dsi->state & DSIM_STATE_VIDOUT_AVAILABLE) 1213e17ddeccSYoungJun Cho exynos_drm_crtc_te_handler(encoder->crtc); 1214e17ddeccSYoungJun Cho 1215e17ddeccSYoungJun Cho return IRQ_HANDLED; 1216e17ddeccSYoungJun Cho } 1217e17ddeccSYoungJun Cho 1218e17ddeccSYoungJun Cho static void exynos_dsi_enable_irq(struct exynos_dsi *dsi) 1219e17ddeccSYoungJun Cho { 1220e17ddeccSYoungJun Cho enable_irq(dsi->irq); 1221e17ddeccSYoungJun Cho 1222e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1223e17ddeccSYoungJun Cho enable_irq(gpio_to_irq(dsi->te_gpio)); 1224e17ddeccSYoungJun Cho } 1225e17ddeccSYoungJun Cho 1226e17ddeccSYoungJun Cho static void exynos_dsi_disable_irq(struct exynos_dsi *dsi) 1227e17ddeccSYoungJun Cho { 1228e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) 1229e17ddeccSYoungJun Cho disable_irq(gpio_to_irq(dsi->te_gpio)); 1230e17ddeccSYoungJun Cho 1231e17ddeccSYoungJun Cho disable_irq(dsi->irq); 1232e17ddeccSYoungJun Cho } 1233e17ddeccSYoungJun Cho 12347eb8f069SAndrzej Hajda static int exynos_dsi_init(struct exynos_dsi *dsi) 12357eb8f069SAndrzej Hajda { 1236d668e8bfSHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 1237d668e8bfSHyungwon Hwang 12387eb8f069SAndrzej Hajda exynos_dsi_reset(dsi); 1239e17ddeccSYoungJun Cho exynos_dsi_enable_irq(dsi); 12409a320415SYoungJun Cho exynos_dsi_enable_clock(dsi); 1241d668e8bfSHyungwon Hwang if (driver_data->wait_for_reset) 12427eb8f069SAndrzej Hajda exynos_dsi_wait_for_reset(dsi); 12439a320415SYoungJun Cho exynos_dsi_set_phy_ctrl(dsi); 12447eb8f069SAndrzej Hajda exynos_dsi_init_link(dsi); 12457eb8f069SAndrzej Hajda 12467eb8f069SAndrzej Hajda return 0; 12477eb8f069SAndrzej Hajda } 12487eb8f069SAndrzej Hajda 1249e17ddeccSYoungJun Cho static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi) 1250e17ddeccSYoungJun Cho { 1251e17ddeccSYoungJun Cho int ret; 12520cef83a5SYoungJun Cho int te_gpio_irq; 1253e17ddeccSYoungJun Cho 1254e17ddeccSYoungJun Cho dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0); 1255e17ddeccSYoungJun Cho if (!gpio_is_valid(dsi->te_gpio)) { 1256e17ddeccSYoungJun Cho dev_err(dsi->dev, "no te-gpios specified\n"); 1257e17ddeccSYoungJun Cho ret = dsi->te_gpio; 1258e17ddeccSYoungJun Cho goto out; 1259e17ddeccSYoungJun Cho } 1260e17ddeccSYoungJun Cho 1261e17ddeccSYoungJun Cho ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio"); 1262e17ddeccSYoungJun Cho if (ret) { 1263e17ddeccSYoungJun Cho dev_err(dsi->dev, "gpio request failed with %d\n", ret); 1264e17ddeccSYoungJun Cho goto out; 1265e17ddeccSYoungJun Cho } 1266e17ddeccSYoungJun Cho 12670cef83a5SYoungJun Cho te_gpio_irq = gpio_to_irq(dsi->te_gpio); 12680cef83a5SYoungJun Cho 12690cef83a5SYoungJun Cho irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN); 12700cef83a5SYoungJun Cho ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL, 1271e17ddeccSYoungJun Cho IRQF_TRIGGER_RISING, "TE", dsi); 1272e17ddeccSYoungJun Cho if (ret) { 1273e17ddeccSYoungJun Cho dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1274e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1275e17ddeccSYoungJun Cho goto out; 1276e17ddeccSYoungJun Cho } 1277e17ddeccSYoungJun Cho 1278e17ddeccSYoungJun Cho out: 1279e17ddeccSYoungJun Cho return ret; 1280e17ddeccSYoungJun Cho } 1281e17ddeccSYoungJun Cho 1282e17ddeccSYoungJun Cho static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi) 1283e17ddeccSYoungJun Cho { 1284e17ddeccSYoungJun Cho if (gpio_is_valid(dsi->te_gpio)) { 1285e17ddeccSYoungJun Cho free_irq(gpio_to_irq(dsi->te_gpio), dsi); 1286e17ddeccSYoungJun Cho gpio_free(dsi->te_gpio); 1287e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1288e17ddeccSYoungJun Cho } 1289e17ddeccSYoungJun Cho } 1290e17ddeccSYoungJun Cho 12917eb8f069SAndrzej Hajda static int exynos_dsi_host_attach(struct mipi_dsi_host *host, 12927eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 12937eb8f069SAndrzej Hajda { 12947eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 12957eb8f069SAndrzej Hajda 12967eb8f069SAndrzej Hajda dsi->lanes = device->lanes; 12977eb8f069SAndrzej Hajda dsi->format = device->format; 12987eb8f069SAndrzej Hajda dsi->mode_flags = device->mode_flags; 12997eb8f069SAndrzej Hajda dsi->panel_node = device->dev.of_node; 13007eb8f069SAndrzej Hajda 1301e17ddeccSYoungJun Cho /* 1302e17ddeccSYoungJun Cho * This is a temporary solution and should be made by more generic way. 1303e17ddeccSYoungJun Cho * 1304e17ddeccSYoungJun Cho * If attached panel device is for command mode one, dsi should register 1305e17ddeccSYoungJun Cho * TE interrupt handler. 1306e17ddeccSYoungJun Cho */ 1307e17ddeccSYoungJun Cho if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1308e17ddeccSYoungJun Cho int ret = exynos_dsi_register_te_irq(dsi); 1309e17ddeccSYoungJun Cho 1310e17ddeccSYoungJun Cho if (ret) 1311e17ddeccSYoungJun Cho return ret; 1312e17ddeccSYoungJun Cho } 1313e17ddeccSYoungJun Cho 1314ecb84157SYoungJun Cho if (dsi->connector.dev) 1315ecb84157SYoungJun Cho drm_helper_hpd_irq_event(dsi->connector.dev); 1316ecb84157SYoungJun Cho 13177eb8f069SAndrzej Hajda return 0; 13187eb8f069SAndrzej Hajda } 13197eb8f069SAndrzej Hajda 13207eb8f069SAndrzej Hajda static int exynos_dsi_host_detach(struct mipi_dsi_host *host, 13217eb8f069SAndrzej Hajda struct mipi_dsi_device *device) 13227eb8f069SAndrzej Hajda { 13237eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 13247eb8f069SAndrzej Hajda 1325e17ddeccSYoungJun Cho exynos_dsi_unregister_te_irq(dsi); 1326e17ddeccSYoungJun Cho 13277eb8f069SAndrzej Hajda dsi->panel_node = NULL; 13287eb8f069SAndrzej Hajda 13297eb8f069SAndrzej Hajda if (dsi->connector.dev) 13307eb8f069SAndrzej Hajda drm_helper_hpd_irq_event(dsi->connector.dev); 13317eb8f069SAndrzej Hajda 13327eb8f069SAndrzej Hajda return 0; 13337eb8f069SAndrzej Hajda } 13347eb8f069SAndrzej Hajda 13357eb8f069SAndrzej Hajda /* distinguish between short and long DSI packet types */ 13367eb8f069SAndrzej Hajda static bool exynos_dsi_is_short_dsi_type(u8 type) 13377eb8f069SAndrzej Hajda { 13387eb8f069SAndrzej Hajda return (type & 0x0f) <= 8; 13397eb8f069SAndrzej Hajda } 13407eb8f069SAndrzej Hajda 13417eb8f069SAndrzej Hajda static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host, 1342ed6ff40eSThierry Reding const struct mipi_dsi_msg *msg) 13437eb8f069SAndrzej Hajda { 13447eb8f069SAndrzej Hajda struct exynos_dsi *dsi = host_to_dsi(host); 13457eb8f069SAndrzej Hajda struct exynos_dsi_transfer xfer; 13467eb8f069SAndrzej Hajda int ret; 13477eb8f069SAndrzej Hajda 13480e480f6fSHyungwon Hwang if (!(dsi->state & DSIM_STATE_ENABLED)) 13490e480f6fSHyungwon Hwang return -EINVAL; 13500e480f6fSHyungwon Hwang 13517eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_INITIALIZED)) { 13527eb8f069SAndrzej Hajda ret = exynos_dsi_init(dsi); 13537eb8f069SAndrzej Hajda if (ret) 13547eb8f069SAndrzej Hajda return ret; 13557eb8f069SAndrzej Hajda dsi->state |= DSIM_STATE_INITIALIZED; 13567eb8f069SAndrzej Hajda } 13577eb8f069SAndrzej Hajda 13587eb8f069SAndrzej Hajda if (msg->tx_len == 0) 13597eb8f069SAndrzej Hajda return -EINVAL; 13607eb8f069SAndrzej Hajda 13617eb8f069SAndrzej Hajda xfer.data_id = msg->type | (msg->channel << 6); 13627eb8f069SAndrzej Hajda 13637eb8f069SAndrzej Hajda if (exynos_dsi_is_short_dsi_type(msg->type)) { 13647eb8f069SAndrzej Hajda const char *tx_buf = msg->tx_buf; 13657eb8f069SAndrzej Hajda 13667eb8f069SAndrzej Hajda if (msg->tx_len > 2) 13677eb8f069SAndrzej Hajda return -EINVAL; 13687eb8f069SAndrzej Hajda xfer.tx_len = 0; 13697eb8f069SAndrzej Hajda xfer.data[0] = tx_buf[0]; 13707eb8f069SAndrzej Hajda xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0; 13717eb8f069SAndrzej Hajda } else { 13727eb8f069SAndrzej Hajda xfer.tx_len = msg->tx_len; 13737eb8f069SAndrzej Hajda xfer.data[0] = msg->tx_len & 0xff; 13747eb8f069SAndrzej Hajda xfer.data[1] = msg->tx_len >> 8; 13757eb8f069SAndrzej Hajda xfer.tx_payload = msg->tx_buf; 13767eb8f069SAndrzej Hajda } 13777eb8f069SAndrzej Hajda 13787eb8f069SAndrzej Hajda xfer.rx_len = msg->rx_len; 13797eb8f069SAndrzej Hajda xfer.rx_payload = msg->rx_buf; 13807eb8f069SAndrzej Hajda xfer.flags = msg->flags; 13817eb8f069SAndrzej Hajda 13827eb8f069SAndrzej Hajda ret = exynos_dsi_transfer(dsi, &xfer); 13837eb8f069SAndrzej Hajda return (ret < 0) ? ret : xfer.rx_done; 13847eb8f069SAndrzej Hajda } 13857eb8f069SAndrzej Hajda 13867eb8f069SAndrzej Hajda static const struct mipi_dsi_host_ops exynos_dsi_ops = { 13877eb8f069SAndrzej Hajda .attach = exynos_dsi_host_attach, 13887eb8f069SAndrzej Hajda .detach = exynos_dsi_host_detach, 13897eb8f069SAndrzej Hajda .transfer = exynos_dsi_host_transfer, 13907eb8f069SAndrzej Hajda }; 13917eb8f069SAndrzej Hajda 13927eb8f069SAndrzej Hajda static int exynos_dsi_poweron(struct exynos_dsi *dsi) 13937eb8f069SAndrzej Hajda { 13940ff03fd1SHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 13950ff03fd1SHyungwon Hwang int ret, i; 13967eb8f069SAndrzej Hajda 13977eb8f069SAndrzej Hajda ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 13987eb8f069SAndrzej Hajda if (ret < 0) { 13997eb8f069SAndrzej Hajda dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 14007eb8f069SAndrzej Hajda return ret; 14017eb8f069SAndrzej Hajda } 14027eb8f069SAndrzej Hajda 14030ff03fd1SHyungwon Hwang for (i = 0; i < driver_data->num_clks; i++) { 14040ff03fd1SHyungwon Hwang ret = clk_prepare_enable(dsi->clks[i]); 14050ff03fd1SHyungwon Hwang if (ret < 0) 14060ff03fd1SHyungwon Hwang goto err_clk; 14077eb8f069SAndrzej Hajda } 14087eb8f069SAndrzej Hajda 14097eb8f069SAndrzej Hajda ret = phy_power_on(dsi->phy); 14107eb8f069SAndrzej Hajda if (ret < 0) { 14117eb8f069SAndrzej Hajda dev_err(dsi->dev, "cannot enable phy %d\n", ret); 14120ff03fd1SHyungwon Hwang goto err_clk; 14137eb8f069SAndrzej Hajda } 14147eb8f069SAndrzej Hajda 14157eb8f069SAndrzej Hajda return 0; 14167eb8f069SAndrzej Hajda 14170ff03fd1SHyungwon Hwang err_clk: 14180ff03fd1SHyungwon Hwang while (--i > -1) 14190ff03fd1SHyungwon Hwang clk_disable_unprepare(dsi->clks[i]); 14207eb8f069SAndrzej Hajda regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 14217eb8f069SAndrzej Hajda 14227eb8f069SAndrzej Hajda return ret; 14237eb8f069SAndrzej Hajda } 14247eb8f069SAndrzej Hajda 14257eb8f069SAndrzej Hajda static void exynos_dsi_poweroff(struct exynos_dsi *dsi) 14267eb8f069SAndrzej Hajda { 14270ff03fd1SHyungwon Hwang struct exynos_dsi_driver_data *driver_data = dsi->driver_data; 14280ff03fd1SHyungwon Hwang int ret, i; 14297eb8f069SAndrzej Hajda 14307eb8f069SAndrzej Hajda usleep_range(10000, 20000); 14317eb8f069SAndrzej Hajda 14327eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_INITIALIZED) { 14337eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_INITIALIZED; 14347eb8f069SAndrzej Hajda 14357eb8f069SAndrzej Hajda exynos_dsi_disable_clock(dsi); 14367eb8f069SAndrzej Hajda 1437e17ddeccSYoungJun Cho exynos_dsi_disable_irq(dsi); 14387eb8f069SAndrzej Hajda } 14397eb8f069SAndrzej Hajda 14407eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_CMD_LPM; 14417eb8f069SAndrzej Hajda 14427eb8f069SAndrzej Hajda phy_power_off(dsi->phy); 14437eb8f069SAndrzej Hajda 14440ff03fd1SHyungwon Hwang for (i = driver_data->num_clks - 1; i > -1; i--) 14450ff03fd1SHyungwon Hwang clk_disable_unprepare(dsi->clks[i]); 14467eb8f069SAndrzej Hajda 14477eb8f069SAndrzej Hajda ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 14487eb8f069SAndrzej Hajda if (ret < 0) 14497eb8f069SAndrzej Hajda dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 14507eb8f069SAndrzej Hajda } 14517eb8f069SAndrzej Hajda 14527eb8f069SAndrzej Hajda static int exynos_dsi_enable(struct exynos_dsi *dsi) 14537eb8f069SAndrzej Hajda { 14547eb8f069SAndrzej Hajda int ret; 14557eb8f069SAndrzej Hajda 14567eb8f069SAndrzej Hajda if (dsi->state & DSIM_STATE_ENABLED) 14577eb8f069SAndrzej Hajda return 0; 14587eb8f069SAndrzej Hajda 14597eb8f069SAndrzej Hajda ret = exynos_dsi_poweron(dsi); 14607eb8f069SAndrzej Hajda if (ret < 0) 14617eb8f069SAndrzej Hajda return ret; 14627eb8f069SAndrzej Hajda 14630e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_ENABLED; 14640e480f6fSHyungwon Hwang 1465cdfb8694SAjay Kumar ret = drm_panel_prepare(dsi->panel); 14667eb8f069SAndrzej Hajda if (ret < 0) { 14670e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_ENABLED; 14687eb8f069SAndrzej Hajda exynos_dsi_poweroff(dsi); 14697eb8f069SAndrzej Hajda return ret; 14707eb8f069SAndrzej Hajda } 14717eb8f069SAndrzej Hajda 14727eb8f069SAndrzej Hajda exynos_dsi_set_display_mode(dsi); 14737eb8f069SAndrzej Hajda exynos_dsi_set_display_enable(dsi, true); 14747eb8f069SAndrzej Hajda 1475cdfb8694SAjay Kumar ret = drm_panel_enable(dsi->panel); 1476cdfb8694SAjay Kumar if (ret < 0) { 1477d41bb38fSYoungJun Cho dsi->state &= ~DSIM_STATE_ENABLED; 1478cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1479cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 1480cdfb8694SAjay Kumar exynos_dsi_poweroff(dsi); 1481cdfb8694SAjay Kumar return ret; 1482cdfb8694SAjay Kumar } 1483cdfb8694SAjay Kumar 14840e480f6fSHyungwon Hwang dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 14850e480f6fSHyungwon Hwang 14867eb8f069SAndrzej Hajda return 0; 14877eb8f069SAndrzej Hajda } 14887eb8f069SAndrzej Hajda 14897eb8f069SAndrzej Hajda static void exynos_dsi_disable(struct exynos_dsi *dsi) 14907eb8f069SAndrzej Hajda { 14917eb8f069SAndrzej Hajda if (!(dsi->state & DSIM_STATE_ENABLED)) 14927eb8f069SAndrzej Hajda return; 14937eb8f069SAndrzej Hajda 14940e480f6fSHyungwon Hwang dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 14950e480f6fSHyungwon Hwang 14967eb8f069SAndrzej Hajda drm_panel_disable(dsi->panel); 1497cdfb8694SAjay Kumar exynos_dsi_set_display_enable(dsi, false); 1498cdfb8694SAjay Kumar drm_panel_unprepare(dsi->panel); 14997eb8f069SAndrzej Hajda 15007eb8f069SAndrzej Hajda dsi->state &= ~DSIM_STATE_ENABLED; 15010e480f6fSHyungwon Hwang 15020e480f6fSHyungwon Hwang exynos_dsi_poweroff(dsi); 15037eb8f069SAndrzej Hajda } 15047eb8f069SAndrzej Hajda 15057eb8f069SAndrzej Hajda static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode) 15067eb8f069SAndrzej Hajda { 15075cd5db80SAndrzej Hajda struct exynos_dsi *dsi = display_to_dsi(display); 15087eb8f069SAndrzej Hajda 15097eb8f069SAndrzej Hajda if (dsi->panel) { 15107eb8f069SAndrzej Hajda switch (mode) { 15117eb8f069SAndrzej Hajda case DRM_MODE_DPMS_ON: 15127eb8f069SAndrzej Hajda exynos_dsi_enable(dsi); 15137eb8f069SAndrzej Hajda break; 15147eb8f069SAndrzej Hajda case DRM_MODE_DPMS_STANDBY: 15157eb8f069SAndrzej Hajda case DRM_MODE_DPMS_SUSPEND: 15167eb8f069SAndrzej Hajda case DRM_MODE_DPMS_OFF: 15177eb8f069SAndrzej Hajda exynos_dsi_disable(dsi); 15187eb8f069SAndrzej Hajda break; 15197eb8f069SAndrzej Hajda default: 15207eb8f069SAndrzej Hajda break; 15217eb8f069SAndrzej Hajda } 15227eb8f069SAndrzej Hajda } 15237eb8f069SAndrzej Hajda } 15247eb8f069SAndrzej Hajda 15257eb8f069SAndrzej Hajda static enum drm_connector_status 15267eb8f069SAndrzej Hajda exynos_dsi_detect(struct drm_connector *connector, bool force) 15277eb8f069SAndrzej Hajda { 15287eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15297eb8f069SAndrzej Hajda 15307eb8f069SAndrzej Hajda if (!dsi->panel) { 15317eb8f069SAndrzej Hajda dsi->panel = of_drm_find_panel(dsi->panel_node); 15327eb8f069SAndrzej Hajda if (dsi->panel) 15337eb8f069SAndrzej Hajda drm_panel_attach(dsi->panel, &dsi->connector); 15347eb8f069SAndrzej Hajda } else if (!dsi->panel_node) { 15357eb8f069SAndrzej Hajda struct exynos_drm_display *display; 15367eb8f069SAndrzej Hajda 15377eb8f069SAndrzej Hajda display = platform_get_drvdata(to_platform_device(dsi->dev)); 15387eb8f069SAndrzej Hajda exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); 15397eb8f069SAndrzej Hajda drm_panel_detach(dsi->panel); 15407eb8f069SAndrzej Hajda dsi->panel = NULL; 15417eb8f069SAndrzej Hajda } 15427eb8f069SAndrzej Hajda 15437eb8f069SAndrzej Hajda if (dsi->panel) 15447eb8f069SAndrzej Hajda return connector_status_connected; 15457eb8f069SAndrzej Hajda 15467eb8f069SAndrzej Hajda return connector_status_disconnected; 15477eb8f069SAndrzej Hajda } 15487eb8f069SAndrzej Hajda 15497eb8f069SAndrzej Hajda static void exynos_dsi_connector_destroy(struct drm_connector *connector) 15507eb8f069SAndrzej Hajda { 15510ae46015SAndrzej Hajda drm_connector_unregister(connector); 15520ae46015SAndrzej Hajda drm_connector_cleanup(connector); 15530ae46015SAndrzej Hajda connector->dev = NULL; 15547eb8f069SAndrzej Hajda } 15557eb8f069SAndrzej Hajda 15567eb8f069SAndrzej Hajda static struct drm_connector_funcs exynos_dsi_connector_funcs = { 155763498e30SGustavo Padovan .dpms = drm_atomic_helper_connector_dpms, 15587eb8f069SAndrzej Hajda .detect = exynos_dsi_detect, 15597eb8f069SAndrzej Hajda .fill_modes = drm_helper_probe_single_connector_modes, 15607eb8f069SAndrzej Hajda .destroy = exynos_dsi_connector_destroy, 15614ea9526bSGustavo Padovan .reset = drm_atomic_helper_connector_reset, 15624ea9526bSGustavo Padovan .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 15634ea9526bSGustavo Padovan .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 15647eb8f069SAndrzej Hajda }; 15657eb8f069SAndrzej Hajda 15667eb8f069SAndrzej Hajda static int exynos_dsi_get_modes(struct drm_connector *connector) 15677eb8f069SAndrzej Hajda { 15687eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15697eb8f069SAndrzej Hajda 15707eb8f069SAndrzej Hajda if (dsi->panel) 15717eb8f069SAndrzej Hajda return dsi->panel->funcs->get_modes(dsi->panel); 15727eb8f069SAndrzej Hajda 15737eb8f069SAndrzej Hajda return 0; 15747eb8f069SAndrzej Hajda } 15757eb8f069SAndrzej Hajda 15767eb8f069SAndrzej Hajda static struct drm_encoder * 15777eb8f069SAndrzej Hajda exynos_dsi_best_encoder(struct drm_connector *connector) 15787eb8f069SAndrzej Hajda { 15797eb8f069SAndrzej Hajda struct exynos_dsi *dsi = connector_to_dsi(connector); 15807eb8f069SAndrzej Hajda 1581e5169723SAndrzej Hajda return dsi->display.encoder; 15827eb8f069SAndrzej Hajda } 15837eb8f069SAndrzej Hajda 15847eb8f069SAndrzej Hajda static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = { 15857eb8f069SAndrzej Hajda .get_modes = exynos_dsi_get_modes, 15867eb8f069SAndrzej Hajda .best_encoder = exynos_dsi_best_encoder, 15877eb8f069SAndrzej Hajda }; 15887eb8f069SAndrzej Hajda 15897eb8f069SAndrzej Hajda static int exynos_dsi_create_connector(struct exynos_drm_display *display, 15907eb8f069SAndrzej Hajda struct drm_encoder *encoder) 15917eb8f069SAndrzej Hajda { 15925cd5db80SAndrzej Hajda struct exynos_dsi *dsi = display_to_dsi(display); 15937eb8f069SAndrzej Hajda struct drm_connector *connector = &dsi->connector; 15947eb8f069SAndrzej Hajda int ret; 15957eb8f069SAndrzej Hajda 15967eb8f069SAndrzej Hajda connector->polled = DRM_CONNECTOR_POLL_HPD; 15977eb8f069SAndrzej Hajda 15987eb8f069SAndrzej Hajda ret = drm_connector_init(encoder->dev, connector, 15997eb8f069SAndrzej Hajda &exynos_dsi_connector_funcs, 16007eb8f069SAndrzej Hajda DRM_MODE_CONNECTOR_DSI); 16017eb8f069SAndrzej Hajda if (ret) { 16027eb8f069SAndrzej Hajda DRM_ERROR("Failed to initialize connector with drm\n"); 16037eb8f069SAndrzej Hajda return ret; 16047eb8f069SAndrzej Hajda } 16057eb8f069SAndrzej Hajda 16067eb8f069SAndrzej Hajda drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs); 160734ea3d38SThomas Wood drm_connector_register(connector); 16087eb8f069SAndrzej Hajda drm_mode_connector_attach_encoder(connector, encoder); 16097eb8f069SAndrzej Hajda 16107eb8f069SAndrzej Hajda return 0; 16117eb8f069SAndrzej Hajda } 16127eb8f069SAndrzej Hajda 16137eb8f069SAndrzej Hajda static void exynos_dsi_mode_set(struct exynos_drm_display *display, 16147eb8f069SAndrzej Hajda struct drm_display_mode *mode) 16157eb8f069SAndrzej Hajda { 16165cd5db80SAndrzej Hajda struct exynos_dsi *dsi = display_to_dsi(display); 16177eb8f069SAndrzej Hajda struct videomode *vm = &dsi->vm; 16187eb8f069SAndrzej Hajda 16197eb8f069SAndrzej Hajda vm->hactive = mode->hdisplay; 16207eb8f069SAndrzej Hajda vm->vactive = mode->vdisplay; 16217eb8f069SAndrzej Hajda vm->vfront_porch = mode->vsync_start - mode->vdisplay; 16227eb8f069SAndrzej Hajda vm->vback_porch = mode->vtotal - mode->vsync_end; 16237eb8f069SAndrzej Hajda vm->vsync_len = mode->vsync_end - mode->vsync_start; 16247eb8f069SAndrzej Hajda vm->hfront_porch = mode->hsync_start - mode->hdisplay; 16257eb8f069SAndrzej Hajda vm->hback_porch = mode->htotal - mode->hsync_end; 16267eb8f069SAndrzej Hajda vm->hsync_len = mode->hsync_end - mode->hsync_start; 16277eb8f069SAndrzej Hajda } 16287eb8f069SAndrzej Hajda 16297eb8f069SAndrzej Hajda static struct exynos_drm_display_ops exynos_dsi_display_ops = { 16307eb8f069SAndrzej Hajda .create_connector = exynos_dsi_create_connector, 16317eb8f069SAndrzej Hajda .mode_set = exynos_dsi_mode_set, 16327eb8f069SAndrzej Hajda .dpms = exynos_dsi_dpms 16337eb8f069SAndrzej Hajda }; 16347eb8f069SAndrzej Hajda 1635bd024b86SSjoerd Simons MODULE_DEVICE_TABLE(of, exynos_dsi_of_match); 16367eb8f069SAndrzej Hajda 16377eb8f069SAndrzej Hajda /* of_* functions will be removed after merge of of_graph patches */ 16387eb8f069SAndrzej Hajda static struct device_node * 16397eb8f069SAndrzej Hajda of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg) 16407eb8f069SAndrzej Hajda { 16417eb8f069SAndrzej Hajda struct device_node *np; 16427eb8f069SAndrzej Hajda 16437eb8f069SAndrzej Hajda for_each_child_of_node(parent, np) { 16447eb8f069SAndrzej Hajda u32 r; 16457eb8f069SAndrzej Hajda 16467eb8f069SAndrzej Hajda if (!np->name || of_node_cmp(np->name, name)) 16477eb8f069SAndrzej Hajda continue; 16487eb8f069SAndrzej Hajda 16497eb8f069SAndrzej Hajda if (of_property_read_u32(np, "reg", &r) < 0) 16507eb8f069SAndrzej Hajda r = 0; 16517eb8f069SAndrzej Hajda 16527eb8f069SAndrzej Hajda if (reg == r) 16537eb8f069SAndrzej Hajda break; 16547eb8f069SAndrzej Hajda } 16557eb8f069SAndrzej Hajda 16567eb8f069SAndrzej Hajda return np; 16577eb8f069SAndrzej Hajda } 16587eb8f069SAndrzej Hajda 16597eb8f069SAndrzej Hajda static struct device_node *of_graph_get_port_by_reg(struct device_node *parent, 16607eb8f069SAndrzej Hajda u32 reg) 16617eb8f069SAndrzej Hajda { 16627eb8f069SAndrzej Hajda struct device_node *ports, *port; 16637eb8f069SAndrzej Hajda 16647eb8f069SAndrzej Hajda ports = of_get_child_by_name(parent, "ports"); 16657eb8f069SAndrzej Hajda if (ports) 16667eb8f069SAndrzej Hajda parent = ports; 16677eb8f069SAndrzej Hajda 16687eb8f069SAndrzej Hajda port = of_get_child_by_name_reg(parent, "port", reg); 16697eb8f069SAndrzej Hajda 16707eb8f069SAndrzej Hajda of_node_put(ports); 16717eb8f069SAndrzej Hajda 16727eb8f069SAndrzej Hajda return port; 16737eb8f069SAndrzej Hajda } 16747eb8f069SAndrzej Hajda 16757eb8f069SAndrzej Hajda static struct device_node * 16767eb8f069SAndrzej Hajda of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg) 16777eb8f069SAndrzej Hajda { 16787eb8f069SAndrzej Hajda return of_get_child_by_name_reg(port, "endpoint", reg); 16797eb8f069SAndrzej Hajda } 16807eb8f069SAndrzej Hajda 16817eb8f069SAndrzej Hajda static int exynos_dsi_of_read_u32(const struct device_node *np, 16827eb8f069SAndrzej Hajda const char *propname, u32 *out_value) 16837eb8f069SAndrzej Hajda { 16847eb8f069SAndrzej Hajda int ret = of_property_read_u32(np, propname, out_value); 16857eb8f069SAndrzej Hajda 16867eb8f069SAndrzej Hajda if (ret < 0) 16877eb8f069SAndrzej Hajda pr_err("%s: failed to get '%s' property\n", np->full_name, 16887eb8f069SAndrzej Hajda propname); 16897eb8f069SAndrzej Hajda 16907eb8f069SAndrzej Hajda return ret; 16917eb8f069SAndrzej Hajda } 16927eb8f069SAndrzej Hajda 16937eb8f069SAndrzej Hajda enum { 16947eb8f069SAndrzej Hajda DSI_PORT_IN, 16957eb8f069SAndrzej Hajda DSI_PORT_OUT 16967eb8f069SAndrzej Hajda }; 16977eb8f069SAndrzej Hajda 16987eb8f069SAndrzej Hajda static int exynos_dsi_parse_dt(struct exynos_dsi *dsi) 16997eb8f069SAndrzej Hajda { 17007eb8f069SAndrzej Hajda struct device *dev = dsi->dev; 17017eb8f069SAndrzej Hajda struct device_node *node = dev->of_node; 17027eb8f069SAndrzej Hajda struct device_node *port, *ep; 17037eb8f069SAndrzej Hajda int ret; 17047eb8f069SAndrzej Hajda 17057eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency", 17067eb8f069SAndrzej Hajda &dsi->pll_clk_rate); 17077eb8f069SAndrzej Hajda if (ret < 0) 17087eb8f069SAndrzej Hajda return ret; 17097eb8f069SAndrzej Hajda 17107eb8f069SAndrzej Hajda port = of_graph_get_port_by_reg(node, DSI_PORT_OUT); 17117eb8f069SAndrzej Hajda if (!port) { 17127eb8f069SAndrzej Hajda dev_err(dev, "no output port specified\n"); 17137eb8f069SAndrzej Hajda return -EINVAL; 17147eb8f069SAndrzej Hajda } 17157eb8f069SAndrzej Hajda 17167eb8f069SAndrzej Hajda ep = of_graph_get_endpoint_by_reg(port, 0); 17177eb8f069SAndrzej Hajda of_node_put(port); 17187eb8f069SAndrzej Hajda if (!ep) { 17197eb8f069SAndrzej Hajda dev_err(dev, "no endpoint specified in output port\n"); 17207eb8f069SAndrzej Hajda return -EINVAL; 17217eb8f069SAndrzej Hajda } 17227eb8f069SAndrzej Hajda 17237eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency", 17247eb8f069SAndrzej Hajda &dsi->burst_clk_rate); 17257eb8f069SAndrzej Hajda if (ret < 0) 17267eb8f069SAndrzej Hajda goto end; 17277eb8f069SAndrzej Hajda 17287eb8f069SAndrzej Hajda ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency", 17297eb8f069SAndrzej Hajda &dsi->esc_clk_rate); 17307eb8f069SAndrzej Hajda 17317eb8f069SAndrzej Hajda end: 17327eb8f069SAndrzej Hajda of_node_put(ep); 17337eb8f069SAndrzej Hajda 17347eb8f069SAndrzej Hajda return ret; 17357eb8f069SAndrzej Hajda } 17367eb8f069SAndrzej Hajda 1737f37cd5e8SInki Dae static int exynos_dsi_bind(struct device *dev, struct device *master, 1738f37cd5e8SInki Dae void *data) 1739f37cd5e8SInki Dae { 17402900c69cSAndrzej Hajda struct exynos_drm_display *display = dev_get_drvdata(dev); 17415cd5db80SAndrzej Hajda struct exynos_dsi *dsi = display_to_dsi(display); 1742f37cd5e8SInki Dae struct drm_device *drm_dev = data; 1743f37cd5e8SInki Dae int ret; 1744f37cd5e8SInki Dae 17452900c69cSAndrzej Hajda ret = exynos_drm_create_enc_conn(drm_dev, display); 1746f37cd5e8SInki Dae if (ret) { 1747f37cd5e8SInki Dae DRM_ERROR("Encoder create [%d] failed with %d\n", 17482900c69cSAndrzej Hajda display->type, ret); 1749f37cd5e8SInki Dae return ret; 1750f37cd5e8SInki Dae } 1751f37cd5e8SInki Dae 1752f37cd5e8SInki Dae return mipi_dsi_host_register(&dsi->dsi_host); 1753f37cd5e8SInki Dae } 1754f37cd5e8SInki Dae 1755f37cd5e8SInki Dae static void exynos_dsi_unbind(struct device *dev, struct device *master, 1756f37cd5e8SInki Dae void *data) 1757f37cd5e8SInki Dae { 17582900c69cSAndrzej Hajda struct exynos_drm_display *display = dev_get_drvdata(dev); 17595cd5db80SAndrzej Hajda struct exynos_dsi *dsi = display_to_dsi(display); 1760f37cd5e8SInki Dae 17612900c69cSAndrzej Hajda exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF); 1762f37cd5e8SInki Dae 17630ae46015SAndrzej Hajda mipi_dsi_host_unregister(&dsi->dsi_host); 1764f37cd5e8SInki Dae } 1765f37cd5e8SInki Dae 1766f37cd5e8SInki Dae static const struct component_ops exynos_dsi_component_ops = { 1767f37cd5e8SInki Dae .bind = exynos_dsi_bind, 1768f37cd5e8SInki Dae .unbind = exynos_dsi_unbind, 1769f37cd5e8SInki Dae }; 1770f37cd5e8SInki Dae 17717eb8f069SAndrzej Hajda static int exynos_dsi_probe(struct platform_device *pdev) 17727eb8f069SAndrzej Hajda { 17732900c69cSAndrzej Hajda struct device *dev = &pdev->dev; 17747eb8f069SAndrzej Hajda struct resource *res; 17757eb8f069SAndrzej Hajda struct exynos_dsi *dsi; 17760ff03fd1SHyungwon Hwang int ret, i; 17777eb8f069SAndrzej Hajda 17782900c69cSAndrzej Hajda dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 17792900c69cSAndrzej Hajda if (!dsi) 17802900c69cSAndrzej Hajda return -ENOMEM; 17812900c69cSAndrzej Hajda 17822900c69cSAndrzej Hajda dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD; 17832900c69cSAndrzej Hajda dsi->display.ops = &exynos_dsi_display_ops; 17842900c69cSAndrzej Hajda 1785e17ddeccSYoungJun Cho /* To be checked as invalid one */ 1786e17ddeccSYoungJun Cho dsi->te_gpio = -ENOENT; 1787e17ddeccSYoungJun Cho 17887eb8f069SAndrzej Hajda init_completion(&dsi->completed); 17897eb8f069SAndrzej Hajda spin_lock_init(&dsi->transfer_lock); 17907eb8f069SAndrzej Hajda INIT_LIST_HEAD(&dsi->transfer_list); 17917eb8f069SAndrzej Hajda 17927eb8f069SAndrzej Hajda dsi->dsi_host.ops = &exynos_dsi_ops; 1793e2d2a1e0SAndrzej Hajda dsi->dsi_host.dev = dev; 17947eb8f069SAndrzej Hajda 1795e2d2a1e0SAndrzej Hajda dsi->dev = dev; 17969a320415SYoungJun Cho dsi->driver_data = exynos_dsi_get_driver_data(pdev); 17977eb8f069SAndrzej Hajda 17987eb8f069SAndrzej Hajda ret = exynos_dsi_parse_dt(dsi); 17997eb8f069SAndrzej Hajda if (ret) 180086650408SAndrzej Hajda return ret; 18017eb8f069SAndrzej Hajda 18027eb8f069SAndrzej Hajda dsi->supplies[0].supply = "vddcore"; 18037eb8f069SAndrzej Hajda dsi->supplies[1].supply = "vddio"; 1804e2d2a1e0SAndrzej Hajda ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 18057eb8f069SAndrzej Hajda dsi->supplies); 18067eb8f069SAndrzej Hajda if (ret) { 1807e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get regulators: %d\n", ret); 18087eb8f069SAndrzej Hajda return -EPROBE_DEFER; 18097eb8f069SAndrzej Hajda } 18107eb8f069SAndrzej Hajda 18110ff03fd1SHyungwon Hwang dsi->clks = devm_kzalloc(dev, 18120ff03fd1SHyungwon Hwang sizeof(*dsi->clks) * dsi->driver_data->num_clks, 18130ff03fd1SHyungwon Hwang GFP_KERNEL); 18140ff03fd1SHyungwon Hwang for (i = 0; i < dsi->driver_data->num_clks; i++) { 18150ff03fd1SHyungwon Hwang dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 18160ff03fd1SHyungwon Hwang if (IS_ERR(dsi->clks[i])) { 18170ff03fd1SHyungwon Hwang if (strcmp(clk_names[i], "sclk_mipi") == 0) { 18180ff03fd1SHyungwon Hwang strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); 18190ff03fd1SHyungwon Hwang i--; 18200ff03fd1SHyungwon Hwang continue; 18217eb8f069SAndrzej Hajda } 18227eb8f069SAndrzej Hajda 18230ff03fd1SHyungwon Hwang dev_info(dev, "failed to get the clock: %s\n", 18240ff03fd1SHyungwon Hwang clk_names[i]); 18250ff03fd1SHyungwon Hwang return PTR_ERR(dsi->clks[i]); 18260ff03fd1SHyungwon Hwang } 18277eb8f069SAndrzej Hajda } 18287eb8f069SAndrzej Hajda 18297eb8f069SAndrzej Hajda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1830e2d2a1e0SAndrzej Hajda dsi->reg_base = devm_ioremap_resource(dev, res); 1831293d3f6aSJingoo Han if (IS_ERR(dsi->reg_base)) { 1832e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to remap io region\n"); 183386650408SAndrzej Hajda return PTR_ERR(dsi->reg_base); 18347eb8f069SAndrzej Hajda } 18357eb8f069SAndrzej Hajda 1836e2d2a1e0SAndrzej Hajda dsi->phy = devm_phy_get(dev, "dsim"); 18377eb8f069SAndrzej Hajda if (IS_ERR(dsi->phy)) { 1838e2d2a1e0SAndrzej Hajda dev_info(dev, "failed to get dsim phy\n"); 183986650408SAndrzej Hajda return PTR_ERR(dsi->phy); 18407eb8f069SAndrzej Hajda } 18417eb8f069SAndrzej Hajda 18427eb8f069SAndrzej Hajda dsi->irq = platform_get_irq(pdev, 0); 18437eb8f069SAndrzej Hajda if (dsi->irq < 0) { 1844e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq resource\n"); 184586650408SAndrzej Hajda return dsi->irq; 18467eb8f069SAndrzej Hajda } 18477eb8f069SAndrzej Hajda 18487eb8f069SAndrzej Hajda irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN); 1849e2d2a1e0SAndrzej Hajda ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 18507eb8f069SAndrzej Hajda exynos_dsi_irq, IRQF_ONESHOT, 1851e2d2a1e0SAndrzej Hajda dev_name(dev), dsi); 18527eb8f069SAndrzej Hajda if (ret) { 1853e2d2a1e0SAndrzej Hajda dev_err(dev, "failed to request dsi irq\n"); 185486650408SAndrzej Hajda return ret; 18557eb8f069SAndrzej Hajda } 18567eb8f069SAndrzej Hajda 1857e2d2a1e0SAndrzej Hajda platform_set_drvdata(pdev, &dsi->display); 18587eb8f069SAndrzej Hajda 185986650408SAndrzej Hajda return component_add(dev, &exynos_dsi_component_ops); 18607eb8f069SAndrzej Hajda } 18617eb8f069SAndrzej Hajda 18627eb8f069SAndrzej Hajda static int exynos_dsi_remove(struct platform_device *pdev) 18637eb8f069SAndrzej Hajda { 1864df5225bcSInki Dae component_del(&pdev->dev, &exynos_dsi_component_ops); 1865df5225bcSInki Dae 18667eb8f069SAndrzej Hajda return 0; 18677eb8f069SAndrzej Hajda } 18687eb8f069SAndrzej Hajda 18697eb8f069SAndrzej Hajda struct platform_driver dsi_driver = { 18707eb8f069SAndrzej Hajda .probe = exynos_dsi_probe, 18717eb8f069SAndrzej Hajda .remove = exynos_dsi_remove, 18727eb8f069SAndrzej Hajda .driver = { 18737eb8f069SAndrzej Hajda .name = "exynos-dsi", 18747eb8f069SAndrzej Hajda .owner = THIS_MODULE, 18757eb8f069SAndrzej Hajda .of_match_table = exynos_dsi_of_match, 18767eb8f069SAndrzej Hajda }, 18777eb8f069SAndrzej Hajda }; 18787eb8f069SAndrzej Hajda 18797eb8f069SAndrzej Hajda MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>"); 18807eb8f069SAndrzej Hajda MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>"); 18817eb8f069SAndrzej Hajda MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master"); 18827eb8f069SAndrzej Hajda MODULE_LICENSE("GPL v2"); 1883