1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/exynos7_decon.h> 29 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_plane.h" 32 #include "exynos_drm_drv.h" 33 #include "exynos_drm_fbdev.h" 34 #include "exynos_drm_iommu.h" 35 36 /* 37 * DECON stands for Display and Enhancement controller. 38 */ 39 40 #define DECON_DEFAULT_FRAMERATE 60 41 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 42 43 #define WINDOWS_NR 2 44 45 struct decon_context { 46 struct device *dev; 47 struct drm_device *drm_dev; 48 struct exynos_drm_crtc *crtc; 49 struct exynos_drm_plane planes[WINDOWS_NR]; 50 struct clk *pclk; 51 struct clk *aclk; 52 struct clk *eclk; 53 struct clk *vclk; 54 void __iomem *regs; 55 unsigned int default_win; 56 unsigned long irq_flags; 57 bool i80_if; 58 bool suspended; 59 int pipe; 60 wait_queue_head_t wait_vsync_queue; 61 atomic_t wait_vsync_event; 62 63 struct exynos_drm_panel_info panel; 64 struct drm_encoder *encoder; 65 }; 66 67 static const struct of_device_id decon_driver_dt_match[] = { 68 {.compatible = "samsung,exynos7-decon"}, 69 {}, 70 }; 71 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 72 73 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 74 { 75 struct decon_context *ctx = crtc->ctx; 76 77 if (ctx->suspended) 78 return; 79 80 atomic_set(&ctx->wait_vsync_event, 1); 81 82 /* 83 * wait for DECON to signal VSYNC interrupt or return after 84 * timeout which is set to 50ms (refresh rate of 20). 85 */ 86 if (!wait_event_timeout(ctx->wait_vsync_queue, 87 !atomic_read(&ctx->wait_vsync_event), 88 HZ/20)) 89 DRM_DEBUG_KMS("vblank wait timed out.\n"); 90 } 91 92 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 93 { 94 struct decon_context *ctx = crtc->ctx; 95 unsigned int win, ch_enabled = 0; 96 97 DRM_DEBUG_KMS("%s\n", __FILE__); 98 99 /* Check if any channel is enabled. */ 100 for (win = 0; win < WINDOWS_NR; win++) { 101 u32 val = readl(ctx->regs + WINCON(win)); 102 103 if (val & WINCONx_ENWIN) { 104 val &= ~WINCONx_ENWIN; 105 writel(val, ctx->regs + WINCON(win)); 106 ch_enabled = 1; 107 } 108 } 109 110 /* Wait for vsync, as disable channel takes effect at next vsync */ 111 if (ch_enabled) { 112 unsigned int state = ctx->suspended; 113 114 ctx->suspended = 0; 115 decon_wait_for_vblank(ctx->crtc); 116 ctx->suspended = state; 117 } 118 } 119 120 static int decon_ctx_initialize(struct decon_context *ctx, 121 struct drm_device *drm_dev) 122 { 123 struct exynos_drm_private *priv = drm_dev->dev_private; 124 int ret; 125 126 ctx->drm_dev = drm_dev; 127 ctx->pipe = priv->pipe++; 128 129 decon_clear_channels(ctx->crtc); 130 131 ret = drm_iommu_attach_device(drm_dev, ctx->dev); 132 if (ret) 133 priv->pipe--; 134 135 return ret; 136 } 137 138 static void decon_ctx_remove(struct decon_context *ctx) 139 { 140 /* detach this sub driver from iommu mapping if supported. */ 141 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 142 } 143 144 static u32 decon_calc_clkdiv(struct decon_context *ctx, 145 const struct drm_display_mode *mode) 146 { 147 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 148 u32 clkdiv; 149 150 /* Find the clock divider value that gets us closest to ideal_clk */ 151 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 152 153 return (clkdiv < 0x100) ? clkdiv : 0xff; 154 } 155 156 static bool decon_mode_fixup(struct exynos_drm_crtc *crtc, 157 const struct drm_display_mode *mode, 158 struct drm_display_mode *adjusted_mode) 159 { 160 if (adjusted_mode->vrefresh == 0) 161 adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE; 162 163 return true; 164 } 165 166 static void decon_commit(struct exynos_drm_crtc *crtc) 167 { 168 struct decon_context *ctx = crtc->ctx; 169 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 170 u32 val, clkdiv; 171 172 if (ctx->suspended) 173 return; 174 175 /* nothing to do if we haven't set the mode yet */ 176 if (mode->htotal == 0 || mode->vtotal == 0) 177 return; 178 179 if (!ctx->i80_if) { 180 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 181 /* setup vertical timing values. */ 182 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 183 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 184 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 185 186 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 187 writel(val, ctx->regs + VIDTCON0); 188 189 val = VIDTCON1_VSPW(vsync_len - 1); 190 writel(val, ctx->regs + VIDTCON1); 191 192 /* setup horizontal timing values. */ 193 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 194 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 195 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 196 197 /* setup horizontal timing values. */ 198 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 199 writel(val, ctx->regs + VIDTCON2); 200 201 val = VIDTCON3_HSPW(hsync_len - 1); 202 writel(val, ctx->regs + VIDTCON3); 203 } 204 205 /* setup horizontal and vertical display size. */ 206 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 207 VIDTCON4_HOZVAL(mode->hdisplay - 1); 208 writel(val, ctx->regs + VIDTCON4); 209 210 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 211 212 /* 213 * fields of register with prefix '_F' would be updated 214 * at vsync(same as dma start) 215 */ 216 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 217 writel(val, ctx->regs + VIDCON0); 218 219 clkdiv = decon_calc_clkdiv(ctx, mode); 220 if (clkdiv > 1) { 221 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 222 writel(val, ctx->regs + VCLKCON1); 223 writel(val, ctx->regs + VCLKCON2); 224 } 225 226 val = readl(ctx->regs + DECON_UPDATE); 227 val |= DECON_UPDATE_STANDALONE_F; 228 writel(val, ctx->regs + DECON_UPDATE); 229 } 230 231 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 232 { 233 struct decon_context *ctx = crtc->ctx; 234 u32 val; 235 236 if (ctx->suspended) 237 return -EPERM; 238 239 if (!test_and_set_bit(0, &ctx->irq_flags)) { 240 val = readl(ctx->regs + VIDINTCON0); 241 242 val |= VIDINTCON0_INT_ENABLE; 243 244 if (!ctx->i80_if) { 245 val |= VIDINTCON0_INT_FRAME; 246 val &= ~VIDINTCON0_FRAMESEL0_MASK; 247 val |= VIDINTCON0_FRAMESEL0_VSYNC; 248 } 249 250 writel(val, ctx->regs + VIDINTCON0); 251 } 252 253 return 0; 254 } 255 256 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 257 { 258 struct decon_context *ctx = crtc->ctx; 259 u32 val; 260 261 if (ctx->suspended) 262 return; 263 264 if (test_and_clear_bit(0, &ctx->irq_flags)) { 265 val = readl(ctx->regs + VIDINTCON0); 266 267 val &= ~VIDINTCON0_INT_ENABLE; 268 if (!ctx->i80_if) 269 val &= ~VIDINTCON0_INT_FRAME; 270 271 writel(val, ctx->regs + VIDINTCON0); 272 } 273 } 274 275 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 276 struct drm_framebuffer *fb) 277 { 278 unsigned long val; 279 int padding; 280 281 val = readl(ctx->regs + WINCON(win)); 282 val &= ~WINCONx_BPPMODE_MASK; 283 284 switch (fb->pixel_format) { 285 case DRM_FORMAT_RGB565: 286 val |= WINCONx_BPPMODE_16BPP_565; 287 val |= WINCONx_BURSTLEN_16WORD; 288 break; 289 case DRM_FORMAT_XRGB8888: 290 val |= WINCONx_BPPMODE_24BPP_xRGB; 291 val |= WINCONx_BURSTLEN_16WORD; 292 break; 293 case DRM_FORMAT_XBGR8888: 294 val |= WINCONx_BPPMODE_24BPP_xBGR; 295 val |= WINCONx_BURSTLEN_16WORD; 296 break; 297 case DRM_FORMAT_RGBX8888: 298 val |= WINCONx_BPPMODE_24BPP_RGBx; 299 val |= WINCONx_BURSTLEN_16WORD; 300 break; 301 case DRM_FORMAT_BGRX8888: 302 val |= WINCONx_BPPMODE_24BPP_BGRx; 303 val |= WINCONx_BURSTLEN_16WORD; 304 break; 305 case DRM_FORMAT_ARGB8888: 306 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 307 WINCONx_ALPHA_SEL; 308 val |= WINCONx_BURSTLEN_16WORD; 309 break; 310 case DRM_FORMAT_ABGR8888: 311 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 312 WINCONx_ALPHA_SEL; 313 val |= WINCONx_BURSTLEN_16WORD; 314 break; 315 case DRM_FORMAT_RGBA8888: 316 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 317 WINCONx_ALPHA_SEL; 318 val |= WINCONx_BURSTLEN_16WORD; 319 break; 320 case DRM_FORMAT_BGRA8888: 321 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 322 WINCONx_ALPHA_SEL; 323 val |= WINCONx_BURSTLEN_16WORD; 324 break; 325 default: 326 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 327 328 val |= WINCONx_BPPMODE_24BPP_xRGB; 329 val |= WINCONx_BURSTLEN_16WORD; 330 break; 331 } 332 333 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); 334 335 /* 336 * In case of exynos, setting dma-burst to 16Word causes permanent 337 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 338 * switching which is based on plane size is not recommended as 339 * plane size varies a lot towards the end of the screen and rapid 340 * movement causes unstable DMA which results into iommu crash/tear. 341 */ 342 343 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width; 344 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 345 val &= ~WINCONx_BURSTLEN_MASK; 346 val |= WINCONx_BURSTLEN_8WORD; 347 } 348 349 writel(val, ctx->regs + WINCON(win)); 350 } 351 352 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 353 { 354 unsigned int keycon0 = 0, keycon1 = 0; 355 356 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 357 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 358 359 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 360 361 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 362 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 363 } 364 365 /** 366 * shadow_protect_win() - disable updating values from shadow registers at vsync 367 * 368 * @win: window to protect registers for 369 * @protect: 1 to protect (disable updates) 370 */ 371 static void decon_shadow_protect_win(struct decon_context *ctx, 372 unsigned int win, bool protect) 373 { 374 u32 bits, val; 375 376 bits = SHADOWCON_WINx_PROTECT(win); 377 378 val = readl(ctx->regs + SHADOWCON); 379 if (protect) 380 val |= bits; 381 else 382 val &= ~bits; 383 writel(val, ctx->regs + SHADOWCON); 384 } 385 386 static void decon_update_plane(struct exynos_drm_crtc *crtc, 387 struct exynos_drm_plane *plane) 388 { 389 struct decon_context *ctx = crtc->ctx; 390 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 391 struct drm_plane_state *state = plane->base.state; 392 int padding; 393 unsigned long val, alpha; 394 unsigned int last_x; 395 unsigned int last_y; 396 unsigned int win = plane->zpos; 397 unsigned int bpp = state->fb->bits_per_pixel >> 3; 398 unsigned int pitch = state->fb->pitches[0]; 399 400 if (ctx->suspended) 401 return; 402 403 /* 404 * SHADOWCON/PRTCON register is used for enabling timing. 405 * 406 * for example, once only width value of a register is set, 407 * if the dma is started then decon hardware could malfunction so 408 * with protect window setting, the register fields with prefix '_F' 409 * wouldn't be updated at vsync also but updated once unprotect window 410 * is set. 411 */ 412 413 /* protect windows */ 414 decon_shadow_protect_win(ctx, win, true); 415 416 /* buffer start address */ 417 val = (unsigned long)plane->dma_addr[0]; 418 writel(val, ctx->regs + VIDW_BUF_START(win)); 419 420 padding = (pitch / bpp) - state->fb->width; 421 422 /* buffer size */ 423 writel(state->fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 424 writel(state->fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 425 426 /* offset from the start of the buffer to read */ 427 writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win)); 428 writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win)); 429 430 DRM_DEBUG_KMS("start addr = 0x%lx\n", 431 (unsigned long)val); 432 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 433 plane->crtc_w, plane->crtc_h); 434 435 /* 436 * OSD position. 437 * In case the window layout goes of LCD layout, DECON fails. 438 */ 439 if ((plane->crtc_x + plane->crtc_w) > mode->hdisplay) 440 plane->crtc_x = mode->hdisplay - plane->crtc_w; 441 if ((plane->crtc_y + plane->crtc_h) > mode->vdisplay) 442 plane->crtc_y = mode->vdisplay - plane->crtc_h; 443 444 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 445 VIDOSDxA_TOPLEFT_Y(plane->crtc_y); 446 writel(val, ctx->regs + VIDOSD_A(win)); 447 448 last_x = plane->crtc_x + plane->crtc_w; 449 if (last_x) 450 last_x--; 451 last_y = plane->crtc_y + plane->crtc_h; 452 if (last_y) 453 last_y--; 454 455 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 456 457 writel(val, ctx->regs + VIDOSD_B(win)); 458 459 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 460 plane->crtc_x, plane->crtc_y, last_x, last_y); 461 462 /* OSD alpha */ 463 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 464 VIDOSDxC_ALPHA0_G_F(0x0) | 465 VIDOSDxC_ALPHA0_B_F(0x0); 466 467 writel(alpha, ctx->regs + VIDOSD_C(win)); 468 469 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 470 VIDOSDxD_ALPHA1_G_F(0xff) | 471 VIDOSDxD_ALPHA1_B_F(0xff); 472 473 writel(alpha, ctx->regs + VIDOSD_D(win)); 474 475 decon_win_set_pixfmt(ctx, win, state->fb); 476 477 /* hardware window 0 doesn't support color key. */ 478 if (win != 0) 479 decon_win_set_colkey(ctx, win); 480 481 /* wincon */ 482 val = readl(ctx->regs + WINCON(win)); 483 val |= WINCONx_TRIPLE_BUF_MODE; 484 val |= WINCONx_ENWIN; 485 writel(val, ctx->regs + WINCON(win)); 486 487 /* Enable DMA channel and unprotect windows */ 488 decon_shadow_protect_win(ctx, win, false); 489 490 val = readl(ctx->regs + DECON_UPDATE); 491 val |= DECON_UPDATE_STANDALONE_F; 492 writel(val, ctx->regs + DECON_UPDATE); 493 } 494 495 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 496 struct exynos_drm_plane *plane) 497 { 498 struct decon_context *ctx = crtc->ctx; 499 unsigned int win = plane->zpos; 500 u32 val; 501 502 if (ctx->suspended) 503 return; 504 505 /* protect windows */ 506 decon_shadow_protect_win(ctx, win, true); 507 508 /* wincon */ 509 val = readl(ctx->regs + WINCON(win)); 510 val &= ~WINCONx_ENWIN; 511 writel(val, ctx->regs + WINCON(win)); 512 513 /* unprotect windows */ 514 decon_shadow_protect_win(ctx, win, false); 515 516 val = readl(ctx->regs + DECON_UPDATE); 517 val |= DECON_UPDATE_STANDALONE_F; 518 writel(val, ctx->regs + DECON_UPDATE); 519 } 520 521 static void decon_init(struct decon_context *ctx) 522 { 523 u32 val; 524 525 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 526 527 val = VIDOUTCON0_DISP_IF_0_ON; 528 if (!ctx->i80_if) 529 val |= VIDOUTCON0_RGBIF; 530 writel(val, ctx->regs + VIDOUTCON0); 531 532 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 533 534 if (!ctx->i80_if) 535 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 536 } 537 538 static void decon_enable(struct exynos_drm_crtc *crtc) 539 { 540 struct decon_context *ctx = crtc->ctx; 541 int ret; 542 543 if (!ctx->suspended) 544 return; 545 546 ctx->suspended = false; 547 548 pm_runtime_get_sync(ctx->dev); 549 550 ret = clk_prepare_enable(ctx->pclk); 551 if (ret < 0) { 552 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); 553 return; 554 } 555 556 ret = clk_prepare_enable(ctx->aclk); 557 if (ret < 0) { 558 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); 559 return; 560 } 561 562 ret = clk_prepare_enable(ctx->eclk); 563 if (ret < 0) { 564 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); 565 return; 566 } 567 568 ret = clk_prepare_enable(ctx->vclk); 569 if (ret < 0) { 570 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); 571 return; 572 } 573 574 decon_init(ctx); 575 576 /* if vblank was enabled status, enable it again. */ 577 if (test_and_clear_bit(0, &ctx->irq_flags)) 578 decon_enable_vblank(ctx->crtc); 579 580 decon_commit(ctx->crtc); 581 } 582 583 static void decon_disable(struct exynos_drm_crtc *crtc) 584 { 585 struct decon_context *ctx = crtc->ctx; 586 int i; 587 588 if (ctx->suspended) 589 return; 590 591 /* 592 * We need to make sure that all windows are disabled before we 593 * suspend that connector. Otherwise we might try to scan from 594 * a destroyed buffer later. 595 */ 596 for (i = 0; i < WINDOWS_NR; i++) 597 decon_disable_plane(crtc, &ctx->planes[i]); 598 599 clk_disable_unprepare(ctx->vclk); 600 clk_disable_unprepare(ctx->eclk); 601 clk_disable_unprepare(ctx->aclk); 602 clk_disable_unprepare(ctx->pclk); 603 604 pm_runtime_put_sync(ctx->dev); 605 606 ctx->suspended = true; 607 } 608 609 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 610 .enable = decon_enable, 611 .disable = decon_disable, 612 .mode_fixup = decon_mode_fixup, 613 .commit = decon_commit, 614 .enable_vblank = decon_enable_vblank, 615 .disable_vblank = decon_disable_vblank, 616 .wait_for_vblank = decon_wait_for_vblank, 617 .update_plane = decon_update_plane, 618 .disable_plane = decon_disable_plane, 619 }; 620 621 622 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 623 { 624 struct decon_context *ctx = (struct decon_context *)dev_id; 625 u32 val, clear_bit; 626 627 val = readl(ctx->regs + VIDINTCON1); 628 629 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 630 if (val & clear_bit) 631 writel(clear_bit, ctx->regs + VIDINTCON1); 632 633 /* check the crtc is detached already from encoder */ 634 if (ctx->pipe < 0 || !ctx->drm_dev) 635 goto out; 636 637 if (!ctx->i80_if) { 638 drm_crtc_handle_vblank(&ctx->crtc->base); 639 exynos_drm_crtc_finish_pageflip(ctx->crtc); 640 641 /* set wait vsync event to zero and wake up queue. */ 642 if (atomic_read(&ctx->wait_vsync_event)) { 643 atomic_set(&ctx->wait_vsync_event, 0); 644 wake_up(&ctx->wait_vsync_queue); 645 } 646 } 647 out: 648 return IRQ_HANDLED; 649 } 650 651 static int decon_bind(struct device *dev, struct device *master, void *data) 652 { 653 struct decon_context *ctx = dev_get_drvdata(dev); 654 struct drm_device *drm_dev = data; 655 struct exynos_drm_plane *exynos_plane; 656 enum drm_plane_type type; 657 unsigned int zpos; 658 int ret; 659 660 ret = decon_ctx_initialize(ctx, drm_dev); 661 if (ret) { 662 DRM_ERROR("decon_ctx_initialize failed.\n"); 663 return ret; 664 } 665 666 for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 667 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 668 DRM_PLANE_TYPE_OVERLAY; 669 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 670 1 << ctx->pipe, type, zpos); 671 if (ret) 672 return ret; 673 } 674 675 exynos_plane = &ctx->planes[ctx->default_win]; 676 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 677 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 678 &decon_crtc_ops, ctx); 679 if (IS_ERR(ctx->crtc)) { 680 decon_ctx_remove(ctx); 681 return PTR_ERR(ctx->crtc); 682 } 683 684 if (ctx->encoder) 685 exynos_dpi_bind(drm_dev, ctx->encoder); 686 687 return 0; 688 689 } 690 691 static void decon_unbind(struct device *dev, struct device *master, 692 void *data) 693 { 694 struct decon_context *ctx = dev_get_drvdata(dev); 695 696 decon_disable(ctx->crtc); 697 698 if (ctx->encoder) 699 exynos_dpi_remove(ctx->encoder); 700 701 decon_ctx_remove(ctx); 702 } 703 704 static const struct component_ops decon_component_ops = { 705 .bind = decon_bind, 706 .unbind = decon_unbind, 707 }; 708 709 static int decon_probe(struct platform_device *pdev) 710 { 711 struct device *dev = &pdev->dev; 712 struct decon_context *ctx; 713 struct device_node *i80_if_timings; 714 struct resource *res; 715 int ret; 716 717 if (!dev->of_node) 718 return -ENODEV; 719 720 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 721 if (!ctx) 722 return -ENOMEM; 723 724 ctx->dev = dev; 725 ctx->suspended = true; 726 727 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 728 if (i80_if_timings) 729 ctx->i80_if = true; 730 of_node_put(i80_if_timings); 731 732 ctx->regs = of_iomap(dev->of_node, 0); 733 if (!ctx->regs) 734 return -ENOMEM; 735 736 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 737 if (IS_ERR(ctx->pclk)) { 738 dev_err(dev, "failed to get bus clock pclk\n"); 739 ret = PTR_ERR(ctx->pclk); 740 goto err_iounmap; 741 } 742 743 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 744 if (IS_ERR(ctx->aclk)) { 745 dev_err(dev, "failed to get bus clock aclk\n"); 746 ret = PTR_ERR(ctx->aclk); 747 goto err_iounmap; 748 } 749 750 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 751 if (IS_ERR(ctx->eclk)) { 752 dev_err(dev, "failed to get eclock\n"); 753 ret = PTR_ERR(ctx->eclk); 754 goto err_iounmap; 755 } 756 757 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 758 if (IS_ERR(ctx->vclk)) { 759 dev_err(dev, "failed to get vclock\n"); 760 ret = PTR_ERR(ctx->vclk); 761 goto err_iounmap; 762 } 763 764 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 765 ctx->i80_if ? "lcd_sys" : "vsync"); 766 if (!res) { 767 dev_err(dev, "irq request failed.\n"); 768 ret = -ENXIO; 769 goto err_iounmap; 770 } 771 772 ret = devm_request_irq(dev, res->start, decon_irq_handler, 773 0, "drm_decon", ctx); 774 if (ret) { 775 dev_err(dev, "irq request failed.\n"); 776 goto err_iounmap; 777 } 778 779 init_waitqueue_head(&ctx->wait_vsync_queue); 780 atomic_set(&ctx->wait_vsync_event, 0); 781 782 platform_set_drvdata(pdev, ctx); 783 784 ctx->encoder = exynos_dpi_probe(dev); 785 if (IS_ERR(ctx->encoder)) { 786 ret = PTR_ERR(ctx->encoder); 787 goto err_iounmap; 788 } 789 790 pm_runtime_enable(dev); 791 792 ret = component_add(dev, &decon_component_ops); 793 if (ret) 794 goto err_disable_pm_runtime; 795 796 return ret; 797 798 err_disable_pm_runtime: 799 pm_runtime_disable(dev); 800 801 err_iounmap: 802 iounmap(ctx->regs); 803 804 return ret; 805 } 806 807 static int decon_remove(struct platform_device *pdev) 808 { 809 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 810 811 pm_runtime_disable(&pdev->dev); 812 813 iounmap(ctx->regs); 814 815 component_del(&pdev->dev, &decon_component_ops); 816 817 return 0; 818 } 819 820 struct platform_driver decon_driver = { 821 .probe = decon_probe, 822 .remove = decon_remove, 823 .driver = { 824 .name = "exynos-decon", 825 .of_match_table = decon_driver_dt_match, 826 }, 827 }; 828