1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/exynos7_decon.h> 29 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_plane.h" 32 #include "exynos_drm_drv.h" 33 #include "exynos_drm_fb.h" 34 #include "exynos_drm_iommu.h" 35 36 /* 37 * DECON stands for Display and Enhancement controller. 38 */ 39 40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 41 42 #define WINDOWS_NR 2 43 44 struct decon_context { 45 struct device *dev; 46 struct drm_device *drm_dev; 47 struct exynos_drm_crtc *crtc; 48 struct exynos_drm_plane planes[WINDOWS_NR]; 49 struct exynos_drm_plane_config configs[WINDOWS_NR]; 50 struct clk *pclk; 51 struct clk *aclk; 52 struct clk *eclk; 53 struct clk *vclk; 54 void __iomem *regs; 55 unsigned long irq_flags; 56 bool i80_if; 57 bool suspended; 58 int pipe; 59 wait_queue_head_t wait_vsync_queue; 60 atomic_t wait_vsync_event; 61 62 struct drm_encoder *encoder; 63 }; 64 65 static const struct of_device_id decon_driver_dt_match[] = { 66 {.compatible = "samsung,exynos7-decon"}, 67 {}, 68 }; 69 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 70 71 static const uint32_t decon_formats[] = { 72 DRM_FORMAT_RGB565, 73 DRM_FORMAT_XRGB8888, 74 DRM_FORMAT_XBGR8888, 75 DRM_FORMAT_RGBX8888, 76 DRM_FORMAT_BGRX8888, 77 DRM_FORMAT_ARGB8888, 78 DRM_FORMAT_ABGR8888, 79 DRM_FORMAT_RGBA8888, 80 DRM_FORMAT_BGRA8888, 81 }; 82 83 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 84 DRM_PLANE_TYPE_PRIMARY, 85 DRM_PLANE_TYPE_CURSOR, 86 }; 87 88 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 89 { 90 struct decon_context *ctx = crtc->ctx; 91 92 if (ctx->suspended) 93 return; 94 95 atomic_set(&ctx->wait_vsync_event, 1); 96 97 /* 98 * wait for DECON to signal VSYNC interrupt or return after 99 * timeout which is set to 50ms (refresh rate of 20). 100 */ 101 if (!wait_event_timeout(ctx->wait_vsync_queue, 102 !atomic_read(&ctx->wait_vsync_event), 103 HZ/20)) 104 DRM_DEBUG_KMS("vblank wait timed out.\n"); 105 } 106 107 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 108 { 109 struct decon_context *ctx = crtc->ctx; 110 unsigned int win, ch_enabled = 0; 111 112 DRM_DEBUG_KMS("%s\n", __FILE__); 113 114 /* Check if any channel is enabled. */ 115 for (win = 0; win < WINDOWS_NR; win++) { 116 u32 val = readl(ctx->regs + WINCON(win)); 117 118 if (val & WINCONx_ENWIN) { 119 val &= ~WINCONx_ENWIN; 120 writel(val, ctx->regs + WINCON(win)); 121 ch_enabled = 1; 122 } 123 } 124 125 /* Wait for vsync, as disable channel takes effect at next vsync */ 126 if (ch_enabled) 127 decon_wait_for_vblank(ctx->crtc); 128 } 129 130 static int decon_ctx_initialize(struct decon_context *ctx, 131 struct drm_device *drm_dev) 132 { 133 struct exynos_drm_private *priv = drm_dev->dev_private; 134 int ret; 135 136 ctx->drm_dev = drm_dev; 137 ctx->pipe = priv->pipe++; 138 139 decon_clear_channels(ctx->crtc); 140 141 ret = drm_iommu_attach_device(drm_dev, ctx->dev); 142 if (ret) 143 priv->pipe--; 144 145 return ret; 146 } 147 148 static void decon_ctx_remove(struct decon_context *ctx) 149 { 150 /* detach this sub driver from iommu mapping if supported. */ 151 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 152 } 153 154 static u32 decon_calc_clkdiv(struct decon_context *ctx, 155 const struct drm_display_mode *mode) 156 { 157 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 158 u32 clkdiv; 159 160 /* Find the clock divider value that gets us closest to ideal_clk */ 161 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 162 163 return (clkdiv < 0x100) ? clkdiv : 0xff; 164 } 165 166 static void decon_commit(struct exynos_drm_crtc *crtc) 167 { 168 struct decon_context *ctx = crtc->ctx; 169 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 170 u32 val, clkdiv; 171 172 if (ctx->suspended) 173 return; 174 175 /* nothing to do if we haven't set the mode yet */ 176 if (mode->htotal == 0 || mode->vtotal == 0) 177 return; 178 179 if (!ctx->i80_if) { 180 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 181 /* setup vertical timing values. */ 182 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 183 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 184 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 185 186 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 187 writel(val, ctx->regs + VIDTCON0); 188 189 val = VIDTCON1_VSPW(vsync_len - 1); 190 writel(val, ctx->regs + VIDTCON1); 191 192 /* setup horizontal timing values. */ 193 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 194 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 195 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 196 197 /* setup horizontal timing values. */ 198 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 199 writel(val, ctx->regs + VIDTCON2); 200 201 val = VIDTCON3_HSPW(hsync_len - 1); 202 writel(val, ctx->regs + VIDTCON3); 203 } 204 205 /* setup horizontal and vertical display size. */ 206 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 207 VIDTCON4_HOZVAL(mode->hdisplay - 1); 208 writel(val, ctx->regs + VIDTCON4); 209 210 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 211 212 /* 213 * fields of register with prefix '_F' would be updated 214 * at vsync(same as dma start) 215 */ 216 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 217 writel(val, ctx->regs + VIDCON0); 218 219 clkdiv = decon_calc_clkdiv(ctx, mode); 220 if (clkdiv > 1) { 221 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 222 writel(val, ctx->regs + VCLKCON1); 223 writel(val, ctx->regs + VCLKCON2); 224 } 225 226 val = readl(ctx->regs + DECON_UPDATE); 227 val |= DECON_UPDATE_STANDALONE_F; 228 writel(val, ctx->regs + DECON_UPDATE); 229 } 230 231 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 232 { 233 struct decon_context *ctx = crtc->ctx; 234 u32 val; 235 236 if (ctx->suspended) 237 return -EPERM; 238 239 if (!test_and_set_bit(0, &ctx->irq_flags)) { 240 val = readl(ctx->regs + VIDINTCON0); 241 242 val |= VIDINTCON0_INT_ENABLE; 243 244 if (!ctx->i80_if) { 245 val |= VIDINTCON0_INT_FRAME; 246 val &= ~VIDINTCON0_FRAMESEL0_MASK; 247 val |= VIDINTCON0_FRAMESEL0_VSYNC; 248 } 249 250 writel(val, ctx->regs + VIDINTCON0); 251 } 252 253 return 0; 254 } 255 256 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 257 { 258 struct decon_context *ctx = crtc->ctx; 259 u32 val; 260 261 if (ctx->suspended) 262 return; 263 264 if (test_and_clear_bit(0, &ctx->irq_flags)) { 265 val = readl(ctx->regs + VIDINTCON0); 266 267 val &= ~VIDINTCON0_INT_ENABLE; 268 if (!ctx->i80_if) 269 val &= ~VIDINTCON0_INT_FRAME; 270 271 writel(val, ctx->regs + VIDINTCON0); 272 } 273 } 274 275 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 276 struct drm_framebuffer *fb) 277 { 278 unsigned long val; 279 int padding; 280 281 val = readl(ctx->regs + WINCON(win)); 282 val &= ~WINCONx_BPPMODE_MASK; 283 284 switch (fb->pixel_format) { 285 case DRM_FORMAT_RGB565: 286 val |= WINCONx_BPPMODE_16BPP_565; 287 val |= WINCONx_BURSTLEN_16WORD; 288 break; 289 case DRM_FORMAT_XRGB8888: 290 val |= WINCONx_BPPMODE_24BPP_xRGB; 291 val |= WINCONx_BURSTLEN_16WORD; 292 break; 293 case DRM_FORMAT_XBGR8888: 294 val |= WINCONx_BPPMODE_24BPP_xBGR; 295 val |= WINCONx_BURSTLEN_16WORD; 296 break; 297 case DRM_FORMAT_RGBX8888: 298 val |= WINCONx_BPPMODE_24BPP_RGBx; 299 val |= WINCONx_BURSTLEN_16WORD; 300 break; 301 case DRM_FORMAT_BGRX8888: 302 val |= WINCONx_BPPMODE_24BPP_BGRx; 303 val |= WINCONx_BURSTLEN_16WORD; 304 break; 305 case DRM_FORMAT_ARGB8888: 306 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 307 WINCONx_ALPHA_SEL; 308 val |= WINCONx_BURSTLEN_16WORD; 309 break; 310 case DRM_FORMAT_ABGR8888: 311 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 312 WINCONx_ALPHA_SEL; 313 val |= WINCONx_BURSTLEN_16WORD; 314 break; 315 case DRM_FORMAT_RGBA8888: 316 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 317 WINCONx_ALPHA_SEL; 318 val |= WINCONx_BURSTLEN_16WORD; 319 break; 320 case DRM_FORMAT_BGRA8888: 321 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 322 WINCONx_ALPHA_SEL; 323 val |= WINCONx_BURSTLEN_16WORD; 324 break; 325 default: 326 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 327 328 val |= WINCONx_BPPMODE_24BPP_xRGB; 329 val |= WINCONx_BURSTLEN_16WORD; 330 break; 331 } 332 333 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel); 334 335 /* 336 * In case of exynos, setting dma-burst to 16Word causes permanent 337 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 338 * switching which is based on plane size is not recommended as 339 * plane size varies a lot towards the end of the screen and rapid 340 * movement causes unstable DMA which results into iommu crash/tear. 341 */ 342 343 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width; 344 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 345 val &= ~WINCONx_BURSTLEN_MASK; 346 val |= WINCONx_BURSTLEN_8WORD; 347 } 348 349 writel(val, ctx->regs + WINCON(win)); 350 } 351 352 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 353 { 354 unsigned int keycon0 = 0, keycon1 = 0; 355 356 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 357 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 358 359 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 360 361 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 362 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 363 } 364 365 /** 366 * shadow_protect_win() - disable updating values from shadow registers at vsync 367 * 368 * @win: window to protect registers for 369 * @protect: 1 to protect (disable updates) 370 */ 371 static void decon_shadow_protect_win(struct decon_context *ctx, 372 unsigned int win, bool protect) 373 { 374 u32 bits, val; 375 376 bits = SHADOWCON_WINx_PROTECT(win); 377 378 val = readl(ctx->regs + SHADOWCON); 379 if (protect) 380 val |= bits; 381 else 382 val &= ~bits; 383 writel(val, ctx->regs + SHADOWCON); 384 } 385 386 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 387 { 388 struct decon_context *ctx = crtc->ctx; 389 int i; 390 391 if (ctx->suspended) 392 return; 393 394 for (i = 0; i < WINDOWS_NR; i++) 395 decon_shadow_protect_win(ctx, i, true); 396 } 397 398 static void decon_update_plane(struct exynos_drm_crtc *crtc, 399 struct exynos_drm_plane *plane) 400 { 401 struct exynos_drm_plane_state *state = 402 to_exynos_plane_state(plane->base.state); 403 struct decon_context *ctx = crtc->ctx; 404 struct drm_framebuffer *fb = state->base.fb; 405 int padding; 406 unsigned long val, alpha; 407 unsigned int last_x; 408 unsigned int last_y; 409 unsigned int win = plane->index; 410 unsigned int bpp = fb->bits_per_pixel >> 3; 411 unsigned int pitch = fb->pitches[0]; 412 413 if (ctx->suspended) 414 return; 415 416 /* 417 * SHADOWCON/PRTCON register is used for enabling timing. 418 * 419 * for example, once only width value of a register is set, 420 * if the dma is started then decon hardware could malfunction so 421 * with protect window setting, the register fields with prefix '_F' 422 * wouldn't be updated at vsync also but updated once unprotect window 423 * is set. 424 */ 425 426 /* buffer start address */ 427 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 428 writel(val, ctx->regs + VIDW_BUF_START(win)); 429 430 padding = (pitch / bpp) - fb->width; 431 432 /* buffer size */ 433 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 434 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 435 436 /* offset from the start of the buffer to read */ 437 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); 438 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); 439 440 DRM_DEBUG_KMS("start addr = 0x%lx\n", 441 (unsigned long)val); 442 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 443 state->crtc.w, state->crtc.h); 444 445 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 446 VIDOSDxA_TOPLEFT_Y(state->crtc.y); 447 writel(val, ctx->regs + VIDOSD_A(win)); 448 449 last_x = state->crtc.x + state->crtc.w; 450 if (last_x) 451 last_x--; 452 last_y = state->crtc.y + state->crtc.h; 453 if (last_y) 454 last_y--; 455 456 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 457 458 writel(val, ctx->regs + VIDOSD_B(win)); 459 460 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 461 state->crtc.x, state->crtc.y, last_x, last_y); 462 463 /* OSD alpha */ 464 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 465 VIDOSDxC_ALPHA0_G_F(0x0) | 466 VIDOSDxC_ALPHA0_B_F(0x0); 467 468 writel(alpha, ctx->regs + VIDOSD_C(win)); 469 470 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 471 VIDOSDxD_ALPHA1_G_F(0xff) | 472 VIDOSDxD_ALPHA1_B_F(0xff); 473 474 writel(alpha, ctx->regs + VIDOSD_D(win)); 475 476 decon_win_set_pixfmt(ctx, win, fb); 477 478 /* hardware window 0 doesn't support color key. */ 479 if (win != 0) 480 decon_win_set_colkey(ctx, win); 481 482 /* wincon */ 483 val = readl(ctx->regs + WINCON(win)); 484 val |= WINCONx_TRIPLE_BUF_MODE; 485 val |= WINCONx_ENWIN; 486 writel(val, ctx->regs + WINCON(win)); 487 488 /* Enable DMA channel and unprotect windows */ 489 decon_shadow_protect_win(ctx, win, false); 490 491 val = readl(ctx->regs + DECON_UPDATE); 492 val |= DECON_UPDATE_STANDALONE_F; 493 writel(val, ctx->regs + DECON_UPDATE); 494 } 495 496 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 497 struct exynos_drm_plane *plane) 498 { 499 struct decon_context *ctx = crtc->ctx; 500 unsigned int win = plane->index; 501 u32 val; 502 503 if (ctx->suspended) 504 return; 505 506 /* protect windows */ 507 decon_shadow_protect_win(ctx, win, true); 508 509 /* wincon */ 510 val = readl(ctx->regs + WINCON(win)); 511 val &= ~WINCONx_ENWIN; 512 writel(val, ctx->regs + WINCON(win)); 513 514 val = readl(ctx->regs + DECON_UPDATE); 515 val |= DECON_UPDATE_STANDALONE_F; 516 writel(val, ctx->regs + DECON_UPDATE); 517 } 518 519 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 520 { 521 struct decon_context *ctx = crtc->ctx; 522 int i; 523 524 if (ctx->suspended) 525 return; 526 527 for (i = 0; i < WINDOWS_NR; i++) 528 decon_shadow_protect_win(ctx, i, false); 529 } 530 531 static void decon_init(struct decon_context *ctx) 532 { 533 u32 val; 534 535 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 536 537 val = VIDOUTCON0_DISP_IF_0_ON; 538 if (!ctx->i80_if) 539 val |= VIDOUTCON0_RGBIF; 540 writel(val, ctx->regs + VIDOUTCON0); 541 542 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 543 544 if (!ctx->i80_if) 545 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 546 } 547 548 static void decon_enable(struct exynos_drm_crtc *crtc) 549 { 550 struct decon_context *ctx = crtc->ctx; 551 552 if (!ctx->suspended) 553 return; 554 555 pm_runtime_get_sync(ctx->dev); 556 557 decon_init(ctx); 558 559 /* if vblank was enabled status, enable it again. */ 560 if (test_and_clear_bit(0, &ctx->irq_flags)) 561 decon_enable_vblank(ctx->crtc); 562 563 decon_commit(ctx->crtc); 564 565 ctx->suspended = false; 566 } 567 568 static void decon_disable(struct exynos_drm_crtc *crtc) 569 { 570 struct decon_context *ctx = crtc->ctx; 571 int i; 572 573 if (ctx->suspended) 574 return; 575 576 /* 577 * We need to make sure that all windows are disabled before we 578 * suspend that connector. Otherwise we might try to scan from 579 * a destroyed buffer later. 580 */ 581 for (i = 0; i < WINDOWS_NR; i++) 582 decon_disable_plane(crtc, &ctx->planes[i]); 583 584 pm_runtime_put_sync(ctx->dev); 585 586 ctx->suspended = true; 587 } 588 589 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 590 .enable = decon_enable, 591 .disable = decon_disable, 592 .commit = decon_commit, 593 .enable_vblank = decon_enable_vblank, 594 .disable_vblank = decon_disable_vblank, 595 .atomic_begin = decon_atomic_begin, 596 .update_plane = decon_update_plane, 597 .disable_plane = decon_disable_plane, 598 .atomic_flush = decon_atomic_flush, 599 }; 600 601 602 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 603 { 604 struct decon_context *ctx = (struct decon_context *)dev_id; 605 u32 val, clear_bit; 606 int win; 607 608 val = readl(ctx->regs + VIDINTCON1); 609 610 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 611 if (val & clear_bit) 612 writel(clear_bit, ctx->regs + VIDINTCON1); 613 614 /* check the crtc is detached already from encoder */ 615 if (ctx->pipe < 0 || !ctx->drm_dev) 616 goto out; 617 618 if (!ctx->i80_if) { 619 drm_crtc_handle_vblank(&ctx->crtc->base); 620 for (win = 0 ; win < WINDOWS_NR ; win++) { 621 struct exynos_drm_plane *plane = &ctx->planes[win]; 622 623 if (!plane->pending_fb) 624 continue; 625 626 exynos_drm_crtc_finish_update(ctx->crtc, plane); 627 } 628 629 /* set wait vsync event to zero and wake up queue. */ 630 if (atomic_read(&ctx->wait_vsync_event)) { 631 atomic_set(&ctx->wait_vsync_event, 0); 632 wake_up(&ctx->wait_vsync_queue); 633 } 634 } 635 out: 636 return IRQ_HANDLED; 637 } 638 639 static int decon_bind(struct device *dev, struct device *master, void *data) 640 { 641 struct decon_context *ctx = dev_get_drvdata(dev); 642 struct drm_device *drm_dev = data; 643 struct exynos_drm_plane *exynos_plane; 644 unsigned int i; 645 int ret; 646 647 ret = decon_ctx_initialize(ctx, drm_dev); 648 if (ret) { 649 DRM_ERROR("decon_ctx_initialize failed.\n"); 650 return ret; 651 } 652 653 for (i = 0; i < WINDOWS_NR; i++) { 654 ctx->configs[i].pixel_formats = decon_formats; 655 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); 656 ctx->configs[i].zpos = i; 657 ctx->configs[i].type = decon_win_types[i]; 658 659 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 660 1 << ctx->pipe, &ctx->configs[i]); 661 if (ret) 662 return ret; 663 } 664 665 exynos_plane = &ctx->planes[DEFAULT_WIN]; 666 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 667 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 668 &decon_crtc_ops, ctx); 669 if (IS_ERR(ctx->crtc)) { 670 decon_ctx_remove(ctx); 671 return PTR_ERR(ctx->crtc); 672 } 673 674 if (ctx->encoder) 675 exynos_dpi_bind(drm_dev, ctx->encoder); 676 677 return 0; 678 679 } 680 681 static void decon_unbind(struct device *dev, struct device *master, 682 void *data) 683 { 684 struct decon_context *ctx = dev_get_drvdata(dev); 685 686 decon_disable(ctx->crtc); 687 688 if (ctx->encoder) 689 exynos_dpi_remove(ctx->encoder); 690 691 decon_ctx_remove(ctx); 692 } 693 694 static const struct component_ops decon_component_ops = { 695 .bind = decon_bind, 696 .unbind = decon_unbind, 697 }; 698 699 static int decon_probe(struct platform_device *pdev) 700 { 701 struct device *dev = &pdev->dev; 702 struct decon_context *ctx; 703 struct device_node *i80_if_timings; 704 struct resource *res; 705 int ret; 706 707 if (!dev->of_node) 708 return -ENODEV; 709 710 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 711 if (!ctx) 712 return -ENOMEM; 713 714 ctx->dev = dev; 715 ctx->suspended = true; 716 717 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 718 if (i80_if_timings) 719 ctx->i80_if = true; 720 of_node_put(i80_if_timings); 721 722 ctx->regs = of_iomap(dev->of_node, 0); 723 if (!ctx->regs) 724 return -ENOMEM; 725 726 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 727 if (IS_ERR(ctx->pclk)) { 728 dev_err(dev, "failed to get bus clock pclk\n"); 729 ret = PTR_ERR(ctx->pclk); 730 goto err_iounmap; 731 } 732 733 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 734 if (IS_ERR(ctx->aclk)) { 735 dev_err(dev, "failed to get bus clock aclk\n"); 736 ret = PTR_ERR(ctx->aclk); 737 goto err_iounmap; 738 } 739 740 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 741 if (IS_ERR(ctx->eclk)) { 742 dev_err(dev, "failed to get eclock\n"); 743 ret = PTR_ERR(ctx->eclk); 744 goto err_iounmap; 745 } 746 747 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 748 if (IS_ERR(ctx->vclk)) { 749 dev_err(dev, "failed to get vclock\n"); 750 ret = PTR_ERR(ctx->vclk); 751 goto err_iounmap; 752 } 753 754 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 755 ctx->i80_if ? "lcd_sys" : "vsync"); 756 if (!res) { 757 dev_err(dev, "irq request failed.\n"); 758 ret = -ENXIO; 759 goto err_iounmap; 760 } 761 762 ret = devm_request_irq(dev, res->start, decon_irq_handler, 763 0, "drm_decon", ctx); 764 if (ret) { 765 dev_err(dev, "irq request failed.\n"); 766 goto err_iounmap; 767 } 768 769 init_waitqueue_head(&ctx->wait_vsync_queue); 770 atomic_set(&ctx->wait_vsync_event, 0); 771 772 platform_set_drvdata(pdev, ctx); 773 774 ctx->encoder = exynos_dpi_probe(dev); 775 if (IS_ERR(ctx->encoder)) { 776 ret = PTR_ERR(ctx->encoder); 777 goto err_iounmap; 778 } 779 780 pm_runtime_enable(dev); 781 782 ret = component_add(dev, &decon_component_ops); 783 if (ret) 784 goto err_disable_pm_runtime; 785 786 return ret; 787 788 err_disable_pm_runtime: 789 pm_runtime_disable(dev); 790 791 err_iounmap: 792 iounmap(ctx->regs); 793 794 return ret; 795 } 796 797 static int decon_remove(struct platform_device *pdev) 798 { 799 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 800 801 pm_runtime_disable(&pdev->dev); 802 803 iounmap(ctx->regs); 804 805 component_del(&pdev->dev, &decon_component_ops); 806 807 return 0; 808 } 809 810 #ifdef CONFIG_PM 811 static int exynos7_decon_suspend(struct device *dev) 812 { 813 struct decon_context *ctx = dev_get_drvdata(dev); 814 815 clk_disable_unprepare(ctx->vclk); 816 clk_disable_unprepare(ctx->eclk); 817 clk_disable_unprepare(ctx->aclk); 818 clk_disable_unprepare(ctx->pclk); 819 820 return 0; 821 } 822 823 static int exynos7_decon_resume(struct device *dev) 824 { 825 struct decon_context *ctx = dev_get_drvdata(dev); 826 int ret; 827 828 ret = clk_prepare_enable(ctx->pclk); 829 if (ret < 0) { 830 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); 831 return ret; 832 } 833 834 ret = clk_prepare_enable(ctx->aclk); 835 if (ret < 0) { 836 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); 837 return ret; 838 } 839 840 ret = clk_prepare_enable(ctx->eclk); 841 if (ret < 0) { 842 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); 843 return ret; 844 } 845 846 ret = clk_prepare_enable(ctx->vclk); 847 if (ret < 0) { 848 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); 849 return ret; 850 } 851 852 return 0; 853 } 854 #endif 855 856 static const struct dev_pm_ops exynos7_decon_pm_ops = { 857 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume, 858 NULL) 859 }; 860 861 struct platform_driver decon_driver = { 862 .probe = decon_probe, 863 .remove = decon_remove, 864 .driver = { 865 .name = "exynos-decon", 866 .pm = &exynos7_decon_pm_ops, 867 .of_match_table = decon_driver_dt_match, 868 }, 869 }; 870