1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/exynos7_decon.h> 29 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_plane.h" 32 #include "exynos_drm_drv.h" 33 #include "exynos_drm_fbdev.h" 34 #include "exynos_drm_iommu.h" 35 36 /* 37 * DECON stands for Display and Enhancement controller. 38 */ 39 40 #define DECON_DEFAULT_FRAMERATE 60 41 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 42 43 #define WINDOWS_NR 2 44 45 struct decon_context { 46 struct device *dev; 47 struct drm_device *drm_dev; 48 struct exynos_drm_crtc *crtc; 49 struct exynos_drm_plane planes[WINDOWS_NR]; 50 struct clk *pclk; 51 struct clk *aclk; 52 struct clk *eclk; 53 struct clk *vclk; 54 void __iomem *regs; 55 unsigned int default_win; 56 unsigned long irq_flags; 57 bool i80_if; 58 bool suspended; 59 int pipe; 60 wait_queue_head_t wait_vsync_queue; 61 atomic_t wait_vsync_event; 62 63 struct exynos_drm_panel_info panel; 64 struct exynos_drm_display *display; 65 }; 66 67 static const struct of_device_id decon_driver_dt_match[] = { 68 {.compatible = "samsung,exynos7-decon"}, 69 {}, 70 }; 71 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 72 73 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 74 { 75 struct decon_context *ctx = crtc->ctx; 76 77 if (ctx->suspended) 78 return; 79 80 atomic_set(&ctx->wait_vsync_event, 1); 81 82 /* 83 * wait for DECON to signal VSYNC interrupt or return after 84 * timeout which is set to 50ms (refresh rate of 20). 85 */ 86 if (!wait_event_timeout(ctx->wait_vsync_queue, 87 !atomic_read(&ctx->wait_vsync_event), 88 HZ/20)) 89 DRM_DEBUG_KMS("vblank wait timed out.\n"); 90 } 91 92 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 93 { 94 struct decon_context *ctx = crtc->ctx; 95 unsigned int win, ch_enabled = 0; 96 97 DRM_DEBUG_KMS("%s\n", __FILE__); 98 99 /* Check if any channel is enabled. */ 100 for (win = 0; win < WINDOWS_NR; win++) { 101 u32 val = readl(ctx->regs + WINCON(win)); 102 103 if (val & WINCONx_ENWIN) { 104 val &= ~WINCONx_ENWIN; 105 writel(val, ctx->regs + WINCON(win)); 106 ch_enabled = 1; 107 } 108 } 109 110 /* Wait for vsync, as disable channel takes effect at next vsync */ 111 if (ch_enabled) { 112 unsigned int state = ctx->suspended; 113 114 ctx->suspended = 0; 115 decon_wait_for_vblank(ctx->crtc); 116 ctx->suspended = state; 117 } 118 } 119 120 static int decon_ctx_initialize(struct decon_context *ctx, 121 struct drm_device *drm_dev) 122 { 123 struct exynos_drm_private *priv = drm_dev->dev_private; 124 int ret; 125 126 ctx->drm_dev = drm_dev; 127 ctx->pipe = priv->pipe++; 128 129 ret = drm_iommu_attach_device_if_possible(ctx->crtc, drm_dev, ctx->dev); 130 if (ret) 131 priv->pipe--; 132 133 return ret; 134 } 135 136 static void decon_ctx_remove(struct decon_context *ctx) 137 { 138 /* detach this sub driver from iommu mapping if supported. */ 139 if (is_drm_iommu_supported(ctx->drm_dev)) 140 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 141 } 142 143 static u32 decon_calc_clkdiv(struct decon_context *ctx, 144 const struct drm_display_mode *mode) 145 { 146 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 147 u32 clkdiv; 148 149 /* Find the clock divider value that gets us closest to ideal_clk */ 150 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 151 152 return (clkdiv < 0x100) ? clkdiv : 0xff; 153 } 154 155 static bool decon_mode_fixup(struct exynos_drm_crtc *crtc, 156 const struct drm_display_mode *mode, 157 struct drm_display_mode *adjusted_mode) 158 { 159 if (adjusted_mode->vrefresh == 0) 160 adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE; 161 162 return true; 163 } 164 165 static void decon_commit(struct exynos_drm_crtc *crtc) 166 { 167 struct decon_context *ctx = crtc->ctx; 168 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 169 u32 val, clkdiv; 170 171 if (ctx->suspended) 172 return; 173 174 /* nothing to do if we haven't set the mode yet */ 175 if (mode->htotal == 0 || mode->vtotal == 0) 176 return; 177 178 if (!ctx->i80_if) { 179 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 180 /* setup vertical timing values. */ 181 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 182 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 183 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 184 185 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 186 writel(val, ctx->regs + VIDTCON0); 187 188 val = VIDTCON1_VSPW(vsync_len - 1); 189 writel(val, ctx->regs + VIDTCON1); 190 191 /* setup horizontal timing values. */ 192 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 193 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 194 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 195 196 /* setup horizontal timing values. */ 197 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 198 writel(val, ctx->regs + VIDTCON2); 199 200 val = VIDTCON3_HSPW(hsync_len - 1); 201 writel(val, ctx->regs + VIDTCON3); 202 } 203 204 /* setup horizontal and vertical display size. */ 205 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 206 VIDTCON4_HOZVAL(mode->hdisplay - 1); 207 writel(val, ctx->regs + VIDTCON4); 208 209 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 210 211 /* 212 * fields of register with prefix '_F' would be updated 213 * at vsync(same as dma start) 214 */ 215 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 216 writel(val, ctx->regs + VIDCON0); 217 218 clkdiv = decon_calc_clkdiv(ctx, mode); 219 if (clkdiv > 1) { 220 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 221 writel(val, ctx->regs + VCLKCON1); 222 writel(val, ctx->regs + VCLKCON2); 223 } 224 225 val = readl(ctx->regs + DECON_UPDATE); 226 val |= DECON_UPDATE_STANDALONE_F; 227 writel(val, ctx->regs + DECON_UPDATE); 228 } 229 230 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 231 { 232 struct decon_context *ctx = crtc->ctx; 233 u32 val; 234 235 if (ctx->suspended) 236 return -EPERM; 237 238 if (!test_and_set_bit(0, &ctx->irq_flags)) { 239 val = readl(ctx->regs + VIDINTCON0); 240 241 val |= VIDINTCON0_INT_ENABLE; 242 243 if (!ctx->i80_if) { 244 val |= VIDINTCON0_INT_FRAME; 245 val &= ~VIDINTCON0_FRAMESEL0_MASK; 246 val |= VIDINTCON0_FRAMESEL0_VSYNC; 247 } 248 249 writel(val, ctx->regs + VIDINTCON0); 250 } 251 252 return 0; 253 } 254 255 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 256 { 257 struct decon_context *ctx = crtc->ctx; 258 u32 val; 259 260 if (ctx->suspended) 261 return; 262 263 if (test_and_clear_bit(0, &ctx->irq_flags)) { 264 val = readl(ctx->regs + VIDINTCON0); 265 266 val &= ~VIDINTCON0_INT_ENABLE; 267 if (!ctx->i80_if) 268 val &= ~VIDINTCON0_INT_FRAME; 269 270 writel(val, ctx->regs + VIDINTCON0); 271 } 272 } 273 274 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win) 275 { 276 struct exynos_drm_plane *plane = &ctx->planes[win]; 277 unsigned long val; 278 int padding; 279 280 val = readl(ctx->regs + WINCON(win)); 281 val &= ~WINCONx_BPPMODE_MASK; 282 283 switch (plane->pixel_format) { 284 case DRM_FORMAT_RGB565: 285 val |= WINCONx_BPPMODE_16BPP_565; 286 val |= WINCONx_BURSTLEN_16WORD; 287 break; 288 case DRM_FORMAT_XRGB8888: 289 val |= WINCONx_BPPMODE_24BPP_xRGB; 290 val |= WINCONx_BURSTLEN_16WORD; 291 break; 292 case DRM_FORMAT_XBGR8888: 293 val |= WINCONx_BPPMODE_24BPP_xBGR; 294 val |= WINCONx_BURSTLEN_16WORD; 295 break; 296 case DRM_FORMAT_RGBX8888: 297 val |= WINCONx_BPPMODE_24BPP_RGBx; 298 val |= WINCONx_BURSTLEN_16WORD; 299 break; 300 case DRM_FORMAT_BGRX8888: 301 val |= WINCONx_BPPMODE_24BPP_BGRx; 302 val |= WINCONx_BURSTLEN_16WORD; 303 break; 304 case DRM_FORMAT_ARGB8888: 305 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 306 WINCONx_ALPHA_SEL; 307 val |= WINCONx_BURSTLEN_16WORD; 308 break; 309 case DRM_FORMAT_ABGR8888: 310 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 311 WINCONx_ALPHA_SEL; 312 val |= WINCONx_BURSTLEN_16WORD; 313 break; 314 case DRM_FORMAT_RGBA8888: 315 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 316 WINCONx_ALPHA_SEL; 317 val |= WINCONx_BURSTLEN_16WORD; 318 break; 319 case DRM_FORMAT_BGRA8888: 320 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 321 WINCONx_ALPHA_SEL; 322 val |= WINCONx_BURSTLEN_16WORD; 323 break; 324 default: 325 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 326 327 val |= WINCONx_BPPMODE_24BPP_xRGB; 328 val |= WINCONx_BURSTLEN_16WORD; 329 break; 330 } 331 332 DRM_DEBUG_KMS("bpp = %d\n", plane->bpp); 333 334 /* 335 * In case of exynos, setting dma-burst to 16Word causes permanent 336 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 337 * switching which is based on plane size is not recommended as 338 * plane size varies a lot towards the end of the screen and rapid 339 * movement causes unstable DMA which results into iommu crash/tear. 340 */ 341 342 padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; 343 if (plane->fb_width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 344 val &= ~WINCONx_BURSTLEN_MASK; 345 val |= WINCONx_BURSTLEN_8WORD; 346 } 347 348 writel(val, ctx->regs + WINCON(win)); 349 } 350 351 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 352 { 353 unsigned int keycon0 = 0, keycon1 = 0; 354 355 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 356 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 357 358 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 359 360 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 361 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 362 } 363 364 /** 365 * shadow_protect_win() - disable updating values from shadow registers at vsync 366 * 367 * @win: window to protect registers for 368 * @protect: 1 to protect (disable updates) 369 */ 370 static void decon_shadow_protect_win(struct decon_context *ctx, 371 unsigned int win, bool protect) 372 { 373 u32 bits, val; 374 375 bits = SHADOWCON_WINx_PROTECT(win); 376 377 val = readl(ctx->regs + SHADOWCON); 378 if (protect) 379 val |= bits; 380 else 381 val &= ~bits; 382 writel(val, ctx->regs + SHADOWCON); 383 } 384 385 static void decon_win_commit(struct exynos_drm_crtc *crtc, unsigned int win) 386 { 387 struct decon_context *ctx = crtc->ctx; 388 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 389 struct exynos_drm_plane *plane; 390 int padding; 391 unsigned long val, alpha; 392 unsigned int last_x; 393 unsigned int last_y; 394 395 if (ctx->suspended) 396 return; 397 398 if (win < 0 || win >= WINDOWS_NR) 399 return; 400 401 plane = &ctx->planes[win]; 402 403 if (ctx->suspended) 404 return; 405 406 /* 407 * SHADOWCON/PRTCON register is used for enabling timing. 408 * 409 * for example, once only width value of a register is set, 410 * if the dma is started then decon hardware could malfunction so 411 * with protect window setting, the register fields with prefix '_F' 412 * wouldn't be updated at vsync also but updated once unprotect window 413 * is set. 414 */ 415 416 /* protect windows */ 417 decon_shadow_protect_win(ctx, win, true); 418 419 /* buffer start address */ 420 val = (unsigned long)plane->dma_addr[0]; 421 writel(val, ctx->regs + VIDW_BUF_START(win)); 422 423 padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width; 424 425 /* buffer size */ 426 writel(plane->fb_width + padding, ctx->regs + VIDW_WHOLE_X(win)); 427 writel(plane->fb_height, ctx->regs + VIDW_WHOLE_Y(win)); 428 429 /* offset from the start of the buffer to read */ 430 writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win)); 431 writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win)); 432 433 DRM_DEBUG_KMS("start addr = 0x%lx\n", 434 (unsigned long)val); 435 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 436 plane->crtc_width, plane->crtc_height); 437 438 /* 439 * OSD position. 440 * In case the window layout goes of LCD layout, DECON fails. 441 */ 442 if ((plane->crtc_x + plane->crtc_width) > mode->hdisplay) 443 plane->crtc_x = mode->hdisplay - plane->crtc_width; 444 if ((plane->crtc_y + plane->crtc_height) > mode->vdisplay) 445 plane->crtc_y = mode->vdisplay - plane->crtc_height; 446 447 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | 448 VIDOSDxA_TOPLEFT_Y(plane->crtc_y); 449 writel(val, ctx->regs + VIDOSD_A(win)); 450 451 last_x = plane->crtc_x + plane->crtc_width; 452 if (last_x) 453 last_x--; 454 last_y = plane->crtc_y + plane->crtc_height; 455 if (last_y) 456 last_y--; 457 458 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 459 460 writel(val, ctx->regs + VIDOSD_B(win)); 461 462 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 463 plane->crtc_x, plane->crtc_y, last_x, last_y); 464 465 /* OSD alpha */ 466 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 467 VIDOSDxC_ALPHA0_G_F(0x0) | 468 VIDOSDxC_ALPHA0_B_F(0x0); 469 470 writel(alpha, ctx->regs + VIDOSD_C(win)); 471 472 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 473 VIDOSDxD_ALPHA1_G_F(0xff) | 474 VIDOSDxD_ALPHA1_B_F(0xff); 475 476 writel(alpha, ctx->regs + VIDOSD_D(win)); 477 478 decon_win_set_pixfmt(ctx, win); 479 480 /* hardware window 0 doesn't support color key. */ 481 if (win != 0) 482 decon_win_set_colkey(ctx, win); 483 484 /* wincon */ 485 val = readl(ctx->regs + WINCON(win)); 486 val |= WINCONx_TRIPLE_BUF_MODE; 487 val |= WINCONx_ENWIN; 488 writel(val, ctx->regs + WINCON(win)); 489 490 /* Enable DMA channel and unprotect windows */ 491 decon_shadow_protect_win(ctx, win, false); 492 493 val = readl(ctx->regs + DECON_UPDATE); 494 val |= DECON_UPDATE_STANDALONE_F; 495 writel(val, ctx->regs + DECON_UPDATE); 496 } 497 498 static void decon_win_disable(struct exynos_drm_crtc *crtc, unsigned int win) 499 { 500 struct decon_context *ctx = crtc->ctx; 501 struct exynos_drm_plane *plane; 502 u32 val; 503 504 if (win < 0 || win >= WINDOWS_NR) 505 return; 506 507 plane = &ctx->planes[win]; 508 509 if (ctx->suspended) 510 return; 511 512 /* protect windows */ 513 decon_shadow_protect_win(ctx, win, true); 514 515 /* wincon */ 516 val = readl(ctx->regs + WINCON(win)); 517 val &= ~WINCONx_ENWIN; 518 writel(val, ctx->regs + WINCON(win)); 519 520 /* unprotect windows */ 521 decon_shadow_protect_win(ctx, win, false); 522 523 val = readl(ctx->regs + DECON_UPDATE); 524 val |= DECON_UPDATE_STANDALONE_F; 525 writel(val, ctx->regs + DECON_UPDATE); 526 } 527 528 static void decon_init(struct decon_context *ctx) 529 { 530 u32 val; 531 532 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 533 534 val = VIDOUTCON0_DISP_IF_0_ON; 535 if (!ctx->i80_if) 536 val |= VIDOUTCON0_RGBIF; 537 writel(val, ctx->regs + VIDOUTCON0); 538 539 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 540 541 if (!ctx->i80_if) 542 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 543 } 544 545 static void decon_enable(struct exynos_drm_crtc *crtc) 546 { 547 struct decon_context *ctx = crtc->ctx; 548 int ret; 549 550 if (!ctx->suspended) 551 return; 552 553 ctx->suspended = false; 554 555 pm_runtime_get_sync(ctx->dev); 556 557 ret = clk_prepare_enable(ctx->pclk); 558 if (ret < 0) { 559 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); 560 return; 561 } 562 563 ret = clk_prepare_enable(ctx->aclk); 564 if (ret < 0) { 565 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); 566 return; 567 } 568 569 ret = clk_prepare_enable(ctx->eclk); 570 if (ret < 0) { 571 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); 572 return; 573 } 574 575 ret = clk_prepare_enable(ctx->vclk); 576 if (ret < 0) { 577 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); 578 return; 579 } 580 581 decon_init(ctx); 582 583 /* if vblank was enabled status, enable it again. */ 584 if (test_and_clear_bit(0, &ctx->irq_flags)) 585 decon_enable_vblank(ctx->crtc); 586 587 decon_commit(ctx->crtc); 588 } 589 590 static void decon_disable(struct exynos_drm_crtc *crtc) 591 { 592 struct decon_context *ctx = crtc->ctx; 593 int i; 594 595 if (ctx->suspended) 596 return; 597 598 /* 599 * We need to make sure that all windows are disabled before we 600 * suspend that connector. Otherwise we might try to scan from 601 * a destroyed buffer later. 602 */ 603 for (i = 0; i < WINDOWS_NR; i++) 604 decon_win_disable(crtc, i); 605 606 clk_disable_unprepare(ctx->vclk); 607 clk_disable_unprepare(ctx->eclk); 608 clk_disable_unprepare(ctx->aclk); 609 clk_disable_unprepare(ctx->pclk); 610 611 pm_runtime_put_sync(ctx->dev); 612 613 ctx->suspended = true; 614 } 615 616 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 617 .enable = decon_enable, 618 .disable = decon_disable, 619 .mode_fixup = decon_mode_fixup, 620 .commit = decon_commit, 621 .enable_vblank = decon_enable_vblank, 622 .disable_vblank = decon_disable_vblank, 623 .wait_for_vblank = decon_wait_for_vblank, 624 .win_commit = decon_win_commit, 625 .win_disable = decon_win_disable, 626 .clear_channels = decon_clear_channels, 627 }; 628 629 630 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 631 { 632 struct decon_context *ctx = (struct decon_context *)dev_id; 633 u32 val, clear_bit; 634 635 val = readl(ctx->regs + VIDINTCON1); 636 637 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 638 if (val & clear_bit) 639 writel(clear_bit, ctx->regs + VIDINTCON1); 640 641 /* check the crtc is detached already from encoder */ 642 if (ctx->pipe < 0 || !ctx->drm_dev) 643 goto out; 644 645 if (!ctx->i80_if) { 646 drm_handle_vblank(ctx->drm_dev, ctx->pipe); 647 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe); 648 649 /* set wait vsync event to zero and wake up queue. */ 650 if (atomic_read(&ctx->wait_vsync_event)) { 651 atomic_set(&ctx->wait_vsync_event, 0); 652 wake_up(&ctx->wait_vsync_queue); 653 } 654 } 655 out: 656 return IRQ_HANDLED; 657 } 658 659 static int decon_bind(struct device *dev, struct device *master, void *data) 660 { 661 struct decon_context *ctx = dev_get_drvdata(dev); 662 struct drm_device *drm_dev = data; 663 struct exynos_drm_plane *exynos_plane; 664 enum drm_plane_type type; 665 unsigned int zpos; 666 int ret; 667 668 ret = decon_ctx_initialize(ctx, drm_dev); 669 if (ret) { 670 DRM_ERROR("decon_ctx_initialize failed.\n"); 671 return ret; 672 } 673 674 for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 675 type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 676 DRM_PLANE_TYPE_OVERLAY; 677 ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 678 1 << ctx->pipe, type, zpos); 679 if (ret) 680 return ret; 681 } 682 683 exynos_plane = &ctx->planes[ctx->default_win]; 684 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 685 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 686 &decon_crtc_ops, ctx); 687 if (IS_ERR(ctx->crtc)) { 688 decon_ctx_remove(ctx); 689 return PTR_ERR(ctx->crtc); 690 } 691 692 if (ctx->display) 693 exynos_drm_create_enc_conn(drm_dev, ctx->display); 694 695 return 0; 696 697 } 698 699 static void decon_unbind(struct device *dev, struct device *master, 700 void *data) 701 { 702 struct decon_context *ctx = dev_get_drvdata(dev); 703 704 decon_disable(ctx->crtc); 705 706 if (ctx->display) 707 exynos_dpi_remove(ctx->display); 708 709 decon_ctx_remove(ctx); 710 } 711 712 static const struct component_ops decon_component_ops = { 713 .bind = decon_bind, 714 .unbind = decon_unbind, 715 }; 716 717 static int decon_probe(struct platform_device *pdev) 718 { 719 struct device *dev = &pdev->dev; 720 struct decon_context *ctx; 721 struct device_node *i80_if_timings; 722 struct resource *res; 723 int ret; 724 725 if (!dev->of_node) 726 return -ENODEV; 727 728 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 729 if (!ctx) 730 return -ENOMEM; 731 732 ctx->dev = dev; 733 ctx->suspended = true; 734 735 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 736 if (i80_if_timings) 737 ctx->i80_if = true; 738 of_node_put(i80_if_timings); 739 740 ctx->regs = of_iomap(dev->of_node, 0); 741 if (!ctx->regs) 742 return -ENOMEM; 743 744 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 745 if (IS_ERR(ctx->pclk)) { 746 dev_err(dev, "failed to get bus clock pclk\n"); 747 ret = PTR_ERR(ctx->pclk); 748 goto err_iounmap; 749 } 750 751 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 752 if (IS_ERR(ctx->aclk)) { 753 dev_err(dev, "failed to get bus clock aclk\n"); 754 ret = PTR_ERR(ctx->aclk); 755 goto err_iounmap; 756 } 757 758 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 759 if (IS_ERR(ctx->eclk)) { 760 dev_err(dev, "failed to get eclock\n"); 761 ret = PTR_ERR(ctx->eclk); 762 goto err_iounmap; 763 } 764 765 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 766 if (IS_ERR(ctx->vclk)) { 767 dev_err(dev, "failed to get vclock\n"); 768 ret = PTR_ERR(ctx->vclk); 769 goto err_iounmap; 770 } 771 772 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 773 ctx->i80_if ? "lcd_sys" : "vsync"); 774 if (!res) { 775 dev_err(dev, "irq request failed.\n"); 776 ret = -ENXIO; 777 goto err_iounmap; 778 } 779 780 ret = devm_request_irq(dev, res->start, decon_irq_handler, 781 0, "drm_decon", ctx); 782 if (ret) { 783 dev_err(dev, "irq request failed.\n"); 784 goto err_iounmap; 785 } 786 787 init_waitqueue_head(&ctx->wait_vsync_queue); 788 atomic_set(&ctx->wait_vsync_event, 0); 789 790 platform_set_drvdata(pdev, ctx); 791 792 ctx->display = exynos_dpi_probe(dev); 793 if (IS_ERR(ctx->display)) { 794 ret = PTR_ERR(ctx->display); 795 goto err_iounmap; 796 } 797 798 pm_runtime_enable(dev); 799 800 ret = component_add(dev, &decon_component_ops); 801 if (ret) 802 goto err_disable_pm_runtime; 803 804 return ret; 805 806 err_disable_pm_runtime: 807 pm_runtime_disable(dev); 808 809 err_iounmap: 810 iounmap(ctx->regs); 811 812 return ret; 813 } 814 815 static int decon_remove(struct platform_device *pdev) 816 { 817 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 818 819 pm_runtime_disable(&pdev->dev); 820 821 iounmap(ctx->regs); 822 823 component_del(&pdev->dev, &decon_component_ops); 824 825 return 0; 826 } 827 828 struct platform_driver decon_driver = { 829 .probe = decon_probe, 830 .remove = decon_remove, 831 .driver = { 832 .name = "exynos-decon", 833 .of_match_table = decon_driver_dt_match, 834 }, 835 }; 836