1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 29 #include "exynos_drm_crtc.h" 30 #include "exynos_drm_plane.h" 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fb.h" 33 #include "regs-decon7.h" 34 35 /* 36 * DECON stands for Display and Enhancement controller. 37 */ 38 39 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 40 41 #define WINDOWS_NR 2 42 43 struct decon_context { 44 struct device *dev; 45 struct drm_device *drm_dev; 46 struct exynos_drm_crtc *crtc; 47 struct exynos_drm_plane planes[WINDOWS_NR]; 48 struct exynos_drm_plane_config configs[WINDOWS_NR]; 49 struct clk *pclk; 50 struct clk *aclk; 51 struct clk *eclk; 52 struct clk *vclk; 53 void __iomem *regs; 54 unsigned long irq_flags; 55 bool i80_if; 56 bool suspended; 57 wait_queue_head_t wait_vsync_queue; 58 atomic_t wait_vsync_event; 59 60 struct drm_encoder *encoder; 61 }; 62 63 static const struct of_device_id decon_driver_dt_match[] = { 64 {.compatible = "samsung,exynos7-decon"}, 65 {}, 66 }; 67 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 68 69 static const uint32_t decon_formats[] = { 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_XRGB8888, 72 DRM_FORMAT_XBGR8888, 73 DRM_FORMAT_RGBX8888, 74 DRM_FORMAT_BGRX8888, 75 DRM_FORMAT_ARGB8888, 76 DRM_FORMAT_ABGR8888, 77 DRM_FORMAT_RGBA8888, 78 DRM_FORMAT_BGRA8888, 79 }; 80 81 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 82 DRM_PLANE_TYPE_PRIMARY, 83 DRM_PLANE_TYPE_CURSOR, 84 }; 85 86 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 87 { 88 struct decon_context *ctx = crtc->ctx; 89 90 if (ctx->suspended) 91 return; 92 93 atomic_set(&ctx->wait_vsync_event, 1); 94 95 /* 96 * wait for DECON to signal VSYNC interrupt or return after 97 * timeout which is set to 50ms (refresh rate of 20). 98 */ 99 if (!wait_event_timeout(ctx->wait_vsync_queue, 100 !atomic_read(&ctx->wait_vsync_event), 101 HZ/20)) 102 DRM_DEBUG_KMS("vblank wait timed out.\n"); 103 } 104 105 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 106 { 107 struct decon_context *ctx = crtc->ctx; 108 unsigned int win, ch_enabled = 0; 109 110 DRM_DEBUG_KMS("%s\n", __FILE__); 111 112 /* Check if any channel is enabled. */ 113 for (win = 0; win < WINDOWS_NR; win++) { 114 u32 val = readl(ctx->regs + WINCON(win)); 115 116 if (val & WINCONx_ENWIN) { 117 val &= ~WINCONx_ENWIN; 118 writel(val, ctx->regs + WINCON(win)); 119 ch_enabled = 1; 120 } 121 } 122 123 /* Wait for vsync, as disable channel takes effect at next vsync */ 124 if (ch_enabled) 125 decon_wait_for_vblank(ctx->crtc); 126 } 127 128 static int decon_ctx_initialize(struct decon_context *ctx, 129 struct drm_device *drm_dev) 130 { 131 ctx->drm_dev = drm_dev; 132 133 decon_clear_channels(ctx->crtc); 134 135 return exynos_drm_register_dma(drm_dev, ctx->dev); 136 } 137 138 static void decon_ctx_remove(struct decon_context *ctx) 139 { 140 /* detach this sub driver from iommu mapping if supported. */ 141 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev); 142 } 143 144 static u32 decon_calc_clkdiv(struct decon_context *ctx, 145 const struct drm_display_mode *mode) 146 { 147 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 148 u32 clkdiv; 149 150 /* Find the clock divider value that gets us closest to ideal_clk */ 151 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 152 153 return (clkdiv < 0x100) ? clkdiv : 0xff; 154 } 155 156 static void decon_commit(struct exynos_drm_crtc *crtc) 157 { 158 struct decon_context *ctx = crtc->ctx; 159 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 160 u32 val, clkdiv; 161 162 if (ctx->suspended) 163 return; 164 165 /* nothing to do if we haven't set the mode yet */ 166 if (mode->htotal == 0 || mode->vtotal == 0) 167 return; 168 169 if (!ctx->i80_if) { 170 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 171 /* setup vertical timing values. */ 172 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 173 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 174 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 175 176 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 177 writel(val, ctx->regs + VIDTCON0); 178 179 val = VIDTCON1_VSPW(vsync_len - 1); 180 writel(val, ctx->regs + VIDTCON1); 181 182 /* setup horizontal timing values. */ 183 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 184 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 185 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 186 187 /* setup horizontal timing values. */ 188 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 189 writel(val, ctx->regs + VIDTCON2); 190 191 val = VIDTCON3_HSPW(hsync_len - 1); 192 writel(val, ctx->regs + VIDTCON3); 193 } 194 195 /* setup horizontal and vertical display size. */ 196 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 197 VIDTCON4_HOZVAL(mode->hdisplay - 1); 198 writel(val, ctx->regs + VIDTCON4); 199 200 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 201 202 /* 203 * fields of register with prefix '_F' would be updated 204 * at vsync(same as dma start) 205 */ 206 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 207 writel(val, ctx->regs + VIDCON0); 208 209 clkdiv = decon_calc_clkdiv(ctx, mode); 210 if (clkdiv > 1) { 211 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 212 writel(val, ctx->regs + VCLKCON1); 213 writel(val, ctx->regs + VCLKCON2); 214 } 215 216 val = readl(ctx->regs + DECON_UPDATE); 217 val |= DECON_UPDATE_STANDALONE_F; 218 writel(val, ctx->regs + DECON_UPDATE); 219 } 220 221 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 222 { 223 struct decon_context *ctx = crtc->ctx; 224 u32 val; 225 226 if (ctx->suspended) 227 return -EPERM; 228 229 if (!test_and_set_bit(0, &ctx->irq_flags)) { 230 val = readl(ctx->regs + VIDINTCON0); 231 232 val |= VIDINTCON0_INT_ENABLE; 233 234 if (!ctx->i80_if) { 235 val |= VIDINTCON0_INT_FRAME; 236 val &= ~VIDINTCON0_FRAMESEL0_MASK; 237 val |= VIDINTCON0_FRAMESEL0_VSYNC; 238 } 239 240 writel(val, ctx->regs + VIDINTCON0); 241 } 242 243 return 0; 244 } 245 246 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 247 { 248 struct decon_context *ctx = crtc->ctx; 249 u32 val; 250 251 if (ctx->suspended) 252 return; 253 254 if (test_and_clear_bit(0, &ctx->irq_flags)) { 255 val = readl(ctx->regs + VIDINTCON0); 256 257 val &= ~VIDINTCON0_INT_ENABLE; 258 if (!ctx->i80_if) 259 val &= ~VIDINTCON0_INT_FRAME; 260 261 writel(val, ctx->regs + VIDINTCON0); 262 } 263 } 264 265 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 266 struct drm_framebuffer *fb) 267 { 268 unsigned long val; 269 int padding; 270 271 val = readl(ctx->regs + WINCON(win)); 272 val &= ~WINCONx_BPPMODE_MASK; 273 274 switch (fb->format->format) { 275 case DRM_FORMAT_RGB565: 276 val |= WINCONx_BPPMODE_16BPP_565; 277 val |= WINCONx_BURSTLEN_16WORD; 278 break; 279 case DRM_FORMAT_XRGB8888: 280 val |= WINCONx_BPPMODE_24BPP_xRGB; 281 val |= WINCONx_BURSTLEN_16WORD; 282 break; 283 case DRM_FORMAT_XBGR8888: 284 val |= WINCONx_BPPMODE_24BPP_xBGR; 285 val |= WINCONx_BURSTLEN_16WORD; 286 break; 287 case DRM_FORMAT_RGBX8888: 288 val |= WINCONx_BPPMODE_24BPP_RGBx; 289 val |= WINCONx_BURSTLEN_16WORD; 290 break; 291 case DRM_FORMAT_BGRX8888: 292 val |= WINCONx_BPPMODE_24BPP_BGRx; 293 val |= WINCONx_BURSTLEN_16WORD; 294 break; 295 case DRM_FORMAT_ARGB8888: 296 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 297 WINCONx_ALPHA_SEL; 298 val |= WINCONx_BURSTLEN_16WORD; 299 break; 300 case DRM_FORMAT_ABGR8888: 301 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 302 WINCONx_ALPHA_SEL; 303 val |= WINCONx_BURSTLEN_16WORD; 304 break; 305 case DRM_FORMAT_RGBA8888: 306 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 307 WINCONx_ALPHA_SEL; 308 val |= WINCONx_BURSTLEN_16WORD; 309 break; 310 case DRM_FORMAT_BGRA8888: 311 default: 312 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 313 WINCONx_ALPHA_SEL; 314 val |= WINCONx_BURSTLEN_16WORD; 315 break; 316 } 317 318 DRM_DEBUG_KMS("cpp = %d\n", fb->format->cpp[0]); 319 320 /* 321 * In case of exynos, setting dma-burst to 16Word causes permanent 322 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 323 * switching which is based on plane size is not recommended as 324 * plane size varies a lot towards the end of the screen and rapid 325 * movement causes unstable DMA which results into iommu crash/tear. 326 */ 327 328 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width; 329 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 330 val &= ~WINCONx_BURSTLEN_MASK; 331 val |= WINCONx_BURSTLEN_8WORD; 332 } 333 334 writel(val, ctx->regs + WINCON(win)); 335 } 336 337 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 338 { 339 unsigned int keycon0 = 0, keycon1 = 0; 340 341 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 342 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 343 344 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 345 346 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 347 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 348 } 349 350 /** 351 * shadow_protect_win() - disable updating values from shadow registers at vsync 352 * 353 * @win: window to protect registers for 354 * @protect: 1 to protect (disable updates) 355 */ 356 static void decon_shadow_protect_win(struct decon_context *ctx, 357 unsigned int win, bool protect) 358 { 359 u32 bits, val; 360 361 bits = SHADOWCON_WINx_PROTECT(win); 362 363 val = readl(ctx->regs + SHADOWCON); 364 if (protect) 365 val |= bits; 366 else 367 val &= ~bits; 368 writel(val, ctx->regs + SHADOWCON); 369 } 370 371 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 372 { 373 struct decon_context *ctx = crtc->ctx; 374 int i; 375 376 if (ctx->suspended) 377 return; 378 379 for (i = 0; i < WINDOWS_NR; i++) 380 decon_shadow_protect_win(ctx, i, true); 381 } 382 383 static void decon_update_plane(struct exynos_drm_crtc *crtc, 384 struct exynos_drm_plane *plane) 385 { 386 struct exynos_drm_plane_state *state = 387 to_exynos_plane_state(plane->base.state); 388 struct decon_context *ctx = crtc->ctx; 389 struct drm_framebuffer *fb = state->base.fb; 390 int padding; 391 unsigned long val, alpha; 392 unsigned int last_x; 393 unsigned int last_y; 394 unsigned int win = plane->index; 395 unsigned int cpp = fb->format->cpp[0]; 396 unsigned int pitch = fb->pitches[0]; 397 398 if (ctx->suspended) 399 return; 400 401 /* 402 * SHADOWCON/PRTCON register is used for enabling timing. 403 * 404 * for example, once only width value of a register is set, 405 * if the dma is started then decon hardware could malfunction so 406 * with protect window setting, the register fields with prefix '_F' 407 * wouldn't be updated at vsync also but updated once unprotect window 408 * is set. 409 */ 410 411 /* buffer start address */ 412 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 413 writel(val, ctx->regs + VIDW_BUF_START(win)); 414 415 padding = (pitch / cpp) - fb->width; 416 417 /* buffer size */ 418 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 419 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 420 421 /* offset from the start of the buffer to read */ 422 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); 423 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); 424 425 DRM_DEBUG_KMS("start addr = 0x%lx\n", 426 (unsigned long)val); 427 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 428 state->crtc.w, state->crtc.h); 429 430 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 431 VIDOSDxA_TOPLEFT_Y(state->crtc.y); 432 writel(val, ctx->regs + VIDOSD_A(win)); 433 434 last_x = state->crtc.x + state->crtc.w; 435 if (last_x) 436 last_x--; 437 last_y = state->crtc.y + state->crtc.h; 438 if (last_y) 439 last_y--; 440 441 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 442 443 writel(val, ctx->regs + VIDOSD_B(win)); 444 445 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 446 state->crtc.x, state->crtc.y, last_x, last_y); 447 448 /* OSD alpha */ 449 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 450 VIDOSDxC_ALPHA0_G_F(0x0) | 451 VIDOSDxC_ALPHA0_B_F(0x0); 452 453 writel(alpha, ctx->regs + VIDOSD_C(win)); 454 455 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 456 VIDOSDxD_ALPHA1_G_F(0xff) | 457 VIDOSDxD_ALPHA1_B_F(0xff); 458 459 writel(alpha, ctx->regs + VIDOSD_D(win)); 460 461 decon_win_set_pixfmt(ctx, win, fb); 462 463 /* hardware window 0 doesn't support color key. */ 464 if (win != 0) 465 decon_win_set_colkey(ctx, win); 466 467 /* wincon */ 468 val = readl(ctx->regs + WINCON(win)); 469 val |= WINCONx_TRIPLE_BUF_MODE; 470 val |= WINCONx_ENWIN; 471 writel(val, ctx->regs + WINCON(win)); 472 473 /* Enable DMA channel and unprotect windows */ 474 decon_shadow_protect_win(ctx, win, false); 475 476 val = readl(ctx->regs + DECON_UPDATE); 477 val |= DECON_UPDATE_STANDALONE_F; 478 writel(val, ctx->regs + DECON_UPDATE); 479 } 480 481 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 482 struct exynos_drm_plane *plane) 483 { 484 struct decon_context *ctx = crtc->ctx; 485 unsigned int win = plane->index; 486 u32 val; 487 488 if (ctx->suspended) 489 return; 490 491 /* protect windows */ 492 decon_shadow_protect_win(ctx, win, true); 493 494 /* wincon */ 495 val = readl(ctx->regs + WINCON(win)); 496 val &= ~WINCONx_ENWIN; 497 writel(val, ctx->regs + WINCON(win)); 498 499 val = readl(ctx->regs + DECON_UPDATE); 500 val |= DECON_UPDATE_STANDALONE_F; 501 writel(val, ctx->regs + DECON_UPDATE); 502 } 503 504 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 505 { 506 struct decon_context *ctx = crtc->ctx; 507 int i; 508 509 if (ctx->suspended) 510 return; 511 512 for (i = 0; i < WINDOWS_NR; i++) 513 decon_shadow_protect_win(ctx, i, false); 514 exynos_crtc_handle_event(crtc); 515 } 516 517 static void decon_init(struct decon_context *ctx) 518 { 519 u32 val; 520 521 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 522 523 val = VIDOUTCON0_DISP_IF_0_ON; 524 if (!ctx->i80_if) 525 val |= VIDOUTCON0_RGBIF; 526 writel(val, ctx->regs + VIDOUTCON0); 527 528 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 529 530 if (!ctx->i80_if) 531 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 532 } 533 534 static void decon_enable(struct exynos_drm_crtc *crtc) 535 { 536 struct decon_context *ctx = crtc->ctx; 537 538 if (!ctx->suspended) 539 return; 540 541 pm_runtime_get_sync(ctx->dev); 542 543 decon_init(ctx); 544 545 /* if vblank was enabled status, enable it again. */ 546 if (test_and_clear_bit(0, &ctx->irq_flags)) 547 decon_enable_vblank(ctx->crtc); 548 549 decon_commit(ctx->crtc); 550 551 ctx->suspended = false; 552 } 553 554 static void decon_disable(struct exynos_drm_crtc *crtc) 555 { 556 struct decon_context *ctx = crtc->ctx; 557 int i; 558 559 if (ctx->suspended) 560 return; 561 562 /* 563 * We need to make sure that all windows are disabled before we 564 * suspend that connector. Otherwise we might try to scan from 565 * a destroyed buffer later. 566 */ 567 for (i = 0; i < WINDOWS_NR; i++) 568 decon_disable_plane(crtc, &ctx->planes[i]); 569 570 pm_runtime_put_sync(ctx->dev); 571 572 ctx->suspended = true; 573 } 574 575 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 576 .enable = decon_enable, 577 .disable = decon_disable, 578 .enable_vblank = decon_enable_vblank, 579 .disable_vblank = decon_disable_vblank, 580 .atomic_begin = decon_atomic_begin, 581 .update_plane = decon_update_plane, 582 .disable_plane = decon_disable_plane, 583 .atomic_flush = decon_atomic_flush, 584 }; 585 586 587 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 588 { 589 struct decon_context *ctx = (struct decon_context *)dev_id; 590 u32 val, clear_bit; 591 592 val = readl(ctx->regs + VIDINTCON1); 593 594 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 595 if (val & clear_bit) 596 writel(clear_bit, ctx->regs + VIDINTCON1); 597 598 /* check the crtc is detached already from encoder */ 599 if (!ctx->drm_dev) 600 goto out; 601 602 if (!ctx->i80_if) { 603 drm_crtc_handle_vblank(&ctx->crtc->base); 604 605 /* set wait vsync event to zero and wake up queue. */ 606 if (atomic_read(&ctx->wait_vsync_event)) { 607 atomic_set(&ctx->wait_vsync_event, 0); 608 wake_up(&ctx->wait_vsync_queue); 609 } 610 } 611 out: 612 return IRQ_HANDLED; 613 } 614 615 static int decon_bind(struct device *dev, struct device *master, void *data) 616 { 617 struct decon_context *ctx = dev_get_drvdata(dev); 618 struct drm_device *drm_dev = data; 619 struct exynos_drm_plane *exynos_plane; 620 unsigned int i; 621 int ret; 622 623 ret = decon_ctx_initialize(ctx, drm_dev); 624 if (ret) { 625 DRM_ERROR("decon_ctx_initialize failed.\n"); 626 return ret; 627 } 628 629 for (i = 0; i < WINDOWS_NR; i++) { 630 ctx->configs[i].pixel_formats = decon_formats; 631 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); 632 ctx->configs[i].zpos = i; 633 ctx->configs[i].type = decon_win_types[i]; 634 635 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 636 &ctx->configs[i]); 637 if (ret) 638 return ret; 639 } 640 641 exynos_plane = &ctx->planes[DEFAULT_WIN]; 642 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 643 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx); 644 if (IS_ERR(ctx->crtc)) { 645 decon_ctx_remove(ctx); 646 return PTR_ERR(ctx->crtc); 647 } 648 649 if (ctx->encoder) 650 exynos_dpi_bind(drm_dev, ctx->encoder); 651 652 return 0; 653 654 } 655 656 static void decon_unbind(struct device *dev, struct device *master, 657 void *data) 658 { 659 struct decon_context *ctx = dev_get_drvdata(dev); 660 661 decon_disable(ctx->crtc); 662 663 if (ctx->encoder) 664 exynos_dpi_remove(ctx->encoder); 665 666 decon_ctx_remove(ctx); 667 } 668 669 static const struct component_ops decon_component_ops = { 670 .bind = decon_bind, 671 .unbind = decon_unbind, 672 }; 673 674 static int decon_probe(struct platform_device *pdev) 675 { 676 struct device *dev = &pdev->dev; 677 struct decon_context *ctx; 678 struct device_node *i80_if_timings; 679 struct resource *res; 680 int ret; 681 682 if (!dev->of_node) 683 return -ENODEV; 684 685 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 686 if (!ctx) 687 return -ENOMEM; 688 689 ctx->dev = dev; 690 ctx->suspended = true; 691 692 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 693 if (i80_if_timings) 694 ctx->i80_if = true; 695 of_node_put(i80_if_timings); 696 697 ctx->regs = of_iomap(dev->of_node, 0); 698 if (!ctx->regs) 699 return -ENOMEM; 700 701 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 702 if (IS_ERR(ctx->pclk)) { 703 dev_err(dev, "failed to get bus clock pclk\n"); 704 ret = PTR_ERR(ctx->pclk); 705 goto err_iounmap; 706 } 707 708 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 709 if (IS_ERR(ctx->aclk)) { 710 dev_err(dev, "failed to get bus clock aclk\n"); 711 ret = PTR_ERR(ctx->aclk); 712 goto err_iounmap; 713 } 714 715 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 716 if (IS_ERR(ctx->eclk)) { 717 dev_err(dev, "failed to get eclock\n"); 718 ret = PTR_ERR(ctx->eclk); 719 goto err_iounmap; 720 } 721 722 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 723 if (IS_ERR(ctx->vclk)) { 724 dev_err(dev, "failed to get vclock\n"); 725 ret = PTR_ERR(ctx->vclk); 726 goto err_iounmap; 727 } 728 729 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 730 ctx->i80_if ? "lcd_sys" : "vsync"); 731 if (!res) { 732 dev_err(dev, "irq request failed.\n"); 733 ret = -ENXIO; 734 goto err_iounmap; 735 } 736 737 ret = devm_request_irq(dev, res->start, decon_irq_handler, 738 0, "drm_decon", ctx); 739 if (ret) { 740 dev_err(dev, "irq request failed.\n"); 741 goto err_iounmap; 742 } 743 744 init_waitqueue_head(&ctx->wait_vsync_queue); 745 atomic_set(&ctx->wait_vsync_event, 0); 746 747 platform_set_drvdata(pdev, ctx); 748 749 ctx->encoder = exynos_dpi_probe(dev); 750 if (IS_ERR(ctx->encoder)) { 751 ret = PTR_ERR(ctx->encoder); 752 goto err_iounmap; 753 } 754 755 pm_runtime_enable(dev); 756 757 ret = component_add(dev, &decon_component_ops); 758 if (ret) 759 goto err_disable_pm_runtime; 760 761 return ret; 762 763 err_disable_pm_runtime: 764 pm_runtime_disable(dev); 765 766 err_iounmap: 767 iounmap(ctx->regs); 768 769 return ret; 770 } 771 772 static int decon_remove(struct platform_device *pdev) 773 { 774 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 775 776 pm_runtime_disable(&pdev->dev); 777 778 iounmap(ctx->regs); 779 780 component_del(&pdev->dev, &decon_component_ops); 781 782 return 0; 783 } 784 785 #ifdef CONFIG_PM 786 static int exynos7_decon_suspend(struct device *dev) 787 { 788 struct decon_context *ctx = dev_get_drvdata(dev); 789 790 clk_disable_unprepare(ctx->vclk); 791 clk_disable_unprepare(ctx->eclk); 792 clk_disable_unprepare(ctx->aclk); 793 clk_disable_unprepare(ctx->pclk); 794 795 return 0; 796 } 797 798 static int exynos7_decon_resume(struct device *dev) 799 { 800 struct decon_context *ctx = dev_get_drvdata(dev); 801 int ret; 802 803 ret = clk_prepare_enable(ctx->pclk); 804 if (ret < 0) { 805 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); 806 return ret; 807 } 808 809 ret = clk_prepare_enable(ctx->aclk); 810 if (ret < 0) { 811 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); 812 return ret; 813 } 814 815 ret = clk_prepare_enable(ctx->eclk); 816 if (ret < 0) { 817 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); 818 return ret; 819 } 820 821 ret = clk_prepare_enable(ctx->vclk); 822 if (ret < 0) { 823 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); 824 return ret; 825 } 826 827 return 0; 828 } 829 #endif 830 831 static const struct dev_pm_ops exynos7_decon_pm_ops = { 832 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume, 833 NULL) 834 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 835 pm_runtime_force_resume) 836 }; 837 838 struct platform_driver decon_driver = { 839 .probe = decon_probe, 840 .remove = decon_remove, 841 .driver = { 842 .name = "exynos-decon", 843 .pm = &exynos7_decon_pm_ops, 844 .of_match_table = decon_driver_dt_match, 845 }, 846 }; 847