1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 #include <video/exynos7_decon.h> 29 30 #include "exynos_drm_crtc.h" 31 #include "exynos_drm_plane.h" 32 #include "exynos_drm_drv.h" 33 #include "exynos_drm_fb.h" 34 #include "exynos_drm_iommu.h" 35 36 /* 37 * DECON stands for Display and Enhancement controller. 38 */ 39 40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 41 42 #define WINDOWS_NR 2 43 44 struct decon_context { 45 struct device *dev; 46 struct drm_device *drm_dev; 47 struct exynos_drm_crtc *crtc; 48 struct exynos_drm_plane planes[WINDOWS_NR]; 49 struct exynos_drm_plane_config configs[WINDOWS_NR]; 50 struct clk *pclk; 51 struct clk *aclk; 52 struct clk *eclk; 53 struct clk *vclk; 54 void __iomem *regs; 55 unsigned long irq_flags; 56 bool i80_if; 57 bool suspended; 58 wait_queue_head_t wait_vsync_queue; 59 atomic_t wait_vsync_event; 60 61 struct drm_encoder *encoder; 62 }; 63 64 static const struct of_device_id decon_driver_dt_match[] = { 65 {.compatible = "samsung,exynos7-decon"}, 66 {}, 67 }; 68 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 69 70 static const uint32_t decon_formats[] = { 71 DRM_FORMAT_RGB565, 72 DRM_FORMAT_XRGB8888, 73 DRM_FORMAT_XBGR8888, 74 DRM_FORMAT_RGBX8888, 75 DRM_FORMAT_BGRX8888, 76 DRM_FORMAT_ARGB8888, 77 DRM_FORMAT_ABGR8888, 78 DRM_FORMAT_RGBA8888, 79 DRM_FORMAT_BGRA8888, 80 }; 81 82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 83 DRM_PLANE_TYPE_PRIMARY, 84 DRM_PLANE_TYPE_CURSOR, 85 }; 86 87 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 88 { 89 struct decon_context *ctx = crtc->ctx; 90 91 if (ctx->suspended) 92 return; 93 94 atomic_set(&ctx->wait_vsync_event, 1); 95 96 /* 97 * wait for DECON to signal VSYNC interrupt or return after 98 * timeout which is set to 50ms (refresh rate of 20). 99 */ 100 if (!wait_event_timeout(ctx->wait_vsync_queue, 101 !atomic_read(&ctx->wait_vsync_event), 102 HZ/20)) 103 DRM_DEBUG_KMS("vblank wait timed out.\n"); 104 } 105 106 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 107 { 108 struct decon_context *ctx = crtc->ctx; 109 unsigned int win, ch_enabled = 0; 110 111 DRM_DEBUG_KMS("%s\n", __FILE__); 112 113 /* Check if any channel is enabled. */ 114 for (win = 0; win < WINDOWS_NR; win++) { 115 u32 val = readl(ctx->regs + WINCON(win)); 116 117 if (val & WINCONx_ENWIN) { 118 val &= ~WINCONx_ENWIN; 119 writel(val, ctx->regs + WINCON(win)); 120 ch_enabled = 1; 121 } 122 } 123 124 /* Wait for vsync, as disable channel takes effect at next vsync */ 125 if (ch_enabled) 126 decon_wait_for_vblank(ctx->crtc); 127 } 128 129 static int decon_ctx_initialize(struct decon_context *ctx, 130 struct drm_device *drm_dev) 131 { 132 ctx->drm_dev = drm_dev; 133 134 decon_clear_channels(ctx->crtc); 135 136 return drm_iommu_attach_device(drm_dev, ctx->dev); 137 } 138 139 static void decon_ctx_remove(struct decon_context *ctx) 140 { 141 /* detach this sub driver from iommu mapping if supported. */ 142 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 143 } 144 145 static u32 decon_calc_clkdiv(struct decon_context *ctx, 146 const struct drm_display_mode *mode) 147 { 148 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 149 u32 clkdiv; 150 151 /* Find the clock divider value that gets us closest to ideal_clk */ 152 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 153 154 return (clkdiv < 0x100) ? clkdiv : 0xff; 155 } 156 157 static void decon_commit(struct exynos_drm_crtc *crtc) 158 { 159 struct decon_context *ctx = crtc->ctx; 160 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 161 u32 val, clkdiv; 162 163 if (ctx->suspended) 164 return; 165 166 /* nothing to do if we haven't set the mode yet */ 167 if (mode->htotal == 0 || mode->vtotal == 0) 168 return; 169 170 if (!ctx->i80_if) { 171 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 172 /* setup vertical timing values. */ 173 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 174 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 175 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 176 177 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 178 writel(val, ctx->regs + VIDTCON0); 179 180 val = VIDTCON1_VSPW(vsync_len - 1); 181 writel(val, ctx->regs + VIDTCON1); 182 183 /* setup horizontal timing values. */ 184 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 185 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 186 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 187 188 /* setup horizontal timing values. */ 189 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 190 writel(val, ctx->regs + VIDTCON2); 191 192 val = VIDTCON3_HSPW(hsync_len - 1); 193 writel(val, ctx->regs + VIDTCON3); 194 } 195 196 /* setup horizontal and vertical display size. */ 197 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 198 VIDTCON4_HOZVAL(mode->hdisplay - 1); 199 writel(val, ctx->regs + VIDTCON4); 200 201 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 202 203 /* 204 * fields of register with prefix '_F' would be updated 205 * at vsync(same as dma start) 206 */ 207 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 208 writel(val, ctx->regs + VIDCON0); 209 210 clkdiv = decon_calc_clkdiv(ctx, mode); 211 if (clkdiv > 1) { 212 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 213 writel(val, ctx->regs + VCLKCON1); 214 writel(val, ctx->regs + VCLKCON2); 215 } 216 217 val = readl(ctx->regs + DECON_UPDATE); 218 val |= DECON_UPDATE_STANDALONE_F; 219 writel(val, ctx->regs + DECON_UPDATE); 220 } 221 222 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 223 { 224 struct decon_context *ctx = crtc->ctx; 225 u32 val; 226 227 if (ctx->suspended) 228 return -EPERM; 229 230 if (!test_and_set_bit(0, &ctx->irq_flags)) { 231 val = readl(ctx->regs + VIDINTCON0); 232 233 val |= VIDINTCON0_INT_ENABLE; 234 235 if (!ctx->i80_if) { 236 val |= VIDINTCON0_INT_FRAME; 237 val &= ~VIDINTCON0_FRAMESEL0_MASK; 238 val |= VIDINTCON0_FRAMESEL0_VSYNC; 239 } 240 241 writel(val, ctx->regs + VIDINTCON0); 242 } 243 244 return 0; 245 } 246 247 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 248 { 249 struct decon_context *ctx = crtc->ctx; 250 u32 val; 251 252 if (ctx->suspended) 253 return; 254 255 if (test_and_clear_bit(0, &ctx->irq_flags)) { 256 val = readl(ctx->regs + VIDINTCON0); 257 258 val &= ~VIDINTCON0_INT_ENABLE; 259 if (!ctx->i80_if) 260 val &= ~VIDINTCON0_INT_FRAME; 261 262 writel(val, ctx->regs + VIDINTCON0); 263 } 264 } 265 266 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 267 struct drm_framebuffer *fb) 268 { 269 unsigned long val; 270 int padding; 271 272 val = readl(ctx->regs + WINCON(win)); 273 val &= ~WINCONx_BPPMODE_MASK; 274 275 switch (fb->format->format) { 276 case DRM_FORMAT_RGB565: 277 val |= WINCONx_BPPMODE_16BPP_565; 278 val |= WINCONx_BURSTLEN_16WORD; 279 break; 280 case DRM_FORMAT_XRGB8888: 281 val |= WINCONx_BPPMODE_24BPP_xRGB; 282 val |= WINCONx_BURSTLEN_16WORD; 283 break; 284 case DRM_FORMAT_XBGR8888: 285 val |= WINCONx_BPPMODE_24BPP_xBGR; 286 val |= WINCONx_BURSTLEN_16WORD; 287 break; 288 case DRM_FORMAT_RGBX8888: 289 val |= WINCONx_BPPMODE_24BPP_RGBx; 290 val |= WINCONx_BURSTLEN_16WORD; 291 break; 292 case DRM_FORMAT_BGRX8888: 293 val |= WINCONx_BPPMODE_24BPP_BGRx; 294 val |= WINCONx_BURSTLEN_16WORD; 295 break; 296 case DRM_FORMAT_ARGB8888: 297 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 298 WINCONx_ALPHA_SEL; 299 val |= WINCONx_BURSTLEN_16WORD; 300 break; 301 case DRM_FORMAT_ABGR8888: 302 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 303 WINCONx_ALPHA_SEL; 304 val |= WINCONx_BURSTLEN_16WORD; 305 break; 306 case DRM_FORMAT_RGBA8888: 307 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 308 WINCONx_ALPHA_SEL; 309 val |= WINCONx_BURSTLEN_16WORD; 310 break; 311 case DRM_FORMAT_BGRA8888: 312 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 313 WINCONx_ALPHA_SEL; 314 val |= WINCONx_BURSTLEN_16WORD; 315 break; 316 default: 317 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); 318 319 val |= WINCONx_BPPMODE_24BPP_xRGB; 320 val |= WINCONx_BURSTLEN_16WORD; 321 break; 322 } 323 324 DRM_DEBUG_KMS("bpp = %d\n", fb->format->cpp[0] * 8); 325 326 /* 327 * In case of exynos, setting dma-burst to 16Word causes permanent 328 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 329 * switching which is based on plane size is not recommended as 330 * plane size varies a lot towards the end of the screen and rapid 331 * movement causes unstable DMA which results into iommu crash/tear. 332 */ 333 334 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width; 335 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 336 val &= ~WINCONx_BURSTLEN_MASK; 337 val |= WINCONx_BURSTLEN_8WORD; 338 } 339 340 writel(val, ctx->regs + WINCON(win)); 341 } 342 343 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 344 { 345 unsigned int keycon0 = 0, keycon1 = 0; 346 347 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 348 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 349 350 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 351 352 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 353 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 354 } 355 356 /** 357 * shadow_protect_win() - disable updating values from shadow registers at vsync 358 * 359 * @win: window to protect registers for 360 * @protect: 1 to protect (disable updates) 361 */ 362 static void decon_shadow_protect_win(struct decon_context *ctx, 363 unsigned int win, bool protect) 364 { 365 u32 bits, val; 366 367 bits = SHADOWCON_WINx_PROTECT(win); 368 369 val = readl(ctx->regs + SHADOWCON); 370 if (protect) 371 val |= bits; 372 else 373 val &= ~bits; 374 writel(val, ctx->regs + SHADOWCON); 375 } 376 377 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 378 { 379 struct decon_context *ctx = crtc->ctx; 380 int i; 381 382 if (ctx->suspended) 383 return; 384 385 for (i = 0; i < WINDOWS_NR; i++) 386 decon_shadow_protect_win(ctx, i, true); 387 } 388 389 static void decon_update_plane(struct exynos_drm_crtc *crtc, 390 struct exynos_drm_plane *plane) 391 { 392 struct exynos_drm_plane_state *state = 393 to_exynos_plane_state(plane->base.state); 394 struct decon_context *ctx = crtc->ctx; 395 struct drm_framebuffer *fb = state->base.fb; 396 int padding; 397 unsigned long val, alpha; 398 unsigned int last_x; 399 unsigned int last_y; 400 unsigned int win = plane->index; 401 unsigned int bpp = fb->format->cpp[0]; 402 unsigned int pitch = fb->pitches[0]; 403 404 if (ctx->suspended) 405 return; 406 407 /* 408 * SHADOWCON/PRTCON register is used for enabling timing. 409 * 410 * for example, once only width value of a register is set, 411 * if the dma is started then decon hardware could malfunction so 412 * with protect window setting, the register fields with prefix '_F' 413 * wouldn't be updated at vsync also but updated once unprotect window 414 * is set. 415 */ 416 417 /* buffer start address */ 418 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 419 writel(val, ctx->regs + VIDW_BUF_START(win)); 420 421 padding = (pitch / bpp) - fb->width; 422 423 /* buffer size */ 424 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 425 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 426 427 /* offset from the start of the buffer to read */ 428 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); 429 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); 430 431 DRM_DEBUG_KMS("start addr = 0x%lx\n", 432 (unsigned long)val); 433 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 434 state->crtc.w, state->crtc.h); 435 436 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 437 VIDOSDxA_TOPLEFT_Y(state->crtc.y); 438 writel(val, ctx->regs + VIDOSD_A(win)); 439 440 last_x = state->crtc.x + state->crtc.w; 441 if (last_x) 442 last_x--; 443 last_y = state->crtc.y + state->crtc.h; 444 if (last_y) 445 last_y--; 446 447 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 448 449 writel(val, ctx->regs + VIDOSD_B(win)); 450 451 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 452 state->crtc.x, state->crtc.y, last_x, last_y); 453 454 /* OSD alpha */ 455 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 456 VIDOSDxC_ALPHA0_G_F(0x0) | 457 VIDOSDxC_ALPHA0_B_F(0x0); 458 459 writel(alpha, ctx->regs + VIDOSD_C(win)); 460 461 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 462 VIDOSDxD_ALPHA1_G_F(0xff) | 463 VIDOSDxD_ALPHA1_B_F(0xff); 464 465 writel(alpha, ctx->regs + VIDOSD_D(win)); 466 467 decon_win_set_pixfmt(ctx, win, fb); 468 469 /* hardware window 0 doesn't support color key. */ 470 if (win != 0) 471 decon_win_set_colkey(ctx, win); 472 473 /* wincon */ 474 val = readl(ctx->regs + WINCON(win)); 475 val |= WINCONx_TRIPLE_BUF_MODE; 476 val |= WINCONx_ENWIN; 477 writel(val, ctx->regs + WINCON(win)); 478 479 /* Enable DMA channel and unprotect windows */ 480 decon_shadow_protect_win(ctx, win, false); 481 482 val = readl(ctx->regs + DECON_UPDATE); 483 val |= DECON_UPDATE_STANDALONE_F; 484 writel(val, ctx->regs + DECON_UPDATE); 485 } 486 487 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 488 struct exynos_drm_plane *plane) 489 { 490 struct decon_context *ctx = crtc->ctx; 491 unsigned int win = plane->index; 492 u32 val; 493 494 if (ctx->suspended) 495 return; 496 497 /* protect windows */ 498 decon_shadow_protect_win(ctx, win, true); 499 500 /* wincon */ 501 val = readl(ctx->regs + WINCON(win)); 502 val &= ~WINCONx_ENWIN; 503 writel(val, ctx->regs + WINCON(win)); 504 505 val = readl(ctx->regs + DECON_UPDATE); 506 val |= DECON_UPDATE_STANDALONE_F; 507 writel(val, ctx->regs + DECON_UPDATE); 508 } 509 510 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 511 { 512 struct decon_context *ctx = crtc->ctx; 513 int i; 514 515 if (ctx->suspended) 516 return; 517 518 for (i = 0; i < WINDOWS_NR; i++) 519 decon_shadow_protect_win(ctx, i, false); 520 exynos_crtc_handle_event(crtc); 521 } 522 523 static void decon_init(struct decon_context *ctx) 524 { 525 u32 val; 526 527 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 528 529 val = VIDOUTCON0_DISP_IF_0_ON; 530 if (!ctx->i80_if) 531 val |= VIDOUTCON0_RGBIF; 532 writel(val, ctx->regs + VIDOUTCON0); 533 534 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 535 536 if (!ctx->i80_if) 537 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 538 } 539 540 static void decon_enable(struct exynos_drm_crtc *crtc) 541 { 542 struct decon_context *ctx = crtc->ctx; 543 544 if (!ctx->suspended) 545 return; 546 547 pm_runtime_get_sync(ctx->dev); 548 549 decon_init(ctx); 550 551 /* if vblank was enabled status, enable it again. */ 552 if (test_and_clear_bit(0, &ctx->irq_flags)) 553 decon_enable_vblank(ctx->crtc); 554 555 decon_commit(ctx->crtc); 556 557 ctx->suspended = false; 558 } 559 560 static void decon_disable(struct exynos_drm_crtc *crtc) 561 { 562 struct decon_context *ctx = crtc->ctx; 563 int i; 564 565 if (ctx->suspended) 566 return; 567 568 /* 569 * We need to make sure that all windows are disabled before we 570 * suspend that connector. Otherwise we might try to scan from 571 * a destroyed buffer later. 572 */ 573 for (i = 0; i < WINDOWS_NR; i++) 574 decon_disable_plane(crtc, &ctx->planes[i]); 575 576 pm_runtime_put_sync(ctx->dev); 577 578 ctx->suspended = true; 579 } 580 581 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 582 .enable = decon_enable, 583 .disable = decon_disable, 584 .enable_vblank = decon_enable_vblank, 585 .disable_vblank = decon_disable_vblank, 586 .atomic_begin = decon_atomic_begin, 587 .update_plane = decon_update_plane, 588 .disable_plane = decon_disable_plane, 589 .atomic_flush = decon_atomic_flush, 590 }; 591 592 593 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 594 { 595 struct decon_context *ctx = (struct decon_context *)dev_id; 596 u32 val, clear_bit; 597 598 val = readl(ctx->regs + VIDINTCON1); 599 600 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 601 if (val & clear_bit) 602 writel(clear_bit, ctx->regs + VIDINTCON1); 603 604 /* check the crtc is detached already from encoder */ 605 if (!ctx->drm_dev) 606 goto out; 607 608 if (!ctx->i80_if) { 609 drm_crtc_handle_vblank(&ctx->crtc->base); 610 611 /* set wait vsync event to zero and wake up queue. */ 612 if (atomic_read(&ctx->wait_vsync_event)) { 613 atomic_set(&ctx->wait_vsync_event, 0); 614 wake_up(&ctx->wait_vsync_queue); 615 } 616 } 617 out: 618 return IRQ_HANDLED; 619 } 620 621 static int decon_bind(struct device *dev, struct device *master, void *data) 622 { 623 struct decon_context *ctx = dev_get_drvdata(dev); 624 struct drm_device *drm_dev = data; 625 struct exynos_drm_plane *exynos_plane; 626 unsigned int i; 627 int ret; 628 629 ret = decon_ctx_initialize(ctx, drm_dev); 630 if (ret) { 631 DRM_ERROR("decon_ctx_initialize failed.\n"); 632 return ret; 633 } 634 635 for (i = 0; i < WINDOWS_NR; i++) { 636 ctx->configs[i].pixel_formats = decon_formats; 637 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); 638 ctx->configs[i].zpos = i; 639 ctx->configs[i].type = decon_win_types[i]; 640 641 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 642 &ctx->configs[i]); 643 if (ret) 644 return ret; 645 } 646 647 exynos_plane = &ctx->planes[DEFAULT_WIN]; 648 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 649 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx); 650 if (IS_ERR(ctx->crtc)) { 651 decon_ctx_remove(ctx); 652 return PTR_ERR(ctx->crtc); 653 } 654 655 if (ctx->encoder) 656 exynos_dpi_bind(drm_dev, ctx->encoder); 657 658 return 0; 659 660 } 661 662 static void decon_unbind(struct device *dev, struct device *master, 663 void *data) 664 { 665 struct decon_context *ctx = dev_get_drvdata(dev); 666 667 decon_disable(ctx->crtc); 668 669 if (ctx->encoder) 670 exynos_dpi_remove(ctx->encoder); 671 672 decon_ctx_remove(ctx); 673 } 674 675 static const struct component_ops decon_component_ops = { 676 .bind = decon_bind, 677 .unbind = decon_unbind, 678 }; 679 680 static int decon_probe(struct platform_device *pdev) 681 { 682 struct device *dev = &pdev->dev; 683 struct decon_context *ctx; 684 struct device_node *i80_if_timings; 685 struct resource *res; 686 int ret; 687 688 if (!dev->of_node) 689 return -ENODEV; 690 691 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 692 if (!ctx) 693 return -ENOMEM; 694 695 ctx->dev = dev; 696 ctx->suspended = true; 697 698 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 699 if (i80_if_timings) 700 ctx->i80_if = true; 701 of_node_put(i80_if_timings); 702 703 ctx->regs = of_iomap(dev->of_node, 0); 704 if (!ctx->regs) 705 return -ENOMEM; 706 707 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 708 if (IS_ERR(ctx->pclk)) { 709 dev_err(dev, "failed to get bus clock pclk\n"); 710 ret = PTR_ERR(ctx->pclk); 711 goto err_iounmap; 712 } 713 714 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 715 if (IS_ERR(ctx->aclk)) { 716 dev_err(dev, "failed to get bus clock aclk\n"); 717 ret = PTR_ERR(ctx->aclk); 718 goto err_iounmap; 719 } 720 721 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 722 if (IS_ERR(ctx->eclk)) { 723 dev_err(dev, "failed to get eclock\n"); 724 ret = PTR_ERR(ctx->eclk); 725 goto err_iounmap; 726 } 727 728 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 729 if (IS_ERR(ctx->vclk)) { 730 dev_err(dev, "failed to get vclock\n"); 731 ret = PTR_ERR(ctx->vclk); 732 goto err_iounmap; 733 } 734 735 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 736 ctx->i80_if ? "lcd_sys" : "vsync"); 737 if (!res) { 738 dev_err(dev, "irq request failed.\n"); 739 ret = -ENXIO; 740 goto err_iounmap; 741 } 742 743 ret = devm_request_irq(dev, res->start, decon_irq_handler, 744 0, "drm_decon", ctx); 745 if (ret) { 746 dev_err(dev, "irq request failed.\n"); 747 goto err_iounmap; 748 } 749 750 init_waitqueue_head(&ctx->wait_vsync_queue); 751 atomic_set(&ctx->wait_vsync_event, 0); 752 753 platform_set_drvdata(pdev, ctx); 754 755 ctx->encoder = exynos_dpi_probe(dev); 756 if (IS_ERR(ctx->encoder)) { 757 ret = PTR_ERR(ctx->encoder); 758 goto err_iounmap; 759 } 760 761 pm_runtime_enable(dev); 762 763 ret = component_add(dev, &decon_component_ops); 764 if (ret) 765 goto err_disable_pm_runtime; 766 767 return ret; 768 769 err_disable_pm_runtime: 770 pm_runtime_disable(dev); 771 772 err_iounmap: 773 iounmap(ctx->regs); 774 775 return ret; 776 } 777 778 static int decon_remove(struct platform_device *pdev) 779 { 780 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 781 782 pm_runtime_disable(&pdev->dev); 783 784 iounmap(ctx->regs); 785 786 component_del(&pdev->dev, &decon_component_ops); 787 788 return 0; 789 } 790 791 #ifdef CONFIG_PM 792 static int exynos7_decon_suspend(struct device *dev) 793 { 794 struct decon_context *ctx = dev_get_drvdata(dev); 795 796 clk_disable_unprepare(ctx->vclk); 797 clk_disable_unprepare(ctx->eclk); 798 clk_disable_unprepare(ctx->aclk); 799 clk_disable_unprepare(ctx->pclk); 800 801 return 0; 802 } 803 804 static int exynos7_decon_resume(struct device *dev) 805 { 806 struct decon_context *ctx = dev_get_drvdata(dev); 807 int ret; 808 809 ret = clk_prepare_enable(ctx->pclk); 810 if (ret < 0) { 811 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); 812 return ret; 813 } 814 815 ret = clk_prepare_enable(ctx->aclk); 816 if (ret < 0) { 817 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); 818 return ret; 819 } 820 821 ret = clk_prepare_enable(ctx->eclk); 822 if (ret < 0) { 823 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); 824 return ret; 825 } 826 827 ret = clk_prepare_enable(ctx->vclk); 828 if (ret < 0) { 829 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); 830 return ret; 831 } 832 833 return 0; 834 } 835 #endif 836 837 static const struct dev_pm_ops exynos7_decon_pm_ops = { 838 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume, 839 NULL) 840 }; 841 842 struct platform_driver decon_driver = { 843 .probe = decon_probe, 844 .remove = decon_remove, 845 .driver = { 846 .name = "exynos-decon", 847 .pm = &exynos7_decon_pm_ops, 848 .of_match_table = decon_driver_dt_match, 849 }, 850 }; 851