1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 29 #include "exynos_drm_crtc.h" 30 #include "exynos_drm_plane.h" 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fb.h" 33 #include "regs-decon7.h" 34 35 /* 36 * DECON stands for Display and Enhancement controller. 37 */ 38 39 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 40 41 #define WINDOWS_NR 2 42 43 struct decon_context { 44 struct device *dev; 45 struct drm_device *drm_dev; 46 struct exynos_drm_crtc *crtc; 47 struct exynos_drm_plane planes[WINDOWS_NR]; 48 struct exynos_drm_plane_config configs[WINDOWS_NR]; 49 struct clk *pclk; 50 struct clk *aclk; 51 struct clk *eclk; 52 struct clk *vclk; 53 void __iomem *regs; 54 unsigned long irq_flags; 55 bool i80_if; 56 bool suspended; 57 wait_queue_head_t wait_vsync_queue; 58 atomic_t wait_vsync_event; 59 60 struct drm_encoder *encoder; 61 }; 62 63 static const struct of_device_id decon_driver_dt_match[] = { 64 {.compatible = "samsung,exynos7-decon"}, 65 {}, 66 }; 67 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 68 69 static const uint32_t decon_formats[] = { 70 DRM_FORMAT_RGB565, 71 DRM_FORMAT_XRGB8888, 72 DRM_FORMAT_XBGR8888, 73 DRM_FORMAT_RGBX8888, 74 DRM_FORMAT_BGRX8888, 75 DRM_FORMAT_ARGB8888, 76 DRM_FORMAT_ABGR8888, 77 DRM_FORMAT_RGBA8888, 78 DRM_FORMAT_BGRA8888, 79 }; 80 81 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 82 DRM_PLANE_TYPE_PRIMARY, 83 DRM_PLANE_TYPE_CURSOR, 84 }; 85 86 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 87 { 88 struct decon_context *ctx = crtc->ctx; 89 90 if (ctx->suspended) 91 return; 92 93 atomic_set(&ctx->wait_vsync_event, 1); 94 95 /* 96 * wait for DECON to signal VSYNC interrupt or return after 97 * timeout which is set to 50ms (refresh rate of 20). 98 */ 99 if (!wait_event_timeout(ctx->wait_vsync_queue, 100 !atomic_read(&ctx->wait_vsync_event), 101 HZ/20)) 102 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n"); 103 } 104 105 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 106 { 107 struct decon_context *ctx = crtc->ctx; 108 unsigned int win, ch_enabled = 0; 109 110 /* Check if any channel is enabled. */ 111 for (win = 0; win < WINDOWS_NR; win++) { 112 u32 val = readl(ctx->regs + WINCON(win)); 113 114 if (val & WINCONx_ENWIN) { 115 val &= ~WINCONx_ENWIN; 116 writel(val, ctx->regs + WINCON(win)); 117 ch_enabled = 1; 118 } 119 } 120 121 /* Wait for vsync, as disable channel takes effect at next vsync */ 122 if (ch_enabled) 123 decon_wait_for_vblank(ctx->crtc); 124 } 125 126 static int decon_ctx_initialize(struct decon_context *ctx, 127 struct drm_device *drm_dev) 128 { 129 ctx->drm_dev = drm_dev; 130 131 decon_clear_channels(ctx->crtc); 132 133 return exynos_drm_register_dma(drm_dev, ctx->dev); 134 } 135 136 static void decon_ctx_remove(struct decon_context *ctx) 137 { 138 /* detach this sub driver from iommu mapping if supported. */ 139 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev); 140 } 141 142 static u32 decon_calc_clkdiv(struct decon_context *ctx, 143 const struct drm_display_mode *mode) 144 { 145 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 146 u32 clkdiv; 147 148 /* Find the clock divider value that gets us closest to ideal_clk */ 149 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 150 151 return (clkdiv < 0x100) ? clkdiv : 0xff; 152 } 153 154 static void decon_commit(struct exynos_drm_crtc *crtc) 155 { 156 struct decon_context *ctx = crtc->ctx; 157 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 158 u32 val, clkdiv; 159 160 if (ctx->suspended) 161 return; 162 163 /* nothing to do if we haven't set the mode yet */ 164 if (mode->htotal == 0 || mode->vtotal == 0) 165 return; 166 167 if (!ctx->i80_if) { 168 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 169 /* setup vertical timing values. */ 170 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 171 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 172 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 173 174 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 175 writel(val, ctx->regs + VIDTCON0); 176 177 val = VIDTCON1_VSPW(vsync_len - 1); 178 writel(val, ctx->regs + VIDTCON1); 179 180 /* setup horizontal timing values. */ 181 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 182 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 183 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 184 185 /* setup horizontal timing values. */ 186 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 187 writel(val, ctx->regs + VIDTCON2); 188 189 val = VIDTCON3_HSPW(hsync_len - 1); 190 writel(val, ctx->regs + VIDTCON3); 191 } 192 193 /* setup horizontal and vertical display size. */ 194 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 195 VIDTCON4_HOZVAL(mode->hdisplay - 1); 196 writel(val, ctx->regs + VIDTCON4); 197 198 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 199 200 /* 201 * fields of register with prefix '_F' would be updated 202 * at vsync(same as dma start) 203 */ 204 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 205 writel(val, ctx->regs + VIDCON0); 206 207 clkdiv = decon_calc_clkdiv(ctx, mode); 208 if (clkdiv > 1) { 209 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 210 writel(val, ctx->regs + VCLKCON1); 211 writel(val, ctx->regs + VCLKCON2); 212 } 213 214 val = readl(ctx->regs + DECON_UPDATE); 215 val |= DECON_UPDATE_STANDALONE_F; 216 writel(val, ctx->regs + DECON_UPDATE); 217 } 218 219 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 220 { 221 struct decon_context *ctx = crtc->ctx; 222 u32 val; 223 224 if (ctx->suspended) 225 return -EPERM; 226 227 if (!test_and_set_bit(0, &ctx->irq_flags)) { 228 val = readl(ctx->regs + VIDINTCON0); 229 230 val |= VIDINTCON0_INT_ENABLE; 231 232 if (!ctx->i80_if) { 233 val |= VIDINTCON0_INT_FRAME; 234 val &= ~VIDINTCON0_FRAMESEL0_MASK; 235 val |= VIDINTCON0_FRAMESEL0_VSYNC; 236 } 237 238 writel(val, ctx->regs + VIDINTCON0); 239 } 240 241 return 0; 242 } 243 244 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 245 { 246 struct decon_context *ctx = crtc->ctx; 247 u32 val; 248 249 if (ctx->suspended) 250 return; 251 252 if (test_and_clear_bit(0, &ctx->irq_flags)) { 253 val = readl(ctx->regs + VIDINTCON0); 254 255 val &= ~VIDINTCON0_INT_ENABLE; 256 if (!ctx->i80_if) 257 val &= ~VIDINTCON0_INT_FRAME; 258 259 writel(val, ctx->regs + VIDINTCON0); 260 } 261 } 262 263 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 264 struct drm_framebuffer *fb) 265 { 266 unsigned long val; 267 int padding; 268 269 val = readl(ctx->regs + WINCON(win)); 270 val &= ~WINCONx_BPPMODE_MASK; 271 272 switch (fb->format->format) { 273 case DRM_FORMAT_RGB565: 274 val |= WINCONx_BPPMODE_16BPP_565; 275 val |= WINCONx_BURSTLEN_16WORD; 276 break; 277 case DRM_FORMAT_XRGB8888: 278 val |= WINCONx_BPPMODE_24BPP_xRGB; 279 val |= WINCONx_BURSTLEN_16WORD; 280 break; 281 case DRM_FORMAT_XBGR8888: 282 val |= WINCONx_BPPMODE_24BPP_xBGR; 283 val |= WINCONx_BURSTLEN_16WORD; 284 break; 285 case DRM_FORMAT_RGBX8888: 286 val |= WINCONx_BPPMODE_24BPP_RGBx; 287 val |= WINCONx_BURSTLEN_16WORD; 288 break; 289 case DRM_FORMAT_BGRX8888: 290 val |= WINCONx_BPPMODE_24BPP_BGRx; 291 val |= WINCONx_BURSTLEN_16WORD; 292 break; 293 case DRM_FORMAT_ARGB8888: 294 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 295 WINCONx_ALPHA_SEL; 296 val |= WINCONx_BURSTLEN_16WORD; 297 break; 298 case DRM_FORMAT_ABGR8888: 299 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 300 WINCONx_ALPHA_SEL; 301 val |= WINCONx_BURSTLEN_16WORD; 302 break; 303 case DRM_FORMAT_RGBA8888: 304 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 305 WINCONx_ALPHA_SEL; 306 val |= WINCONx_BURSTLEN_16WORD; 307 break; 308 case DRM_FORMAT_BGRA8888: 309 default: 310 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 311 WINCONx_ALPHA_SEL; 312 val |= WINCONx_BURSTLEN_16WORD; 313 break; 314 } 315 316 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %d\n", fb->format->cpp[0]); 317 318 /* 319 * In case of exynos, setting dma-burst to 16Word causes permanent 320 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 321 * switching which is based on plane size is not recommended as 322 * plane size varies a lot towards the end of the screen and rapid 323 * movement causes unstable DMA which results into iommu crash/tear. 324 */ 325 326 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width; 327 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 328 val &= ~WINCONx_BURSTLEN_MASK; 329 val |= WINCONx_BURSTLEN_8WORD; 330 } 331 332 writel(val, ctx->regs + WINCON(win)); 333 } 334 335 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 336 { 337 unsigned int keycon0 = 0, keycon1 = 0; 338 339 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 340 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 341 342 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 343 344 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 345 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 346 } 347 348 /** 349 * shadow_protect_win() - disable updating values from shadow registers at vsync 350 * 351 * @win: window to protect registers for 352 * @protect: 1 to protect (disable updates) 353 */ 354 static void decon_shadow_protect_win(struct decon_context *ctx, 355 unsigned int win, bool protect) 356 { 357 u32 bits, val; 358 359 bits = SHADOWCON_WINx_PROTECT(win); 360 361 val = readl(ctx->regs + SHADOWCON); 362 if (protect) 363 val |= bits; 364 else 365 val &= ~bits; 366 writel(val, ctx->regs + SHADOWCON); 367 } 368 369 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 370 { 371 struct decon_context *ctx = crtc->ctx; 372 int i; 373 374 if (ctx->suspended) 375 return; 376 377 for (i = 0; i < WINDOWS_NR; i++) 378 decon_shadow_protect_win(ctx, i, true); 379 } 380 381 static void decon_update_plane(struct exynos_drm_crtc *crtc, 382 struct exynos_drm_plane *plane) 383 { 384 struct exynos_drm_plane_state *state = 385 to_exynos_plane_state(plane->base.state); 386 struct decon_context *ctx = crtc->ctx; 387 struct drm_framebuffer *fb = state->base.fb; 388 int padding; 389 unsigned long val, alpha; 390 unsigned int last_x; 391 unsigned int last_y; 392 unsigned int win = plane->index; 393 unsigned int cpp = fb->format->cpp[0]; 394 unsigned int pitch = fb->pitches[0]; 395 396 if (ctx->suspended) 397 return; 398 399 /* 400 * SHADOWCON/PRTCON register is used for enabling timing. 401 * 402 * for example, once only width value of a register is set, 403 * if the dma is started then decon hardware could malfunction so 404 * with protect window setting, the register fields with prefix '_F' 405 * wouldn't be updated at vsync also but updated once unprotect window 406 * is set. 407 */ 408 409 /* buffer start address */ 410 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 411 writel(val, ctx->regs + VIDW_BUF_START(win)); 412 413 padding = (pitch / cpp) - fb->width; 414 415 /* buffer size */ 416 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 417 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 418 419 /* offset from the start of the buffer to read */ 420 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); 421 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); 422 423 DRM_DEV_DEBUG_KMS(ctx->dev, "start addr = 0x%lx\n", 424 (unsigned long)val); 425 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n", 426 state->crtc.w, state->crtc.h); 427 428 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 429 VIDOSDxA_TOPLEFT_Y(state->crtc.y); 430 writel(val, ctx->regs + VIDOSD_A(win)); 431 432 last_x = state->crtc.x + state->crtc.w; 433 if (last_x) 434 last_x--; 435 last_y = state->crtc.y + state->crtc.h; 436 if (last_y) 437 last_y--; 438 439 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 440 441 writel(val, ctx->regs + VIDOSD_B(win)); 442 443 DRM_DEV_DEBUG_KMS(ctx->dev, "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 444 state->crtc.x, state->crtc.y, last_x, last_y); 445 446 /* OSD alpha */ 447 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 448 VIDOSDxC_ALPHA0_G_F(0x0) | 449 VIDOSDxC_ALPHA0_B_F(0x0); 450 451 writel(alpha, ctx->regs + VIDOSD_C(win)); 452 453 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 454 VIDOSDxD_ALPHA1_G_F(0xff) | 455 VIDOSDxD_ALPHA1_B_F(0xff); 456 457 writel(alpha, ctx->regs + VIDOSD_D(win)); 458 459 decon_win_set_pixfmt(ctx, win, fb); 460 461 /* hardware window 0 doesn't support color key. */ 462 if (win != 0) 463 decon_win_set_colkey(ctx, win); 464 465 /* wincon */ 466 val = readl(ctx->regs + WINCON(win)); 467 val |= WINCONx_TRIPLE_BUF_MODE; 468 val |= WINCONx_ENWIN; 469 writel(val, ctx->regs + WINCON(win)); 470 471 /* Enable DMA channel and unprotect windows */ 472 decon_shadow_protect_win(ctx, win, false); 473 474 val = readl(ctx->regs + DECON_UPDATE); 475 val |= DECON_UPDATE_STANDALONE_F; 476 writel(val, ctx->regs + DECON_UPDATE); 477 } 478 479 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 480 struct exynos_drm_plane *plane) 481 { 482 struct decon_context *ctx = crtc->ctx; 483 unsigned int win = plane->index; 484 u32 val; 485 486 if (ctx->suspended) 487 return; 488 489 /* protect windows */ 490 decon_shadow_protect_win(ctx, win, true); 491 492 /* wincon */ 493 val = readl(ctx->regs + WINCON(win)); 494 val &= ~WINCONx_ENWIN; 495 writel(val, ctx->regs + WINCON(win)); 496 497 val = readl(ctx->regs + DECON_UPDATE); 498 val |= DECON_UPDATE_STANDALONE_F; 499 writel(val, ctx->regs + DECON_UPDATE); 500 } 501 502 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 503 { 504 struct decon_context *ctx = crtc->ctx; 505 int i; 506 507 if (ctx->suspended) 508 return; 509 510 for (i = 0; i < WINDOWS_NR; i++) 511 decon_shadow_protect_win(ctx, i, false); 512 exynos_crtc_handle_event(crtc); 513 } 514 515 static void decon_init(struct decon_context *ctx) 516 { 517 u32 val; 518 519 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 520 521 val = VIDOUTCON0_DISP_IF_0_ON; 522 if (!ctx->i80_if) 523 val |= VIDOUTCON0_RGBIF; 524 writel(val, ctx->regs + VIDOUTCON0); 525 526 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 527 528 if (!ctx->i80_if) 529 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 530 } 531 532 static void decon_enable(struct exynos_drm_crtc *crtc) 533 { 534 struct decon_context *ctx = crtc->ctx; 535 536 if (!ctx->suspended) 537 return; 538 539 pm_runtime_get_sync(ctx->dev); 540 541 decon_init(ctx); 542 543 /* if vblank was enabled status, enable it again. */ 544 if (test_and_clear_bit(0, &ctx->irq_flags)) 545 decon_enable_vblank(ctx->crtc); 546 547 decon_commit(ctx->crtc); 548 549 ctx->suspended = false; 550 } 551 552 static void decon_disable(struct exynos_drm_crtc *crtc) 553 { 554 struct decon_context *ctx = crtc->ctx; 555 int i; 556 557 if (ctx->suspended) 558 return; 559 560 /* 561 * We need to make sure that all windows are disabled before we 562 * suspend that connector. Otherwise we might try to scan from 563 * a destroyed buffer later. 564 */ 565 for (i = 0; i < WINDOWS_NR; i++) 566 decon_disable_plane(crtc, &ctx->planes[i]); 567 568 pm_runtime_put_sync(ctx->dev); 569 570 ctx->suspended = true; 571 } 572 573 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 574 .enable = decon_enable, 575 .disable = decon_disable, 576 .enable_vblank = decon_enable_vblank, 577 .disable_vblank = decon_disable_vblank, 578 .atomic_begin = decon_atomic_begin, 579 .update_plane = decon_update_plane, 580 .disable_plane = decon_disable_plane, 581 .atomic_flush = decon_atomic_flush, 582 }; 583 584 585 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 586 { 587 struct decon_context *ctx = (struct decon_context *)dev_id; 588 u32 val, clear_bit; 589 590 val = readl(ctx->regs + VIDINTCON1); 591 592 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 593 if (val & clear_bit) 594 writel(clear_bit, ctx->regs + VIDINTCON1); 595 596 /* check the crtc is detached already from encoder */ 597 if (!ctx->drm_dev) 598 goto out; 599 600 if (!ctx->i80_if) { 601 drm_crtc_handle_vblank(&ctx->crtc->base); 602 603 /* set wait vsync event to zero and wake up queue. */ 604 if (atomic_read(&ctx->wait_vsync_event)) { 605 atomic_set(&ctx->wait_vsync_event, 0); 606 wake_up(&ctx->wait_vsync_queue); 607 } 608 } 609 out: 610 return IRQ_HANDLED; 611 } 612 613 static int decon_bind(struct device *dev, struct device *master, void *data) 614 { 615 struct decon_context *ctx = dev_get_drvdata(dev); 616 struct drm_device *drm_dev = data; 617 struct exynos_drm_plane *exynos_plane; 618 unsigned int i; 619 int ret; 620 621 ret = decon_ctx_initialize(ctx, drm_dev); 622 if (ret) { 623 DRM_DEV_ERROR(dev, "decon_ctx_initialize failed.\n"); 624 return ret; 625 } 626 627 for (i = 0; i < WINDOWS_NR; i++) { 628 ctx->configs[i].pixel_formats = decon_formats; 629 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); 630 ctx->configs[i].zpos = i; 631 ctx->configs[i].type = decon_win_types[i]; 632 633 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 634 &ctx->configs[i]); 635 if (ret) 636 return ret; 637 } 638 639 exynos_plane = &ctx->planes[DEFAULT_WIN]; 640 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 641 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx); 642 if (IS_ERR(ctx->crtc)) { 643 decon_ctx_remove(ctx); 644 return PTR_ERR(ctx->crtc); 645 } 646 647 if (ctx->encoder) 648 exynos_dpi_bind(drm_dev, ctx->encoder); 649 650 return 0; 651 652 } 653 654 static void decon_unbind(struct device *dev, struct device *master, 655 void *data) 656 { 657 struct decon_context *ctx = dev_get_drvdata(dev); 658 659 decon_disable(ctx->crtc); 660 661 if (ctx->encoder) 662 exynos_dpi_remove(ctx->encoder); 663 664 decon_ctx_remove(ctx); 665 } 666 667 static const struct component_ops decon_component_ops = { 668 .bind = decon_bind, 669 .unbind = decon_unbind, 670 }; 671 672 static int decon_probe(struct platform_device *pdev) 673 { 674 struct device *dev = &pdev->dev; 675 struct decon_context *ctx; 676 struct device_node *i80_if_timings; 677 struct resource *res; 678 int ret; 679 680 if (!dev->of_node) 681 return -ENODEV; 682 683 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 684 if (!ctx) 685 return -ENOMEM; 686 687 ctx->dev = dev; 688 ctx->suspended = true; 689 690 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 691 if (i80_if_timings) 692 ctx->i80_if = true; 693 of_node_put(i80_if_timings); 694 695 ctx->regs = of_iomap(dev->of_node, 0); 696 if (!ctx->regs) 697 return -ENOMEM; 698 699 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 700 if (IS_ERR(ctx->pclk)) { 701 dev_err(dev, "failed to get bus clock pclk\n"); 702 ret = PTR_ERR(ctx->pclk); 703 goto err_iounmap; 704 } 705 706 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 707 if (IS_ERR(ctx->aclk)) { 708 dev_err(dev, "failed to get bus clock aclk\n"); 709 ret = PTR_ERR(ctx->aclk); 710 goto err_iounmap; 711 } 712 713 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 714 if (IS_ERR(ctx->eclk)) { 715 dev_err(dev, "failed to get eclock\n"); 716 ret = PTR_ERR(ctx->eclk); 717 goto err_iounmap; 718 } 719 720 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 721 if (IS_ERR(ctx->vclk)) { 722 dev_err(dev, "failed to get vclock\n"); 723 ret = PTR_ERR(ctx->vclk); 724 goto err_iounmap; 725 } 726 727 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 728 ctx->i80_if ? "lcd_sys" : "vsync"); 729 if (!res) { 730 dev_err(dev, "irq request failed.\n"); 731 ret = -ENXIO; 732 goto err_iounmap; 733 } 734 735 ret = devm_request_irq(dev, res->start, decon_irq_handler, 736 0, "drm_decon", ctx); 737 if (ret) { 738 dev_err(dev, "irq request failed.\n"); 739 goto err_iounmap; 740 } 741 742 init_waitqueue_head(&ctx->wait_vsync_queue); 743 atomic_set(&ctx->wait_vsync_event, 0); 744 745 platform_set_drvdata(pdev, ctx); 746 747 ctx->encoder = exynos_dpi_probe(dev); 748 if (IS_ERR(ctx->encoder)) { 749 ret = PTR_ERR(ctx->encoder); 750 goto err_iounmap; 751 } 752 753 pm_runtime_enable(dev); 754 755 ret = component_add(dev, &decon_component_ops); 756 if (ret) 757 goto err_disable_pm_runtime; 758 759 return ret; 760 761 err_disable_pm_runtime: 762 pm_runtime_disable(dev); 763 764 err_iounmap: 765 iounmap(ctx->regs); 766 767 return ret; 768 } 769 770 static int decon_remove(struct platform_device *pdev) 771 { 772 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 773 774 pm_runtime_disable(&pdev->dev); 775 776 iounmap(ctx->regs); 777 778 component_del(&pdev->dev, &decon_component_ops); 779 780 return 0; 781 } 782 783 #ifdef CONFIG_PM 784 static int exynos7_decon_suspend(struct device *dev) 785 { 786 struct decon_context *ctx = dev_get_drvdata(dev); 787 788 clk_disable_unprepare(ctx->vclk); 789 clk_disable_unprepare(ctx->eclk); 790 clk_disable_unprepare(ctx->aclk); 791 clk_disable_unprepare(ctx->pclk); 792 793 return 0; 794 } 795 796 static int exynos7_decon_resume(struct device *dev) 797 { 798 struct decon_context *ctx = dev_get_drvdata(dev); 799 int ret; 800 801 ret = clk_prepare_enable(ctx->pclk); 802 if (ret < 0) { 803 DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n", 804 ret); 805 return ret; 806 } 807 808 ret = clk_prepare_enable(ctx->aclk); 809 if (ret < 0) { 810 DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n", 811 ret); 812 return ret; 813 } 814 815 ret = clk_prepare_enable(ctx->eclk); 816 if (ret < 0) { 817 DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n", 818 ret); 819 return ret; 820 } 821 822 ret = clk_prepare_enable(ctx->vclk); 823 if (ret < 0) { 824 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n", 825 ret); 826 return ret; 827 } 828 829 return 0; 830 } 831 #endif 832 833 static const struct dev_pm_ops exynos7_decon_pm_ops = { 834 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume, 835 NULL) 836 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 837 pm_runtime_force_resume) 838 }; 839 840 struct platform_driver decon_driver = { 841 .probe = decon_probe, 842 .remove = decon_remove, 843 .driver = { 844 .name = "exynos-decon", 845 .pm = &exynos7_decon_pm_ops, 846 .of_match_table = decon_driver_dt_match, 847 }, 848 }; 849