1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c 2 * 3 * Copyright (C) 2014 Samsung Electronics Co.Ltd 4 * Authors: 5 * Akshu Agarwal <akshua@gmail.com> 6 * Ajay Kumar <ajaykumar.rs@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 #include <drm/drmP.h> 15 #include <drm/exynos_drm.h> 16 17 #include <linux/clk.h> 18 #include <linux/component.h> 19 #include <linux/kernel.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #include <video/of_display_timing.h> 27 #include <video/of_videomode.h> 28 29 #include "exynos_drm_crtc.h" 30 #include "exynos_drm_plane.h" 31 #include "exynos_drm_drv.h" 32 #include "exynos_drm_fb.h" 33 #include "exynos_drm_iommu.h" 34 #include "regs-decon7.h" 35 36 /* 37 * DECON stands for Display and Enhancement controller. 38 */ 39 40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 41 42 #define WINDOWS_NR 2 43 44 struct decon_context { 45 struct device *dev; 46 struct drm_device *drm_dev; 47 struct exynos_drm_crtc *crtc; 48 struct exynos_drm_plane planes[WINDOWS_NR]; 49 struct exynos_drm_plane_config configs[WINDOWS_NR]; 50 struct clk *pclk; 51 struct clk *aclk; 52 struct clk *eclk; 53 struct clk *vclk; 54 void __iomem *regs; 55 unsigned long irq_flags; 56 bool i80_if; 57 bool suspended; 58 wait_queue_head_t wait_vsync_queue; 59 atomic_t wait_vsync_event; 60 61 struct drm_encoder *encoder; 62 }; 63 64 static const struct of_device_id decon_driver_dt_match[] = { 65 {.compatible = "samsung,exynos7-decon"}, 66 {}, 67 }; 68 MODULE_DEVICE_TABLE(of, decon_driver_dt_match); 69 70 static const uint32_t decon_formats[] = { 71 DRM_FORMAT_RGB565, 72 DRM_FORMAT_XRGB8888, 73 DRM_FORMAT_XBGR8888, 74 DRM_FORMAT_RGBX8888, 75 DRM_FORMAT_BGRX8888, 76 DRM_FORMAT_ARGB8888, 77 DRM_FORMAT_ABGR8888, 78 DRM_FORMAT_RGBA8888, 79 DRM_FORMAT_BGRA8888, 80 }; 81 82 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 83 DRM_PLANE_TYPE_PRIMARY, 84 DRM_PLANE_TYPE_CURSOR, 85 }; 86 87 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc) 88 { 89 struct decon_context *ctx = crtc->ctx; 90 91 if (ctx->suspended) 92 return; 93 94 atomic_set(&ctx->wait_vsync_event, 1); 95 96 /* 97 * wait for DECON to signal VSYNC interrupt or return after 98 * timeout which is set to 50ms (refresh rate of 20). 99 */ 100 if (!wait_event_timeout(ctx->wait_vsync_queue, 101 !atomic_read(&ctx->wait_vsync_event), 102 HZ/20)) 103 DRM_DEBUG_KMS("vblank wait timed out.\n"); 104 } 105 106 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 107 { 108 struct decon_context *ctx = crtc->ctx; 109 unsigned int win, ch_enabled = 0; 110 111 DRM_DEBUG_KMS("%s\n", __FILE__); 112 113 /* Check if any channel is enabled. */ 114 for (win = 0; win < WINDOWS_NR; win++) { 115 u32 val = readl(ctx->regs + WINCON(win)); 116 117 if (val & WINCONx_ENWIN) { 118 val &= ~WINCONx_ENWIN; 119 writel(val, ctx->regs + WINCON(win)); 120 ch_enabled = 1; 121 } 122 } 123 124 /* Wait for vsync, as disable channel takes effect at next vsync */ 125 if (ch_enabled) 126 decon_wait_for_vblank(ctx->crtc); 127 } 128 129 static int decon_ctx_initialize(struct decon_context *ctx, 130 struct drm_device *drm_dev) 131 { 132 ctx->drm_dev = drm_dev; 133 134 decon_clear_channels(ctx->crtc); 135 136 return drm_iommu_attach_device(drm_dev, ctx->dev); 137 } 138 139 static void decon_ctx_remove(struct decon_context *ctx) 140 { 141 /* detach this sub driver from iommu mapping if supported. */ 142 drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 143 } 144 145 static u32 decon_calc_clkdiv(struct decon_context *ctx, 146 const struct drm_display_mode *mode) 147 { 148 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; 149 u32 clkdiv; 150 151 /* Find the clock divider value that gets us closest to ideal_clk */ 152 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk); 153 154 return (clkdiv < 0x100) ? clkdiv : 0xff; 155 } 156 157 static void decon_commit(struct exynos_drm_crtc *crtc) 158 { 159 struct decon_context *ctx = crtc->ctx; 160 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; 161 u32 val, clkdiv; 162 163 if (ctx->suspended) 164 return; 165 166 /* nothing to do if we haven't set the mode yet */ 167 if (mode->htotal == 0 || mode->vtotal == 0) 168 return; 169 170 if (!ctx->i80_if) { 171 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd; 172 /* setup vertical timing values. */ 173 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 174 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end; 175 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay; 176 177 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1); 178 writel(val, ctx->regs + VIDTCON0); 179 180 val = VIDTCON1_VSPW(vsync_len - 1); 181 writel(val, ctx->regs + VIDTCON1); 182 183 /* setup horizontal timing values. */ 184 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 185 hbpd = mode->crtc_htotal - mode->crtc_hsync_end; 186 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay; 187 188 /* setup horizontal timing values. */ 189 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1); 190 writel(val, ctx->regs + VIDTCON2); 191 192 val = VIDTCON3_HSPW(hsync_len - 1); 193 writel(val, ctx->regs + VIDTCON3); 194 } 195 196 /* setup horizontal and vertical display size. */ 197 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) | 198 VIDTCON4_HOZVAL(mode->hdisplay - 1); 199 writel(val, ctx->regs + VIDTCON4); 200 201 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); 202 203 /* 204 * fields of register with prefix '_F' would be updated 205 * at vsync(same as dma start) 206 */ 207 val = VIDCON0_ENVID | VIDCON0_ENVID_F; 208 writel(val, ctx->regs + VIDCON0); 209 210 clkdiv = decon_calc_clkdiv(ctx, mode); 211 if (clkdiv > 1) { 212 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1); 213 writel(val, ctx->regs + VCLKCON1); 214 writel(val, ctx->regs + VCLKCON2); 215 } 216 217 val = readl(ctx->regs + DECON_UPDATE); 218 val |= DECON_UPDATE_STANDALONE_F; 219 writel(val, ctx->regs + DECON_UPDATE); 220 } 221 222 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 223 { 224 struct decon_context *ctx = crtc->ctx; 225 u32 val; 226 227 if (ctx->suspended) 228 return -EPERM; 229 230 if (!test_and_set_bit(0, &ctx->irq_flags)) { 231 val = readl(ctx->regs + VIDINTCON0); 232 233 val |= VIDINTCON0_INT_ENABLE; 234 235 if (!ctx->i80_if) { 236 val |= VIDINTCON0_INT_FRAME; 237 val &= ~VIDINTCON0_FRAMESEL0_MASK; 238 val |= VIDINTCON0_FRAMESEL0_VSYNC; 239 } 240 241 writel(val, ctx->regs + VIDINTCON0); 242 } 243 244 return 0; 245 } 246 247 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 248 { 249 struct decon_context *ctx = crtc->ctx; 250 u32 val; 251 252 if (ctx->suspended) 253 return; 254 255 if (test_and_clear_bit(0, &ctx->irq_flags)) { 256 val = readl(ctx->regs + VIDINTCON0); 257 258 val &= ~VIDINTCON0_INT_ENABLE; 259 if (!ctx->i80_if) 260 val &= ~VIDINTCON0_INT_FRAME; 261 262 writel(val, ctx->regs + VIDINTCON0); 263 } 264 } 265 266 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 267 struct drm_framebuffer *fb) 268 { 269 unsigned long val; 270 int padding; 271 272 val = readl(ctx->regs + WINCON(win)); 273 val &= ~WINCONx_BPPMODE_MASK; 274 275 switch (fb->format->format) { 276 case DRM_FORMAT_RGB565: 277 val |= WINCONx_BPPMODE_16BPP_565; 278 val |= WINCONx_BURSTLEN_16WORD; 279 break; 280 case DRM_FORMAT_XRGB8888: 281 val |= WINCONx_BPPMODE_24BPP_xRGB; 282 val |= WINCONx_BURSTLEN_16WORD; 283 break; 284 case DRM_FORMAT_XBGR8888: 285 val |= WINCONx_BPPMODE_24BPP_xBGR; 286 val |= WINCONx_BURSTLEN_16WORD; 287 break; 288 case DRM_FORMAT_RGBX8888: 289 val |= WINCONx_BPPMODE_24BPP_RGBx; 290 val |= WINCONx_BURSTLEN_16WORD; 291 break; 292 case DRM_FORMAT_BGRX8888: 293 val |= WINCONx_BPPMODE_24BPP_BGRx; 294 val |= WINCONx_BURSTLEN_16WORD; 295 break; 296 case DRM_FORMAT_ARGB8888: 297 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX | 298 WINCONx_ALPHA_SEL; 299 val |= WINCONx_BURSTLEN_16WORD; 300 break; 301 case DRM_FORMAT_ABGR8888: 302 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX | 303 WINCONx_ALPHA_SEL; 304 val |= WINCONx_BURSTLEN_16WORD; 305 break; 306 case DRM_FORMAT_RGBA8888: 307 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX | 308 WINCONx_ALPHA_SEL; 309 val |= WINCONx_BURSTLEN_16WORD; 310 break; 311 case DRM_FORMAT_BGRA8888: 312 default: 313 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX | 314 WINCONx_ALPHA_SEL; 315 val |= WINCONx_BURSTLEN_16WORD; 316 break; 317 } 318 319 DRM_DEBUG_KMS("cpp = %d\n", fb->format->cpp[0]); 320 321 /* 322 * In case of exynos, setting dma-burst to 16Word causes permanent 323 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 324 * switching which is based on plane size is not recommended as 325 * plane size varies a lot towards the end of the screen and rapid 326 * movement causes unstable DMA which results into iommu crash/tear. 327 */ 328 329 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width; 330 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) { 331 val &= ~WINCONx_BURSTLEN_MASK; 332 val |= WINCONx_BURSTLEN_8WORD; 333 } 334 335 writel(val, ctx->regs + WINCON(win)); 336 } 337 338 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win) 339 { 340 unsigned int keycon0 = 0, keycon1 = 0; 341 342 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | 343 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); 344 345 keycon1 = WxKEYCON1_COLVAL(0xffffffff); 346 347 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); 348 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); 349 } 350 351 /** 352 * shadow_protect_win() - disable updating values from shadow registers at vsync 353 * 354 * @win: window to protect registers for 355 * @protect: 1 to protect (disable updates) 356 */ 357 static void decon_shadow_protect_win(struct decon_context *ctx, 358 unsigned int win, bool protect) 359 { 360 u32 bits, val; 361 362 bits = SHADOWCON_WINx_PROTECT(win); 363 364 val = readl(ctx->regs + SHADOWCON); 365 if (protect) 366 val |= bits; 367 else 368 val &= ~bits; 369 writel(val, ctx->regs + SHADOWCON); 370 } 371 372 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 373 { 374 struct decon_context *ctx = crtc->ctx; 375 int i; 376 377 if (ctx->suspended) 378 return; 379 380 for (i = 0; i < WINDOWS_NR; i++) 381 decon_shadow_protect_win(ctx, i, true); 382 } 383 384 static void decon_update_plane(struct exynos_drm_crtc *crtc, 385 struct exynos_drm_plane *plane) 386 { 387 struct exynos_drm_plane_state *state = 388 to_exynos_plane_state(plane->base.state); 389 struct decon_context *ctx = crtc->ctx; 390 struct drm_framebuffer *fb = state->base.fb; 391 int padding; 392 unsigned long val, alpha; 393 unsigned int last_x; 394 unsigned int last_y; 395 unsigned int win = plane->index; 396 unsigned int cpp = fb->format->cpp[0]; 397 unsigned int pitch = fb->pitches[0]; 398 399 if (ctx->suspended) 400 return; 401 402 /* 403 * SHADOWCON/PRTCON register is used for enabling timing. 404 * 405 * for example, once only width value of a register is set, 406 * if the dma is started then decon hardware could malfunction so 407 * with protect window setting, the register fields with prefix '_F' 408 * wouldn't be updated at vsync also but updated once unprotect window 409 * is set. 410 */ 411 412 /* buffer start address */ 413 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0); 414 writel(val, ctx->regs + VIDW_BUF_START(win)); 415 416 padding = (pitch / cpp) - fb->width; 417 418 /* buffer size */ 419 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); 420 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win)); 421 422 /* offset from the start of the buffer to read */ 423 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win)); 424 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win)); 425 426 DRM_DEBUG_KMS("start addr = 0x%lx\n", 427 (unsigned long)val); 428 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", 429 state->crtc.w, state->crtc.h); 430 431 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) | 432 VIDOSDxA_TOPLEFT_Y(state->crtc.y); 433 writel(val, ctx->regs + VIDOSD_A(win)); 434 435 last_x = state->crtc.x + state->crtc.w; 436 if (last_x) 437 last_x--; 438 last_y = state->crtc.y + state->crtc.h; 439 if (last_y) 440 last_y--; 441 442 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y); 443 444 writel(val, ctx->regs + VIDOSD_B(win)); 445 446 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", 447 state->crtc.x, state->crtc.y, last_x, last_y); 448 449 /* OSD alpha */ 450 alpha = VIDOSDxC_ALPHA0_R_F(0x0) | 451 VIDOSDxC_ALPHA0_G_F(0x0) | 452 VIDOSDxC_ALPHA0_B_F(0x0); 453 454 writel(alpha, ctx->regs + VIDOSD_C(win)); 455 456 alpha = VIDOSDxD_ALPHA1_R_F(0xff) | 457 VIDOSDxD_ALPHA1_G_F(0xff) | 458 VIDOSDxD_ALPHA1_B_F(0xff); 459 460 writel(alpha, ctx->regs + VIDOSD_D(win)); 461 462 decon_win_set_pixfmt(ctx, win, fb); 463 464 /* hardware window 0 doesn't support color key. */ 465 if (win != 0) 466 decon_win_set_colkey(ctx, win); 467 468 /* wincon */ 469 val = readl(ctx->regs + WINCON(win)); 470 val |= WINCONx_TRIPLE_BUF_MODE; 471 val |= WINCONx_ENWIN; 472 writel(val, ctx->regs + WINCON(win)); 473 474 /* Enable DMA channel and unprotect windows */ 475 decon_shadow_protect_win(ctx, win, false); 476 477 val = readl(ctx->regs + DECON_UPDATE); 478 val |= DECON_UPDATE_STANDALONE_F; 479 writel(val, ctx->regs + DECON_UPDATE); 480 } 481 482 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 483 struct exynos_drm_plane *plane) 484 { 485 struct decon_context *ctx = crtc->ctx; 486 unsigned int win = plane->index; 487 u32 val; 488 489 if (ctx->suspended) 490 return; 491 492 /* protect windows */ 493 decon_shadow_protect_win(ctx, win, true); 494 495 /* wincon */ 496 val = readl(ctx->regs + WINCON(win)); 497 val &= ~WINCONx_ENWIN; 498 writel(val, ctx->regs + WINCON(win)); 499 500 val = readl(ctx->regs + DECON_UPDATE); 501 val |= DECON_UPDATE_STANDALONE_F; 502 writel(val, ctx->regs + DECON_UPDATE); 503 } 504 505 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 506 { 507 struct decon_context *ctx = crtc->ctx; 508 int i; 509 510 if (ctx->suspended) 511 return; 512 513 for (i = 0; i < WINDOWS_NR; i++) 514 decon_shadow_protect_win(ctx, i, false); 515 exynos_crtc_handle_event(crtc); 516 } 517 518 static void decon_init(struct decon_context *ctx) 519 { 520 u32 val; 521 522 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); 523 524 val = VIDOUTCON0_DISP_IF_0_ON; 525 if (!ctx->i80_if) 526 val |= VIDOUTCON0_RGBIF; 527 writel(val, ctx->regs + VIDOUTCON0); 528 529 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); 530 531 if (!ctx->i80_if) 532 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); 533 } 534 535 static void decon_enable(struct exynos_drm_crtc *crtc) 536 { 537 struct decon_context *ctx = crtc->ctx; 538 539 if (!ctx->suspended) 540 return; 541 542 pm_runtime_get_sync(ctx->dev); 543 544 decon_init(ctx); 545 546 /* if vblank was enabled status, enable it again. */ 547 if (test_and_clear_bit(0, &ctx->irq_flags)) 548 decon_enable_vblank(ctx->crtc); 549 550 decon_commit(ctx->crtc); 551 552 ctx->suspended = false; 553 } 554 555 static void decon_disable(struct exynos_drm_crtc *crtc) 556 { 557 struct decon_context *ctx = crtc->ctx; 558 int i; 559 560 if (ctx->suspended) 561 return; 562 563 /* 564 * We need to make sure that all windows are disabled before we 565 * suspend that connector. Otherwise we might try to scan from 566 * a destroyed buffer later. 567 */ 568 for (i = 0; i < WINDOWS_NR; i++) 569 decon_disable_plane(crtc, &ctx->planes[i]); 570 571 pm_runtime_put_sync(ctx->dev); 572 573 ctx->suspended = true; 574 } 575 576 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 577 .enable = decon_enable, 578 .disable = decon_disable, 579 .enable_vblank = decon_enable_vblank, 580 .disable_vblank = decon_disable_vblank, 581 .atomic_begin = decon_atomic_begin, 582 .update_plane = decon_update_plane, 583 .disable_plane = decon_disable_plane, 584 .atomic_flush = decon_atomic_flush, 585 }; 586 587 588 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 589 { 590 struct decon_context *ctx = (struct decon_context *)dev_id; 591 u32 val, clear_bit; 592 593 val = readl(ctx->regs + VIDINTCON1); 594 595 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME; 596 if (val & clear_bit) 597 writel(clear_bit, ctx->regs + VIDINTCON1); 598 599 /* check the crtc is detached already from encoder */ 600 if (!ctx->drm_dev) 601 goto out; 602 603 if (!ctx->i80_if) { 604 drm_crtc_handle_vblank(&ctx->crtc->base); 605 606 /* set wait vsync event to zero and wake up queue. */ 607 if (atomic_read(&ctx->wait_vsync_event)) { 608 atomic_set(&ctx->wait_vsync_event, 0); 609 wake_up(&ctx->wait_vsync_queue); 610 } 611 } 612 out: 613 return IRQ_HANDLED; 614 } 615 616 static int decon_bind(struct device *dev, struct device *master, void *data) 617 { 618 struct decon_context *ctx = dev_get_drvdata(dev); 619 struct drm_device *drm_dev = data; 620 struct exynos_drm_plane *exynos_plane; 621 unsigned int i; 622 int ret; 623 624 ret = decon_ctx_initialize(ctx, drm_dev); 625 if (ret) { 626 DRM_ERROR("decon_ctx_initialize failed.\n"); 627 return ret; 628 } 629 630 for (i = 0; i < WINDOWS_NR; i++) { 631 ctx->configs[i].pixel_formats = decon_formats; 632 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats); 633 ctx->configs[i].zpos = i; 634 ctx->configs[i].type = decon_win_types[i]; 635 636 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i, 637 &ctx->configs[i]); 638 if (ret) 639 return ret; 640 } 641 642 exynos_plane = &ctx->planes[DEFAULT_WIN]; 643 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 644 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx); 645 if (IS_ERR(ctx->crtc)) { 646 decon_ctx_remove(ctx); 647 return PTR_ERR(ctx->crtc); 648 } 649 650 if (ctx->encoder) 651 exynos_dpi_bind(drm_dev, ctx->encoder); 652 653 return 0; 654 655 } 656 657 static void decon_unbind(struct device *dev, struct device *master, 658 void *data) 659 { 660 struct decon_context *ctx = dev_get_drvdata(dev); 661 662 decon_disable(ctx->crtc); 663 664 if (ctx->encoder) 665 exynos_dpi_remove(ctx->encoder); 666 667 decon_ctx_remove(ctx); 668 } 669 670 static const struct component_ops decon_component_ops = { 671 .bind = decon_bind, 672 .unbind = decon_unbind, 673 }; 674 675 static int decon_probe(struct platform_device *pdev) 676 { 677 struct device *dev = &pdev->dev; 678 struct decon_context *ctx; 679 struct device_node *i80_if_timings; 680 struct resource *res; 681 int ret; 682 683 if (!dev->of_node) 684 return -ENODEV; 685 686 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 687 if (!ctx) 688 return -ENOMEM; 689 690 ctx->dev = dev; 691 ctx->suspended = true; 692 693 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings"); 694 if (i80_if_timings) 695 ctx->i80_if = true; 696 of_node_put(i80_if_timings); 697 698 ctx->regs = of_iomap(dev->of_node, 0); 699 if (!ctx->regs) 700 return -ENOMEM; 701 702 ctx->pclk = devm_clk_get(dev, "pclk_decon0"); 703 if (IS_ERR(ctx->pclk)) { 704 dev_err(dev, "failed to get bus clock pclk\n"); 705 ret = PTR_ERR(ctx->pclk); 706 goto err_iounmap; 707 } 708 709 ctx->aclk = devm_clk_get(dev, "aclk_decon0"); 710 if (IS_ERR(ctx->aclk)) { 711 dev_err(dev, "failed to get bus clock aclk\n"); 712 ret = PTR_ERR(ctx->aclk); 713 goto err_iounmap; 714 } 715 716 ctx->eclk = devm_clk_get(dev, "decon0_eclk"); 717 if (IS_ERR(ctx->eclk)) { 718 dev_err(dev, "failed to get eclock\n"); 719 ret = PTR_ERR(ctx->eclk); 720 goto err_iounmap; 721 } 722 723 ctx->vclk = devm_clk_get(dev, "decon0_vclk"); 724 if (IS_ERR(ctx->vclk)) { 725 dev_err(dev, "failed to get vclock\n"); 726 ret = PTR_ERR(ctx->vclk); 727 goto err_iounmap; 728 } 729 730 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 731 ctx->i80_if ? "lcd_sys" : "vsync"); 732 if (!res) { 733 dev_err(dev, "irq request failed.\n"); 734 ret = -ENXIO; 735 goto err_iounmap; 736 } 737 738 ret = devm_request_irq(dev, res->start, decon_irq_handler, 739 0, "drm_decon", ctx); 740 if (ret) { 741 dev_err(dev, "irq request failed.\n"); 742 goto err_iounmap; 743 } 744 745 init_waitqueue_head(&ctx->wait_vsync_queue); 746 atomic_set(&ctx->wait_vsync_event, 0); 747 748 platform_set_drvdata(pdev, ctx); 749 750 ctx->encoder = exynos_dpi_probe(dev); 751 if (IS_ERR(ctx->encoder)) { 752 ret = PTR_ERR(ctx->encoder); 753 goto err_iounmap; 754 } 755 756 pm_runtime_enable(dev); 757 758 ret = component_add(dev, &decon_component_ops); 759 if (ret) 760 goto err_disable_pm_runtime; 761 762 return ret; 763 764 err_disable_pm_runtime: 765 pm_runtime_disable(dev); 766 767 err_iounmap: 768 iounmap(ctx->regs); 769 770 return ret; 771 } 772 773 static int decon_remove(struct platform_device *pdev) 774 { 775 struct decon_context *ctx = dev_get_drvdata(&pdev->dev); 776 777 pm_runtime_disable(&pdev->dev); 778 779 iounmap(ctx->regs); 780 781 component_del(&pdev->dev, &decon_component_ops); 782 783 return 0; 784 } 785 786 #ifdef CONFIG_PM 787 static int exynos7_decon_suspend(struct device *dev) 788 { 789 struct decon_context *ctx = dev_get_drvdata(dev); 790 791 clk_disable_unprepare(ctx->vclk); 792 clk_disable_unprepare(ctx->eclk); 793 clk_disable_unprepare(ctx->aclk); 794 clk_disable_unprepare(ctx->pclk); 795 796 return 0; 797 } 798 799 static int exynos7_decon_resume(struct device *dev) 800 { 801 struct decon_context *ctx = dev_get_drvdata(dev); 802 int ret; 803 804 ret = clk_prepare_enable(ctx->pclk); 805 if (ret < 0) { 806 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret); 807 return ret; 808 } 809 810 ret = clk_prepare_enable(ctx->aclk); 811 if (ret < 0) { 812 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret); 813 return ret; 814 } 815 816 ret = clk_prepare_enable(ctx->eclk); 817 if (ret < 0) { 818 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret); 819 return ret; 820 } 821 822 ret = clk_prepare_enable(ctx->vclk); 823 if (ret < 0) { 824 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret); 825 return ret; 826 } 827 828 return 0; 829 } 830 #endif 831 832 static const struct dev_pm_ops exynos7_decon_pm_ops = { 833 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume, 834 NULL) 835 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 836 pm_runtime_force_resume) 837 }; 838 839 struct platform_driver decon_driver = { 840 .probe = decon_probe, 841 .remove = decon_remove, 842 .driver = { 843 .name = "exynos-decon", 844 .pm = &exynos7_decon_pm_ops, 845 .of_match_table = decon_driver_dt_match, 846 }, 847 }; 848