1 /* drivers/gpu/drm/exynos5433_drm_decon.c 2 * 3 * Copyright (C) 2015 Samsung Electronics Co.Ltd 4 * Authors: 5 * Joonyoung Shim <jy0922.shim@samsung.com> 6 * Hyungwon Hwang <human.hwang@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundationr 11 */ 12 13 #include <linux/platform_device.h> 14 #include <linux/clk.h> 15 #include <linux/component.h> 16 #include <linux/iopoll.h> 17 #include <linux/irq.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regmap.h> 23 24 #include "exynos_drm_drv.h" 25 #include "exynos_drm_crtc.h" 26 #include "exynos_drm_fb.h" 27 #include "exynos_drm_plane.h" 28 #include "regs-decon5433.h" 29 30 #define DSD_CFG_MUX 0x1004 31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13) 32 33 #define WINDOWS_NR 5 34 #define PRIMARY_WIN 2 35 #define CURSON_WIN 4 36 37 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 38 39 #define I80_HW_TRG (1 << 0) 40 #define IFTYPE_HDMI (1 << 1) 41 42 static const char * const decon_clks_name[] = { 43 "pclk", 44 "aclk_decon", 45 "aclk_smmu_decon0x", 46 "aclk_xiu_decon0x", 47 "pclk_smmu_decon0x", 48 "aclk_smmu_decon1x", 49 "aclk_xiu_decon1x", 50 "pclk_smmu_decon1x", 51 "sclk_decon_vclk", 52 "sclk_decon_eclk", 53 }; 54 55 struct decon_context { 56 struct device *dev; 57 struct drm_device *drm_dev; 58 struct exynos_drm_crtc *crtc; 59 struct exynos_drm_plane planes[WINDOWS_NR]; 60 struct exynos_drm_plane_config configs[WINDOWS_NR]; 61 void __iomem *addr; 62 struct regmap *sysreg; 63 struct clk *clks[ARRAY_SIZE(decon_clks_name)]; 64 unsigned int irq; 65 unsigned int irq_vsync; 66 unsigned int irq_lcd_sys; 67 unsigned int te_irq; 68 unsigned long out_type; 69 int first_win; 70 spinlock_t vblank_lock; 71 u32 frame_id; 72 }; 73 74 static const uint32_t decon_formats[] = { 75 DRM_FORMAT_XRGB1555, 76 DRM_FORMAT_RGB565, 77 DRM_FORMAT_XRGB8888, 78 DRM_FORMAT_ARGB8888, 79 }; 80 81 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = { 82 [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY, 83 [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR, 84 }; 85 86 static const unsigned int capabilities[WINDOWS_NR] = { 87 0, 88 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 89 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 90 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 91 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND, 92 }; 93 94 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, 95 u32 val) 96 { 97 val = (val & mask) | (readl(ctx->addr + reg) & ~mask); 98 writel(val, ctx->addr + reg); 99 } 100 101 static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 102 { 103 struct decon_context *ctx = crtc->ctx; 104 u32 val; 105 106 val = VIDINTCON0_INTEN; 107 if (crtc->i80_mode) 108 val |= VIDINTCON0_FRAMEDONE; 109 else 110 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP; 111 112 writel(val, ctx->addr + DECON_VIDINTCON0); 113 114 enable_irq(ctx->irq); 115 if (!(ctx->out_type & I80_HW_TRG)) 116 enable_irq(ctx->te_irq); 117 118 return 0; 119 } 120 121 static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 122 { 123 struct decon_context *ctx = crtc->ctx; 124 125 if (!(ctx->out_type & I80_HW_TRG)) 126 disable_irq_nosync(ctx->te_irq); 127 disable_irq_nosync(ctx->irq); 128 129 writel(0, ctx->addr + DECON_VIDINTCON0); 130 } 131 132 /* return number of starts/ends of frame transmissions since reset */ 133 static u32 decon_get_frame_count(struct decon_context *ctx, bool end) 134 { 135 u32 frm, pfrm, status, cnt = 2; 136 137 /* To get consistent result repeat read until frame id is stable. 138 * Usually the loop will be executed once, in rare cases when the loop 139 * is executed at frame change time 2nd pass will be needed. 140 */ 141 frm = readl(ctx->addr + DECON_CRFMID); 142 do { 143 status = readl(ctx->addr + DECON_VIDCON1); 144 pfrm = frm; 145 frm = readl(ctx->addr + DECON_CRFMID); 146 } while (frm != pfrm && --cnt); 147 148 /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case 149 * of RGB, it should be taken into account. 150 */ 151 if (!frm) 152 return 0; 153 154 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) { 155 case VIDCON1_VSTATUS_VS: 156 if (!(ctx->crtc->i80_mode)) 157 --frm; 158 break; 159 case VIDCON1_VSTATUS_BP: 160 --frm; 161 break; 162 case VIDCON1_I80_ACTIVE: 163 case VIDCON1_VSTATUS_AC: 164 if (end) 165 --frm; 166 break; 167 default: 168 break; 169 } 170 171 return frm; 172 } 173 174 static void decon_setup_trigger(struct decon_context *ctx) 175 { 176 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG)) 177 return; 178 179 if (!(ctx->out_type & I80_HW_TRG)) { 180 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 181 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN, 182 ctx->addr + DECON_TRIGCON); 183 return; 184 } 185 186 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK 187 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON); 188 189 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX, 190 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0)) 191 DRM_ERROR("Cannot update sysreg.\n"); 192 } 193 194 static void decon_commit(struct exynos_drm_crtc *crtc) 195 { 196 struct decon_context *ctx = crtc->ctx; 197 struct drm_display_mode *m = &crtc->base.mode; 198 bool interlaced = false; 199 u32 val; 200 201 if (ctx->out_type & IFTYPE_HDMI) { 202 m->crtc_hsync_start = m->crtc_hdisplay + 10; 203 m->crtc_hsync_end = m->crtc_htotal - 92; 204 m->crtc_vsync_start = m->crtc_vdisplay + 1; 205 m->crtc_vsync_end = m->crtc_vsync_start + 1; 206 if (m->flags & DRM_MODE_FLAG_INTERLACE) 207 interlaced = true; 208 } 209 210 decon_setup_trigger(ctx); 211 212 /* lcd on and use command if */ 213 val = VIDOUT_LCD_ON; 214 if (interlaced) 215 val |= VIDOUT_INTERLACE_EN_F; 216 if (crtc->i80_mode) { 217 val |= VIDOUT_COMMAND_IF; 218 } else { 219 val |= VIDOUT_RGB_IF; 220 } 221 222 writel(val, ctx->addr + DECON_VIDOUTCON0); 223 224 if (interlaced) 225 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) | 226 VIDTCON2_HOZVAL(m->hdisplay - 1); 227 else 228 val = VIDTCON2_LINEVAL(m->vdisplay - 1) | 229 VIDTCON2_HOZVAL(m->hdisplay - 1); 230 writel(val, ctx->addr + DECON_VIDTCON2); 231 232 if (!crtc->i80_mode) { 233 int vbp = m->crtc_vtotal - m->crtc_vsync_end; 234 int vfp = m->crtc_vsync_start - m->crtc_vdisplay; 235 236 if (interlaced) 237 vbp = vbp / 2 - 1; 238 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1); 239 writel(val, ctx->addr + DECON_VIDTCON00); 240 241 val = VIDTCON01_VSPW_F( 242 m->crtc_vsync_end - m->crtc_vsync_start - 1); 243 writel(val, ctx->addr + DECON_VIDTCON01); 244 245 val = VIDTCON10_HBPD_F( 246 m->crtc_htotal - m->crtc_hsync_end - 1) | 247 VIDTCON10_HFPD_F( 248 m->crtc_hsync_start - m->crtc_hdisplay - 1); 249 writel(val, ctx->addr + DECON_VIDTCON10); 250 251 val = VIDTCON11_HSPW_F( 252 m->crtc_hsync_end - m->crtc_hsync_start - 1); 253 writel(val, ctx->addr + DECON_VIDTCON11); 254 } 255 256 /* enable output and display signal */ 257 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); 258 259 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 260 } 261 262 static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win, 263 unsigned int alpha, unsigned int pixel_alpha) 264 { 265 u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf); 266 u32 val = 0; 267 268 switch (pixel_alpha) { 269 case DRM_MODE_BLEND_PIXEL_NONE: 270 case DRM_MODE_BLEND_COVERAGE: 271 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A); 272 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); 273 break; 274 case DRM_MODE_BLEND_PREMULTI: 275 default: 276 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 277 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0); 278 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); 279 } else { 280 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE); 281 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A); 282 } 283 break; 284 } 285 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val); 286 } 287 288 static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win, 289 unsigned int alpha, unsigned int pixel_alpha) 290 { 291 u32 win_alpha = alpha >> 8; 292 u32 val = 0; 293 294 switch (pixel_alpha) { 295 case DRM_MODE_BLEND_PIXEL_NONE: 296 break; 297 case DRM_MODE_BLEND_COVERAGE: 298 case DRM_MODE_BLEND_PREMULTI: 299 default: 300 val |= WINCONx_ALPHA_SEL_F; 301 val |= WINCONx_BLD_PIX_F; 302 val |= WINCONx_ALPHA_MUL_F; 303 break; 304 } 305 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val); 306 307 if (alpha != DRM_BLEND_ALPHA_OPAQUE) { 308 val = VIDOSD_Wx_ALPHA_R_F(win_alpha) | 309 VIDOSD_Wx_ALPHA_G_F(win_alpha) | 310 VIDOSD_Wx_ALPHA_B_F(win_alpha); 311 decon_set_bits(ctx, DECON_VIDOSDxC(win), 312 VIDOSDxC_ALPHA0_RGB_MASK, val); 313 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW); 314 } 315 } 316 317 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 318 struct drm_framebuffer *fb) 319 { 320 struct exynos_drm_plane plane = ctx->planes[win]; 321 struct exynos_drm_plane_state *state = 322 to_exynos_plane_state(plane.base.state); 323 unsigned int alpha = state->base.alpha; 324 unsigned int pixel_alpha; 325 unsigned long val; 326 327 if (fb->format->has_alpha) 328 pixel_alpha = state->base.pixel_blend_mode; 329 else 330 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE; 331 332 val = readl(ctx->addr + DECON_WINCONx(win)); 333 val &= WINCONx_ENWIN_F; 334 335 switch (fb->format->format) { 336 case DRM_FORMAT_XRGB1555: 337 val |= WINCONx_BPPMODE_16BPP_I1555; 338 val |= WINCONx_HAWSWP_F; 339 val |= WINCONx_BURSTLEN_16WORD; 340 break; 341 case DRM_FORMAT_RGB565: 342 val |= WINCONx_BPPMODE_16BPP_565; 343 val |= WINCONx_HAWSWP_F; 344 val |= WINCONx_BURSTLEN_16WORD; 345 break; 346 case DRM_FORMAT_XRGB8888: 347 val |= WINCONx_BPPMODE_24BPP_888; 348 val |= WINCONx_WSWP_F; 349 val |= WINCONx_BURSTLEN_16WORD; 350 break; 351 case DRM_FORMAT_ARGB8888: 352 default: 353 val |= WINCONx_BPPMODE_32BPP_A8888; 354 val |= WINCONx_WSWP_F; 355 val |= WINCONx_BURSTLEN_16WORD; 356 break; 357 } 358 359 DRM_DEBUG_KMS("cpp = %u\n", fb->format->cpp[0]); 360 361 /* 362 * In case of exynos, setting dma-burst to 16Word causes permanent 363 * tearing for very small buffers, e.g. cursor buffer. Burst Mode 364 * switching which is based on plane size is not recommended as 365 * plane size varies a lot towards the end of the screen and rapid 366 * movement causes unstable DMA which results into iommu crash/tear. 367 */ 368 369 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 370 val &= ~WINCONx_BURSTLEN_MASK; 371 val |= WINCONx_BURSTLEN_8WORD; 372 } 373 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val); 374 375 if (win > 0) { 376 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha); 377 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha); 378 } 379 } 380 381 static void decon_shadow_protect(struct decon_context *ctx, bool protect) 382 { 383 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK, 384 protect ? ~0 : 0); 385 } 386 387 static void decon_atomic_begin(struct exynos_drm_crtc *crtc) 388 { 389 struct decon_context *ctx = crtc->ctx; 390 391 decon_shadow_protect(ctx, true); 392 } 393 394 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) 395 #define COORDINATE_X(x) BIT_VAL((x), 23, 12) 396 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0) 397 398 static void decon_update_plane(struct exynos_drm_crtc *crtc, 399 struct exynos_drm_plane *plane) 400 { 401 struct exynos_drm_plane_state *state = 402 to_exynos_plane_state(plane->base.state); 403 struct decon_context *ctx = crtc->ctx; 404 struct drm_framebuffer *fb = state->base.fb; 405 unsigned int win = plane->index; 406 unsigned int cpp = fb->format->cpp[0]; 407 unsigned int pitch = fb->pitches[0]; 408 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0); 409 u32 val; 410 411 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) { 412 val = COORDINATE_X(state->crtc.x) | 413 COORDINATE_Y(state->crtc.y / 2); 414 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 415 416 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 417 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1); 418 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 419 } else { 420 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y); 421 writel(val, ctx->addr + DECON_VIDOSDxA(win)); 422 423 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) | 424 COORDINATE_Y(state->crtc.y + state->crtc.h - 1); 425 writel(val, ctx->addr + DECON_VIDOSDxB(win)); 426 } 427 428 val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) | 429 VIDOSD_Wx_ALPHA_B_F(0xff); 430 writel(val, ctx->addr + DECON_VIDOSDxC(win)); 431 432 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 433 VIDOSD_Wx_ALPHA_B_F(0x0); 434 writel(val, ctx->addr + DECON_VIDOSDxD(win)); 435 436 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win)); 437 438 val = dma_addr + pitch * state->src.h; 439 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); 440 441 if (!(ctx->out_type & IFTYPE_HDMI)) 442 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14) 443 | BIT_VAL(state->crtc.w * cpp, 13, 0); 444 else 445 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15) 446 | BIT_VAL(state->crtc.w * cpp, 14, 0); 447 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); 448 449 decon_win_set_pixfmt(ctx, win, fb); 450 451 /* window enable */ 452 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); 453 } 454 455 static void decon_disable_plane(struct exynos_drm_crtc *crtc, 456 struct exynos_drm_plane *plane) 457 { 458 struct decon_context *ctx = crtc->ctx; 459 unsigned int win = plane->index; 460 461 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 462 } 463 464 static void decon_atomic_flush(struct exynos_drm_crtc *crtc) 465 { 466 struct decon_context *ctx = crtc->ctx; 467 unsigned long flags; 468 469 spin_lock_irqsave(&ctx->vblank_lock, flags); 470 471 decon_shadow_protect(ctx, false); 472 473 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 474 475 ctx->frame_id = decon_get_frame_count(ctx, true); 476 477 exynos_crtc_handle_event(crtc); 478 479 spin_unlock_irqrestore(&ctx->vblank_lock, flags); 480 } 481 482 static void decon_swreset(struct decon_context *ctx) 483 { 484 unsigned long flags; 485 u32 val; 486 int ret; 487 488 writel(0, ctx->addr + DECON_VIDCON0); 489 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, 490 ~val & VIDCON0_STOP_STATUS, 12, 20000); 491 492 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); 493 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val, 494 ~val & VIDCON0_SWRESET, 12, 20000); 495 496 WARN(ret < 0, "failed to software reset DECON\n"); 497 498 spin_lock_irqsave(&ctx->vblank_lock, flags); 499 ctx->frame_id = 0; 500 spin_unlock_irqrestore(&ctx->vblank_lock, flags); 501 502 if (!(ctx->out_type & IFTYPE_HDMI)) 503 return; 504 505 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); 506 decon_set_bits(ctx, DECON_CMU, 507 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); 508 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); 509 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, 510 ctx->addr + DECON_CRCCTRL); 511 } 512 513 static void decon_enable(struct exynos_drm_crtc *crtc) 514 { 515 struct decon_context *ctx = crtc->ctx; 516 517 pm_runtime_get_sync(ctx->dev); 518 519 exynos_drm_pipe_clk_enable(crtc, true); 520 521 decon_swreset(ctx); 522 523 decon_commit(ctx->crtc); 524 } 525 526 static void decon_disable(struct exynos_drm_crtc *crtc) 527 { 528 struct decon_context *ctx = crtc->ctx; 529 int i; 530 531 if (!(ctx->out_type & I80_HW_TRG)) 532 synchronize_irq(ctx->te_irq); 533 synchronize_irq(ctx->irq); 534 535 /* 536 * We need to make sure that all windows are disabled before we 537 * suspend that connector. Otherwise we might try to scan from 538 * a destroyed buffer later. 539 */ 540 for (i = ctx->first_win; i < WINDOWS_NR; i++) 541 decon_disable_plane(crtc, &ctx->planes[i]); 542 543 decon_swreset(ctx); 544 545 exynos_drm_pipe_clk_enable(crtc, false); 546 547 pm_runtime_put_sync(ctx->dev); 548 } 549 550 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id) 551 { 552 struct decon_context *ctx = dev_id; 553 554 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); 555 556 return IRQ_HANDLED; 557 } 558 559 static void decon_clear_channels(struct exynos_drm_crtc *crtc) 560 { 561 struct decon_context *ctx = crtc->ctx; 562 int win, i, ret; 563 564 DRM_DEBUG_KMS("%s\n", __FILE__); 565 566 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 567 ret = clk_prepare_enable(ctx->clks[i]); 568 if (ret < 0) 569 goto err; 570 } 571 572 decon_shadow_protect(ctx, true); 573 for (win = 0; win < WINDOWS_NR; win++) 574 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); 575 decon_shadow_protect(ctx, false); 576 577 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); 578 579 /* TODO: wait for possible vsync */ 580 msleep(50); 581 582 err: 583 while (--i >= 0) 584 clk_disable_unprepare(ctx->clks[i]); 585 } 586 587 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc, 588 const struct drm_display_mode *mode) 589 { 590 struct decon_context *ctx = crtc->ctx; 591 592 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync; 593 594 if (ctx->irq) 595 return MODE_OK; 596 597 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n", 598 crtc->i80_mode ? "command" : "video"); 599 600 return MODE_BAD; 601 } 602 603 static const struct exynos_drm_crtc_ops decon_crtc_ops = { 604 .enable = decon_enable, 605 .disable = decon_disable, 606 .enable_vblank = decon_enable_vblank, 607 .disable_vblank = decon_disable_vblank, 608 .atomic_begin = decon_atomic_begin, 609 .update_plane = decon_update_plane, 610 .disable_plane = decon_disable_plane, 611 .mode_valid = decon_mode_valid, 612 .atomic_flush = decon_atomic_flush, 613 }; 614 615 static int decon_bind(struct device *dev, struct device *master, void *data) 616 { 617 struct decon_context *ctx = dev_get_drvdata(dev); 618 struct drm_device *drm_dev = data; 619 struct exynos_drm_plane *exynos_plane; 620 enum exynos_drm_output_type out_type; 621 unsigned int win; 622 int ret; 623 624 ctx->drm_dev = drm_dev; 625 626 for (win = ctx->first_win; win < WINDOWS_NR; win++) { 627 ctx->configs[win].pixel_formats = decon_formats; 628 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats); 629 ctx->configs[win].zpos = win - ctx->first_win; 630 ctx->configs[win].type = decon_win_types[win]; 631 ctx->configs[win].capabilities = capabilities[win]; 632 633 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win, 634 &ctx->configs[win]); 635 if (ret) 636 return ret; 637 } 638 639 exynos_plane = &ctx->planes[PRIMARY_WIN]; 640 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI 641 : EXYNOS_DISPLAY_TYPE_LCD; 642 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 643 out_type, &decon_crtc_ops, ctx); 644 if (IS_ERR(ctx->crtc)) 645 return PTR_ERR(ctx->crtc); 646 647 decon_clear_channels(ctx->crtc); 648 649 return exynos_drm_register_dma(drm_dev, dev); 650 } 651 652 static void decon_unbind(struct device *dev, struct device *master, void *data) 653 { 654 struct decon_context *ctx = dev_get_drvdata(dev); 655 656 decon_disable(ctx->crtc); 657 658 /* detach this sub driver from iommu mapping if supported. */ 659 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev); 660 } 661 662 static const struct component_ops decon_component_ops = { 663 .bind = decon_bind, 664 .unbind = decon_unbind, 665 }; 666 667 static void decon_handle_vblank(struct decon_context *ctx) 668 { 669 u32 frm; 670 671 spin_lock(&ctx->vblank_lock); 672 673 frm = decon_get_frame_count(ctx, true); 674 675 if (frm != ctx->frame_id) { 676 /* handle only if incremented, take care of wrap-around */ 677 if ((s32)(frm - ctx->frame_id) > 0) 678 drm_crtc_handle_vblank(&ctx->crtc->base); 679 ctx->frame_id = frm; 680 } 681 682 spin_unlock(&ctx->vblank_lock); 683 } 684 685 static irqreturn_t decon_irq_handler(int irq, void *dev_id) 686 { 687 struct decon_context *ctx = dev_id; 688 u32 val; 689 690 val = readl(ctx->addr + DECON_VIDINTCON1); 691 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; 692 693 if (val) { 694 writel(val, ctx->addr + DECON_VIDINTCON1); 695 if (ctx->out_type & IFTYPE_HDMI) { 696 val = readl(ctx->addr + DECON_VIDOUTCON0); 697 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F; 698 if (val == 699 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F)) 700 return IRQ_HANDLED; 701 } 702 decon_handle_vblank(ctx); 703 } 704 705 return IRQ_HANDLED; 706 } 707 708 #ifdef CONFIG_PM 709 static int exynos5433_decon_suspend(struct device *dev) 710 { 711 struct decon_context *ctx = dev_get_drvdata(dev); 712 int i = ARRAY_SIZE(decon_clks_name); 713 714 while (--i >= 0) 715 clk_disable_unprepare(ctx->clks[i]); 716 717 return 0; 718 } 719 720 static int exynos5433_decon_resume(struct device *dev) 721 { 722 struct decon_context *ctx = dev_get_drvdata(dev); 723 int i, ret; 724 725 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 726 ret = clk_prepare_enable(ctx->clks[i]); 727 if (ret < 0) 728 goto err; 729 } 730 731 return 0; 732 733 err: 734 while (--i >= 0) 735 clk_disable_unprepare(ctx->clks[i]); 736 737 return ret; 738 } 739 #endif 740 741 static const struct dev_pm_ops exynos5433_decon_pm_ops = { 742 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume, 743 NULL) 744 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 745 pm_runtime_force_resume) 746 }; 747 748 static const struct of_device_id exynos5433_decon_driver_dt_match[] = { 749 { 750 .compatible = "samsung,exynos5433-decon", 751 .data = (void *)I80_HW_TRG 752 }, 753 { 754 .compatible = "samsung,exynos5433-decon-tv", 755 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI) 756 }, 757 {}, 758 }; 759 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); 760 761 static int decon_conf_irq(struct decon_context *ctx, const char *name, 762 irq_handler_t handler, unsigned long int flags) 763 { 764 struct platform_device *pdev = to_platform_device(ctx->dev); 765 int ret, irq = platform_get_irq_byname(pdev, name); 766 767 if (irq < 0) { 768 switch (irq) { 769 case -EPROBE_DEFER: 770 return irq; 771 case -ENODATA: 772 case -ENXIO: 773 return 0; 774 default: 775 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq); 776 return irq; 777 } 778 } 779 irq_set_status_flags(irq, IRQ_NOAUTOEN); 780 ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx); 781 if (ret < 0) { 782 dev_err(ctx->dev, "IRQ %s request failed\n", name); 783 return ret; 784 } 785 786 return irq; 787 } 788 789 static int exynos5433_decon_probe(struct platform_device *pdev) 790 { 791 struct device *dev = &pdev->dev; 792 struct decon_context *ctx; 793 struct resource *res; 794 int ret; 795 int i; 796 797 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 798 if (!ctx) 799 return -ENOMEM; 800 801 ctx->dev = dev; 802 ctx->out_type = (unsigned long)of_device_get_match_data(dev); 803 spin_lock_init(&ctx->vblank_lock); 804 805 if (ctx->out_type & IFTYPE_HDMI) 806 ctx->first_win = 1; 807 808 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 809 struct clk *clk; 810 811 clk = devm_clk_get(ctx->dev, decon_clks_name[i]); 812 if (IS_ERR(clk)) 813 return PTR_ERR(clk); 814 815 ctx->clks[i] = clk; 816 } 817 818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 819 ctx->addr = devm_ioremap_resource(dev, res); 820 if (IS_ERR(ctx->addr)) { 821 dev_err(dev, "ioremap failed\n"); 822 return PTR_ERR(ctx->addr); 823 } 824 825 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0); 826 if (ret < 0) 827 return ret; 828 ctx->irq_vsync = ret; 829 830 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0); 831 if (ret < 0) 832 return ret; 833 ctx->irq_lcd_sys = ret; 834 835 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler, 836 IRQF_TRIGGER_RISING); 837 if (ret < 0) 838 return ret; 839 if (ret) { 840 ctx->te_irq = ret; 841 ctx->out_type &= ~I80_HW_TRG; 842 } 843 844 if (ctx->out_type & I80_HW_TRG) { 845 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node, 846 "samsung,disp-sysreg"); 847 if (IS_ERR(ctx->sysreg)) { 848 dev_err(dev, "failed to get system register\n"); 849 return PTR_ERR(ctx->sysreg); 850 } 851 } 852 853 platform_set_drvdata(pdev, ctx); 854 855 pm_runtime_enable(dev); 856 857 ret = component_add(dev, &decon_component_ops); 858 if (ret) 859 goto err_disable_pm_runtime; 860 861 return 0; 862 863 err_disable_pm_runtime: 864 pm_runtime_disable(dev); 865 866 return ret; 867 } 868 869 static int exynos5433_decon_remove(struct platform_device *pdev) 870 { 871 pm_runtime_disable(&pdev->dev); 872 873 component_del(&pdev->dev, &decon_component_ops); 874 875 return 0; 876 } 877 878 struct platform_driver exynos5433_decon_driver = { 879 .probe = exynos5433_decon_probe, 880 .remove = exynos5433_decon_remove, 881 .driver = { 882 .name = "exynos5433-decon", 883 .pm = &exynos5433_decon_pm_ops, 884 .of_match_table = exynos5433_decon_driver_dt_match, 885 }, 886 }; 887