1c8466a91SJoonyoung Shim /* drivers/gpu/drm/exynos5433_drm_decon.c 2c8466a91SJoonyoung Shim * 3c8466a91SJoonyoung Shim * Copyright (C) 2015 Samsung Electronics Co.Ltd 4c8466a91SJoonyoung Shim * Authors: 5c8466a91SJoonyoung Shim * Joonyoung Shim <jy0922.shim@samsung.com> 6c8466a91SJoonyoung Shim * Hyungwon Hwang <human.hwang@samsung.com> 7c8466a91SJoonyoung Shim * 8c8466a91SJoonyoung Shim * This program is free software; you can redistribute it and/or modify 9c8466a91SJoonyoung Shim * it under the terms of the GNU General Public License version 2 as 10c8466a91SJoonyoung Shim * published by the Free Software Foundationr 11c8466a91SJoonyoung Shim */ 12c8466a91SJoonyoung Shim 13c8466a91SJoonyoung Shim #include <linux/platform_device.h> 14c8466a91SJoonyoung Shim #include <linux/clk.h> 15c8466a91SJoonyoung Shim #include <linux/component.h> 16c8466a91SJoonyoung Shim #include <linux/of_gpio.h> 17c8466a91SJoonyoung Shim #include <linux/pm_runtime.h> 18c8466a91SJoonyoung Shim 19c8466a91SJoonyoung Shim #include <video/exynos5433_decon.h> 20c8466a91SJoonyoung Shim 21c8466a91SJoonyoung Shim #include "exynos_drm_drv.h" 22c8466a91SJoonyoung Shim #include "exynos_drm_crtc.h" 23c8466a91SJoonyoung Shim #include "exynos_drm_plane.h" 24c8466a91SJoonyoung Shim #include "exynos_drm_iommu.h" 25c8466a91SJoonyoung Shim 26c8466a91SJoonyoung Shim #define WINDOWS_NR 3 27c8466a91SJoonyoung Shim #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 28c8466a91SJoonyoung Shim 29c8466a91SJoonyoung Shim struct decon_context { 30c8466a91SJoonyoung Shim struct device *dev; 31c8466a91SJoonyoung Shim struct drm_device *drm_dev; 32c8466a91SJoonyoung Shim struct exynos_drm_crtc *crtc; 33c8466a91SJoonyoung Shim struct exynos_drm_plane planes[WINDOWS_NR]; 34c8466a91SJoonyoung Shim void __iomem *addr; 35c8466a91SJoonyoung Shim struct clk *clks[6]; 36c8466a91SJoonyoung Shim unsigned int default_win; 37c8466a91SJoonyoung Shim unsigned long irq_flags; 38c8466a91SJoonyoung Shim int pipe; 39c8466a91SJoonyoung Shim bool suspended; 40c8466a91SJoonyoung Shim 41c8466a91SJoonyoung Shim #define BIT_CLKS_ENABLED 0 42c8466a91SJoonyoung Shim #define BIT_IRQS_ENABLED 1 43c8466a91SJoonyoung Shim unsigned long enabled; 44c8466a91SJoonyoung Shim bool i80_if; 45c8466a91SJoonyoung Shim atomic_t win_updated; 46c8466a91SJoonyoung Shim }; 47c8466a91SJoonyoung Shim 48c8466a91SJoonyoung Shim static const char * const decon_clks_name[] = { 49c8466a91SJoonyoung Shim "aclk_decon", 50c8466a91SJoonyoung Shim "aclk_smmu_decon0x", 51c8466a91SJoonyoung Shim "aclk_xiu_decon0x", 52c8466a91SJoonyoung Shim "pclk_smmu_decon0x", 53c8466a91SJoonyoung Shim "sclk_decon_vclk", 54c8466a91SJoonyoung Shim "sclk_decon_eclk", 55c8466a91SJoonyoung Shim }; 56c8466a91SJoonyoung Shim 57c8466a91SJoonyoung Shim static int decon_enable_vblank(struct exynos_drm_crtc *crtc) 58c8466a91SJoonyoung Shim { 59c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 60c8466a91SJoonyoung Shim u32 val; 61c8466a91SJoonyoung Shim 62c8466a91SJoonyoung Shim if (ctx->suspended) 63c8466a91SJoonyoung Shim return -EPERM; 64c8466a91SJoonyoung Shim 65c8466a91SJoonyoung Shim if (test_and_set_bit(0, &ctx->irq_flags)) { 66c8466a91SJoonyoung Shim val = VIDINTCON0_INTEN; 67c8466a91SJoonyoung Shim if (ctx->i80_if) 68c8466a91SJoonyoung Shim val |= VIDINTCON0_FRAMEDONE; 69c8466a91SJoonyoung Shim else 70c8466a91SJoonyoung Shim val |= VIDINTCON0_INTFRMEN; 71c8466a91SJoonyoung Shim 72c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDINTCON0); 73c8466a91SJoonyoung Shim } 74c8466a91SJoonyoung Shim 75c8466a91SJoonyoung Shim return 0; 76c8466a91SJoonyoung Shim } 77c8466a91SJoonyoung Shim 78c8466a91SJoonyoung Shim static void decon_disable_vblank(struct exynos_drm_crtc *crtc) 79c8466a91SJoonyoung Shim { 80c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 81c8466a91SJoonyoung Shim 82c8466a91SJoonyoung Shim if (ctx->suspended) 83c8466a91SJoonyoung Shim return; 84c8466a91SJoonyoung Shim 85c8466a91SJoonyoung Shim if (test_and_clear_bit(0, &ctx->irq_flags)) 86c8466a91SJoonyoung Shim writel(0, ctx->addr + DECON_VIDINTCON0); 87c8466a91SJoonyoung Shim } 88c8466a91SJoonyoung Shim 89c8466a91SJoonyoung Shim static void decon_setup_trigger(struct decon_context *ctx) 90c8466a91SJoonyoung Shim { 91c8466a91SJoonyoung Shim u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | 92c8466a91SJoonyoung Shim TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN; 93c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_TRIGCON); 94c8466a91SJoonyoung Shim } 95c8466a91SJoonyoung Shim 96c8466a91SJoonyoung Shim static void decon_commit(struct exynos_drm_crtc *crtc) 97c8466a91SJoonyoung Shim { 98c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 99c8466a91SJoonyoung Shim struct drm_display_mode *mode = &crtc->base.mode; 100c8466a91SJoonyoung Shim u32 val; 101c8466a91SJoonyoung Shim 102c8466a91SJoonyoung Shim if (ctx->suspended) 103c8466a91SJoonyoung Shim return; 104c8466a91SJoonyoung Shim 105c8466a91SJoonyoung Shim /* enable clock gate */ 106c8466a91SJoonyoung Shim val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; 107c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_CMU); 108c8466a91SJoonyoung Shim 109c8466a91SJoonyoung Shim /* lcd on and use command if */ 110c8466a91SJoonyoung Shim val = VIDOUT_LCD_ON; 111c8466a91SJoonyoung Shim if (ctx->i80_if) 112c8466a91SJoonyoung Shim val |= VIDOUT_COMMAND_IF; 113c8466a91SJoonyoung Shim else 114c8466a91SJoonyoung Shim val |= VIDOUT_RGB_IF; 115c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOUTCON0); 116c8466a91SJoonyoung Shim 117c8466a91SJoonyoung Shim val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | 118c8466a91SJoonyoung Shim VIDTCON2_HOZVAL(mode->hdisplay - 1); 119c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON2); 120c8466a91SJoonyoung Shim 121c8466a91SJoonyoung Shim if (!ctx->i80_if) { 122c8466a91SJoonyoung Shim val = VIDTCON00_VBPD_F( 123c8466a91SJoonyoung Shim mode->crtc_vtotal - mode->crtc_vsync_end) | 124c8466a91SJoonyoung Shim VIDTCON00_VFPD_F( 125c8466a91SJoonyoung Shim mode->crtc_vsync_start - mode->crtc_vdisplay); 126c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON00); 127c8466a91SJoonyoung Shim 128c8466a91SJoonyoung Shim val = VIDTCON01_VSPW_F( 129c8466a91SJoonyoung Shim mode->crtc_vsync_end - mode->crtc_vsync_start); 130c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON01); 131c8466a91SJoonyoung Shim 132c8466a91SJoonyoung Shim val = VIDTCON10_HBPD_F( 133c8466a91SJoonyoung Shim mode->crtc_htotal - mode->crtc_hsync_end) | 134c8466a91SJoonyoung Shim VIDTCON10_HFPD_F( 135c8466a91SJoonyoung Shim mode->crtc_hsync_start - mode->crtc_hdisplay); 136c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON10); 137c8466a91SJoonyoung Shim 138c8466a91SJoonyoung Shim val = VIDTCON11_HSPW_F( 139c8466a91SJoonyoung Shim mode->crtc_hsync_end - mode->crtc_hsync_start); 140c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON11); 141c8466a91SJoonyoung Shim } 142c8466a91SJoonyoung Shim 143c8466a91SJoonyoung Shim decon_setup_trigger(ctx); 144c8466a91SJoonyoung Shim 145c8466a91SJoonyoung Shim /* enable output and display signal */ 146c8466a91SJoonyoung Shim val = VIDCON0_ENVID | VIDCON0_ENVID_F; 147c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDCON0); 148c8466a91SJoonyoung Shim } 149c8466a91SJoonyoung Shim 150c8466a91SJoonyoung Shim #define COORDINATE_X(x) (((x) & 0xfff) << 12) 151c8466a91SJoonyoung Shim #define COORDINATE_Y(x) ((x) & 0xfff) 152c8466a91SJoonyoung Shim #define OFFSIZE(x) (((x) & 0x3fff) << 14) 153c8466a91SJoonyoung Shim #define PAGEWIDTH(x) ((x) & 0x3fff) 154c8466a91SJoonyoung Shim 1552eeb2e5eSGustavo Padovan static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, 1562eeb2e5eSGustavo Padovan struct drm_framebuffer *fb) 157c8466a91SJoonyoung Shim { 158c8466a91SJoonyoung Shim unsigned long val; 159c8466a91SJoonyoung Shim 160c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_WINCONx(win)); 161c8466a91SJoonyoung Shim val &= ~WINCONx_BPPMODE_MASK; 162c8466a91SJoonyoung Shim 1632eeb2e5eSGustavo Padovan switch (fb->pixel_format) { 164c8466a91SJoonyoung Shim case DRM_FORMAT_XRGB1555: 165c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_16BPP_I1555; 166c8466a91SJoonyoung Shim val |= WINCONx_HAWSWP_F; 167c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD; 168c8466a91SJoonyoung Shim break; 169c8466a91SJoonyoung Shim case DRM_FORMAT_RGB565: 170c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_16BPP_565; 171c8466a91SJoonyoung Shim val |= WINCONx_HAWSWP_F; 172c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD; 173c8466a91SJoonyoung Shim break; 174c8466a91SJoonyoung Shim case DRM_FORMAT_XRGB8888: 175c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_24BPP_888; 176c8466a91SJoonyoung Shim val |= WINCONx_WSWP_F; 177c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD; 178c8466a91SJoonyoung Shim break; 179c8466a91SJoonyoung Shim case DRM_FORMAT_ARGB8888: 180c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_32BPP_A8888; 181c8466a91SJoonyoung Shim val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F; 182c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD; 183c8466a91SJoonyoung Shim break; 184c8466a91SJoonyoung Shim default: 185c8466a91SJoonyoung Shim DRM_ERROR("Proper pixel format is not set\n"); 186c8466a91SJoonyoung Shim return; 187c8466a91SJoonyoung Shim } 188c8466a91SJoonyoung Shim 1892eeb2e5eSGustavo Padovan DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel); 190c8466a91SJoonyoung Shim 191c8466a91SJoonyoung Shim /* 192c8466a91SJoonyoung Shim * In case of exynos, setting dma-burst to 16Word causes permanent 193c8466a91SJoonyoung Shim * tearing for very small buffers, e.g. cursor buffer. Burst Mode 194c8466a91SJoonyoung Shim * switching which is based on plane size is not recommended as 195c8466a91SJoonyoung Shim * plane size varies a lot towards the end of the screen and rapid 196c8466a91SJoonyoung Shim * movement causes unstable DMA which results into iommu crash/tear. 197c8466a91SJoonyoung Shim */ 198c8466a91SJoonyoung Shim 1992eeb2e5eSGustavo Padovan if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) { 200c8466a91SJoonyoung Shim val &= ~WINCONx_BURSTLEN_MASK; 201c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_8WORD; 202c8466a91SJoonyoung Shim } 203c8466a91SJoonyoung Shim 204c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_WINCONx(win)); 205c8466a91SJoonyoung Shim } 206c8466a91SJoonyoung Shim 207c8466a91SJoonyoung Shim static void decon_shadow_protect_win(struct decon_context *ctx, int win, 208c8466a91SJoonyoung Shim bool protect) 209c8466a91SJoonyoung Shim { 210c8466a91SJoonyoung Shim u32 val; 211c8466a91SJoonyoung Shim 212c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_SHADOWCON); 213c8466a91SJoonyoung Shim 214c8466a91SJoonyoung Shim if (protect) 215c8466a91SJoonyoung Shim val |= SHADOWCON_Wx_PROTECT(win); 216c8466a91SJoonyoung Shim else 217c8466a91SJoonyoung Shim val &= ~SHADOWCON_Wx_PROTECT(win); 218c8466a91SJoonyoung Shim 219c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_SHADOWCON); 220c8466a91SJoonyoung Shim } 221c8466a91SJoonyoung Shim 2221e1d1393SGustavo Padovan static void decon_update_plane(struct exynos_drm_crtc *crtc, 2231e1d1393SGustavo Padovan struct exynos_drm_plane *plane) 224c8466a91SJoonyoung Shim { 225c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 2262eeb2e5eSGustavo Padovan struct drm_plane_state *state = plane->base.state; 2271e1d1393SGustavo Padovan unsigned int win = plane->zpos; 2282eeb2e5eSGustavo Padovan unsigned int bpp = state->fb->bits_per_pixel >> 3; 2292eeb2e5eSGustavo Padovan unsigned int pitch = state->fb->pitches[0]; 230c8466a91SJoonyoung Shim u32 val; 231c8466a91SJoonyoung Shim 232c8466a91SJoonyoung Shim if (ctx->suspended) 233c8466a91SJoonyoung Shim return; 234c8466a91SJoonyoung Shim 235c8466a91SJoonyoung Shim decon_shadow_protect_win(ctx, win, true); 236c8466a91SJoonyoung Shim 237c8466a91SJoonyoung Shim val = COORDINATE_X(plane->crtc_x) | COORDINATE_Y(plane->crtc_y); 238c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxA(win)); 239c8466a91SJoonyoung Shim 240c8466a91SJoonyoung Shim val = COORDINATE_X(plane->crtc_x + plane->crtc_width - 1) | 241c8466a91SJoonyoung Shim COORDINATE_Y(plane->crtc_y + plane->crtc_height - 1); 242c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxB(win)); 243c8466a91SJoonyoung Shim 244c8466a91SJoonyoung Shim val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 245c8466a91SJoonyoung Shim VIDOSD_Wx_ALPHA_B_F(0x0); 246c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxC(win)); 247c8466a91SJoonyoung Shim 248c8466a91SJoonyoung Shim val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) | 249c8466a91SJoonyoung Shim VIDOSD_Wx_ALPHA_B_F(0x0); 250c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxD(win)); 251c8466a91SJoonyoung Shim 252c8466a91SJoonyoung Shim writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win)); 253c8466a91SJoonyoung Shim 2542eeb2e5eSGustavo Padovan val = plane->dma_addr[0] + pitch * plane->crtc_height; 255c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); 256c8466a91SJoonyoung Shim 2572eeb2e5eSGustavo Padovan val = OFFSIZE(pitch - plane->crtc_width * bpp) 2582eeb2e5eSGustavo Padovan | PAGEWIDTH(plane->crtc_width * bpp); 259c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDW0xADD2(win)); 260c8466a91SJoonyoung Shim 2612eeb2e5eSGustavo Padovan decon_win_set_pixfmt(ctx, win, state->fb); 262c8466a91SJoonyoung Shim 263c8466a91SJoonyoung Shim /* window enable */ 264c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_WINCONx(win)); 265c8466a91SJoonyoung Shim val |= WINCONx_ENWIN_F; 266c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_WINCONx(win)); 267c8466a91SJoonyoung Shim 268c8466a91SJoonyoung Shim decon_shadow_protect_win(ctx, win, false); 269c8466a91SJoonyoung Shim 270c8466a91SJoonyoung Shim /* standalone update */ 271c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_UPDATE); 272c8466a91SJoonyoung Shim val |= STANDALONE_UPDATE_F; 273c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_UPDATE); 274c8466a91SJoonyoung Shim 275c8466a91SJoonyoung Shim if (ctx->i80_if) 276c8466a91SJoonyoung Shim atomic_set(&ctx->win_updated, 1); 277c8466a91SJoonyoung Shim } 278c8466a91SJoonyoung Shim 2791e1d1393SGustavo Padovan static void decon_disable_plane(struct exynos_drm_crtc *crtc, 2801e1d1393SGustavo Padovan struct exynos_drm_plane *plane) 281c8466a91SJoonyoung Shim { 282c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 2831e1d1393SGustavo Padovan unsigned int win = plane->zpos; 284c8466a91SJoonyoung Shim u32 val; 285c8466a91SJoonyoung Shim 286c8466a91SJoonyoung Shim if (ctx->suspended) 287c8466a91SJoonyoung Shim return; 288c8466a91SJoonyoung Shim 289c8466a91SJoonyoung Shim decon_shadow_protect_win(ctx, win, true); 290c8466a91SJoonyoung Shim 291c8466a91SJoonyoung Shim /* window disable */ 292c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_WINCONx(win)); 293c8466a91SJoonyoung Shim val &= ~WINCONx_ENWIN_F; 294c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_WINCONx(win)); 295c8466a91SJoonyoung Shim 296c8466a91SJoonyoung Shim decon_shadow_protect_win(ctx, win, false); 297c8466a91SJoonyoung Shim 298c8466a91SJoonyoung Shim /* standalone update */ 299c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_UPDATE); 300c8466a91SJoonyoung Shim val |= STANDALONE_UPDATE_F; 301c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_UPDATE); 302c8466a91SJoonyoung Shim } 303c8466a91SJoonyoung Shim 304c8466a91SJoonyoung Shim static void decon_swreset(struct decon_context *ctx) 305c8466a91SJoonyoung Shim { 306c8466a91SJoonyoung Shim unsigned int tries; 307c8466a91SJoonyoung Shim 308c8466a91SJoonyoung Shim writel(0, ctx->addr + DECON_VIDCON0); 309c8466a91SJoonyoung Shim for (tries = 2000; tries; --tries) { 310c8466a91SJoonyoung Shim if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS) 311c8466a91SJoonyoung Shim break; 312c8466a91SJoonyoung Shim udelay(10); 313c8466a91SJoonyoung Shim } 314c8466a91SJoonyoung Shim 315c8466a91SJoonyoung Shim WARN(tries == 0, "failed to disable DECON\n"); 316c8466a91SJoonyoung Shim 317c8466a91SJoonyoung Shim writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); 318c8466a91SJoonyoung Shim for (tries = 2000; tries; --tries) { 319c8466a91SJoonyoung Shim if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET) 320c8466a91SJoonyoung Shim break; 321c8466a91SJoonyoung Shim udelay(10); 322c8466a91SJoonyoung Shim } 323c8466a91SJoonyoung Shim 324c8466a91SJoonyoung Shim WARN(tries == 0, "failed to software reset DECON\n"); 325c8466a91SJoonyoung Shim } 326c8466a91SJoonyoung Shim 327c8466a91SJoonyoung Shim static void decon_enable(struct exynos_drm_crtc *crtc) 328c8466a91SJoonyoung Shim { 329c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 330c8466a91SJoonyoung Shim int ret; 331c8466a91SJoonyoung Shim int i; 332c8466a91SJoonyoung Shim 333c8466a91SJoonyoung Shim if (!ctx->suspended) 334c8466a91SJoonyoung Shim return; 335c8466a91SJoonyoung Shim 336c8466a91SJoonyoung Shim ctx->suspended = false; 337c8466a91SJoonyoung Shim 338c8466a91SJoonyoung Shim pm_runtime_get_sync(ctx->dev); 339c8466a91SJoonyoung Shim 340c8466a91SJoonyoung Shim for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 341c8466a91SJoonyoung Shim ret = clk_prepare_enable(ctx->clks[i]); 342c8466a91SJoonyoung Shim if (ret < 0) 343c8466a91SJoonyoung Shim goto err; 344c8466a91SJoonyoung Shim } 345c8466a91SJoonyoung Shim 346c8466a91SJoonyoung Shim set_bit(BIT_CLKS_ENABLED, &ctx->enabled); 347c8466a91SJoonyoung Shim 348c8466a91SJoonyoung Shim /* if vblank was enabled status, enable it again. */ 349c8466a91SJoonyoung Shim if (test_and_clear_bit(0, &ctx->irq_flags)) 350c8466a91SJoonyoung Shim decon_enable_vblank(ctx->crtc); 351c8466a91SJoonyoung Shim 352c8466a91SJoonyoung Shim decon_commit(ctx->crtc); 353c8466a91SJoonyoung Shim 354c8466a91SJoonyoung Shim return; 355c8466a91SJoonyoung Shim err: 356c8466a91SJoonyoung Shim while (--i >= 0) 357c8466a91SJoonyoung Shim clk_disable_unprepare(ctx->clks[i]); 358c8466a91SJoonyoung Shim 359c8466a91SJoonyoung Shim ctx->suspended = true; 360c8466a91SJoonyoung Shim } 361c8466a91SJoonyoung Shim 362c8466a91SJoonyoung Shim static void decon_disable(struct exynos_drm_crtc *crtc) 363c8466a91SJoonyoung Shim { 364c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 365c8466a91SJoonyoung Shim int i; 366c8466a91SJoonyoung Shim 367c8466a91SJoonyoung Shim if (ctx->suspended) 368c8466a91SJoonyoung Shim return; 369c8466a91SJoonyoung Shim 370c8466a91SJoonyoung Shim /* 371c8466a91SJoonyoung Shim * We need to make sure that all windows are disabled before we 372c8466a91SJoonyoung Shim * suspend that connector. Otherwise we might try to scan from 373c8466a91SJoonyoung Shim * a destroyed buffer later. 374c8466a91SJoonyoung Shim */ 375c8466a91SJoonyoung Shim for (i = 0; i < WINDOWS_NR; i++) 3761e1d1393SGustavo Padovan decon_disable_plane(crtc, &ctx->planes[i]); 377c8466a91SJoonyoung Shim 378c8466a91SJoonyoung Shim decon_swreset(ctx); 379c8466a91SJoonyoung Shim 380c8466a91SJoonyoung Shim for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) 381c8466a91SJoonyoung Shim clk_disable_unprepare(ctx->clks[i]); 382c8466a91SJoonyoung Shim 383c8466a91SJoonyoung Shim clear_bit(BIT_CLKS_ENABLED, &ctx->enabled); 384c8466a91SJoonyoung Shim 385c8466a91SJoonyoung Shim pm_runtime_put_sync(ctx->dev); 386c8466a91SJoonyoung Shim 387c8466a91SJoonyoung Shim ctx->suspended = true; 388c8466a91SJoonyoung Shim } 389c8466a91SJoonyoung Shim 390c8466a91SJoonyoung Shim void decon_te_irq_handler(struct exynos_drm_crtc *crtc) 391c8466a91SJoonyoung Shim { 392c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 393c8466a91SJoonyoung Shim u32 val; 394c8466a91SJoonyoung Shim 395c8466a91SJoonyoung Shim if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) 396c8466a91SJoonyoung Shim return; 397c8466a91SJoonyoung Shim 398c8466a91SJoonyoung Shim if (atomic_add_unless(&ctx->win_updated, -1, 0)) { 399c8466a91SJoonyoung Shim /* trigger */ 400c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_TRIGCON); 401c8466a91SJoonyoung Shim val |= TRIGCON_SWTRIGCMD; 402c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_TRIGCON); 403c8466a91SJoonyoung Shim } 404c8466a91SJoonyoung Shim 405eafd540aSGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base); 406c8466a91SJoonyoung Shim } 407c8466a91SJoonyoung Shim 408c8466a91SJoonyoung Shim static void decon_clear_channels(struct exynos_drm_crtc *crtc) 409c8466a91SJoonyoung Shim { 410c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx; 411c8466a91SJoonyoung Shim int win, i, ret; 412c8466a91SJoonyoung Shim u32 val; 413c8466a91SJoonyoung Shim 414c8466a91SJoonyoung Shim DRM_DEBUG_KMS("%s\n", __FILE__); 415c8466a91SJoonyoung Shim 416c8466a91SJoonyoung Shim for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 417c8466a91SJoonyoung Shim ret = clk_prepare_enable(ctx->clks[i]); 418c8466a91SJoonyoung Shim if (ret < 0) 419c8466a91SJoonyoung Shim goto err; 420c8466a91SJoonyoung Shim } 421c8466a91SJoonyoung Shim 422c8466a91SJoonyoung Shim for (win = 0; win < WINDOWS_NR; win++) { 423c8466a91SJoonyoung Shim /* shadow update disable */ 424c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_SHADOWCON); 425c8466a91SJoonyoung Shim val |= SHADOWCON_Wx_PROTECT(win); 426c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_SHADOWCON); 427c8466a91SJoonyoung Shim 428c8466a91SJoonyoung Shim /* window disable */ 429c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_WINCONx(win)); 430c8466a91SJoonyoung Shim val &= ~WINCONx_ENWIN_F; 431c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_WINCONx(win)); 432c8466a91SJoonyoung Shim 433c8466a91SJoonyoung Shim /* shadow update enable */ 434c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_SHADOWCON); 435c8466a91SJoonyoung Shim val &= ~SHADOWCON_Wx_PROTECT(win); 436c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_SHADOWCON); 437c8466a91SJoonyoung Shim 438c8466a91SJoonyoung Shim /* standalone update */ 439c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_UPDATE); 440c8466a91SJoonyoung Shim val |= STANDALONE_UPDATE_F; 441c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_UPDATE); 442c8466a91SJoonyoung Shim } 443c8466a91SJoonyoung Shim /* TODO: wait for possible vsync */ 444c8466a91SJoonyoung Shim msleep(50); 445c8466a91SJoonyoung Shim 446c8466a91SJoonyoung Shim err: 447c8466a91SJoonyoung Shim while (--i >= 0) 448c8466a91SJoonyoung Shim clk_disable_unprepare(ctx->clks[i]); 449c8466a91SJoonyoung Shim } 450c8466a91SJoonyoung Shim 451c8466a91SJoonyoung Shim static struct exynos_drm_crtc_ops decon_crtc_ops = { 452c8466a91SJoonyoung Shim .enable = decon_enable, 453c8466a91SJoonyoung Shim .disable = decon_disable, 454c8466a91SJoonyoung Shim .commit = decon_commit, 455c8466a91SJoonyoung Shim .enable_vblank = decon_enable_vblank, 456c8466a91SJoonyoung Shim .disable_vblank = decon_disable_vblank, 457c8466a91SJoonyoung Shim .commit = decon_commit, 4589cc7610aSGustavo Padovan .update_plane = decon_update_plane, 4599cc7610aSGustavo Padovan .disable_plane = decon_disable_plane, 460c8466a91SJoonyoung Shim .te_handler = decon_te_irq_handler, 461c8466a91SJoonyoung Shim }; 462c8466a91SJoonyoung Shim 463c8466a91SJoonyoung Shim static int decon_bind(struct device *dev, struct device *master, void *data) 464c8466a91SJoonyoung Shim { 465c8466a91SJoonyoung Shim struct decon_context *ctx = dev_get_drvdata(dev); 466c8466a91SJoonyoung Shim struct drm_device *drm_dev = data; 467c8466a91SJoonyoung Shim struct exynos_drm_private *priv = drm_dev->dev_private; 468c8466a91SJoonyoung Shim struct exynos_drm_plane *exynos_plane; 469c8466a91SJoonyoung Shim enum drm_plane_type type; 470c8466a91SJoonyoung Shim unsigned int zpos; 471c8466a91SJoonyoung Shim int ret; 472c8466a91SJoonyoung Shim 473c8466a91SJoonyoung Shim ctx->drm_dev = drm_dev; 474c8466a91SJoonyoung Shim ctx->pipe = priv->pipe++; 475c8466a91SJoonyoung Shim 476c8466a91SJoonyoung Shim for (zpos = 0; zpos < WINDOWS_NR; zpos++) { 477c8466a91SJoonyoung Shim type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : 478c8466a91SJoonyoung Shim DRM_PLANE_TYPE_OVERLAY; 479c8466a91SJoonyoung Shim ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 480c8466a91SJoonyoung Shim 1 << ctx->pipe, type, zpos); 481c8466a91SJoonyoung Shim if (ret) 482c8466a91SJoonyoung Shim return ret; 483c8466a91SJoonyoung Shim } 484c8466a91SJoonyoung Shim 485c8466a91SJoonyoung Shim exynos_plane = &ctx->planes[ctx->default_win]; 486c8466a91SJoonyoung Shim ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, 487c8466a91SJoonyoung Shim ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, 488c8466a91SJoonyoung Shim &decon_crtc_ops, ctx); 489c8466a91SJoonyoung Shim if (IS_ERR(ctx->crtc)) { 490c8466a91SJoonyoung Shim ret = PTR_ERR(ctx->crtc); 491c8466a91SJoonyoung Shim goto err; 492c8466a91SJoonyoung Shim } 493c8466a91SJoonyoung Shim 494eb7a3fc7SJoonyoung Shim decon_clear_channels(ctx->crtc); 495eb7a3fc7SJoonyoung Shim 496eb7a3fc7SJoonyoung Shim ret = drm_iommu_attach_device(drm_dev, dev); 497c8466a91SJoonyoung Shim if (ret) 498c8466a91SJoonyoung Shim goto err; 499c8466a91SJoonyoung Shim 500c8466a91SJoonyoung Shim return ret; 501c8466a91SJoonyoung Shim err: 502c8466a91SJoonyoung Shim priv->pipe--; 503c8466a91SJoonyoung Shim return ret; 504c8466a91SJoonyoung Shim } 505c8466a91SJoonyoung Shim 506c8466a91SJoonyoung Shim static void decon_unbind(struct device *dev, struct device *master, void *data) 507c8466a91SJoonyoung Shim { 508c8466a91SJoonyoung Shim struct decon_context *ctx = dev_get_drvdata(dev); 509c8466a91SJoonyoung Shim 510c8466a91SJoonyoung Shim decon_disable(ctx->crtc); 511c8466a91SJoonyoung Shim 512c8466a91SJoonyoung Shim /* detach this sub driver from iommu mapping if supported. */ 513c8466a91SJoonyoung Shim drm_iommu_detach_device(ctx->drm_dev, ctx->dev); 514c8466a91SJoonyoung Shim } 515c8466a91SJoonyoung Shim 516c8466a91SJoonyoung Shim static const struct component_ops decon_component_ops = { 517c8466a91SJoonyoung Shim .bind = decon_bind, 518c8466a91SJoonyoung Shim .unbind = decon_unbind, 519c8466a91SJoonyoung Shim }; 520c8466a91SJoonyoung Shim 521c8466a91SJoonyoung Shim static irqreturn_t decon_vsync_irq_handler(int irq, void *dev_id) 522c8466a91SJoonyoung Shim { 523c8466a91SJoonyoung Shim struct decon_context *ctx = dev_id; 524c8466a91SJoonyoung Shim u32 val; 525c8466a91SJoonyoung Shim 526c8466a91SJoonyoung Shim if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) 527c8466a91SJoonyoung Shim goto out; 528c8466a91SJoonyoung Shim 529c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_VIDINTCON1); 530c8466a91SJoonyoung Shim if (val & VIDINTCON1_INTFRMPEND) { 531eafd540aSGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base); 532c8466a91SJoonyoung Shim 533c8466a91SJoonyoung Shim /* clear */ 534c8466a91SJoonyoung Shim writel(VIDINTCON1_INTFRMPEND, ctx->addr + DECON_VIDINTCON1); 535c8466a91SJoonyoung Shim } 536c8466a91SJoonyoung Shim 537c8466a91SJoonyoung Shim out: 538c8466a91SJoonyoung Shim return IRQ_HANDLED; 539c8466a91SJoonyoung Shim } 540c8466a91SJoonyoung Shim 541c8466a91SJoonyoung Shim static irqreturn_t decon_lcd_sys_irq_handler(int irq, void *dev_id) 542c8466a91SJoonyoung Shim { 543c8466a91SJoonyoung Shim struct decon_context *ctx = dev_id; 544c8466a91SJoonyoung Shim u32 val; 545c8466a91SJoonyoung Shim 546c8466a91SJoonyoung Shim if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) 547c8466a91SJoonyoung Shim goto out; 548c8466a91SJoonyoung Shim 549c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_VIDINTCON1); 550c8466a91SJoonyoung Shim if (val & VIDINTCON1_INTFRMDONEPEND) { 551eafd540aSGustavo Padovan exynos_drm_crtc_finish_pageflip(ctx->crtc); 552c8466a91SJoonyoung Shim 553c8466a91SJoonyoung Shim /* clear */ 554c8466a91SJoonyoung Shim writel(VIDINTCON1_INTFRMDONEPEND, 555c8466a91SJoonyoung Shim ctx->addr + DECON_VIDINTCON1); 556c8466a91SJoonyoung Shim } 557c8466a91SJoonyoung Shim 558c8466a91SJoonyoung Shim out: 559c8466a91SJoonyoung Shim return IRQ_HANDLED; 560c8466a91SJoonyoung Shim } 561c8466a91SJoonyoung Shim 562c8466a91SJoonyoung Shim static int exynos5433_decon_probe(struct platform_device *pdev) 563c8466a91SJoonyoung Shim { 564c8466a91SJoonyoung Shim struct device *dev = &pdev->dev; 565c8466a91SJoonyoung Shim struct decon_context *ctx; 566c8466a91SJoonyoung Shim struct resource *res; 567c8466a91SJoonyoung Shim int ret; 568c8466a91SJoonyoung Shim int i; 569c8466a91SJoonyoung Shim 570c8466a91SJoonyoung Shim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 571c8466a91SJoonyoung Shim if (!ctx) 572c8466a91SJoonyoung Shim return -ENOMEM; 573c8466a91SJoonyoung Shim 574c8466a91SJoonyoung Shim ctx->default_win = 0; 575c8466a91SJoonyoung Shim ctx->suspended = true; 576c8466a91SJoonyoung Shim ctx->dev = dev; 577c8466a91SJoonyoung Shim if (of_get_child_by_name(dev->of_node, "i80-if-timings")) 578c8466a91SJoonyoung Shim ctx->i80_if = true; 579c8466a91SJoonyoung Shim 580c8466a91SJoonyoung Shim for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { 581c8466a91SJoonyoung Shim struct clk *clk; 582c8466a91SJoonyoung Shim 583c8466a91SJoonyoung Shim clk = devm_clk_get(ctx->dev, decon_clks_name[i]); 584c8466a91SJoonyoung Shim if (IS_ERR(clk)) 585c8466a91SJoonyoung Shim return PTR_ERR(clk); 586c8466a91SJoonyoung Shim 587c8466a91SJoonyoung Shim ctx->clks[i] = clk; 588c8466a91SJoonyoung Shim } 589c8466a91SJoonyoung Shim 590c8466a91SJoonyoung Shim res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 591c8466a91SJoonyoung Shim if (!res) { 592c8466a91SJoonyoung Shim dev_err(dev, "cannot find IO resource\n"); 593c8466a91SJoonyoung Shim return -ENXIO; 594c8466a91SJoonyoung Shim } 595c8466a91SJoonyoung Shim 596c8466a91SJoonyoung Shim ctx->addr = devm_ioremap_resource(dev, res); 597c8466a91SJoonyoung Shim if (IS_ERR(ctx->addr)) { 598c8466a91SJoonyoung Shim dev_err(dev, "ioremap failed\n"); 599c8466a91SJoonyoung Shim return PTR_ERR(ctx->addr); 600c8466a91SJoonyoung Shim } 601c8466a91SJoonyoung Shim 602c8466a91SJoonyoung Shim res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 603c8466a91SJoonyoung Shim ctx->i80_if ? "lcd_sys" : "vsync"); 604c8466a91SJoonyoung Shim if (!res) { 605c8466a91SJoonyoung Shim dev_err(dev, "cannot find IRQ resource\n"); 606c8466a91SJoonyoung Shim return -ENXIO; 607c8466a91SJoonyoung Shim } 608c8466a91SJoonyoung Shim 609c8466a91SJoonyoung Shim ret = devm_request_irq(dev, res->start, ctx->i80_if ? 610c8466a91SJoonyoung Shim decon_lcd_sys_irq_handler : decon_vsync_irq_handler, 0, 611c8466a91SJoonyoung Shim "drm_decon", ctx); 612c8466a91SJoonyoung Shim if (ret < 0) { 613c8466a91SJoonyoung Shim dev_err(dev, "lcd_sys irq request failed\n"); 614c8466a91SJoonyoung Shim return ret; 615c8466a91SJoonyoung Shim } 616c8466a91SJoonyoung Shim 617c8466a91SJoonyoung Shim platform_set_drvdata(pdev, ctx); 618c8466a91SJoonyoung Shim 619c8466a91SJoonyoung Shim pm_runtime_enable(dev); 620c8466a91SJoonyoung Shim 621c8466a91SJoonyoung Shim ret = component_add(dev, &decon_component_ops); 622c8466a91SJoonyoung Shim if (ret) 623c8466a91SJoonyoung Shim goto err_disable_pm_runtime; 624c8466a91SJoonyoung Shim 625c8466a91SJoonyoung Shim return 0; 626c8466a91SJoonyoung Shim 627c8466a91SJoonyoung Shim err_disable_pm_runtime: 628c8466a91SJoonyoung Shim pm_runtime_disable(dev); 629c8466a91SJoonyoung Shim 630c8466a91SJoonyoung Shim return ret; 631c8466a91SJoonyoung Shim } 632c8466a91SJoonyoung Shim 633c8466a91SJoonyoung Shim static int exynos5433_decon_remove(struct platform_device *pdev) 634c8466a91SJoonyoung Shim { 635c8466a91SJoonyoung Shim pm_runtime_disable(&pdev->dev); 636c8466a91SJoonyoung Shim 637c8466a91SJoonyoung Shim component_del(&pdev->dev, &decon_component_ops); 638c8466a91SJoonyoung Shim 639c8466a91SJoonyoung Shim return 0; 640c8466a91SJoonyoung Shim } 641c8466a91SJoonyoung Shim 642c8466a91SJoonyoung Shim static const struct of_device_id exynos5433_decon_driver_dt_match[] = { 643c8466a91SJoonyoung Shim { .compatible = "samsung,exynos5433-decon" }, 644c8466a91SJoonyoung Shim {}, 645c8466a91SJoonyoung Shim }; 646c8466a91SJoonyoung Shim MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); 647c8466a91SJoonyoung Shim 648c8466a91SJoonyoung Shim struct platform_driver exynos5433_decon_driver = { 649c8466a91SJoonyoung Shim .probe = exynos5433_decon_probe, 650c8466a91SJoonyoung Shim .remove = exynos5433_decon_remove, 651c8466a91SJoonyoung Shim .driver = { 652c8466a91SJoonyoung Shim .name = "exynos5433-decon", 653c8466a91SJoonyoung Shim .of_match_table = exynos5433_decon_driver_dt_match, 654c8466a91SJoonyoung Shim }, 655c8466a91SJoonyoung Shim }; 656