19f06080fSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2c8466a91SJoonyoung Shim /* drivers/gpu/drm/exynos5433_drm_decon.c
3c8466a91SJoonyoung Shim *
4c8466a91SJoonyoung Shim * Copyright (C) 2015 Samsung Electronics Co.Ltd
5c8466a91SJoonyoung Shim * Authors:
6c8466a91SJoonyoung Shim * Joonyoung Shim <jy0922.shim@samsung.com>
7c8466a91SJoonyoung Shim * Hyungwon Hwang <human.hwang@samsung.com>
8c8466a91SJoonyoung Shim */
9c8466a91SJoonyoung Shim
10c8466a91SJoonyoung Shim #include <linux/clk.h>
11c8466a91SJoonyoung Shim #include <linux/component.h>
1230b8913fSAndrzej Hajda #include <linux/iopoll.h>
139ac30ef6SArnd Bergmann #include <linux/irq.h>
14b93c2e8bSAndrzej Hajda #include <linux/mfd/syscon.h>
15722d4f06SRob Herring #include <linux/of.h>
162bda34d7SSam Ravnborg #include <linux/platform_device.h>
17c8466a91SJoonyoung Shim #include <linux/pm_runtime.h>
18b93c2e8bSAndrzej Hajda #include <linux/regmap.h>
19c8466a91SJoonyoung Shim
2090bb087fSVille Syrjälä #include <drm/drm_blend.h>
212bda34d7SSam Ravnborg #include <drm/drm_fourcc.h>
22720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
232bda34d7SSam Ravnborg #include <drm/drm_vblank.h>
242bda34d7SSam Ravnborg
25c8466a91SJoonyoung Shim #include "exynos_drm_crtc.h"
262bda34d7SSam Ravnborg #include "exynos_drm_drv.h"
270488f50eSMarek Szyprowski #include "exynos_drm_fb.h"
28c8466a91SJoonyoung Shim #include "exynos_drm_plane.h"
294f52e550SKrzysztof Kozlowski #include "regs-decon5433.h"
30c8466a91SJoonyoung Shim
31b93c2e8bSAndrzej Hajda #define DSD_CFG_MUX 0x1004
32b93c2e8bSAndrzej Hajda #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
33b93c2e8bSAndrzej Hajda
34cb5fba71SMarek Szyprowski #define WINDOWS_NR 5
35cb5fba71SMarek Szyprowski #define PRIMARY_WIN 2
36cb5fba71SMarek Szyprowski #define CURSON_WIN 4
37cb5fba71SMarek Szyprowski
38c8466a91SJoonyoung Shim #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
39c8466a91SJoonyoung Shim
40461e60eaSAndrzej Hajda #define I80_HW_TRG (1 << 0)
41461e60eaSAndrzej Hajda #define IFTYPE_HDMI (1 << 1)
429ac26de8SInki Dae
434f54f21cSAndrzej Hajda static const char * const decon_clks_name[] = {
444f54f21cSAndrzej Hajda "pclk",
454f54f21cSAndrzej Hajda "aclk_decon",
464f54f21cSAndrzej Hajda "aclk_smmu_decon0x",
474f54f21cSAndrzej Hajda "aclk_xiu_decon0x",
484f54f21cSAndrzej Hajda "pclk_smmu_decon0x",
49cb5fba71SMarek Szyprowski "aclk_smmu_decon1x",
50cb5fba71SMarek Szyprowski "aclk_xiu_decon1x",
51cb5fba71SMarek Szyprowski "pclk_smmu_decon1x",
524f54f21cSAndrzej Hajda "sclk_decon_vclk",
534f54f21cSAndrzej Hajda "sclk_decon_eclk",
544f54f21cSAndrzej Hajda };
554f54f21cSAndrzej Hajda
56c8466a91SJoonyoung Shim struct decon_context {
57c8466a91SJoonyoung Shim struct device *dev;
58c8466a91SJoonyoung Shim struct drm_device *drm_dev;
5907dc3678SMarek Szyprowski void *dma_priv;
60c8466a91SJoonyoung Shim struct exynos_drm_crtc *crtc;
61c8466a91SJoonyoung Shim struct exynos_drm_plane planes[WINDOWS_NR];
62fd2d2fc2SMarek Szyprowski struct exynos_drm_plane_config configs[WINDOWS_NR];
63c8466a91SJoonyoung Shim void __iomem *addr;
64b93c2e8bSAndrzej Hajda struct regmap *sysreg;
654f54f21cSAndrzej Hajda struct clk *clks[ARRAY_SIZE(decon_clks_name)];
66b37d53a0SAndrzej Hajda unsigned int irq;
6734c3db6cSAndrzej Hajda unsigned int irq_vsync;
6834c3db6cSAndrzej Hajda unsigned int irq_lcd_sys;
69b37d53a0SAndrzej Hajda unsigned int te_irq;
709ac26de8SInki Dae unsigned long out_type;
71b8182832SAndrzej Hajda int first_win;
7273488331SAndrzej Hajda spinlock_t vblank_lock;
7373488331SAndrzej Hajda u32 frame_id;
74c8466a91SJoonyoung Shim };
75c8466a91SJoonyoung Shim
76fbbb1e1aSMarek Szyprowski static const uint32_t decon_formats[] = {
77fbbb1e1aSMarek Szyprowski DRM_FORMAT_XRGB1555,
78fbbb1e1aSMarek Szyprowski DRM_FORMAT_RGB565,
79fbbb1e1aSMarek Szyprowski DRM_FORMAT_XRGB8888,
80fbbb1e1aSMarek Szyprowski DRM_FORMAT_ARGB8888,
81fbbb1e1aSMarek Szyprowski };
82fbbb1e1aSMarek Szyprowski
83fd2d2fc2SMarek Szyprowski static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
84cb5fba71SMarek Szyprowski [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
85cb5fba71SMarek Szyprowski [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
86fd2d2fc2SMarek Szyprowski };
87fd2d2fc2SMarek Szyprowski
8854947290SChristoph Manszewski static const unsigned int capabilities[WINDOWS_NR] = {
8954947290SChristoph Manszewski 0,
90af130280SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
91af130280SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
92af130280SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
93af130280SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
9454947290SChristoph Manszewski };
9554947290SChristoph Manszewski
decon_set_bits(struct decon_context * ctx,u32 reg,u32 mask,u32 val)96b2192073SAndrzej Hajda static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
97b2192073SAndrzej Hajda u32 val)
98b2192073SAndrzej Hajda {
99b2192073SAndrzej Hajda val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
100b2192073SAndrzej Hajda writel(val, ctx->addr + reg);
101b2192073SAndrzej Hajda }
102b2192073SAndrzej Hajda
decon_enable_vblank(struct exynos_drm_crtc * crtc)103c8466a91SJoonyoung Shim static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
104c8466a91SJoonyoung Shim {
105c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
106c8466a91SJoonyoung Shim u32 val;
107c8466a91SJoonyoung Shim
108c8466a91SJoonyoung Shim val = VIDINTCON0_INTEN;
109461e60eaSAndrzej Hajda if (crtc->i80_mode)
110c8466a91SJoonyoung Shim val |= VIDINTCON0_FRAMEDONE;
111c8466a91SJoonyoung Shim else
112f3cce673SAndrzej Hajda val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
113c8466a91SJoonyoung Shim
114c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDINTCON0);
115b37d53a0SAndrzej Hajda
116b37d53a0SAndrzej Hajda enable_irq(ctx->irq);
117b37d53a0SAndrzej Hajda if (!(ctx->out_type & I80_HW_TRG))
118b37d53a0SAndrzej Hajda enable_irq(ctx->te_irq);
119b37d53a0SAndrzej Hajda
120c8466a91SJoonyoung Shim return 0;
121c8466a91SJoonyoung Shim }
122c8466a91SJoonyoung Shim
decon_disable_vblank(struct exynos_drm_crtc * crtc)123c8466a91SJoonyoung Shim static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
124c8466a91SJoonyoung Shim {
125c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
126c8466a91SJoonyoung Shim
127b37d53a0SAndrzej Hajda if (!(ctx->out_type & I80_HW_TRG))
128b37d53a0SAndrzej Hajda disable_irq_nosync(ctx->te_irq);
129b37d53a0SAndrzej Hajda disable_irq_nosync(ctx->irq);
130b37d53a0SAndrzej Hajda
131c8466a91SJoonyoung Shim writel(0, ctx->addr + DECON_VIDINTCON0);
132c8466a91SJoonyoung Shim }
133c8466a91SJoonyoung Shim
13473488331SAndrzej Hajda /* return number of starts/ends of frame transmissions since reset */
decon_get_frame_count(struct decon_context * ctx,bool end)13573488331SAndrzej Hajda static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
13673488331SAndrzej Hajda {
13773488331SAndrzej Hajda u32 frm, pfrm, status, cnt = 2;
13873488331SAndrzej Hajda
13973488331SAndrzej Hajda /* To get consistent result repeat read until frame id is stable.
14073488331SAndrzej Hajda * Usually the loop will be executed once, in rare cases when the loop
14173488331SAndrzej Hajda * is executed at frame change time 2nd pass will be needed.
14273488331SAndrzej Hajda */
14373488331SAndrzej Hajda frm = readl(ctx->addr + DECON_CRFMID);
14473488331SAndrzej Hajda do {
14573488331SAndrzej Hajda status = readl(ctx->addr + DECON_VIDCON1);
14673488331SAndrzej Hajda pfrm = frm;
14773488331SAndrzej Hajda frm = readl(ctx->addr + DECON_CRFMID);
14873488331SAndrzej Hajda } while (frm != pfrm && --cnt);
14973488331SAndrzej Hajda
15073488331SAndrzej Hajda /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
15173488331SAndrzej Hajda * of RGB, it should be taken into account.
15273488331SAndrzej Hajda */
15373488331SAndrzej Hajda if (!frm)
15473488331SAndrzej Hajda return 0;
15573488331SAndrzej Hajda
15673488331SAndrzej Hajda switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
15773488331SAndrzej Hajda case VIDCON1_VSTATUS_VS:
158461e60eaSAndrzej Hajda if (!(ctx->crtc->i80_mode))
15973488331SAndrzej Hajda --frm;
16073488331SAndrzej Hajda break;
16173488331SAndrzej Hajda case VIDCON1_VSTATUS_BP:
16273488331SAndrzej Hajda --frm;
16373488331SAndrzej Hajda break;
16473488331SAndrzej Hajda case VIDCON1_I80_ACTIVE:
16573488331SAndrzej Hajda case VIDCON1_VSTATUS_AC:
16673488331SAndrzej Hajda if (end)
16773488331SAndrzej Hajda --frm;
16873488331SAndrzej Hajda break;
16973488331SAndrzej Hajda default:
17073488331SAndrzej Hajda break;
17173488331SAndrzej Hajda }
17273488331SAndrzej Hajda
17373488331SAndrzej Hajda return frm;
17473488331SAndrzej Hajda }
17573488331SAndrzej Hajda
decon_setup_trigger(struct decon_context * ctx)176c8466a91SJoonyoung Shim static void decon_setup_trigger(struct decon_context *ctx)
177c8466a91SJoonyoung Shim {
178461e60eaSAndrzej Hajda if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
179b93c2e8bSAndrzej Hajda return;
180b93c2e8bSAndrzej Hajda
181b93c2e8bSAndrzej Hajda if (!(ctx->out_type & I80_HW_TRG)) {
182f07d9c28SAndrzej Hajda writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
183f07d9c28SAndrzej Hajda TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
184b93c2e8bSAndrzej Hajda ctx->addr + DECON_TRIGCON);
185b93c2e8bSAndrzej Hajda return;
186b93c2e8bSAndrzej Hajda }
187b93c2e8bSAndrzej Hajda
188b93c2e8bSAndrzej Hajda writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
189b93c2e8bSAndrzej Hajda | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
190b93c2e8bSAndrzej Hajda
191b93c2e8bSAndrzej Hajda if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
192b93c2e8bSAndrzej Hajda DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
1936f83d208SInki Dae DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
194c8466a91SJoonyoung Shim }
195c8466a91SJoonyoung Shim
decon_commit(struct exynos_drm_crtc * crtc)196c8466a91SJoonyoung Shim static void decon_commit(struct exynos_drm_crtc *crtc)
197c8466a91SJoonyoung Shim {
198c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
19985de275aSAndrzej Hajda struct drm_display_mode *m = &crtc->base.mode;
2005aa6c9acSAndrzej Hajda bool interlaced = false;
201c8466a91SJoonyoung Shim u32 val;
202c8466a91SJoonyoung Shim
2039ac26de8SInki Dae if (ctx->out_type & IFTYPE_HDMI) {
204b8182832SAndrzej Hajda m->crtc_hsync_start = m->crtc_hdisplay + 10;
205b8182832SAndrzej Hajda m->crtc_hsync_end = m->crtc_htotal - 92;
206b8182832SAndrzej Hajda m->crtc_vsync_start = m->crtc_vdisplay + 1;
207b8182832SAndrzej Hajda m->crtc_vsync_end = m->crtc_vsync_start + 1;
2085aa6c9acSAndrzej Hajda if (m->flags & DRM_MODE_FLAG_INTERLACE)
2095aa6c9acSAndrzej Hajda interlaced = true;
210b8182832SAndrzej Hajda }
211b8182832SAndrzej Hajda
212dd65a686SAndrzej Hajda decon_setup_trigger(ctx);
213dd65a686SAndrzej Hajda
214c8466a91SJoonyoung Shim /* lcd on and use command if */
215c8466a91SJoonyoung Shim val = VIDOUT_LCD_ON;
2165aa6c9acSAndrzej Hajda if (interlaced)
2175aa6c9acSAndrzej Hajda val |= VIDOUT_INTERLACE_EN_F;
218461e60eaSAndrzej Hajda if (crtc->i80_mode) {
219c8466a91SJoonyoung Shim val |= VIDOUT_COMMAND_IF;
2209ac26de8SInki Dae } else {
221c8466a91SJoonyoung Shim val |= VIDOUT_RGB_IF;
2229ac26de8SInki Dae }
2239ac26de8SInki Dae
224c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOUTCON0);
225c8466a91SJoonyoung Shim
2265aa6c9acSAndrzej Hajda if (interlaced)
2275aa6c9acSAndrzej Hajda val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
2285aa6c9acSAndrzej Hajda VIDTCON2_HOZVAL(m->hdisplay - 1);
2295aa6c9acSAndrzej Hajda else
23085de275aSAndrzej Hajda val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
23185de275aSAndrzej Hajda VIDTCON2_HOZVAL(m->hdisplay - 1);
232c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON2);
233c8466a91SJoonyoung Shim
234461e60eaSAndrzej Hajda if (!crtc->i80_mode) {
2355aa6c9acSAndrzej Hajda int vbp = m->crtc_vtotal - m->crtc_vsync_end;
2365aa6c9acSAndrzej Hajda int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
2375aa6c9acSAndrzej Hajda
2385aa6c9acSAndrzej Hajda if (interlaced)
2395aa6c9acSAndrzej Hajda vbp = vbp / 2 - 1;
2405aa6c9acSAndrzej Hajda val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
241c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON00);
242c8466a91SJoonyoung Shim
243c8466a91SJoonyoung Shim val = VIDTCON01_VSPW_F(
24485de275aSAndrzej Hajda m->crtc_vsync_end - m->crtc_vsync_start - 1);
245c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON01);
246c8466a91SJoonyoung Shim
247c8466a91SJoonyoung Shim val = VIDTCON10_HBPD_F(
24885de275aSAndrzej Hajda m->crtc_htotal - m->crtc_hsync_end - 1) |
249c8466a91SJoonyoung Shim VIDTCON10_HFPD_F(
25085de275aSAndrzej Hajda m->crtc_hsync_start - m->crtc_hdisplay - 1);
251c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON10);
252c8466a91SJoonyoung Shim
253c8466a91SJoonyoung Shim val = VIDTCON11_HSPW_F(
25485de275aSAndrzej Hajda m->crtc_hsync_end - m->crtc_hsync_start - 1);
255c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDTCON11);
256c8466a91SJoonyoung Shim }
257c8466a91SJoonyoung Shim
258c8466a91SJoonyoung Shim /* enable output and display signal */
259b8182832SAndrzej Hajda decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
26092ead494SAndrzej Hajda
26192ead494SAndrzej Hajda decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
262c8466a91SJoonyoung Shim }
263c8466a91SJoonyoung Shim
decon_win_set_bldeq(struct decon_context * ctx,unsigned int win,unsigned int alpha,unsigned int pixel_alpha)264af130280SChristoph Manszewski static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
265af130280SChristoph Manszewski unsigned int alpha, unsigned int pixel_alpha)
266af130280SChristoph Manszewski {
267af130280SChristoph Manszewski u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
268af130280SChristoph Manszewski u32 val = 0;
269af130280SChristoph Manszewski
270af130280SChristoph Manszewski switch (pixel_alpha) {
271af130280SChristoph Manszewski case DRM_MODE_BLEND_PIXEL_NONE:
272af130280SChristoph Manszewski case DRM_MODE_BLEND_COVERAGE:
273af130280SChristoph Manszewski val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
274af130280SChristoph Manszewski val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
275af130280SChristoph Manszewski break;
276af130280SChristoph Manszewski case DRM_MODE_BLEND_PREMULTI:
277af130280SChristoph Manszewski default:
278af130280SChristoph Manszewski if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
279af130280SChristoph Manszewski val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
280af130280SChristoph Manszewski val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
281af130280SChristoph Manszewski } else {
282af130280SChristoph Manszewski val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
283af130280SChristoph Manszewski val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
284af130280SChristoph Manszewski }
285af130280SChristoph Manszewski break;
286af130280SChristoph Manszewski }
287af130280SChristoph Manszewski decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
288af130280SChristoph Manszewski }
28954947290SChristoph Manszewski
decon_win_set_bldmod(struct decon_context * ctx,unsigned int win,unsigned int alpha,unsigned int pixel_alpha)29054947290SChristoph Manszewski static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
291af130280SChristoph Manszewski unsigned int alpha, unsigned int pixel_alpha)
29254947290SChristoph Manszewski {
29354947290SChristoph Manszewski u32 win_alpha = alpha >> 8;
29454947290SChristoph Manszewski u32 val = 0;
29554947290SChristoph Manszewski
296af130280SChristoph Manszewski switch (pixel_alpha) {
297af130280SChristoph Manszewski case DRM_MODE_BLEND_PIXEL_NONE:
298af130280SChristoph Manszewski break;
299af130280SChristoph Manszewski case DRM_MODE_BLEND_COVERAGE:
300af130280SChristoph Manszewski case DRM_MODE_BLEND_PREMULTI:
301af130280SChristoph Manszewski default:
302af130280SChristoph Manszewski val |= WINCONx_ALPHA_SEL_F;
303af130280SChristoph Manszewski val |= WINCONx_BLD_PIX_F;
304af130280SChristoph Manszewski val |= WINCONx_ALPHA_MUL_F;
305af130280SChristoph Manszewski break;
306af130280SChristoph Manszewski }
307af130280SChristoph Manszewski decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
308af130280SChristoph Manszewski
30954947290SChristoph Manszewski if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
31054947290SChristoph Manszewski val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
31154947290SChristoph Manszewski VIDOSD_Wx_ALPHA_G_F(win_alpha) |
31254947290SChristoph Manszewski VIDOSD_Wx_ALPHA_B_F(win_alpha);
31354947290SChristoph Manszewski decon_set_bits(ctx, DECON_VIDOSDxC(win),
31454947290SChristoph Manszewski VIDOSDxC_ALPHA0_RGB_MASK, val);
31554947290SChristoph Manszewski decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
31654947290SChristoph Manszewski }
31754947290SChristoph Manszewski }
31854947290SChristoph Manszewski
decon_win_set_pixfmt(struct decon_context * ctx,unsigned int win,struct drm_framebuffer * fb)3192eeb2e5eSGustavo Padovan static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
3202eeb2e5eSGustavo Padovan struct drm_framebuffer *fb)
321c8466a91SJoonyoung Shim {
322*38a31370SArnd Bergmann struct exynos_drm_plane *plane = &ctx->planes[win];
32354947290SChristoph Manszewski struct exynos_drm_plane_state *state =
324*38a31370SArnd Bergmann to_exynos_plane_state(plane->base.state);
32554947290SChristoph Manszewski unsigned int alpha = state->base.alpha;
326af130280SChristoph Manszewski unsigned int pixel_alpha;
327c8466a91SJoonyoung Shim unsigned long val;
328c8466a91SJoonyoung Shim
329af130280SChristoph Manszewski if (fb->format->has_alpha)
330af130280SChristoph Manszewski pixel_alpha = state->base.pixel_blend_mode;
331af130280SChristoph Manszewski else
332af130280SChristoph Manszewski pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
333af130280SChristoph Manszewski
334c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_WINCONx(win));
3357b7aa62cSMarek Szyprowski val &= WINCONx_ENWIN_F;
336c8466a91SJoonyoung Shim
337438b74a5SVille Syrjälä switch (fb->format->format) {
338c8466a91SJoonyoung Shim case DRM_FORMAT_XRGB1555:
339c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_16BPP_I1555;
340c8466a91SJoonyoung Shim val |= WINCONx_HAWSWP_F;
341c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD;
342c8466a91SJoonyoung Shim break;
343c8466a91SJoonyoung Shim case DRM_FORMAT_RGB565:
344c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_16BPP_565;
345c8466a91SJoonyoung Shim val |= WINCONx_HAWSWP_F;
346c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD;
347c8466a91SJoonyoung Shim break;
348c8466a91SJoonyoung Shim case DRM_FORMAT_XRGB8888:
349c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_24BPP_888;
350c8466a91SJoonyoung Shim val |= WINCONx_WSWP_F;
351c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD;
352c8466a91SJoonyoung Shim break;
353c8466a91SJoonyoung Shim case DRM_FORMAT_ARGB8888:
3545b7b1b7fSTobias Jakobi default:
355c8466a91SJoonyoung Shim val |= WINCONx_BPPMODE_32BPP_A8888;
356af130280SChristoph Manszewski val |= WINCONx_WSWP_F;
357c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_16WORD;
358c8466a91SJoonyoung Shim break;
359c8466a91SJoonyoung Shim }
360c8466a91SJoonyoung Shim
3616be90056SInki Dae DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
362c8466a91SJoonyoung Shim
363c8466a91SJoonyoung Shim /*
364c8466a91SJoonyoung Shim * In case of exynos, setting dma-burst to 16Word causes permanent
365c8466a91SJoonyoung Shim * tearing for very small buffers, e.g. cursor buffer. Burst Mode
366c8466a91SJoonyoung Shim * switching which is based on plane size is not recommended as
367c8466a91SJoonyoung Shim * plane size varies a lot towards the end of the screen and rapid
368c8466a91SJoonyoung Shim * movement causes unstable DMA which results into iommu crash/tear.
369c8466a91SJoonyoung Shim */
370c8466a91SJoonyoung Shim
3712eeb2e5eSGustavo Padovan if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
372c8466a91SJoonyoung Shim val &= ~WINCONx_BURSTLEN_MASK;
373c8466a91SJoonyoung Shim val |= WINCONx_BURSTLEN_8WORD;
374c8466a91SJoonyoung Shim }
375af130280SChristoph Manszewski decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
376c8466a91SJoonyoung Shim
377af130280SChristoph Manszewski if (win > 0) {
378af130280SChristoph Manszewski decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
379af130280SChristoph Manszewski decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
380af130280SChristoph Manszewski }
381c8466a91SJoonyoung Shim }
382c8466a91SJoonyoung Shim
decon_shadow_protect(struct decon_context * ctx,bool protect)383b2adc530SAndrzej Hajda static void decon_shadow_protect(struct decon_context *ctx, bool protect)
384c8466a91SJoonyoung Shim {
385b2adc530SAndrzej Hajda decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
386b2192073SAndrzej Hajda protect ? ~0 : 0);
387c8466a91SJoonyoung Shim }
388c8466a91SJoonyoung Shim
decon_atomic_begin(struct exynos_drm_crtc * crtc)389d29c2c14SMarek Szyprowski static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
390cc5a7b35SHyungwon Hwang {
391cc5a7b35SHyungwon Hwang struct decon_context *ctx = crtc->ctx;
392cc5a7b35SHyungwon Hwang
393b2adc530SAndrzej Hajda decon_shadow_protect(ctx, true);
394cc5a7b35SHyungwon Hwang }
395cc5a7b35SHyungwon Hwang
396b8182832SAndrzej Hajda #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
397b8182832SAndrzej Hajda #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
398b8182832SAndrzej Hajda #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
399b8182832SAndrzej Hajda
decon_update_plane(struct exynos_drm_crtc * crtc,struct exynos_drm_plane * plane)4001e1d1393SGustavo Padovan static void decon_update_plane(struct exynos_drm_crtc *crtc,
4011e1d1393SGustavo Padovan struct exynos_drm_plane *plane)
402c8466a91SJoonyoung Shim {
4030114f404SMarek Szyprowski struct exynos_drm_plane_state *state =
4040114f404SMarek Szyprowski to_exynos_plane_state(plane->base.state);
405c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
4060114f404SMarek Szyprowski struct drm_framebuffer *fb = state->base.fb;
40740bdfb0aSMarek Szyprowski unsigned int win = plane->index;
408ac60944cSTobias Jakobi unsigned int cpp = fb->format->cpp[0];
4090488f50eSMarek Szyprowski unsigned int pitch = fb->pitches[0];
4100488f50eSMarek Szyprowski dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
411c8466a91SJoonyoung Shim u32 val;
412c8466a91SJoonyoung Shim
4135aa6c9acSAndrzej Hajda if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
4145aa6c9acSAndrzej Hajda val = COORDINATE_X(state->crtc.x) |
4155aa6c9acSAndrzej Hajda COORDINATE_Y(state->crtc.y / 2);
4165aa6c9acSAndrzej Hajda writel(val, ctx->addr + DECON_VIDOSDxA(win));
4175aa6c9acSAndrzej Hajda
4185aa6c9acSAndrzej Hajda val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
4195aa6c9acSAndrzej Hajda COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
4205aa6c9acSAndrzej Hajda writel(val, ctx->addr + DECON_VIDOSDxB(win));
4215aa6c9acSAndrzej Hajda } else {
4220114f404SMarek Szyprowski val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
423c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxA(win));
424c8466a91SJoonyoung Shim
4250114f404SMarek Szyprowski val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
4260114f404SMarek Szyprowski COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
427c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxB(win));
4285aa6c9acSAndrzej Hajda }
429c8466a91SJoonyoung Shim
430ab337fc2SMarek Szyprowski val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
431ab337fc2SMarek Szyprowski VIDOSD_Wx_ALPHA_B_F(0xff);
432c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxC(win));
433c8466a91SJoonyoung Shim
434c8466a91SJoonyoung Shim val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
435c8466a91SJoonyoung Shim VIDOSD_Wx_ALPHA_B_F(0x0);
436c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDOSDxD(win));
437c8466a91SJoonyoung Shim
4380488f50eSMarek Szyprowski writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
439c8466a91SJoonyoung Shim
4400114f404SMarek Szyprowski val = dma_addr + pitch * state->src.h;
441c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
442c8466a91SJoonyoung Shim
4439ac26de8SInki Dae if (!(ctx->out_type & IFTYPE_HDMI))
444ac60944cSTobias Jakobi val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
445ac60944cSTobias Jakobi | BIT_VAL(state->crtc.w * cpp, 13, 0);
446b8182832SAndrzej Hajda else
447ac60944cSTobias Jakobi val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
448ac60944cSTobias Jakobi | BIT_VAL(state->crtc.w * cpp, 14, 0);
449c8466a91SJoonyoung Shim writel(val, ctx->addr + DECON_VIDW0xADD2(win));
450c8466a91SJoonyoung Shim
4510488f50eSMarek Szyprowski decon_win_set_pixfmt(ctx, win, fb);
452c8466a91SJoonyoung Shim
453c8466a91SJoonyoung Shim /* window enable */
454b2192073SAndrzej Hajda decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
455c8466a91SJoonyoung Shim }
456c8466a91SJoonyoung Shim
decon_disable_plane(struct exynos_drm_crtc * crtc,struct exynos_drm_plane * plane)4571e1d1393SGustavo Padovan static void decon_disable_plane(struct exynos_drm_crtc *crtc,
4581e1d1393SGustavo Padovan struct exynos_drm_plane *plane)
459c8466a91SJoonyoung Shim {
460c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
46140bdfb0aSMarek Szyprowski unsigned int win = plane->index;
462c8466a91SJoonyoung Shim
463b2192073SAndrzej Hajda decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
464c8466a91SJoonyoung Shim }
465c8466a91SJoonyoung Shim
decon_atomic_flush(struct exynos_drm_crtc * crtc)466d29c2c14SMarek Szyprowski static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
467cc5a7b35SHyungwon Hwang {
468cc5a7b35SHyungwon Hwang struct decon_context *ctx = crtc->ctx;
46973488331SAndrzej Hajda unsigned long flags;
470cc5a7b35SHyungwon Hwang
47173488331SAndrzej Hajda spin_lock_irqsave(&ctx->vblank_lock, flags);
47273488331SAndrzej Hajda
473b2adc530SAndrzej Hajda decon_shadow_protect(ctx, false);
474cc5a7b35SHyungwon Hwang
47592ead494SAndrzej Hajda decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
47692ead494SAndrzej Hajda
47773488331SAndrzej Hajda ctx->frame_id = decon_get_frame_count(ctx, true);
47873488331SAndrzej Hajda
479a392276dSAndrzej Hajda exynos_crtc_handle_event(crtc);
48073488331SAndrzej Hajda
48173488331SAndrzej Hajda spin_unlock_irqrestore(&ctx->vblank_lock, flags);
482cc5a7b35SHyungwon Hwang }
483cc5a7b35SHyungwon Hwang
decon_swreset(struct decon_context * ctx)484c8466a91SJoonyoung Shim static void decon_swreset(struct decon_context *ctx)
485c8466a91SJoonyoung Shim {
48673488331SAndrzej Hajda unsigned long flags;
48730b8913fSAndrzej Hajda u32 val;
48830b8913fSAndrzej Hajda int ret;
489c8466a91SJoonyoung Shim
490c8466a91SJoonyoung Shim writel(0, ctx->addr + DECON_VIDCON0);
49130b8913fSAndrzej Hajda readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
49230b8913fSAndrzej Hajda ~val & VIDCON0_STOP_STATUS, 12, 20000);
493c8466a91SJoonyoung Shim
494c8466a91SJoonyoung Shim writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
49530b8913fSAndrzej Hajda ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
49630b8913fSAndrzej Hajda ~val & VIDCON0_SWRESET, 12, 20000);
497c8466a91SJoonyoung Shim
49830b8913fSAndrzej Hajda WARN(ret < 0, "failed to software reset DECON\n");
499b8182832SAndrzej Hajda
50073488331SAndrzej Hajda spin_lock_irqsave(&ctx->vblank_lock, flags);
50173488331SAndrzej Hajda ctx->frame_id = 0;
50273488331SAndrzej Hajda spin_unlock_irqrestore(&ctx->vblank_lock, flags);
50373488331SAndrzej Hajda
5049ac26de8SInki Dae if (!(ctx->out_type & IFTYPE_HDMI))
505b8182832SAndrzej Hajda return;
506b8182832SAndrzej Hajda
507b8182832SAndrzej Hajda writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
508b8182832SAndrzej Hajda decon_set_bits(ctx, DECON_CMU,
509b8182832SAndrzej Hajda CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
510b8182832SAndrzej Hajda writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
511b8182832SAndrzej Hajda writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
512b8182832SAndrzej Hajda ctx->addr + DECON_CRCCTRL);
513c8466a91SJoonyoung Shim }
514c8466a91SJoonyoung Shim
decon_atomic_enable(struct exynos_drm_crtc * crtc)51511f95489SInki Dae static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
516c8466a91SJoonyoung Shim {
517c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
518445d3bedSInki Dae int ret;
519c8466a91SJoonyoung Shim
520445d3bedSInki Dae ret = pm_runtime_resume_and_get(ctx->dev);
521445d3bedSInki Dae if (ret < 0) {
522445d3bedSInki Dae DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n");
523445d3bedSInki Dae return;
524445d3bedSInki Dae }
525c8466a91SJoonyoung Shim
526c60230ebSAndrzej Hajda exynos_drm_pipe_clk_enable(crtc, true);
527c60230ebSAndrzej Hajda
528e87b3c62SAndrzej Hajda decon_swreset(ctx);
529e87b3c62SAndrzej Hajda
530c8466a91SJoonyoung Shim decon_commit(ctx->crtc);
531c8466a91SJoonyoung Shim }
532c8466a91SJoonyoung Shim
decon_atomic_disable(struct exynos_drm_crtc * crtc)53311f95489SInki Dae static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
534c8466a91SJoonyoung Shim {
535c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
536c8466a91SJoonyoung Shim int i;
537c8466a91SJoonyoung Shim
538b37d53a0SAndrzej Hajda if (!(ctx->out_type & I80_HW_TRG))
539b37d53a0SAndrzej Hajda synchronize_irq(ctx->te_irq);
540b37d53a0SAndrzej Hajda synchronize_irq(ctx->irq);
541b37d53a0SAndrzej Hajda
542c8466a91SJoonyoung Shim /*
543c8466a91SJoonyoung Shim * We need to make sure that all windows are disabled before we
544c8466a91SJoonyoung Shim * suspend that connector. Otherwise we might try to scan from
545c8466a91SJoonyoung Shim * a destroyed buffer later.
546c8466a91SJoonyoung Shim */
547b8182832SAndrzej Hajda for (i = ctx->first_win; i < WINDOWS_NR; i++)
5481e1d1393SGustavo Padovan decon_disable_plane(crtc, &ctx->planes[i]);
549c8466a91SJoonyoung Shim
550c8466a91SJoonyoung Shim decon_swreset(ctx);
551c8466a91SJoonyoung Shim
552c60230ebSAndrzej Hajda exynos_drm_pipe_clk_enable(crtc, false);
553c60230ebSAndrzej Hajda
554c8466a91SJoonyoung Shim pm_runtime_put_sync(ctx->dev);
555c8466a91SJoonyoung Shim }
556c8466a91SJoonyoung Shim
decon_te_irq_handler(int irq,void * dev_id)557b37d53a0SAndrzej Hajda static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
558c8466a91SJoonyoung Shim {
559b37d53a0SAndrzej Hajda struct decon_context *ctx = dev_id;
560c8466a91SJoonyoung Shim
561b2192073SAndrzej Hajda decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
562b37d53a0SAndrzej Hajda
563b37d53a0SAndrzej Hajda return IRQ_HANDLED;
564c8466a91SJoonyoung Shim }
565c8466a91SJoonyoung Shim
decon_clear_channels(struct exynos_drm_crtc * crtc)566c8466a91SJoonyoung Shim static void decon_clear_channels(struct exynos_drm_crtc *crtc)
567c8466a91SJoonyoung Shim {
568c8466a91SJoonyoung Shim struct decon_context *ctx = crtc->ctx;
569c8466a91SJoonyoung Shim int win, i, ret;
570c8466a91SJoonyoung Shim
571c8466a91SJoonyoung Shim for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
572c8466a91SJoonyoung Shim ret = clk_prepare_enable(ctx->clks[i]);
573c8466a91SJoonyoung Shim if (ret < 0)
574c8466a91SJoonyoung Shim goto err;
575c8466a91SJoonyoung Shim }
576c8466a91SJoonyoung Shim
577b2adc530SAndrzej Hajda decon_shadow_protect(ctx, true);
578b2adc530SAndrzej Hajda for (win = 0; win < WINDOWS_NR; win++)
579b2192073SAndrzej Hajda decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
580b2adc530SAndrzej Hajda decon_shadow_protect(ctx, false);
58192ead494SAndrzej Hajda
58292ead494SAndrzej Hajda decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
58392ead494SAndrzej Hajda
584c8466a91SJoonyoung Shim /* TODO: wait for possible vsync */
585c8466a91SJoonyoung Shim msleep(50);
586c8466a91SJoonyoung Shim
587c8466a91SJoonyoung Shim err:
588c8466a91SJoonyoung Shim while (--i >= 0)
589c8466a91SJoonyoung Shim clk_disable_unprepare(ctx->clks[i]);
590c8466a91SJoonyoung Shim }
591c8466a91SJoonyoung Shim
decon_mode_valid(struct exynos_drm_crtc * crtc,const struct drm_display_mode * mode)592461e60eaSAndrzej Hajda static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
593461e60eaSAndrzej Hajda const struct drm_display_mode *mode)
594461e60eaSAndrzej Hajda {
595461e60eaSAndrzej Hajda struct decon_context *ctx = crtc->ctx;
596461e60eaSAndrzej Hajda
597461e60eaSAndrzej Hajda ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
598461e60eaSAndrzej Hajda
599461e60eaSAndrzej Hajda if (ctx->irq)
600461e60eaSAndrzej Hajda return MODE_OK;
601461e60eaSAndrzej Hajda
602461e60eaSAndrzej Hajda dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
603461e60eaSAndrzej Hajda crtc->i80_mode ? "command" : "video");
604461e60eaSAndrzej Hajda
605461e60eaSAndrzej Hajda return MODE_BAD;
606461e60eaSAndrzej Hajda }
607461e60eaSAndrzej Hajda
608fc36ec76SBhumika Goyal static const struct exynos_drm_crtc_ops decon_crtc_ops = {
60911f95489SInki Dae .atomic_enable = decon_atomic_enable,
61011f95489SInki Dae .atomic_disable = decon_atomic_disable,
611c8466a91SJoonyoung Shim .enable_vblank = decon_enable_vblank,
612c8466a91SJoonyoung Shim .disable_vblank = decon_disable_vblank,
613cc5a7b35SHyungwon Hwang .atomic_begin = decon_atomic_begin,
6149cc7610aSGustavo Padovan .update_plane = decon_update_plane,
6159cc7610aSGustavo Padovan .disable_plane = decon_disable_plane,
616461e60eaSAndrzej Hajda .mode_valid = decon_mode_valid,
617cc5a7b35SHyungwon Hwang .atomic_flush = decon_atomic_flush,
618c8466a91SJoonyoung Shim };
619c8466a91SJoonyoung Shim
decon_bind(struct device * dev,struct device * master,void * data)620c8466a91SJoonyoung Shim static int decon_bind(struct device *dev, struct device *master, void *data)
621c8466a91SJoonyoung Shim {
622c8466a91SJoonyoung Shim struct decon_context *ctx = dev_get_drvdata(dev);
623c8466a91SJoonyoung Shim struct drm_device *drm_dev = data;
624c8466a91SJoonyoung Shim struct exynos_drm_plane *exynos_plane;
625b8182832SAndrzej Hajda enum exynos_drm_output_type out_type;
626b8182832SAndrzej Hajda unsigned int win;
627c8466a91SJoonyoung Shim int ret;
628c8466a91SJoonyoung Shim
629c8466a91SJoonyoung Shim ctx->drm_dev = drm_dev;
630c8466a91SJoonyoung Shim
631b8182832SAndrzej Hajda for (win = ctx->first_win; win < WINDOWS_NR; win++) {
632fd2d2fc2SMarek Szyprowski ctx->configs[win].pixel_formats = decon_formats;
633fd2d2fc2SMarek Szyprowski ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
634cb5fba71SMarek Szyprowski ctx->configs[win].zpos = win - ctx->first_win;
635cb5fba71SMarek Szyprowski ctx->configs[win].type = decon_win_types[win];
63654947290SChristoph Manszewski ctx->configs[win].capabilities = capabilities[win];
637fd2d2fc2SMarek Szyprowski
63840bdfb0aSMarek Szyprowski ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
6392c82607bSAndrzej Hajda &ctx->configs[win]);
640c8466a91SJoonyoung Shim if (ret)
641c8466a91SJoonyoung Shim return ret;
642c8466a91SJoonyoung Shim }
643c8466a91SJoonyoung Shim
644cb5fba71SMarek Szyprowski exynos_plane = &ctx->planes[PRIMARY_WIN];
6459ac26de8SInki Dae out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
646b8182832SAndrzej Hajda : EXYNOS_DISPLAY_TYPE_LCD;
647c8466a91SJoonyoung Shim ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
648d644951cSAndrzej Hajda out_type, &decon_crtc_ops, ctx);
649f44d3d2fSAndrzej Hajda if (IS_ERR(ctx->crtc))
650f44d3d2fSAndrzej Hajda return PTR_ERR(ctx->crtc);
651c8466a91SJoonyoung Shim
652eb7a3fc7SJoonyoung Shim decon_clear_channels(ctx->crtc);
653eb7a3fc7SJoonyoung Shim
65407dc3678SMarek Szyprowski return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
655c8466a91SJoonyoung Shim }
656c8466a91SJoonyoung Shim
decon_unbind(struct device * dev,struct device * master,void * data)657c8466a91SJoonyoung Shim static void decon_unbind(struct device *dev, struct device *master, void *data)
658c8466a91SJoonyoung Shim {
659c8466a91SJoonyoung Shim struct decon_context *ctx = dev_get_drvdata(dev);
660c8466a91SJoonyoung Shim
66111f95489SInki Dae decon_atomic_disable(ctx->crtc);
662c8466a91SJoonyoung Shim
663c8466a91SJoonyoung Shim /* detach this sub driver from iommu mapping if supported. */
66407dc3678SMarek Szyprowski exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
665c8466a91SJoonyoung Shim }
666c8466a91SJoonyoung Shim
667c8466a91SJoonyoung Shim static const struct component_ops decon_component_ops = {
668c8466a91SJoonyoung Shim .bind = decon_bind,
669c8466a91SJoonyoung Shim .unbind = decon_unbind,
670c8466a91SJoonyoung Shim };
671c8466a91SJoonyoung Shim
decon_handle_vblank(struct decon_context * ctx)67273488331SAndrzej Hajda static void decon_handle_vblank(struct decon_context *ctx)
67373488331SAndrzej Hajda {
67473488331SAndrzej Hajda u32 frm;
67573488331SAndrzej Hajda
67673488331SAndrzej Hajda spin_lock(&ctx->vblank_lock);
67773488331SAndrzej Hajda
67873488331SAndrzej Hajda frm = decon_get_frame_count(ctx, true);
67973488331SAndrzej Hajda
68073488331SAndrzej Hajda if (frm != ctx->frame_id) {
68173488331SAndrzej Hajda /* handle only if incremented, take care of wrap-around */
68273488331SAndrzej Hajda if ((s32)(frm - ctx->frame_id) > 0)
68373488331SAndrzej Hajda drm_crtc_handle_vblank(&ctx->crtc->base);
68473488331SAndrzej Hajda ctx->frame_id = frm;
68573488331SAndrzej Hajda }
68673488331SAndrzej Hajda
68773488331SAndrzej Hajda spin_unlock(&ctx->vblank_lock);
68873488331SAndrzej Hajda }
68973488331SAndrzej Hajda
decon_irq_handler(int irq,void * dev_id)690b8182832SAndrzej Hajda static irqreturn_t decon_irq_handler(int irq, void *dev_id)
691c8466a91SJoonyoung Shim {
692c8466a91SJoonyoung Shim struct decon_context *ctx = dev_id;
693c8466a91SJoonyoung Shim u32 val;
694c8466a91SJoonyoung Shim
695c8466a91SJoonyoung Shim val = readl(ctx->addr + DECON_VIDINTCON1);
696b8182832SAndrzej Hajda val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
697b8182832SAndrzej Hajda
698b8182832SAndrzej Hajda if (val) {
699b8182832SAndrzej Hajda writel(val, ctx->addr + DECON_VIDINTCON1);
7001514d50bSAndrzej Hajda if (ctx->out_type & IFTYPE_HDMI) {
7011514d50bSAndrzej Hajda val = readl(ctx->addr + DECON_VIDOUTCON0);
7021514d50bSAndrzej Hajda val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
7031514d50bSAndrzej Hajda if (val ==
7041514d50bSAndrzej Hajda (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
7051514d50bSAndrzej Hajda return IRQ_HANDLED;
7061514d50bSAndrzej Hajda }
70773488331SAndrzej Hajda decon_handle_vblank(ctx);
708c8466a91SJoonyoung Shim }
709c8466a91SJoonyoung Shim
710c8466a91SJoonyoung Shim return IRQ_HANDLED;
711c8466a91SJoonyoung Shim }
712c8466a91SJoonyoung Shim
exynos5433_decon_suspend(struct device * dev)713ebf3fd40SGustavo Padovan static int exynos5433_decon_suspend(struct device *dev)
714ebf3fd40SGustavo Padovan {
715ebf3fd40SGustavo Padovan struct decon_context *ctx = dev_get_drvdata(dev);
71692c96ff8SAndrzej Hajda int i = ARRAY_SIZE(decon_clks_name);
717ebf3fd40SGustavo Padovan
71892c96ff8SAndrzej Hajda while (--i >= 0)
719ebf3fd40SGustavo Padovan clk_disable_unprepare(ctx->clks[i]);
720ebf3fd40SGustavo Padovan
721ebf3fd40SGustavo Padovan return 0;
722ebf3fd40SGustavo Padovan }
723ebf3fd40SGustavo Padovan
exynos5433_decon_resume(struct device * dev)724ebf3fd40SGustavo Padovan static int exynos5433_decon_resume(struct device *dev)
725ebf3fd40SGustavo Padovan {
726ebf3fd40SGustavo Padovan struct decon_context *ctx = dev_get_drvdata(dev);
727ebf3fd40SGustavo Padovan int i, ret;
728ebf3fd40SGustavo Padovan
729ebf3fd40SGustavo Padovan for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
730ebf3fd40SGustavo Padovan ret = clk_prepare_enable(ctx->clks[i]);
731ebf3fd40SGustavo Padovan if (ret < 0)
732ebf3fd40SGustavo Padovan goto err;
733ebf3fd40SGustavo Padovan }
734ebf3fd40SGustavo Padovan
735ebf3fd40SGustavo Padovan return 0;
736ebf3fd40SGustavo Padovan
737ebf3fd40SGustavo Padovan err:
738ebf3fd40SGustavo Padovan while (--i >= 0)
739ebf3fd40SGustavo Padovan clk_disable_unprepare(ctx->clks[i]);
740ebf3fd40SGustavo Padovan
741ebf3fd40SGustavo Padovan return ret;
742ebf3fd40SGustavo Padovan }
743ebf3fd40SGustavo Padovan
7441d9e6664SPaul Cercueil static DEFINE_RUNTIME_DEV_PM_OPS(exynos5433_decon_pm_ops,
7451d9e6664SPaul Cercueil exynos5433_decon_suspend,
7461d9e6664SPaul Cercueil exynos5433_decon_resume, NULL);
747ebf3fd40SGustavo Padovan
748b8182832SAndrzej Hajda static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
749b8182832SAndrzej Hajda {
750b8182832SAndrzej Hajda .compatible = "samsung,exynos5433-decon",
7519ac26de8SInki Dae .data = (void *)I80_HW_TRG
752b8182832SAndrzej Hajda },
753b8182832SAndrzej Hajda {
754b8182832SAndrzej Hajda .compatible = "samsung,exynos5433-decon-tv",
7559ac26de8SInki Dae .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
756b8182832SAndrzej Hajda },
757b8182832SAndrzej Hajda {},
758b8182832SAndrzej Hajda };
759b8182832SAndrzej Hajda MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
760b8182832SAndrzej Hajda
decon_conf_irq(struct decon_context * ctx,const char * name,irq_handler_t handler,unsigned long int flags)761b37d53a0SAndrzej Hajda static int decon_conf_irq(struct decon_context *ctx, const char *name,
76234c3db6cSAndrzej Hajda irq_handler_t handler, unsigned long int flags)
763b37d53a0SAndrzej Hajda {
764b37d53a0SAndrzej Hajda struct platform_device *pdev = to_platform_device(ctx->dev);
765b37d53a0SAndrzej Hajda int ret, irq = platform_get_irq_byname(pdev, name);
766b37d53a0SAndrzej Hajda
767b37d53a0SAndrzej Hajda if (irq < 0) {
76834c3db6cSAndrzej Hajda switch (irq) {
76934c3db6cSAndrzej Hajda case -EPROBE_DEFER:
770b37d53a0SAndrzej Hajda return irq;
77134c3db6cSAndrzej Hajda case -ENODATA:
77234c3db6cSAndrzej Hajda case -ENXIO:
77334c3db6cSAndrzej Hajda return 0;
77434c3db6cSAndrzej Hajda default:
77534c3db6cSAndrzej Hajda dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
776b37d53a0SAndrzej Hajda return irq;
777b37d53a0SAndrzej Hajda }
77834c3db6cSAndrzej Hajda }
779a4e5eed2STian Tao ret = devm_request_irq(ctx->dev, irq, handler,
780a4e5eed2STian Tao flags | IRQF_NO_AUTOEN, "drm_decon", ctx);
781b37d53a0SAndrzej Hajda if (ret < 0) {
782b37d53a0SAndrzej Hajda dev_err(ctx->dev, "IRQ %s request failed\n", name);
783b37d53a0SAndrzej Hajda return ret;
784b37d53a0SAndrzej Hajda }
785b37d53a0SAndrzej Hajda
786b37d53a0SAndrzej Hajda return irq;
787b37d53a0SAndrzej Hajda }
788b37d53a0SAndrzej Hajda
exynos5433_decon_probe(struct platform_device * pdev)789c8466a91SJoonyoung Shim static int exynos5433_decon_probe(struct platform_device *pdev)
790c8466a91SJoonyoung Shim {
791c8466a91SJoonyoung Shim struct device *dev = &pdev->dev;
792c8466a91SJoonyoung Shim struct decon_context *ctx;
793c8466a91SJoonyoung Shim int ret;
794c8466a91SJoonyoung Shim int i;
795c8466a91SJoonyoung Shim
796c8466a91SJoonyoung Shim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
797c8466a91SJoonyoung Shim if (!ctx)
798c8466a91SJoonyoung Shim return -ENOMEM;
799c8466a91SJoonyoung Shim
800c8466a91SJoonyoung Shim ctx->dev = dev;
8019ac26de8SInki Dae ctx->out_type = (unsigned long)of_device_get_match_data(dev);
80273488331SAndrzej Hajda spin_lock_init(&ctx->vblank_lock);
803b8182832SAndrzej Hajda
804461e60eaSAndrzej Hajda if (ctx->out_type & IFTYPE_HDMI)
805b8182832SAndrzej Hajda ctx->first_win = 1;
806c8466a91SJoonyoung Shim
807c8466a91SJoonyoung Shim for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
808c8466a91SJoonyoung Shim struct clk *clk;
809c8466a91SJoonyoung Shim
810c8466a91SJoonyoung Shim clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
811c8466a91SJoonyoung Shim if (IS_ERR(clk))
812c8466a91SJoonyoung Shim return PTR_ERR(clk);
813c8466a91SJoonyoung Shim
814c8466a91SJoonyoung Shim ctx->clks[i] = clk;
815c8466a91SJoonyoung Shim }
816c8466a91SJoonyoung Shim
81717ac76e0SCai Huoqing ctx->addr = devm_platform_ioremap_resource(pdev, 0);
818a470c566SZhen Lei if (IS_ERR(ctx->addr))
819c8466a91SJoonyoung Shim return PTR_ERR(ctx->addr);
820c8466a91SJoonyoung Shim
82134c3db6cSAndrzej Hajda ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
822b37d53a0SAndrzej Hajda if (ret < 0)
823b37d53a0SAndrzej Hajda return ret;
82434c3db6cSAndrzej Hajda ctx->irq_vsync = ret;
82534c3db6cSAndrzej Hajda
82634c3db6cSAndrzej Hajda ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
82734c3db6cSAndrzej Hajda if (ret < 0)
82834c3db6cSAndrzej Hajda return ret;
82934c3db6cSAndrzej Hajda ctx->irq_lcd_sys = ret;
83034c3db6cSAndrzej Hajda
831b37d53a0SAndrzej Hajda ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
83234c3db6cSAndrzej Hajda IRQF_TRIGGER_RISING);
833b37d53a0SAndrzej Hajda if (ret < 0)
834b37d53a0SAndrzej Hajda return ret;
835b37d53a0SAndrzej Hajda if (ret) {
836b37d53a0SAndrzej Hajda ctx->te_irq = ret;
837b37d53a0SAndrzej Hajda ctx->out_type &= ~I80_HW_TRG;
838b37d53a0SAndrzej Hajda }
839c8466a91SJoonyoung Shim
840b37d53a0SAndrzej Hajda if (ctx->out_type & I80_HW_TRG) {
841b37d53a0SAndrzej Hajda ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
842b37d53a0SAndrzej Hajda "samsung,disp-sysreg");
843b37d53a0SAndrzej Hajda if (IS_ERR(ctx->sysreg)) {
844b37d53a0SAndrzej Hajda dev_err(dev, "failed to get system register\n");
845b37d53a0SAndrzej Hajda return PTR_ERR(ctx->sysreg);
846b37d53a0SAndrzej Hajda }
847c8466a91SJoonyoung Shim }
848c8466a91SJoonyoung Shim
849c8466a91SJoonyoung Shim platform_set_drvdata(pdev, ctx);
850c8466a91SJoonyoung Shim
851c8466a91SJoonyoung Shim pm_runtime_enable(dev);
852c8466a91SJoonyoung Shim
853c8466a91SJoonyoung Shim ret = component_add(dev, &decon_component_ops);
854c8466a91SJoonyoung Shim if (ret)
855c8466a91SJoonyoung Shim goto err_disable_pm_runtime;
856c8466a91SJoonyoung Shim
857c8466a91SJoonyoung Shim return 0;
858c8466a91SJoonyoung Shim
859c8466a91SJoonyoung Shim err_disable_pm_runtime:
860c8466a91SJoonyoung Shim pm_runtime_disable(dev);
861c8466a91SJoonyoung Shim
862c8466a91SJoonyoung Shim return ret;
863c8466a91SJoonyoung Shim }
864c8466a91SJoonyoung Shim
exynos5433_decon_remove(struct platform_device * pdev)865c8466a91SJoonyoung Shim static int exynos5433_decon_remove(struct platform_device *pdev)
866c8466a91SJoonyoung Shim {
867c8466a91SJoonyoung Shim pm_runtime_disable(&pdev->dev);
868c8466a91SJoonyoung Shim
869c8466a91SJoonyoung Shim component_del(&pdev->dev, &decon_component_ops);
870c8466a91SJoonyoung Shim
871c8466a91SJoonyoung Shim return 0;
872c8466a91SJoonyoung Shim }
873c8466a91SJoonyoung Shim
874c8466a91SJoonyoung Shim struct platform_driver exynos5433_decon_driver = {
875c8466a91SJoonyoung Shim .probe = exynos5433_decon_probe,
876c8466a91SJoonyoung Shim .remove = exynos5433_decon_remove,
877c8466a91SJoonyoung Shim .driver = {
878c8466a91SJoonyoung Shim .name = "exynos5433-decon",
8791d9e6664SPaul Cercueil .pm = pm_ptr(&exynos5433_decon_pm_ops),
880c8466a91SJoonyoung Shim .of_match_table = exynos5433_decon_driver_dt_match,
881c8466a91SJoonyoung Shim },
882c8466a91SJoonyoung Shim };
883