1a8c21a54SThe etnaviv authors #ifndef STATE_HI_XML 2a8c21a54SThe etnaviv authors #define STATE_HI_XML 3a8c21a54SThe etnaviv authors 4a8c21a54SThe etnaviv authors /* Autogenerated file, DO NOT EDIT manually! 5a8c21a54SThe etnaviv authors 6a8c21a54SThe etnaviv authors This file was generated by the rules-ng-ng headergen tool in this git repository: 7a8c21a54SThe etnaviv authors http://0x04.net/cgit/index.cgi/rules-ng-ng 8a8c21a54SThe etnaviv authors git clone git://0x04.net/rules-ng-ng 9a8c21a54SThe etnaviv authors 10a8c21a54SThe etnaviv authors The rules-ng-ng source files this header was generated from are: 118ed226ffSChristian Gmeiner - state.xml ( 26666 bytes, from 2019-12-20 21:20:35) 128ed226ffSChristian Gmeiner - common.xml ( 35468 bytes, from 2018-02-10 13:09:26) 138ed226ffSChristian Gmeiner - common_3d.xml ( 15058 bytes, from 2019-12-28 20:02:03) 148ed226ffSChristian Gmeiner - state_hi.xml ( 30552 bytes, from 2019-12-28 20:02:48) 158ed226ffSChristian Gmeiner - copyright.xml ( 1597 bytes, from 2018-02-10 13:09:26) 168ed226ffSChristian Gmeiner - state_2d.xml ( 51552 bytes, from 2018-02-10 13:09:26) 178ed226ffSChristian Gmeiner - state_3d.xml ( 83098 bytes, from 2019-12-28 20:02:03) 188ed226ffSChristian Gmeiner - state_blt.xml ( 14252 bytes, from 2019-10-20 19:59:15) 198ed226ffSChristian Gmeiner - state_vg.xml ( 5975 bytes, from 2018-02-10 13:09:26) 20a8c21a54SThe etnaviv authors 218ed226ffSChristian Gmeiner Copyright (C) 2012-2019 by the following authors: 22059ad731SLucas Stach - Wladimir J. van der Laan <laanwj@gmail.com> 23059ad731SLucas Stach - Christian Gmeiner <christian.gmeiner@gmail.com> 24059ad731SLucas Stach - Lucas Stach <l.stach@pengutronix.de> 25059ad731SLucas Stach - Russell King <rmk@arm.linux.org.uk> 26059ad731SLucas Stach 27059ad731SLucas Stach Permission is hereby granted, free of charge, to any person obtaining a 28059ad731SLucas Stach copy of this software and associated documentation files (the "Software"), 29059ad731SLucas Stach to deal in the Software without restriction, including without limitation 30059ad731SLucas Stach the rights to use, copy, modify, merge, publish, distribute, sub license, 31059ad731SLucas Stach and/or sell copies of the Software, and to permit persons to whom the 32059ad731SLucas Stach Software is furnished to do so, subject to the following conditions: 33059ad731SLucas Stach 34059ad731SLucas Stach The above copyright notice and this permission notice (including the 35059ad731SLucas Stach next paragraph) shall be included in all copies or substantial portions 36059ad731SLucas Stach of the Software. 37059ad731SLucas Stach 38059ad731SLucas Stach THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 39059ad731SLucas Stach IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 40059ad731SLucas Stach FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 41059ad731SLucas Stach THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 42059ad731SLucas Stach LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43059ad731SLucas Stach FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 44059ad731SLucas Stach DEALINGS IN THE SOFTWARE. 45a8c21a54SThe etnaviv authors */ 46a8c21a54SThe etnaviv authors 47a8c21a54SThe etnaviv authors 48a8c21a54SThe etnaviv authors #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001 49a8c21a54SThe etnaviv authors #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002 50a8c21a54SThe etnaviv authors #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003 518ed226ffSChristian Gmeiner #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004 528ed226ffSChristian Gmeiner #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005 538ed226ffSChristian Gmeiner #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006 54a8c21a54SThe etnaviv authors #define VIVS_HI 0x00000000 55a8c21a54SThe etnaviv authors 56a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL 0x00000000 57a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001 58a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002 59a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc 60a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT 2 61a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x) (((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK) 62a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200 63a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400 64a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800 65a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000 66a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000 67a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000 68a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000 69a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000 70a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000 71a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT 20 72a8c21a54SThe etnaviv authors #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x) (((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK) 73a8c21a54SThe etnaviv authors 74a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE 0x00000004 75a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_FE 0x00000001 76a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_DE 0x00000002 77a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_PE 0x00000004 78a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_SH 0x00000008 79a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_PA 0x00000010 80a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_SE 0x00000020 81a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_RA 0x00000040 82a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_TX 0x00000080 83a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_VG 0x00000100 84a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_IM 0x00000200 85a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_FP 0x00000400 86a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_TS 0x00000800 87a8c21a54SThe etnaviv authors #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000 88a8c21a54SThe etnaviv authors 89a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG 0x00000008 90a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f 91a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0 92a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWID(x) (((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK) 93a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0 94a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARID__SHIFT 4 95a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARID(x) (((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK) 96a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00 97a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT 8 98a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_AWCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK) 99a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000 100a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT 12 101a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONFIG_ARCACHE(x) (((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK) 102a8c21a54SThe etnaviv authors 103a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS 0x0000000c 104a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f 105a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0 106a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_WR_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK) 107a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0 108a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT 4 109a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_RD_ERR_ID(x) (((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK) 110a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100 111a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 112a8c21a54SThe etnaviv authors 113a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 114128a9b1dSLucas Stach #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff 115a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 116a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) 117128a9b1dSLucas Stach #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 118a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 119a8c21a54SThe etnaviv authors 120a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL 0x00000014 121a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff 122a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0 123a8c21a54SThe etnaviv authors #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x) (((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK) 124a8c21a54SThe etnaviv authors 125a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY 0x00000018 126a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000 127a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT 24 128a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_FAMILY(x) (((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK) 129a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000 130a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT 16 131a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_PRODUCT(x) (((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK) 132a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000 133a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT 12 134a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_IDENTITY_REVISION(x) (((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK) 135a8c21a54SThe etnaviv authors 136a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_FEATURE 0x0000001c 137a8c21a54SThe etnaviv authors 138a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MODEL 0x00000020 139a8c21a54SThe etnaviv authors 140a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_REV 0x00000024 141a8c21a54SThe etnaviv authors 142a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_DATE 0x00000028 143a8c21a54SThe etnaviv authors 144a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_TIME 0x0000002c 145a8c21a54SThe etnaviv authors 1468ed226ffSChristian Gmeiner #define VIVS_HI_CHIP_CUSTOMER_ID 0x00000030 1478ed226ffSChristian Gmeiner 148a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034 149a8c21a54SThe etnaviv authors 150a8c21a54SThe etnaviv authors #define VIVS_HI_CACHE_CONTROL 0x00000038 151a8c21a54SThe etnaviv authors 152a8c21a54SThe etnaviv authors #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c 153a8c21a54SThe etnaviv authors 154a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040 155a8c21a54SThe etnaviv authors 156a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044 157a8c21a54SThe etnaviv authors 158a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS 0x00000048 159a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f 160a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0 161a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK) 162a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0 163a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT 4 164a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_REGISTER_MAX(x) (((x) << VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT) & VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK) 165a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00 166a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT 8 167a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_THREAD_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK) 168a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000 169a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT 12 170a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK) 171a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000 172a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT 20 173a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK) 174a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000 175a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT 25 176a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES(x) (((x) << VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT) & VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK) 177a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000 178a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT 28 179a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK) 180a8c21a54SThe etnaviv authors 181a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c 182a8c21a54SThe etnaviv authors 183a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050 184a8c21a54SThe etnaviv authors 185a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058 186a8c21a54SThe etnaviv authors 187a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c 188a8c21a54SThe etnaviv authors 189a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_READ_LASTS 0x00000060 190a8c21a54SThe etnaviv authors 191a8c21a54SThe etnaviv authors #define VIVS_HI_GP_OUT0 0x00000064 192a8c21a54SThe etnaviv authors 193a8c21a54SThe etnaviv authors #define VIVS_HI_GP_OUT1 0x00000068 194a8c21a54SThe etnaviv authors 195a8c21a54SThe etnaviv authors #define VIVS_HI_GP_OUT2 0x0000006c 196a8c21a54SThe etnaviv authors 197a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONTROL 0x00000070 198a8c21a54SThe etnaviv authors #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001 199a8c21a54SThe etnaviv authors 200a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074 201a8c21a54SThe etnaviv authors 202a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078 203a8c21a54SThe etnaviv authors 204a8c21a54SThe etnaviv authors #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c 205a8c21a54SThe etnaviv authors 206a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2 0x00000080 207a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff 208a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0 209a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE(x) (((x) << VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT) & VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK) 210a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00 211a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT 8 212a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK) 213a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000 214a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT 16 215a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS(x) (((x) << VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT) & VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK) 216a8c21a54SThe etnaviv authors 217a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084 218a8c21a54SThe etnaviv authors 219a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088 220a8c21a54SThe etnaviv authors 221e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3 0x0000008c 222e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0 223e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT 4 224e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK) 225e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007 226e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0 227e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK) 228e2a2e263SRussell King 229059ad731SLucas Stach #define VIVS_HI_COMPRESSION_FLAGS 0x00000090 230059ad731SLucas Stach #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040 231059ad731SLucas Stach 232a8c21a54SThe etnaviv authors #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094 233a8c21a54SThe etnaviv authors 234e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4 0x0000009c 235e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000 236e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT 12 237e2a2e263SRussell King #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT(x) (((x) << VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT) & VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK) 238e2a2e263SRussell King 239e2a2e263SRussell King #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0 240e2a2e263SRussell King 241e2a2e263SRussell King #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8 242e2a2e263SRussell King 243059ad731SLucas Stach #define VIVS_HI_BLT_INTR 0x000000d4 244059ad731SLucas Stach 2458ed226ffSChristian Gmeiner #define VIVS_HI_CHIP_ECO_ID 0x000000e8 2468ed226ffSChristian Gmeiner 247059ad731SLucas Stach #define VIVS_HI_AUXBIT 0x000000ec 248059ad731SLucas Stach 249a8c21a54SThe etnaviv authors #define VIVS_PM 0x00000000 250a8c21a54SThe etnaviv authors 251a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS 0x00000100 252a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001 253a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002 254a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004 255a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0 256a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT 4 257a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK) 258a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000 259a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT 16 260a8c21a54SThe etnaviv authors #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x) (((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK) 261a8c21a54SThe etnaviv authors 262a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS 0x00000104 263a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001 264a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002 265a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004 2667d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008 2677d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010 2687d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020 2697d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040 2707d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080 2717d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000 2727d0c6e71SRussell King #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000 273a8c21a54SThe etnaviv authors 274a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS 0x00000108 275a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 276a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002 277a8c21a54SThe etnaviv authors #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004 278e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008 279e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010 280e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020 281e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040 282e2a2e263SRussell King #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080 283a8c21a54SThe etnaviv authors 284a8c21a54SThe etnaviv authors #define VIVS_PM_PULSE_EATER 0x0000010c 285059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001 286059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00 287059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT 8 288059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_DVFS_PERIOD(x) (((x) << VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT) & VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK) 289059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK16 0x00010000 290059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK17 0x00020000 291059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000 292059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK19 0x00080000 293059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK20 0x00100000 294059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK22 0x00400000 295059ad731SLucas Stach #define VIVS_PM_PULSE_EATER_UNK23 0x00800000 296a8c21a54SThe etnaviv authors 297a8c21a54SThe etnaviv authors #define VIVS_MMUv2 0x00000000 298a8c21a54SThe etnaviv authors 299a8c21a54SThe etnaviv authors #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180 300a8c21a54SThe etnaviv authors 301a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION 0x00000184 302a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001 303a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0 304a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000 305a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001 306a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008 307a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010 308a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT 4 309a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010 310a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080 311a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100 312a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00 313a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT 10 314a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONFIGURATION_ADDRESS(x) (((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK) 315a8c21a54SThe etnaviv authors 316a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS 0x00000188 317a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x00000003 318a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0 319a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK) 320a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x00000030 321a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT 4 322a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK) 323a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000300 324a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT 8 325a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK) 326a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x00003000 327a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT 12 328a8c21a54SThe etnaviv authors #define VIVS_MMUv2_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK) 329a8c21a54SThe etnaviv authors 330a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONTROL 0x0000018c 331a8c21a54SThe etnaviv authors #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001 332a8c21a54SThe etnaviv authors 333a8c21a54SThe etnaviv authors #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) 334a8c21a54SThe etnaviv authors #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004 335a8c21a54SThe etnaviv authors #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004 336a8c21a54SThe etnaviv authors 337059ad731SLucas Stach #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4 338059ad731SLucas Stach 339059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG 0x000001ac 340059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff 341059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0 342059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_INDEX(x) (((x) << VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT) & VIVS_MMUv2_PTA_CONFIG_INDEX__MASK) 343059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000 344059ad731SLucas Stach 345059ad731SLucas Stach #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) 346059ad731SLucas Stach #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004 347059ad731SLucas Stach #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008 348059ad731SLucas Stach 349059ad731SLucas Stach #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380 350059ad731SLucas Stach 351059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS 0x00000384 352059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003 353059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0 354059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK) 355059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030 356059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT 4 357059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK) 358059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300 359059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT 8 360059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK) 361059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000 362059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT 12 363059ad731SLucas Stach #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3(x) (((x) << VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK) 364059ad731SLucas Stach 365059ad731SLucas Stach #define VIVS_MMUv2_SEC_CONTROL 0x00000388 366059ad731SLucas Stach #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001 367059ad731SLucas Stach 368059ad731SLucas Stach #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c 369059ad731SLucas Stach 370059ad731SLucas Stach #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390 371059ad731SLucas Stach 372059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONTROL 0x00000394 373059ad731SLucas Stach #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001 374059ad731SLucas Stach 375059ad731SLucas Stach #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398 376059ad731SLucas Stach 377059ad731SLucas Stach #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c 378059ad731SLucas Stach 379059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0 380059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff 381059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0 382059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK) 383059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000 384059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000 385059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT 16 386059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(x) (((x) << VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT) & VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK) 387059ad731SLucas Stach #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000 388059ad731SLucas Stach 389059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4 390059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff 391059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0 392059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK) 393059ad731SLucas Stach #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000 394059ad731SLucas Stach 395059ad731SLucas Stach #define VIVS_MMUv2_AHB_CONTROL 0x000003a8 396059ad731SLucas Stach #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001 397059ad731SLucas Stach #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002 398059ad731SLucas Stach 399a8c21a54SThe etnaviv authors #define VIVS_MC 0x00000000 400a8c21a54SThe etnaviv authors 401a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400 402a8c21a54SThe etnaviv authors 403a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404 404a8c21a54SThe etnaviv authors 405a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408 406a8c21a54SThe etnaviv authors 407a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c 408a8c21a54SThe etnaviv authors 409a8c21a54SThe etnaviv authors #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410 410a8c21a54SThe etnaviv authors 411a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY 0x00000414 412a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008 413a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000 414a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000 415a8c21a54SThe etnaviv authors 416a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418 417a8c21a54SThe etnaviv authors 418a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c 419a8c21a54SThe etnaviv authors 420a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420 421a8c21a54SThe etnaviv authors 422a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424 423a8c21a54SThe etnaviv authors 424a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428 425a8c21a54SThe etnaviv authors 426a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c 427a8c21a54SThe etnaviv authors 428a8c21a54SThe etnaviv authors #define VIVS_MC_MEMORY_FLUSH 0x00000430 429a8c21a54SThe etnaviv authors 430a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438 431a8c21a54SThe etnaviv authors 432a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_READ0 0x0000043c 433a8c21a54SThe etnaviv authors 434a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_READ1 0x00000440 435a8c21a54SThe etnaviv authors 436a8c21a54SThe etnaviv authors #define VIVS_MC_DEBUG_WRITE 0x00000444 437a8c21a54SThe etnaviv authors 438a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_RA_READ 0x00000448 439a8c21a54SThe etnaviv authors 440a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_TX_READ 0x0000044c 441a8c21a54SThe etnaviv authors 442a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_FE_READ 0x00000450 443a8c21a54SThe etnaviv authors 444a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_PE_READ 0x00000454 445a8c21a54SThe etnaviv authors 446a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_DE_READ 0x00000458 447a8c21a54SThe etnaviv authors 448a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_SH_READ 0x0000045c 449a8c21a54SThe etnaviv authors 450a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_PA_READ 0x00000460 451a8c21a54SThe etnaviv authors 452a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_SE_READ 0x00000464 453a8c21a54SThe etnaviv authors 454a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_MC_READ 0x00000468 455a8c21a54SThe etnaviv authors 456a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_HI_READ 0x0000046c 457a8c21a54SThe etnaviv authors 458a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0 0x00000470 459059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff 460a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0 461a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f 462059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00 463a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT 8 464a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00 465059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000 466a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT 16 467a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000 468a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000 469a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000 470a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000 471a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000 472a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000 473059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000 474a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT 24 475a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000 476a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000 477a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000 478a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000 479a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000 480a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000 481a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000 482a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000 483a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000 484a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000 485a8c21a54SThe etnaviv authors 486a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1 0x00000474 487059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff 488a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0 489a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003 490a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004 491a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005 492a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006 493a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007 494a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008 495a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f 496059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00 497a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT 8 498a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000 499a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100 500a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00 501059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000 502a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT 16 503a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000 504a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000 505a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000 506a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000 507a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000 508a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000 509a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000 510a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000 511059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000 512a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT 24 513a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000 514a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000 515a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000 516a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000 517a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000 518a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000 519a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000 520a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000 521a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000 522a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000 523a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000 524a8c21a54SThe etnaviv authors 525a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2 0x00000478 526059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff 527a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0 528a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001 529a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002 530a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003 531a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_MC_RESET 0x0000000f 532059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00 533a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT 8 534a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000 535a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100 536a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200 537a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00 538059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000 539059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT 24 540059ad731SLucas Stach #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000 541a8c21a54SThe etnaviv authors 542a8c21a54SThe etnaviv authors #define VIVS_MC_PROFILE_CONFIG3 0x0000047c 543a8c21a54SThe etnaviv authors 544a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG 0x00000480 545a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f 546a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0 547a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK) 548a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0 549a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT 4 550a8c21a54SThe etnaviv authors #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(x) (((x) << VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT) & VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK) 551a8c21a54SThe etnaviv authors 552a8c21a54SThe etnaviv authors #define VIVS_MC_START_COMPOSITION 0x00000554 553a8c21a54SThe etnaviv authors 554059ad731SLucas Stach #define VIVS_MC_FLAGS 0x00000558 555059ad731SLucas Stach #define VIVS_MC_FLAGS_128B_MERGE 0x00000001 556059ad731SLucas Stach #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000 557059ad731SLucas Stach 558059ad731SLucas Stach #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c 559059ad731SLucas Stach 560059ad731SLucas Stach #define VIVS_MC_PROFILE_L2_READ 0x00000564 561a8c21a54SThe etnaviv authors 562a8c21a54SThe etnaviv authors 563a8c21a54SThe etnaviv authors #endif /* STATE_HI_XML */ 564