1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ETNAVIV_GPU_H__ 18 #define __ETNAVIV_GPU_H__ 19 20 #include <linux/clk.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "etnaviv_cmdbuf.h" 24 #include "etnaviv_drv.h" 25 26 struct etnaviv_gem_submit; 27 struct etnaviv_vram_mapping; 28 29 struct etnaviv_chip_identity { 30 /* Chip model. */ 31 u32 model; 32 33 /* Revision value.*/ 34 u32 revision; 35 36 /* Supported feature fields. */ 37 u32 features; 38 39 /* Supported minor feature fields. */ 40 u32 minor_features0; 41 u32 minor_features1; 42 u32 minor_features2; 43 u32 minor_features3; 44 u32 minor_features4; 45 u32 minor_features5; 46 u32 minor_features6; 47 u32 minor_features7; 48 u32 minor_features8; 49 u32 minor_features9; 50 u32 minor_features10; 51 u32 minor_features11; 52 53 /* Number of streams supported. */ 54 u32 stream_count; 55 56 /* Total number of temporary registers per thread. */ 57 u32 register_max; 58 59 /* Maximum number of threads. */ 60 u32 thread_count; 61 62 /* Number of shader cores. */ 63 u32 shader_core_count; 64 65 /* Size of the vertex cache. */ 66 u32 vertex_cache_size; 67 68 /* Number of entries in the vertex output buffer. */ 69 u32 vertex_output_buffer_size; 70 71 /* Number of pixel pipes. */ 72 u32 pixel_pipes; 73 74 /* Number of instructions. */ 75 u32 instruction_count; 76 77 /* Number of constants. */ 78 u32 num_constants; 79 80 /* Buffer size */ 81 u32 buffer_size; 82 83 /* Number of varyings */ 84 u8 varyings_count; 85 }; 86 87 enum etnaviv_sec_mode { 88 ETNA_SEC_NONE = 0, 89 ETNA_SEC_KERNEL, 90 ETNA_SEC_TZ 91 }; 92 93 struct etnaviv_event { 94 struct dma_fence *fence; 95 struct etnaviv_gem_submit *submit; 96 97 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event); 98 }; 99 100 struct etnaviv_cmdbuf_suballoc; 101 struct etnaviv_cmdbuf; 102 103 #define ETNA_NR_EVENTS 30 104 105 struct etnaviv_gpu { 106 struct drm_device *drm; 107 struct thermal_cooling_device *cooling; 108 struct device *dev; 109 struct mutex lock; 110 struct etnaviv_chip_identity identity; 111 enum etnaviv_sec_mode sec_mode; 112 struct etnaviv_file_private *lastctx; 113 struct workqueue_struct *wq; 114 struct drm_gpu_scheduler sched; 115 116 /* 'ring'-buffer: */ 117 struct etnaviv_cmdbuf buffer; 118 int exec_state; 119 120 /* bus base address of memory */ 121 u32 memory_base; 122 123 /* event management: */ 124 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS); 125 struct etnaviv_event event[ETNA_NR_EVENTS]; 126 struct completion event_free; 127 spinlock_t event_spinlock; 128 129 u32 idle_mask; 130 131 /* Fencing support */ 132 struct mutex fence_idr_lock; 133 struct idr fence_idr; 134 u32 next_fence; 135 u32 active_fence; 136 u32 completed_fence; 137 wait_queue_head_t fence_event; 138 u64 fence_context; 139 spinlock_t fence_spinlock; 140 141 /* worker for handling 'sync' points: */ 142 struct work_struct sync_point_work; 143 int sync_point_event; 144 145 void __iomem *mmio; 146 int irq; 147 148 struct etnaviv_iommu *mmu; 149 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc; 150 151 /* Power Control: */ 152 struct clk *clk_bus; 153 struct clk *clk_reg; 154 struct clk *clk_core; 155 struct clk *clk_shader; 156 157 unsigned int freq_scale; 158 unsigned long base_rate_core; 159 unsigned long base_rate_shader; 160 }; 161 162 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) 163 { 164 etnaviv_writel(data, gpu->mmio + reg); 165 } 166 167 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) 168 { 169 return etnaviv_readl(gpu->mmio + reg); 170 } 171 172 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence) 173 { 174 return fence_after_eq(gpu->completed_fence, fence); 175 } 176 177 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 178 179 int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 180 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu); 181 182 #ifdef CONFIG_DEBUG_FS 183 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 184 #endif 185 186 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu); 187 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); 188 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 189 u32 fence, struct timespec *timeout); 190 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 191 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); 192 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit); 193 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); 194 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); 195 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms); 196 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch); 197 198 extern struct platform_driver etnaviv_gpu_driver; 199 200 #endif /* __ETNAVIV_GPU_H__ */ 201