1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ETNAVIV_GPU_H__ 18 #define __ETNAVIV_GPU_H__ 19 20 #include <linux/clk.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "etnaviv_drv.h" 24 25 struct etnaviv_gem_submit; 26 27 struct etnaviv_chip_identity { 28 /* Chip model. */ 29 u32 model; 30 31 /* Revision value.*/ 32 u32 revision; 33 34 /* Supported feature fields. */ 35 u32 features; 36 37 /* Supported minor feature fields. */ 38 u32 minor_features0; 39 40 /* Supported minor feature 1 fields. */ 41 u32 minor_features1; 42 43 /* Supported minor feature 2 fields. */ 44 u32 minor_features2; 45 46 /* Supported minor feature 3 fields. */ 47 u32 minor_features3; 48 49 /* Number of streams supported. */ 50 u32 stream_count; 51 52 /* Total number of temporary registers per thread. */ 53 u32 register_max; 54 55 /* Maximum number of threads. */ 56 u32 thread_count; 57 58 /* Number of shader cores. */ 59 u32 shader_core_count; 60 61 /* Size of the vertex cache. */ 62 u32 vertex_cache_size; 63 64 /* Number of entries in the vertex output buffer. */ 65 u32 vertex_output_buffer_size; 66 67 /* Number of pixel pipes. */ 68 u32 pixel_pipes; 69 70 /* Number of instructions. */ 71 u32 instruction_count; 72 73 /* Number of constants. */ 74 u32 num_constants; 75 76 /* Buffer size */ 77 u32 buffer_size; 78 }; 79 80 struct etnaviv_event { 81 bool used; 82 struct fence *fence; 83 }; 84 85 struct etnaviv_cmdbuf; 86 87 struct etnaviv_gpu { 88 struct drm_device *drm; 89 struct device *dev; 90 struct mutex lock; 91 struct etnaviv_chip_identity identity; 92 struct etnaviv_file_private *lastctx; 93 bool switch_context; 94 95 /* 'ring'-buffer: */ 96 struct etnaviv_cmdbuf *buffer; 97 98 /* bus base address of memory */ 99 u32 memory_base; 100 101 /* event management: */ 102 struct etnaviv_event event[30]; 103 struct completion event_free; 104 spinlock_t event_spinlock; 105 106 /* list of currently in-flight command buffers */ 107 struct list_head active_cmd_list; 108 109 u32 idle_mask; 110 111 /* Fencing support */ 112 u32 next_fence; 113 u32 active_fence; 114 u32 completed_fence; 115 u32 retired_fence; 116 wait_queue_head_t fence_event; 117 unsigned int fence_context; 118 spinlock_t fence_spinlock; 119 120 /* worker for handling active-list retiring: */ 121 struct work_struct retire_work; 122 123 void __iomem *mmio; 124 int irq; 125 126 struct etnaviv_iommu *mmu; 127 128 /* Power Control: */ 129 struct clk *clk_bus; 130 struct clk *clk_core; 131 struct clk *clk_shader; 132 133 /* Hang Detction: */ 134 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */ 135 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD) 136 struct timer_list hangcheck_timer; 137 u32 hangcheck_fence; 138 u32 hangcheck_dma_addr; 139 struct work_struct recover_work; 140 }; 141 142 struct etnaviv_cmdbuf { 143 /* device this cmdbuf is allocated for */ 144 struct etnaviv_gpu *gpu; 145 /* user context key, must be unique between all active users */ 146 struct etnaviv_file_private *ctx; 147 /* cmdbuf properties */ 148 void *vaddr; 149 dma_addr_t paddr; 150 u32 size; 151 u32 user_size; 152 /* fence after which this buffer is to be disposed */ 153 struct fence *fence; 154 /* target exec state */ 155 u32 exec_state; 156 /* per GPU in-flight list */ 157 struct list_head node; 158 /* BOs attached to this command buffer */ 159 unsigned int nr_bos; 160 struct etnaviv_gem_object *bo[0]; 161 }; 162 163 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) 164 { 165 etnaviv_writel(data, gpu->mmio + reg); 166 } 167 168 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) 169 { 170 return etnaviv_readl(gpu->mmio + reg); 171 } 172 173 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence) 174 { 175 return fence_after_eq(gpu->completed_fence, fence); 176 } 177 178 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence) 179 { 180 return fence_after_eq(gpu->retired_fence, fence); 181 } 182 183 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 184 185 int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 186 187 #ifdef CONFIG_DEBUG_FS 188 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 189 #endif 190 191 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 192 unsigned int context, bool exclusive); 193 194 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); 195 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 196 u32 fence, struct timespec *timeout); 197 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 198 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); 199 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 200 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf); 201 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, 202 u32 size, size_t nr_bos); 203 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf); 204 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); 205 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); 206 207 extern struct platform_driver etnaviv_gpu_driver; 208 209 #endif /* __ETNAVIV_GPU_H__ */ 210