1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ETNAVIV_GPU_H__ 18 #define __ETNAVIV_GPU_H__ 19 20 #include <linux/clk.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "etnaviv_cmdbuf.h" 24 #include "etnaviv_drv.h" 25 26 struct etnaviv_gem_submit; 27 struct etnaviv_vram_mapping; 28 29 struct etnaviv_chip_identity { 30 /* Chip model. */ 31 u32 model; 32 33 /* Revision value.*/ 34 u32 revision; 35 36 /* Supported feature fields. */ 37 u32 features; 38 39 /* Supported minor feature fields. */ 40 u32 minor_features0; 41 42 /* Supported minor feature 1 fields. */ 43 u32 minor_features1; 44 45 /* Supported minor feature 2 fields. */ 46 u32 minor_features2; 47 48 /* Supported minor feature 3 fields. */ 49 u32 minor_features3; 50 51 /* Supported minor feature 4 fields. */ 52 u32 minor_features4; 53 54 /* Supported minor feature 5 fields. */ 55 u32 minor_features5; 56 57 /* Number of streams supported. */ 58 u32 stream_count; 59 60 /* Total number of temporary registers per thread. */ 61 u32 register_max; 62 63 /* Maximum number of threads. */ 64 u32 thread_count; 65 66 /* Number of shader cores. */ 67 u32 shader_core_count; 68 69 /* Size of the vertex cache. */ 70 u32 vertex_cache_size; 71 72 /* Number of entries in the vertex output buffer. */ 73 u32 vertex_output_buffer_size; 74 75 /* Number of pixel pipes. */ 76 u32 pixel_pipes; 77 78 /* Number of instructions. */ 79 u32 instruction_count; 80 81 /* Number of constants. */ 82 u32 num_constants; 83 84 /* Buffer size */ 85 u32 buffer_size; 86 87 /* Number of varyings */ 88 u8 varyings_count; 89 }; 90 91 struct etnaviv_event { 92 struct dma_fence *fence; 93 struct etnaviv_gem_submit *submit; 94 95 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event); 96 }; 97 98 struct etnaviv_cmdbuf_suballoc; 99 struct etnaviv_cmdbuf; 100 101 #define ETNA_NR_EVENTS 30 102 103 struct etnaviv_gpu { 104 struct drm_device *drm; 105 struct thermal_cooling_device *cooling; 106 struct device *dev; 107 struct mutex lock; 108 struct etnaviv_chip_identity identity; 109 struct etnaviv_file_private *lastctx; 110 struct workqueue_struct *wq; 111 112 /* 'ring'-buffer: */ 113 struct etnaviv_cmdbuf buffer; 114 int exec_state; 115 116 /* bus base address of memory */ 117 u32 memory_base; 118 119 /* event management: */ 120 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS); 121 struct etnaviv_event event[ETNA_NR_EVENTS]; 122 struct completion event_free; 123 spinlock_t event_spinlock; 124 125 /* list of currently in-flight command buffers */ 126 struct list_head active_submit_list; 127 128 u32 idle_mask; 129 130 /* Fencing support */ 131 u32 next_fence; 132 u32 active_fence; 133 u32 completed_fence; 134 u32 retired_fence; 135 wait_queue_head_t fence_event; 136 u64 fence_context; 137 spinlock_t fence_spinlock; 138 139 /* worker for handling active-list retiring: */ 140 struct work_struct retire_work; 141 142 /* worker for handling 'sync' points: */ 143 struct work_struct sync_point_work; 144 int sync_point_event; 145 146 void __iomem *mmio; 147 int irq; 148 149 struct etnaviv_iommu *mmu; 150 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc; 151 152 /* Power Control: */ 153 struct clk *clk_bus; 154 struct clk *clk_core; 155 struct clk *clk_shader; 156 157 /* Hang Detction: */ 158 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */ 159 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD) 160 struct timer_list hangcheck_timer; 161 u32 hangcheck_fence; 162 u32 hangcheck_dma_addr; 163 struct work_struct recover_work; 164 unsigned int freq_scale; 165 unsigned long base_rate_core; 166 unsigned long base_rate_shader; 167 }; 168 169 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) 170 { 171 etnaviv_writel(data, gpu->mmio + reg); 172 } 173 174 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) 175 { 176 return etnaviv_readl(gpu->mmio + reg); 177 } 178 179 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence) 180 { 181 return fence_after_eq(gpu->completed_fence, fence); 182 } 183 184 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence) 185 { 186 return fence_after_eq(gpu->retired_fence, fence); 187 } 188 189 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 190 191 int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 192 193 #ifdef CONFIG_DEBUG_FS 194 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 195 #endif 196 197 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 198 unsigned int context, bool exclusive, bool implicit); 199 200 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); 201 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 202 u32 fence, struct timespec *timeout); 203 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 204 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); 205 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 206 struct etnaviv_gem_submit *submit); 207 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); 208 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); 209 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms); 210 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch); 211 212 extern struct platform_driver etnaviv_gpu_driver; 213 214 #endif /* __ETNAVIV_GPU_H__ */ 215