1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ETNAVIV_GPU_H__ 18 #define __ETNAVIV_GPU_H__ 19 20 #include <linux/clk.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "etnaviv_drv.h" 24 25 struct etnaviv_gem_submit; 26 struct etnaviv_vram_mapping; 27 28 struct etnaviv_chip_identity { 29 /* Chip model. */ 30 u32 model; 31 32 /* Revision value.*/ 33 u32 revision; 34 35 /* Supported feature fields. */ 36 u32 features; 37 38 /* Supported minor feature fields. */ 39 u32 minor_features0; 40 41 /* Supported minor feature 1 fields. */ 42 u32 minor_features1; 43 44 /* Supported minor feature 2 fields. */ 45 u32 minor_features2; 46 47 /* Supported minor feature 3 fields. */ 48 u32 minor_features3; 49 50 /* Supported minor feature 4 fields. */ 51 u32 minor_features4; 52 53 /* Supported minor feature 5 fields. */ 54 u32 minor_features5; 55 56 /* Number of streams supported. */ 57 u32 stream_count; 58 59 /* Total number of temporary registers per thread. */ 60 u32 register_max; 61 62 /* Maximum number of threads. */ 63 u32 thread_count; 64 65 /* Number of shader cores. */ 66 u32 shader_core_count; 67 68 /* Size of the vertex cache. */ 69 u32 vertex_cache_size; 70 71 /* Number of entries in the vertex output buffer. */ 72 u32 vertex_output_buffer_size; 73 74 /* Number of pixel pipes. */ 75 u32 pixel_pipes; 76 77 /* Number of instructions. */ 78 u32 instruction_count; 79 80 /* Number of constants. */ 81 u32 num_constants; 82 83 /* Buffer size */ 84 u32 buffer_size; 85 86 /* Number of varyings */ 87 u8 varyings_count; 88 }; 89 90 struct etnaviv_event { 91 struct dma_fence *fence; 92 struct etnaviv_cmdbuf *cmdbuf; 93 94 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event); 95 }; 96 97 struct etnaviv_cmdbuf_suballoc; 98 struct etnaviv_cmdbuf; 99 100 #define ETNA_NR_EVENTS 30 101 102 struct etnaviv_gpu { 103 struct drm_device *drm; 104 struct thermal_cooling_device *cooling; 105 struct device *dev; 106 struct mutex lock; 107 struct etnaviv_chip_identity identity; 108 struct etnaviv_file_private *lastctx; 109 bool switch_context; 110 111 /* 'ring'-buffer: */ 112 struct etnaviv_cmdbuf *buffer; 113 int exec_state; 114 115 /* bus base address of memory */ 116 u32 memory_base; 117 118 /* event management: */ 119 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS); 120 struct etnaviv_event event[ETNA_NR_EVENTS]; 121 struct completion event_free; 122 spinlock_t event_spinlock; 123 124 /* list of currently in-flight command buffers */ 125 struct list_head active_cmd_list; 126 127 u32 idle_mask; 128 129 /* Fencing support */ 130 u32 next_fence; 131 u32 active_fence; 132 u32 completed_fence; 133 u32 retired_fence; 134 wait_queue_head_t fence_event; 135 u64 fence_context; 136 spinlock_t fence_spinlock; 137 138 /* worker for handling active-list retiring: */ 139 struct work_struct retire_work; 140 141 /* worker for handling 'sync' points: */ 142 struct work_struct sync_point_work; 143 int sync_point_event; 144 145 void __iomem *mmio; 146 int irq; 147 148 struct etnaviv_iommu *mmu; 149 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc; 150 151 /* Power Control: */ 152 struct clk *clk_bus; 153 struct clk *clk_core; 154 struct clk *clk_shader; 155 156 /* Hang Detction: */ 157 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */ 158 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD) 159 struct timer_list hangcheck_timer; 160 u32 hangcheck_fence; 161 u32 hangcheck_dma_addr; 162 struct work_struct recover_work; 163 unsigned int freq_scale; 164 unsigned long base_rate_core; 165 unsigned long base_rate_shader; 166 }; 167 168 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) 169 { 170 etnaviv_writel(data, gpu->mmio + reg); 171 } 172 173 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) 174 { 175 return etnaviv_readl(gpu->mmio + reg); 176 } 177 178 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence) 179 { 180 return fence_after_eq(gpu->completed_fence, fence); 181 } 182 183 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence) 184 { 185 return fence_after_eq(gpu->retired_fence, fence); 186 } 187 188 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 189 190 int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 191 192 #ifdef CONFIG_DEBUG_FS 193 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 194 #endif 195 196 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 197 unsigned int context, bool exclusive, bool implicit); 198 199 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); 200 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 201 u32 fence, struct timespec *timeout); 202 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 203 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); 204 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 205 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf); 206 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); 207 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); 208 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms); 209 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch); 210 211 extern struct platform_driver etnaviv_gpu_driver; 212 213 #endif /* __ETNAVIV_GPU_H__ */ 214