1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2015-2018 Etnaviv Project
4  */
5 
6 #ifndef __ETNAVIV_GPU_H__
7 #define __ETNAVIV_GPU_H__
8 
9 #include "etnaviv_cmdbuf.h"
10 #include "etnaviv_drv.h"
11 
12 struct etnaviv_gem_submit;
13 struct etnaviv_vram_mapping;
14 
15 struct etnaviv_chip_identity {
16 	/* Chip model. */
17 	u32 model;
18 
19 	/* Revision value.*/
20 	u32 revision;
21 
22 	/* Supported feature fields. */
23 	u32 features;
24 
25 	/* Supported minor feature fields. */
26 	u32 minor_features0;
27 	u32 minor_features1;
28 	u32 minor_features2;
29 	u32 minor_features3;
30 	u32 minor_features4;
31 	u32 minor_features5;
32 	u32 minor_features6;
33 	u32 minor_features7;
34 	u32 minor_features8;
35 	u32 minor_features9;
36 	u32 minor_features10;
37 	u32 minor_features11;
38 
39 	/* Number of streams supported. */
40 	u32 stream_count;
41 
42 	/* Total number of temporary registers per thread. */
43 	u32 register_max;
44 
45 	/* Maximum number of threads. */
46 	u32 thread_count;
47 
48 	/* Number of shader cores. */
49 	u32 shader_core_count;
50 
51 	/* Size of the vertex cache. */
52 	u32 vertex_cache_size;
53 
54 	/* Number of entries in the vertex output buffer. */
55 	u32 vertex_output_buffer_size;
56 
57 	/* Number of pixel pipes. */
58 	u32 pixel_pipes;
59 
60 	/* Number of instructions. */
61 	u32 instruction_count;
62 
63 	/* Number of constants. */
64 	u32 num_constants;
65 
66 	/* Buffer size */
67 	u32 buffer_size;
68 
69 	/* Number of varyings */
70 	u8 varyings_count;
71 };
72 
73 enum etnaviv_sec_mode {
74 	ETNA_SEC_NONE = 0,
75 	ETNA_SEC_KERNEL,
76 	ETNA_SEC_TZ
77 };
78 
79 struct etnaviv_event {
80 	struct dma_fence *fence;
81 	struct etnaviv_gem_submit *submit;
82 
83 	void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
84 };
85 
86 struct etnaviv_cmdbuf_suballoc;
87 struct etnaviv_cmdbuf;
88 struct regulator;
89 struct clk;
90 
91 #define ETNA_NR_EVENTS 30
92 
93 struct etnaviv_gpu {
94 	struct drm_device *drm;
95 	struct thermal_cooling_device *cooling;
96 	struct device *dev;
97 	struct mutex lock;
98 	struct etnaviv_chip_identity identity;
99 	enum etnaviv_sec_mode sec_mode;
100 	struct workqueue_struct *wq;
101 	struct drm_gpu_scheduler sched;
102 
103 	/* 'ring'-buffer: */
104 	struct etnaviv_cmdbuf buffer;
105 	int exec_state;
106 
107 	/* bus base address of memory  */
108 	u32 memory_base;
109 
110 	/* event management: */
111 	DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
112 	struct etnaviv_event event[ETNA_NR_EVENTS];
113 	struct completion event_free;
114 	spinlock_t event_spinlock;
115 
116 	u32 idle_mask;
117 
118 	/* Fencing support */
119 	struct mutex fence_lock;
120 	struct idr fence_idr;
121 	u32 next_fence;
122 	u32 completed_fence;
123 	wait_queue_head_t fence_event;
124 	u64 fence_context;
125 	spinlock_t fence_spinlock;
126 
127 	/* worker for handling 'sync' points: */
128 	struct work_struct sync_point_work;
129 	int sync_point_event;
130 
131 	/* hang detection */
132 	u32 hangcheck_dma_addr;
133 
134 	void __iomem *mmio;
135 	int irq;
136 
137 	struct etnaviv_iommu *mmu;
138 	struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
139 
140 	/* Power Control: */
141 	struct clk *clk_bus;
142 	struct clk *clk_reg;
143 	struct clk *clk_core;
144 	struct clk *clk_shader;
145 
146 	unsigned int freq_scale;
147 	unsigned long base_rate_core;
148 	unsigned long base_rate_shader;
149 };
150 
151 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
152 {
153 	writel(data, gpu->mmio + reg);
154 }
155 
156 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
157 {
158 	return readl(gpu->mmio + reg);
159 }
160 
161 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
162 
163 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
164 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
165 
166 #ifdef CONFIG_DEBUG_FS
167 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
168 #endif
169 
170 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
171 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
172 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
173 	u32 fence, struct timespec *timeout);
174 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
175 	struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
176 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
177 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
178 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
179 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
180 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
181 
182 extern struct platform_driver etnaviv_gpu_driver;
183 
184 #endif /* __ETNAVIV_GPU_H__ */
185