1 /* 2 * Copyright (C) 2015 Etnaviv Project 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ETNAVIV_GPU_H__ 18 #define __ETNAVIV_GPU_H__ 19 20 #include <linux/clk.h> 21 #include <linux/regulator/consumer.h> 22 23 #include "etnaviv_drv.h" 24 25 struct etnaviv_gem_submit; 26 struct etnaviv_vram_mapping; 27 28 struct etnaviv_chip_identity { 29 /* Chip model. */ 30 u32 model; 31 32 /* Revision value.*/ 33 u32 revision; 34 35 /* Supported feature fields. */ 36 u32 features; 37 38 /* Supported minor feature fields. */ 39 u32 minor_features0; 40 41 /* Supported minor feature 1 fields. */ 42 u32 minor_features1; 43 44 /* Supported minor feature 2 fields. */ 45 u32 minor_features2; 46 47 /* Supported minor feature 3 fields. */ 48 u32 minor_features3; 49 50 /* Supported minor feature 4 fields. */ 51 u32 minor_features4; 52 53 /* Supported minor feature 5 fields. */ 54 u32 minor_features5; 55 56 /* Number of streams supported. */ 57 u32 stream_count; 58 59 /* Total number of temporary registers per thread. */ 60 u32 register_max; 61 62 /* Maximum number of threads. */ 63 u32 thread_count; 64 65 /* Number of shader cores. */ 66 u32 shader_core_count; 67 68 /* Size of the vertex cache. */ 69 u32 vertex_cache_size; 70 71 /* Number of entries in the vertex output buffer. */ 72 u32 vertex_output_buffer_size; 73 74 /* Number of pixel pipes. */ 75 u32 pixel_pipes; 76 77 /* Number of instructions. */ 78 u32 instruction_count; 79 80 /* Number of constants. */ 81 u32 num_constants; 82 83 /* Buffer size */ 84 u32 buffer_size; 85 86 /* Number of varyings */ 87 u8 varyings_count; 88 }; 89 90 struct etnaviv_event { 91 bool used; 92 struct dma_fence *fence; 93 }; 94 95 struct etnaviv_cmdbuf_suballoc; 96 struct etnaviv_cmdbuf; 97 98 struct etnaviv_gpu { 99 struct drm_device *drm; 100 struct device *dev; 101 struct mutex lock; 102 struct etnaviv_chip_identity identity; 103 struct etnaviv_file_private *lastctx; 104 bool switch_context; 105 106 /* 'ring'-buffer: */ 107 struct etnaviv_cmdbuf *buffer; 108 int exec_state; 109 110 /* bus base address of memory */ 111 u32 memory_base; 112 113 /* event management: */ 114 struct etnaviv_event event[30]; 115 struct completion event_free; 116 spinlock_t event_spinlock; 117 118 /* list of currently in-flight command buffers */ 119 struct list_head active_cmd_list; 120 121 u32 idle_mask; 122 123 /* Fencing support */ 124 u32 next_fence; 125 u32 active_fence; 126 u32 completed_fence; 127 u32 retired_fence; 128 wait_queue_head_t fence_event; 129 u64 fence_context; 130 spinlock_t fence_spinlock; 131 132 /* worker for handling active-list retiring: */ 133 struct work_struct retire_work; 134 135 void __iomem *mmio; 136 int irq; 137 138 struct etnaviv_iommu *mmu; 139 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc; 140 141 /* Power Control: */ 142 struct clk *clk_bus; 143 struct clk *clk_core; 144 struct clk *clk_shader; 145 146 /* Hang Detction: */ 147 #define DRM_ETNAVIV_HANGCHECK_PERIOD 500 /* in ms */ 148 #define DRM_ETNAVIV_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_ETNAVIV_HANGCHECK_PERIOD) 149 struct timer_list hangcheck_timer; 150 u32 hangcheck_fence; 151 u32 hangcheck_dma_addr; 152 struct work_struct recover_work; 153 }; 154 155 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) 156 { 157 etnaviv_writel(data, gpu->mmio + reg); 158 } 159 160 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) 161 { 162 return etnaviv_readl(gpu->mmio + reg); 163 } 164 165 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence) 166 { 167 return fence_after_eq(gpu->completed_fence, fence); 168 } 169 170 static inline bool fence_retired(struct etnaviv_gpu *gpu, u32 fence) 171 { 172 return fence_after_eq(gpu->retired_fence, fence); 173 } 174 175 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 176 177 int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 178 179 #ifdef CONFIG_DEBUG_FS 180 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 181 #endif 182 183 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj, 184 unsigned int context, bool exclusive); 185 186 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); 187 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 188 u32 fence, struct timespec *timeout); 189 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 190 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); 191 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu, 192 struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf); 193 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); 194 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); 195 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms); 196 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch); 197 198 extern struct platform_driver etnaviv_gpu_driver; 199 200 #endif /* __ETNAVIV_GPU_H__ */ 201