1f6ffbd4fSLucas Stach /* SPDX-License-Identifier: GPL-2.0 */ 2a8c21a54SThe etnaviv authors /* 3f6ffbd4fSLucas Stach * Copyright (C) 2015-2018 Etnaviv Project 4a8c21a54SThe etnaviv authors */ 5a8c21a54SThe etnaviv authors 6a8c21a54SThe etnaviv authors #ifndef __ETNAVIV_GPU_H__ 7a8c21a54SThe etnaviv authors #define __ETNAVIV_GPU_H__ 8a8c21a54SThe etnaviv authors 92f9225dbSLucas Stach #include "etnaviv_cmdbuf.h" 10db82a043SLucas Stach #include "etnaviv_gem.h" 1127b67278SLucas Stach #include "etnaviv_mmu.h" 12a8c21a54SThe etnaviv authors #include "etnaviv_drv.h" 13a8c21a54SThe etnaviv authors 14a8c21a54SThe etnaviv authors struct etnaviv_gem_submit; 15b6325f40SRussell King struct etnaviv_vram_mapping; 16a8c21a54SThe etnaviv authors 17a8c21a54SThe etnaviv authors struct etnaviv_chip_identity { 18a8c21a54SThe etnaviv authors /* Chip model. */ 19a8c21a54SThe etnaviv authors u32 model; 20a8c21a54SThe etnaviv authors 21a8c21a54SThe etnaviv authors /* Revision value.*/ 22a8c21a54SThe etnaviv authors u32 revision; 23a8c21a54SThe etnaviv authors 24a8c21a54SThe etnaviv authors /* Supported feature fields. */ 25a8c21a54SThe etnaviv authors u32 features; 26a8c21a54SThe etnaviv authors 27a8c21a54SThe etnaviv authors /* Supported minor feature fields. */ 28a8c21a54SThe etnaviv authors u32 minor_features0; 29a8c21a54SThe etnaviv authors u32 minor_features1; 30a8c21a54SThe etnaviv authors u32 minor_features2; 31a8c21a54SThe etnaviv authors u32 minor_features3; 32602eb489SRussell King u32 minor_features4; 33602eb489SRussell King u32 minor_features5; 340538aaf9SLucas Stach u32 minor_features6; 350538aaf9SLucas Stach u32 minor_features7; 360538aaf9SLucas Stach u32 minor_features8; 370538aaf9SLucas Stach u32 minor_features9; 380538aaf9SLucas Stach u32 minor_features10; 390538aaf9SLucas Stach u32 minor_features11; 40602eb489SRussell King 41a8c21a54SThe etnaviv authors /* Number of streams supported. */ 42a8c21a54SThe etnaviv authors u32 stream_count; 43a8c21a54SThe etnaviv authors 44a8c21a54SThe etnaviv authors /* Total number of temporary registers per thread. */ 45a8c21a54SThe etnaviv authors u32 register_max; 46a8c21a54SThe etnaviv authors 47a8c21a54SThe etnaviv authors /* Maximum number of threads. */ 48a8c21a54SThe etnaviv authors u32 thread_count; 49a8c21a54SThe etnaviv authors 50a8c21a54SThe etnaviv authors /* Number of shader cores. */ 51a8c21a54SThe etnaviv authors u32 shader_core_count; 52a8c21a54SThe etnaviv authors 53a8c21a54SThe etnaviv authors /* Size of the vertex cache. */ 54a8c21a54SThe etnaviv authors u32 vertex_cache_size; 55a8c21a54SThe etnaviv authors 56a8c21a54SThe etnaviv authors /* Number of entries in the vertex output buffer. */ 57a8c21a54SThe etnaviv authors u32 vertex_output_buffer_size; 58a8c21a54SThe etnaviv authors 59a8c21a54SThe etnaviv authors /* Number of pixel pipes. */ 60a8c21a54SThe etnaviv authors u32 pixel_pipes; 61a8c21a54SThe etnaviv authors 62a8c21a54SThe etnaviv authors /* Number of instructions. */ 63a8c21a54SThe etnaviv authors u32 instruction_count; 64a8c21a54SThe etnaviv authors 65a8c21a54SThe etnaviv authors /* Number of constants. */ 66a8c21a54SThe etnaviv authors u32 num_constants; 67a8c21a54SThe etnaviv authors 68a8c21a54SThe etnaviv authors /* Buffer size */ 69a8c21a54SThe etnaviv authors u32 buffer_size; 70602eb489SRussell King 71602eb489SRussell King /* Number of varyings */ 72602eb489SRussell King u8 varyings_count; 73a8c21a54SThe etnaviv authors }; 74a8c21a54SThe etnaviv authors 75007ad58dSLucas Stach enum etnaviv_sec_mode { 76007ad58dSLucas Stach ETNA_SEC_NONE = 0, 77007ad58dSLucas Stach ETNA_SEC_KERNEL, 78007ad58dSLucas Stach ETNA_SEC_TZ 79007ad58dSLucas Stach }; 80007ad58dSLucas Stach 81a8c21a54SThe etnaviv authors struct etnaviv_event { 82f54d1867SChris Wilson struct dma_fence *fence; 83ef146c00SLucas Stach struct etnaviv_gem_submit *submit; 84357713ceSChristian Gmeiner 85357713ceSChristian Gmeiner void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event); 86a8c21a54SThe etnaviv authors }; 87a8c21a54SThe etnaviv authors 88e66774ddSLucas Stach struct etnaviv_cmdbuf_suballoc; 89f9d255f4SLucas Stach struct regulator; 90f9d255f4SLucas Stach struct clk; 91a8c21a54SThe etnaviv authors 92355502e0SChristian Gmeiner #define ETNA_NR_EVENTS 30 93355502e0SChristian Gmeiner 94a8c21a54SThe etnaviv authors struct etnaviv_gpu { 95a8c21a54SThe etnaviv authors struct drm_device *drm; 96bcdfb5e5SRussell King struct thermal_cooling_device *cooling; 97a8c21a54SThe etnaviv authors struct device *dev; 98a8c21a54SThe etnaviv authors struct mutex lock; 99a8c21a54SThe etnaviv authors struct etnaviv_chip_identity identity; 100007ad58dSLucas Stach enum etnaviv_sec_mode sec_mode; 101a7790d78SLucas Stach struct workqueue_struct *wq; 102e93b6deeSLucas Stach struct drm_gpu_scheduler sched; 103db41fe7dSLucas Stach bool initialized; 104a8c21a54SThe etnaviv authors 105a8c21a54SThe etnaviv authors /* 'ring'-buffer: */ 106db82a043SLucas Stach struct etnaviv_vram_mapping cmdbuf_mapping; 1072f9225dbSLucas Stach struct etnaviv_cmdbuf buffer; 108f6086311SRussell King int exec_state; 109a8c21a54SThe etnaviv authors 110a8c21a54SThe etnaviv authors /* bus base address of memory */ 111a8c21a54SThe etnaviv authors u32 memory_base; 112a8c21a54SThe etnaviv authors 113a8c21a54SThe etnaviv authors /* event management: */ 114355502e0SChristian Gmeiner DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS); 115355502e0SChristian Gmeiner struct etnaviv_event event[ETNA_NR_EVENTS]; 116a8c21a54SThe etnaviv authors struct completion event_free; 117a8c21a54SThe etnaviv authors spinlock_t event_spinlock; 118a8c21a54SThe etnaviv authors 119a8c21a54SThe etnaviv authors u32 idle_mask; 120a8c21a54SThe etnaviv authors 121a8c21a54SThe etnaviv authors /* Fencing support */ 122a0780bb1SLucas Stach struct mutex fence_lock; 1238bc4d885SLucas Stach struct idr fence_idr; 124a8c21a54SThe etnaviv authors u32 next_fence; 125a8c21a54SThe etnaviv authors u32 completed_fence; 126a8c21a54SThe etnaviv authors wait_queue_head_t fence_event; 12776bf0db5SChristian König u64 fence_context; 128a8c21a54SThe etnaviv authors spinlock_t fence_spinlock; 129a8c21a54SThe etnaviv authors 130357713ceSChristian Gmeiner /* worker for handling 'sync' points: */ 131357713ceSChristian Gmeiner struct work_struct sync_point_work; 132357713ceSChristian Gmeiner int sync_point_event; 133357713ceSChristian Gmeiner 1342c83a726SLucas Stach /* hang detection */ 1352c83a726SLucas Stach u32 hangcheck_dma_addr; 1362c83a726SLucas Stach 137a8c21a54SThe etnaviv authors void __iomem *mmio; 138a8c21a54SThe etnaviv authors int irq; 139a8c21a54SThe etnaviv authors 14027b67278SLucas Stach struct etnaviv_iommu_context *mmu_context; 1414900dda9SLucas Stach unsigned int flush_seq; 142a8c21a54SThe etnaviv authors 143a8c21a54SThe etnaviv authors /* Power Control: */ 144a8c21a54SThe etnaviv authors struct clk *clk_bus; 14565f037e8SLucas Stach struct clk *clk_reg; 146a8c21a54SThe etnaviv authors struct clk *clk_core; 147a8c21a54SThe etnaviv authors struct clk *clk_shader; 148a8c21a54SThe etnaviv authors 149bcdfb5e5SRussell King unsigned int freq_scale; 150d79fd1ccSLucas Stach unsigned long base_rate_core; 151d79fd1ccSLucas Stach unsigned long base_rate_shader; 152a8c21a54SThe etnaviv authors }; 153a8c21a54SThe etnaviv authors 154a8c21a54SThe etnaviv authors static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) 155a8c21a54SThe etnaviv authors { 156a98b1e78SLucas Stach writel(data, gpu->mmio + reg); 157a8c21a54SThe etnaviv authors } 158a8c21a54SThe etnaviv authors 159a8c21a54SThe etnaviv authors static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) 160a8c21a54SThe etnaviv authors { 161a98b1e78SLucas Stach return readl(gpu->mmio + reg); 162a8c21a54SThe etnaviv authors } 163a8c21a54SThe etnaviv authors 164a8c21a54SThe etnaviv authors int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value); 165a8c21a54SThe etnaviv authors 166a8c21a54SThe etnaviv authors int etnaviv_gpu_init(struct etnaviv_gpu *gpu); 167681c19c8SLucas Stach bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu); 168a8c21a54SThe etnaviv authors 169a8c21a54SThe etnaviv authors #ifdef CONFIG_DEBUG_FS 170a8c21a54SThe etnaviv authors int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m); 171a8c21a54SThe etnaviv authors #endif 172a8c21a54SThe etnaviv authors 1736d7a20c0SLucas Stach void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu); 174a8c21a54SThe etnaviv authors void etnaviv_gpu_retire(struct etnaviv_gpu *gpu); 175a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 176a8c21a54SThe etnaviv authors u32 fence, struct timespec *timeout); 177a8c21a54SThe etnaviv authors int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 178a8c21a54SThe etnaviv authors struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout); 179e93b6deeSLucas Stach struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit); 180a8c21a54SThe etnaviv authors int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu); 181a8c21a54SThe etnaviv authors void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu); 182b88163e3SLucas Stach int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms); 183229855b6SLucas Stach void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch); 184a8c21a54SThe etnaviv authors 185a8c21a54SThe etnaviv authors extern struct platform_driver etnaviv_gpu_driver; 186a8c21a54SThe etnaviv authors 187a8c21a54SThe etnaviv authors #endif /* __ETNAVIV_GPU_H__ */ 188