1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2015-2018 Etnaviv Project 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/delay.h> 9 #include <linux/dma-fence.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/thermal.h> 17 18 #include "etnaviv_cmdbuf.h" 19 #include "etnaviv_dump.h" 20 #include "etnaviv_gpu.h" 21 #include "etnaviv_gem.h" 22 #include "etnaviv_mmu.h" 23 #include "etnaviv_perfmon.h" 24 #include "etnaviv_sched.h" 25 #include "common.xml.h" 26 #include "state.xml.h" 27 #include "state_hi.xml.h" 28 #include "cmdstream.xml.h" 29 30 static const struct platform_device_id gpu_ids[] = { 31 { .name = "etnaviv-gpu,2d" }, 32 { }, 33 }; 34 35 /* 36 * Driver functions: 37 */ 38 39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) 40 { 41 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 42 43 switch (param) { 44 case ETNAVIV_PARAM_GPU_MODEL: 45 *value = gpu->identity.model; 46 break; 47 48 case ETNAVIV_PARAM_GPU_REVISION: 49 *value = gpu->identity.revision; 50 break; 51 52 case ETNAVIV_PARAM_GPU_FEATURES_0: 53 *value = gpu->identity.features; 54 break; 55 56 case ETNAVIV_PARAM_GPU_FEATURES_1: 57 *value = gpu->identity.minor_features0; 58 break; 59 60 case ETNAVIV_PARAM_GPU_FEATURES_2: 61 *value = gpu->identity.minor_features1; 62 break; 63 64 case ETNAVIV_PARAM_GPU_FEATURES_3: 65 *value = gpu->identity.minor_features2; 66 break; 67 68 case ETNAVIV_PARAM_GPU_FEATURES_4: 69 *value = gpu->identity.minor_features3; 70 break; 71 72 case ETNAVIV_PARAM_GPU_FEATURES_5: 73 *value = gpu->identity.minor_features4; 74 break; 75 76 case ETNAVIV_PARAM_GPU_FEATURES_6: 77 *value = gpu->identity.minor_features5; 78 break; 79 80 case ETNAVIV_PARAM_GPU_FEATURES_7: 81 *value = gpu->identity.minor_features6; 82 break; 83 84 case ETNAVIV_PARAM_GPU_FEATURES_8: 85 *value = gpu->identity.minor_features7; 86 break; 87 88 case ETNAVIV_PARAM_GPU_FEATURES_9: 89 *value = gpu->identity.minor_features8; 90 break; 91 92 case ETNAVIV_PARAM_GPU_FEATURES_10: 93 *value = gpu->identity.minor_features9; 94 break; 95 96 case ETNAVIV_PARAM_GPU_FEATURES_11: 97 *value = gpu->identity.minor_features10; 98 break; 99 100 case ETNAVIV_PARAM_GPU_FEATURES_12: 101 *value = gpu->identity.minor_features11; 102 break; 103 104 case ETNAVIV_PARAM_GPU_STREAM_COUNT: 105 *value = gpu->identity.stream_count; 106 break; 107 108 case ETNAVIV_PARAM_GPU_REGISTER_MAX: 109 *value = gpu->identity.register_max; 110 break; 111 112 case ETNAVIV_PARAM_GPU_THREAD_COUNT: 113 *value = gpu->identity.thread_count; 114 break; 115 116 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE: 117 *value = gpu->identity.vertex_cache_size; 118 break; 119 120 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT: 121 *value = gpu->identity.shader_core_count; 122 break; 123 124 case ETNAVIV_PARAM_GPU_PIXEL_PIPES: 125 *value = gpu->identity.pixel_pipes; 126 break; 127 128 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE: 129 *value = gpu->identity.vertex_output_buffer_size; 130 break; 131 132 case ETNAVIV_PARAM_GPU_BUFFER_SIZE: 133 *value = gpu->identity.buffer_size; 134 break; 135 136 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT: 137 *value = gpu->identity.instruction_count; 138 break; 139 140 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS: 141 *value = gpu->identity.num_constants; 142 break; 143 144 case ETNAVIV_PARAM_GPU_NUM_VARYINGS: 145 *value = gpu->identity.varyings_count; 146 break; 147 148 case ETNAVIV_PARAM_SOFTPIN_START_ADDR: 149 if (priv->mmu_global->version == ETNAVIV_IOMMU_V2) 150 *value = ETNAVIV_SOFTPIN_START_ADDRESS; 151 else 152 *value = ~0ULL; 153 break; 154 155 case ETNAVIV_PARAM_GPU_PRODUCT_ID: 156 *value = gpu->identity.product_id; 157 break; 158 159 case ETNAVIV_PARAM_GPU_CUSTOMER_ID: 160 *value = gpu->identity.customer_id; 161 break; 162 163 case ETNAVIV_PARAM_GPU_ECO_ID: 164 *value = gpu->identity.eco_id; 165 break; 166 167 default: 168 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); 169 return -EINVAL; 170 } 171 172 return 0; 173 } 174 175 176 #define etnaviv_is_model_rev(gpu, mod, rev) \ 177 ((gpu)->identity.model == chipModel_##mod && \ 178 (gpu)->identity.revision == rev) 179 #define etnaviv_field(val, field) \ 180 (((val) & field##__MASK) >> field##__SHIFT) 181 182 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) 183 { 184 if (gpu->identity.minor_features0 & 185 chipMinorFeatures0_MORE_MINOR_FEATURES) { 186 u32 specs[4]; 187 unsigned int streams; 188 189 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); 190 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); 191 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); 192 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); 193 194 gpu->identity.stream_count = etnaviv_field(specs[0], 195 VIVS_HI_CHIP_SPECS_STREAM_COUNT); 196 gpu->identity.register_max = etnaviv_field(specs[0], 197 VIVS_HI_CHIP_SPECS_REGISTER_MAX); 198 gpu->identity.thread_count = etnaviv_field(specs[0], 199 VIVS_HI_CHIP_SPECS_THREAD_COUNT); 200 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], 201 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE); 202 gpu->identity.shader_core_count = etnaviv_field(specs[0], 203 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT); 204 gpu->identity.pixel_pipes = etnaviv_field(specs[0], 205 VIVS_HI_CHIP_SPECS_PIXEL_PIPES); 206 gpu->identity.vertex_output_buffer_size = 207 etnaviv_field(specs[0], 208 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE); 209 210 gpu->identity.buffer_size = etnaviv_field(specs[1], 211 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE); 212 gpu->identity.instruction_count = etnaviv_field(specs[1], 213 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT); 214 gpu->identity.num_constants = etnaviv_field(specs[1], 215 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS); 216 217 gpu->identity.varyings_count = etnaviv_field(specs[2], 218 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT); 219 220 /* This overrides the value from older register if non-zero */ 221 streams = etnaviv_field(specs[3], 222 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT); 223 if (streams) 224 gpu->identity.stream_count = streams; 225 } 226 227 /* Fill in the stream count if not specified */ 228 if (gpu->identity.stream_count == 0) { 229 if (gpu->identity.model >= 0x1000) 230 gpu->identity.stream_count = 4; 231 else 232 gpu->identity.stream_count = 1; 233 } 234 235 /* Convert the register max value */ 236 if (gpu->identity.register_max) 237 gpu->identity.register_max = 1 << gpu->identity.register_max; 238 else if (gpu->identity.model == chipModel_GC400) 239 gpu->identity.register_max = 32; 240 else 241 gpu->identity.register_max = 64; 242 243 /* Convert thread count */ 244 if (gpu->identity.thread_count) 245 gpu->identity.thread_count = 1 << gpu->identity.thread_count; 246 else if (gpu->identity.model == chipModel_GC400) 247 gpu->identity.thread_count = 64; 248 else if (gpu->identity.model == chipModel_GC500 || 249 gpu->identity.model == chipModel_GC530) 250 gpu->identity.thread_count = 128; 251 else 252 gpu->identity.thread_count = 256; 253 254 if (gpu->identity.vertex_cache_size == 0) 255 gpu->identity.vertex_cache_size = 8; 256 257 if (gpu->identity.shader_core_count == 0) { 258 if (gpu->identity.model >= 0x1000) 259 gpu->identity.shader_core_count = 2; 260 else 261 gpu->identity.shader_core_count = 1; 262 } 263 264 if (gpu->identity.pixel_pipes == 0) 265 gpu->identity.pixel_pipes = 1; 266 267 /* Convert virtex buffer size */ 268 if (gpu->identity.vertex_output_buffer_size) { 269 gpu->identity.vertex_output_buffer_size = 270 1 << gpu->identity.vertex_output_buffer_size; 271 } else if (gpu->identity.model == chipModel_GC400) { 272 if (gpu->identity.revision < 0x4000) 273 gpu->identity.vertex_output_buffer_size = 512; 274 else if (gpu->identity.revision < 0x4200) 275 gpu->identity.vertex_output_buffer_size = 256; 276 else 277 gpu->identity.vertex_output_buffer_size = 128; 278 } else { 279 gpu->identity.vertex_output_buffer_size = 512; 280 } 281 282 switch (gpu->identity.instruction_count) { 283 case 0: 284 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 285 gpu->identity.model == chipModel_GC880) 286 gpu->identity.instruction_count = 512; 287 else 288 gpu->identity.instruction_count = 256; 289 break; 290 291 case 1: 292 gpu->identity.instruction_count = 1024; 293 break; 294 295 case 2: 296 gpu->identity.instruction_count = 2048; 297 break; 298 299 default: 300 gpu->identity.instruction_count = 256; 301 break; 302 } 303 304 if (gpu->identity.num_constants == 0) 305 gpu->identity.num_constants = 168; 306 307 if (gpu->identity.varyings_count == 0) { 308 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) 309 gpu->identity.varyings_count = 12; 310 else 311 gpu->identity.varyings_count = 8; 312 } 313 314 /* 315 * For some cores, two varyings are consumed for position, so the 316 * maximum varying count needs to be reduced by one. 317 */ 318 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || 319 etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 320 etnaviv_is_model_rev(gpu, GC4000, 0x5245) || 321 etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 322 etnaviv_is_model_rev(gpu, GC3000, 0x5435) || 323 etnaviv_is_model_rev(gpu, GC2200, 0x5244) || 324 etnaviv_is_model_rev(gpu, GC2100, 0x5108) || 325 etnaviv_is_model_rev(gpu, GC2000, 0x5108) || 326 etnaviv_is_model_rev(gpu, GC1500, 0x5246) || 327 etnaviv_is_model_rev(gpu, GC880, 0x5107) || 328 etnaviv_is_model_rev(gpu, GC880, 0x5106)) 329 gpu->identity.varyings_count -= 1; 330 } 331 332 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) 333 { 334 u32 chipIdentity; 335 336 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); 337 338 /* Special case for older graphic cores. */ 339 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) { 340 gpu->identity.model = chipModel_GC500; 341 gpu->identity.revision = etnaviv_field(chipIdentity, 342 VIVS_HI_CHIP_IDENTITY_REVISION); 343 } else { 344 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); 345 346 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); 347 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); 348 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); 349 350 /* 351 * Reading these two registers on GC600 rev 0x19 result in a 352 * unhandled fault: external abort on non-linefetch 353 */ 354 if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { 355 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); 356 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); 357 } 358 359 /* 360 * !!!! HACK ALERT !!!! 361 * Because people change device IDs without letting software 362 * know about it - here is the hack to make it all look the 363 * same. Only for GC400 family. 364 */ 365 if ((gpu->identity.model & 0xff00) == 0x0400 && 366 gpu->identity.model != chipModel_GC420) { 367 gpu->identity.model = gpu->identity.model & 0x0400; 368 } 369 370 /* Another special case */ 371 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { 372 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); 373 374 if (chipDate == 0x20080814 && chipTime == 0x12051100) { 375 /* 376 * This IP has an ECO; put the correct 377 * revision in it. 378 */ 379 gpu->identity.revision = 0x1051; 380 } 381 } 382 383 /* 384 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in 385 * reality it's just a re-branded GC3000. We can identify this 386 * core by the upper half of the revision register being all 1. 387 * Fix model/rev here, so all other places can refer to this 388 * core by its real identity. 389 */ 390 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { 391 gpu->identity.model = chipModel_GC3000; 392 gpu->identity.revision &= 0xffff; 393 } 394 395 if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) 396 gpu->identity.eco_id = 1; 397 398 if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) 399 gpu->identity.eco_id = 1; 400 } 401 402 dev_info(gpu->dev, "model: GC%x, revision: %x\n", 403 gpu->identity.model, gpu->identity.revision); 404 405 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; 406 /* 407 * If there is a match in the HWDB, we aren't interested in the 408 * remaining register values, as they might be wrong. 409 */ 410 if (etnaviv_fill_identity_from_hwdb(gpu)) 411 return; 412 413 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); 414 415 /* Disable fast clear on GC700. */ 416 if (gpu->identity.model == chipModel_GC700) 417 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 418 419 if ((gpu->identity.model == chipModel_GC500 && 420 gpu->identity.revision < 2) || 421 (gpu->identity.model == chipModel_GC300 && 422 gpu->identity.revision < 0x2000)) { 423 424 /* 425 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these 426 * registers. 427 */ 428 gpu->identity.minor_features0 = 0; 429 gpu->identity.minor_features1 = 0; 430 gpu->identity.minor_features2 = 0; 431 gpu->identity.minor_features3 = 0; 432 gpu->identity.minor_features4 = 0; 433 gpu->identity.minor_features5 = 0; 434 } else 435 gpu->identity.minor_features0 = 436 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); 437 438 if (gpu->identity.minor_features0 & 439 chipMinorFeatures0_MORE_MINOR_FEATURES) { 440 gpu->identity.minor_features1 = 441 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); 442 gpu->identity.minor_features2 = 443 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); 444 gpu->identity.minor_features3 = 445 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); 446 gpu->identity.minor_features4 = 447 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); 448 gpu->identity.minor_features5 = 449 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); 450 } 451 452 /* GC600 idle register reports zero bits where modules aren't present */ 453 if (gpu->identity.model == chipModel_GC600) 454 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | 455 VIVS_HI_IDLE_STATE_RA | 456 VIVS_HI_IDLE_STATE_SE | 457 VIVS_HI_IDLE_STATE_PA | 458 VIVS_HI_IDLE_STATE_SH | 459 VIVS_HI_IDLE_STATE_PE | 460 VIVS_HI_IDLE_STATE_DE | 461 VIVS_HI_IDLE_STATE_FE; 462 463 etnaviv_hw_specs(gpu); 464 } 465 466 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) 467 { 468 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | 469 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD); 470 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); 471 } 472 473 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) 474 { 475 if (gpu->identity.minor_features2 & 476 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) { 477 clk_set_rate(gpu->clk_core, 478 gpu->base_rate_core >> gpu->freq_scale); 479 clk_set_rate(gpu->clk_shader, 480 gpu->base_rate_shader >> gpu->freq_scale); 481 } else { 482 unsigned int fscale = 1 << (6 - gpu->freq_scale); 483 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 484 485 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK; 486 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 487 etnaviv_gpu_load_clock(gpu, clock); 488 } 489 } 490 491 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) 492 { 493 u32 control, idle; 494 unsigned long timeout; 495 bool failed = true; 496 497 /* We hope that the GPU resets in under one second */ 498 timeout = jiffies + msecs_to_jiffies(1000); 499 500 while (time_is_after_jiffies(timeout)) { 501 /* enable clock */ 502 unsigned int fscale = 1 << (6 - gpu->freq_scale); 503 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale); 504 etnaviv_gpu_load_clock(gpu, control); 505 506 /* isolate the GPU. */ 507 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 508 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 509 510 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 511 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, 512 VIVS_MMUv2_AHB_CONTROL_RESET); 513 } else { 514 /* set soft reset. */ 515 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 516 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 517 } 518 519 /* wait for reset. */ 520 usleep_range(10, 20); 521 522 /* reset soft reset bit. */ 523 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET; 524 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 525 526 /* reset GPU isolation. */ 527 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU; 528 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 529 530 /* read idle register. */ 531 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 532 533 /* try resetting again if FE is not idle */ 534 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) { 535 dev_dbg(gpu->dev, "FE is not idle\n"); 536 continue; 537 } 538 539 /* read reset register. */ 540 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 541 542 /* is the GPU idle? */ 543 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) || 544 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) { 545 dev_dbg(gpu->dev, "GPU is not idle\n"); 546 continue; 547 } 548 549 /* disable debug registers, as they are not normally needed */ 550 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 551 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); 552 553 failed = false; 554 break; 555 } 556 557 if (failed) { 558 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 559 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 560 561 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", 562 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ", 563 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ", 564 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not "); 565 566 return -EBUSY; 567 } 568 569 /* We rely on the GPU running, so program the clock */ 570 etnaviv_gpu_update_clock(gpu); 571 572 return 0; 573 } 574 575 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 576 { 577 u32 pmc, ppc; 578 579 /* enable clock gating */ 580 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 581 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 582 583 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */ 584 if (gpu->identity.revision == 0x4301 || 585 gpu->identity.revision == 0x4302) 586 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING; 587 588 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); 589 590 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS); 591 592 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */ 593 if (gpu->identity.model >= chipModel_GC400 && 594 gpu->identity.model != chipModel_GC420 && 595 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) 596 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA; 597 598 /* 599 * Disable PE clock gating on revs < 5.0.0.0 when HZ is 600 * present without a bug fix. 601 */ 602 if (gpu->identity.revision < 0x5000 && 603 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && 604 !(gpu->identity.minor_features1 & 605 chipMinorFeatures1_DISABLE_PE_GATING)) 606 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE; 607 608 if (gpu->identity.revision < 0x5422) 609 pmc |= BIT(15); /* Unknown bit */ 610 611 /* Disable TX clock gating on affected core revisions. */ 612 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || 613 etnaviv_is_model_rev(gpu, GC2000, 0x5108)) 614 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 615 616 /* Disable SE, RA and TX clock gating on affected core revisions. */ 617 if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) 618 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | 619 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA | 620 VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; 621 622 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; 623 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; 624 625 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); 626 } 627 628 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) 629 { 630 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); 631 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, 632 VIVS_FE_COMMAND_CONTROL_ENABLE | 633 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch)); 634 635 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 636 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, 637 VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE | 638 VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch)); 639 } 640 } 641 642 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu) 643 { 644 u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer, 645 &gpu->mmu_context->cmdbuf_mapping); 646 u16 prefetch; 647 648 /* setup the MMU */ 649 etnaviv_iommu_restore(gpu, gpu->mmu_context); 650 651 /* Start command processor */ 652 prefetch = etnaviv_buffer_init(gpu); 653 654 etnaviv_gpu_start_fe(gpu, address, prefetch); 655 } 656 657 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) 658 { 659 /* 660 * Base value for VIVS_PM_PULSE_EATER register on models where it 661 * cannot be read, extracted from vivante kernel driver. 662 */ 663 u32 pulse_eater = 0x01590880; 664 665 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || 666 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { 667 pulse_eater |= BIT(23); 668 669 } 670 671 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || 672 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { 673 pulse_eater &= ~BIT(16); 674 pulse_eater |= BIT(17); 675 } 676 677 if ((gpu->identity.revision > 0x5420) && 678 (gpu->identity.features & chipFeatures_PIPE_3D)) 679 { 680 /* Performance fix: disable internal DFS */ 681 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER); 682 pulse_eater |= BIT(18); 683 } 684 685 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater); 686 } 687 688 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) 689 { 690 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || 691 etnaviv_is_model_rev(gpu, GC320, 0x5220)) && 692 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { 693 u32 mc_memory_debug; 694 695 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; 696 697 if (gpu->identity.revision == 0x5007) 698 mc_memory_debug |= 0x0c; 699 else 700 mc_memory_debug |= 0x08; 701 702 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); 703 } 704 705 /* enable module-level clock gating */ 706 etnaviv_gpu_enable_mlcg(gpu); 707 708 /* 709 * Update GPU AXI cache atttribute to "cacheable, no allocate". 710 * This is necessary to prevent the iMX6 SoC locking up. 711 */ 712 gpu_write(gpu, VIVS_HI_AXI_CONFIG, 713 VIVS_HI_AXI_CONFIG_AWCACHE(2) | 714 VIVS_HI_AXI_CONFIG_ARCACHE(2)); 715 716 /* GC2000 rev 5108 needs a special bus config */ 717 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { 718 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); 719 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | 720 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); 721 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) | 722 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0); 723 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); 724 } 725 726 if (gpu->sec_mode == ETNA_SEC_KERNEL) { 727 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); 728 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS; 729 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); 730 } 731 732 /* setup the pulse eater */ 733 etnaviv_gpu_setup_pulse_eater(gpu); 734 735 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); 736 } 737 738 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) 739 { 740 struct etnaviv_drm_private *priv = gpu->drm->dev_private; 741 dma_addr_t cmdbuf_paddr; 742 int ret, i; 743 744 ret = pm_runtime_get_sync(gpu->dev); 745 if (ret < 0) { 746 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); 747 goto pm_put; 748 } 749 750 etnaviv_hw_identify(gpu); 751 752 if (gpu->identity.model == 0) { 753 dev_err(gpu->dev, "Unknown GPU model\n"); 754 ret = -ENXIO; 755 goto fail; 756 } 757 758 /* Exclude VG cores with FE2.0 */ 759 if (gpu->identity.features & chipFeatures_PIPE_VG && 760 gpu->identity.features & chipFeatures_FE20) { 761 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); 762 ret = -ENXIO; 763 goto fail; 764 } 765 766 /* 767 * On cores with security features supported, we claim control over the 768 * security states. 769 */ 770 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && 771 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) 772 gpu->sec_mode = ETNA_SEC_KERNEL; 773 774 ret = etnaviv_hw_reset(gpu); 775 if (ret) { 776 dev_err(gpu->dev, "GPU reset failed\n"); 777 goto fail; 778 } 779 780 ret = etnaviv_iommu_global_init(gpu); 781 if (ret) 782 goto fail; 783 784 /* 785 * If the GPU is part of a system with DMA addressing limitations, 786 * request pages for our SHM backend buffers from the DMA32 zone to 787 * hopefully avoid performance killing SWIOTLB bounce buffering. 788 */ 789 if (dma_addressing_limited(gpu->dev)) 790 priv->shm_gfp_mask |= GFP_DMA32; 791 792 /* Create buffer: */ 793 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, 794 PAGE_SIZE); 795 if (ret) { 796 dev_err(gpu->dev, "could not create command buffer\n"); 797 goto fail; 798 } 799 800 /* 801 * Set the GPU linear window to cover the cmdbuf region, as the GPU 802 * won't be able to start execution otherwise. The alignment to 128M is 803 * chosen arbitrarily but helps in debugging, as the MMU offset 804 * calculations are much more straight forward this way. 805 * 806 * On MC1.0 cores the linear window offset is ignored by the TS engine, 807 * leading to inconsistent memory views. Avoid using the offset on those 808 * cores if possible, otherwise disable the TS feature. 809 */ 810 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); 811 812 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || 813 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { 814 if (cmdbuf_paddr >= SZ_2G) 815 priv->mmu_global->memory_base = SZ_2G; 816 else 817 priv->mmu_global->memory_base = cmdbuf_paddr; 818 } else if (cmdbuf_paddr + SZ_128M >= SZ_2G) { 819 dev_info(gpu->dev, 820 "Need to move linear window on MC1.0, disabling TS\n"); 821 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; 822 priv->mmu_global->memory_base = SZ_2G; 823 } 824 825 /* Setup event management */ 826 spin_lock_init(&gpu->event_spinlock); 827 init_completion(&gpu->event_free); 828 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 829 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) 830 complete(&gpu->event_free); 831 832 /* Now program the hardware */ 833 mutex_lock(&gpu->lock); 834 etnaviv_gpu_hw_init(gpu); 835 gpu->exec_state = -1; 836 mutex_unlock(&gpu->lock); 837 838 pm_runtime_mark_last_busy(gpu->dev); 839 pm_runtime_put_autosuspend(gpu->dev); 840 841 gpu->initialized = true; 842 843 return 0; 844 845 fail: 846 pm_runtime_mark_last_busy(gpu->dev); 847 pm_put: 848 pm_runtime_put_autosuspend(gpu->dev); 849 850 return ret; 851 } 852 853 #ifdef CONFIG_DEBUG_FS 854 struct dma_debug { 855 u32 address[2]; 856 u32 state[2]; 857 }; 858 859 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) 860 { 861 u32 i; 862 863 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 864 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 865 866 for (i = 0; i < 500; i++) { 867 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 868 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); 869 870 if (debug->address[0] != debug->address[1]) 871 break; 872 873 if (debug->state[0] != debug->state[1]) 874 break; 875 } 876 } 877 878 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) 879 { 880 struct dma_debug debug; 881 u32 dma_lo, dma_hi, axi, idle; 882 int ret; 883 884 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); 885 886 ret = pm_runtime_get_sync(gpu->dev); 887 if (ret < 0) 888 goto pm_put; 889 890 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); 891 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); 892 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); 893 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 894 895 verify_dma(gpu, &debug); 896 897 seq_puts(m, "\tidentity\n"); 898 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); 899 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); 900 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); 901 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); 902 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); 903 904 seq_puts(m, "\tfeatures\n"); 905 seq_printf(m, "\t major_features: 0x%08x\n", 906 gpu->identity.features); 907 seq_printf(m, "\t minor_features0: 0x%08x\n", 908 gpu->identity.minor_features0); 909 seq_printf(m, "\t minor_features1: 0x%08x\n", 910 gpu->identity.minor_features1); 911 seq_printf(m, "\t minor_features2: 0x%08x\n", 912 gpu->identity.minor_features2); 913 seq_printf(m, "\t minor_features3: 0x%08x\n", 914 gpu->identity.minor_features3); 915 seq_printf(m, "\t minor_features4: 0x%08x\n", 916 gpu->identity.minor_features4); 917 seq_printf(m, "\t minor_features5: 0x%08x\n", 918 gpu->identity.minor_features5); 919 seq_printf(m, "\t minor_features6: 0x%08x\n", 920 gpu->identity.minor_features6); 921 seq_printf(m, "\t minor_features7: 0x%08x\n", 922 gpu->identity.minor_features7); 923 seq_printf(m, "\t minor_features8: 0x%08x\n", 924 gpu->identity.minor_features8); 925 seq_printf(m, "\t minor_features9: 0x%08x\n", 926 gpu->identity.minor_features9); 927 seq_printf(m, "\t minor_features10: 0x%08x\n", 928 gpu->identity.minor_features10); 929 seq_printf(m, "\t minor_features11: 0x%08x\n", 930 gpu->identity.minor_features11); 931 932 seq_puts(m, "\tspecs\n"); 933 seq_printf(m, "\t stream_count: %d\n", 934 gpu->identity.stream_count); 935 seq_printf(m, "\t register_max: %d\n", 936 gpu->identity.register_max); 937 seq_printf(m, "\t thread_count: %d\n", 938 gpu->identity.thread_count); 939 seq_printf(m, "\t vertex_cache_size: %d\n", 940 gpu->identity.vertex_cache_size); 941 seq_printf(m, "\t shader_core_count: %d\n", 942 gpu->identity.shader_core_count); 943 seq_printf(m, "\t pixel_pipes: %d\n", 944 gpu->identity.pixel_pipes); 945 seq_printf(m, "\t vertex_output_buffer_size: %d\n", 946 gpu->identity.vertex_output_buffer_size); 947 seq_printf(m, "\t buffer_size: %d\n", 948 gpu->identity.buffer_size); 949 seq_printf(m, "\t instruction_count: %d\n", 950 gpu->identity.instruction_count); 951 seq_printf(m, "\t num_constants: %d\n", 952 gpu->identity.num_constants); 953 seq_printf(m, "\t varyings_count: %d\n", 954 gpu->identity.varyings_count); 955 956 seq_printf(m, "\taxi: 0x%08x\n", axi); 957 seq_printf(m, "\tidle: 0x%08x\n", idle); 958 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; 959 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) 960 seq_puts(m, "\t FE is not idle\n"); 961 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0) 962 seq_puts(m, "\t DE is not idle\n"); 963 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0) 964 seq_puts(m, "\t PE is not idle\n"); 965 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0) 966 seq_puts(m, "\t SH is not idle\n"); 967 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0) 968 seq_puts(m, "\t PA is not idle\n"); 969 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0) 970 seq_puts(m, "\t SE is not idle\n"); 971 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0) 972 seq_puts(m, "\t RA is not idle\n"); 973 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0) 974 seq_puts(m, "\t TX is not idle\n"); 975 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0) 976 seq_puts(m, "\t VG is not idle\n"); 977 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0) 978 seq_puts(m, "\t IM is not idle\n"); 979 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0) 980 seq_puts(m, "\t FP is not idle\n"); 981 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0) 982 seq_puts(m, "\t TS is not idle\n"); 983 if ((idle & VIVS_HI_IDLE_STATE_BL) == 0) 984 seq_puts(m, "\t BL is not idle\n"); 985 if ((idle & VIVS_HI_IDLE_STATE_ASYNCFE) == 0) 986 seq_puts(m, "\t ASYNCFE is not idle\n"); 987 if ((idle & VIVS_HI_IDLE_STATE_MC) == 0) 988 seq_puts(m, "\t MC is not idle\n"); 989 if ((idle & VIVS_HI_IDLE_STATE_PPA) == 0) 990 seq_puts(m, "\t PPA is not idle\n"); 991 if ((idle & VIVS_HI_IDLE_STATE_WD) == 0) 992 seq_puts(m, "\t WD is not idle\n"); 993 if ((idle & VIVS_HI_IDLE_STATE_NN) == 0) 994 seq_puts(m, "\t NN is not idle\n"); 995 if ((idle & VIVS_HI_IDLE_STATE_TP) == 0) 996 seq_puts(m, "\t TP is not idle\n"); 997 if (idle & VIVS_HI_IDLE_STATE_AXI_LP) 998 seq_puts(m, "\t AXI low power mode\n"); 999 1000 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { 1001 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); 1002 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); 1003 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); 1004 1005 seq_puts(m, "\tMC\n"); 1006 seq_printf(m, "\t read0: 0x%08x\n", read0); 1007 seq_printf(m, "\t read1: 0x%08x\n", read1); 1008 seq_printf(m, "\t write: 0x%08x\n", write); 1009 } 1010 1011 seq_puts(m, "\tDMA "); 1012 1013 if (debug.address[0] == debug.address[1] && 1014 debug.state[0] == debug.state[1]) { 1015 seq_puts(m, "seems to be stuck\n"); 1016 } else if (debug.address[0] == debug.address[1]) { 1017 seq_puts(m, "address is constant\n"); 1018 } else { 1019 seq_puts(m, "is running\n"); 1020 } 1021 1022 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]); 1023 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]); 1024 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]); 1025 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]); 1026 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n", 1027 dma_lo, dma_hi); 1028 1029 ret = 0; 1030 1031 pm_runtime_mark_last_busy(gpu->dev); 1032 pm_put: 1033 pm_runtime_put_autosuspend(gpu->dev); 1034 1035 return ret; 1036 } 1037 #endif 1038 1039 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu) 1040 { 1041 unsigned int i = 0; 1042 1043 dev_err(gpu->dev, "recover hung GPU!\n"); 1044 1045 if (pm_runtime_get_sync(gpu->dev) < 0) 1046 goto pm_put; 1047 1048 mutex_lock(&gpu->lock); 1049 1050 etnaviv_hw_reset(gpu); 1051 1052 /* complete all events, the GPU won't do it after the reset */ 1053 spin_lock(&gpu->event_spinlock); 1054 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) 1055 complete(&gpu->event_free); 1056 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); 1057 spin_unlock(&gpu->event_spinlock); 1058 1059 etnaviv_gpu_hw_init(gpu); 1060 gpu->exec_state = -1; 1061 gpu->mmu_context = NULL; 1062 1063 mutex_unlock(&gpu->lock); 1064 pm_runtime_mark_last_busy(gpu->dev); 1065 pm_put: 1066 pm_runtime_put_autosuspend(gpu->dev); 1067 } 1068 1069 /* fence object management */ 1070 struct etnaviv_fence { 1071 struct etnaviv_gpu *gpu; 1072 struct dma_fence base; 1073 }; 1074 1075 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence) 1076 { 1077 return container_of(fence, struct etnaviv_fence, base); 1078 } 1079 1080 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence) 1081 { 1082 return "etnaviv"; 1083 } 1084 1085 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence) 1086 { 1087 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1088 1089 return dev_name(f->gpu->dev); 1090 } 1091 1092 static bool etnaviv_fence_signaled(struct dma_fence *fence) 1093 { 1094 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1095 1096 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; 1097 } 1098 1099 static void etnaviv_fence_release(struct dma_fence *fence) 1100 { 1101 struct etnaviv_fence *f = to_etnaviv_fence(fence); 1102 1103 kfree_rcu(f, base.rcu); 1104 } 1105 1106 static const struct dma_fence_ops etnaviv_fence_ops = { 1107 .get_driver_name = etnaviv_fence_get_driver_name, 1108 .get_timeline_name = etnaviv_fence_get_timeline_name, 1109 .signaled = etnaviv_fence_signaled, 1110 .release = etnaviv_fence_release, 1111 }; 1112 1113 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) 1114 { 1115 struct etnaviv_fence *f; 1116 1117 /* 1118 * GPU lock must already be held, otherwise fence completion order might 1119 * not match the seqno order assigned here. 1120 */ 1121 lockdep_assert_held(&gpu->lock); 1122 1123 f = kzalloc(sizeof(*f), GFP_KERNEL); 1124 if (!f) 1125 return NULL; 1126 1127 f->gpu = gpu; 1128 1129 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, 1130 gpu->fence_context, ++gpu->next_fence); 1131 1132 return &f->base; 1133 } 1134 1135 /* returns true if fence a comes after fence b */ 1136 static inline bool fence_after(u32 a, u32 b) 1137 { 1138 return (s32)(a - b) > 0; 1139 } 1140 1141 /* 1142 * event management: 1143 */ 1144 1145 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, 1146 unsigned int *events) 1147 { 1148 unsigned long timeout = msecs_to_jiffies(10 * 10000); 1149 unsigned i, acquired = 0; 1150 1151 for (i = 0; i < nr_events; i++) { 1152 unsigned long ret; 1153 1154 ret = wait_for_completion_timeout(&gpu->event_free, timeout); 1155 1156 if (!ret) { 1157 dev_err(gpu->dev, "wait_for_completion_timeout failed"); 1158 goto out; 1159 } 1160 1161 acquired++; 1162 timeout = ret; 1163 } 1164 1165 spin_lock(&gpu->event_spinlock); 1166 1167 for (i = 0; i < nr_events; i++) { 1168 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); 1169 1170 events[i] = event; 1171 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); 1172 set_bit(event, gpu->event_bitmap); 1173 } 1174 1175 spin_unlock(&gpu->event_spinlock); 1176 1177 return 0; 1178 1179 out: 1180 for (i = 0; i < acquired; i++) 1181 complete(&gpu->event_free); 1182 1183 return -EBUSY; 1184 } 1185 1186 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) 1187 { 1188 if (!test_bit(event, gpu->event_bitmap)) { 1189 dev_warn(gpu->dev, "event %u is already marked as free", 1190 event); 1191 } else { 1192 clear_bit(event, gpu->event_bitmap); 1193 complete(&gpu->event_free); 1194 } 1195 } 1196 1197 /* 1198 * Cmdstream submission/retirement: 1199 */ 1200 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, 1201 u32 id, struct drm_etnaviv_timespec *timeout) 1202 { 1203 struct dma_fence *fence; 1204 int ret; 1205 1206 /* 1207 * Look up the fence and take a reference. We might still find a fence 1208 * whose refcount has already dropped to zero. dma_fence_get_rcu 1209 * pretends we didn't find a fence in that case. 1210 */ 1211 rcu_read_lock(); 1212 fence = idr_find(&gpu->fence_idr, id); 1213 if (fence) 1214 fence = dma_fence_get_rcu(fence); 1215 rcu_read_unlock(); 1216 1217 if (!fence) 1218 return 0; 1219 1220 if (!timeout) { 1221 /* No timeout was requested: just test for completion */ 1222 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY; 1223 } else { 1224 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout); 1225 1226 ret = dma_fence_wait_timeout(fence, true, remaining); 1227 if (ret == 0) 1228 ret = -ETIMEDOUT; 1229 else if (ret != -ERESTARTSYS) 1230 ret = 0; 1231 1232 } 1233 1234 dma_fence_put(fence); 1235 return ret; 1236 } 1237 1238 /* 1239 * Wait for an object to become inactive. This, on it's own, is not race 1240 * free: the object is moved by the scheduler off the active list, and 1241 * then the iova is put. Moreover, the object could be re-submitted just 1242 * after we notice that it's become inactive. 1243 * 1244 * Although the retirement happens under the gpu lock, we don't want to hold 1245 * that lock in this function while waiting. 1246 */ 1247 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, 1248 struct etnaviv_gem_object *etnaviv_obj, 1249 struct drm_etnaviv_timespec *timeout) 1250 { 1251 unsigned long remaining; 1252 long ret; 1253 1254 if (!timeout) 1255 return !is_active(etnaviv_obj) ? 0 : -EBUSY; 1256 1257 remaining = etnaviv_timeout_to_jiffies(timeout); 1258 1259 ret = wait_event_interruptible_timeout(gpu->fence_event, 1260 !is_active(etnaviv_obj), 1261 remaining); 1262 if (ret > 0) 1263 return 0; 1264 else if (ret == -ERESTARTSYS) 1265 return -ERESTARTSYS; 1266 else 1267 return -ETIMEDOUT; 1268 } 1269 1270 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, 1271 struct etnaviv_event *event, unsigned int flags) 1272 { 1273 const struct etnaviv_gem_submit *submit = event->submit; 1274 unsigned int i; 1275 1276 for (i = 0; i < submit->nr_pmrs; i++) { 1277 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1278 1279 if (pmr->flags == flags) 1280 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); 1281 } 1282 } 1283 1284 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, 1285 struct etnaviv_event *event) 1286 { 1287 u32 val; 1288 1289 /* disable clock gating */ 1290 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 1291 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1292 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 1293 1294 /* enable debug register */ 1295 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1296 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1297 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1298 1299 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); 1300 } 1301 1302 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, 1303 struct etnaviv_event *event) 1304 { 1305 const struct etnaviv_gem_submit *submit = event->submit; 1306 unsigned int i; 1307 u32 val; 1308 1309 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); 1310 1311 for (i = 0; i < submit->nr_pmrs; i++) { 1312 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i; 1313 1314 *pmr->bo_vma = pmr->sequence; 1315 } 1316 1317 /* disable debug register */ 1318 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); 1319 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS; 1320 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); 1321 1322 /* enable clock gating */ 1323 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); 1324 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; 1325 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); 1326 } 1327 1328 1329 /* add bo's to gpu's ring, and kick gpu: */ 1330 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit) 1331 { 1332 struct etnaviv_gpu *gpu = submit->gpu; 1333 struct dma_fence *gpu_fence; 1334 unsigned int i, nr_events = 1, event[3]; 1335 int ret; 1336 1337 if (!submit->runtime_resumed) { 1338 ret = pm_runtime_get_sync(gpu->dev); 1339 if (ret < 0) { 1340 pm_runtime_put_noidle(gpu->dev); 1341 return NULL; 1342 } 1343 submit->runtime_resumed = true; 1344 } 1345 1346 /* 1347 * if there are performance monitor requests we need to have 1348 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE 1349 * requests. 1350 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests 1351 * and update the sequence number for userspace. 1352 */ 1353 if (submit->nr_pmrs) 1354 nr_events = 3; 1355 1356 ret = event_alloc(gpu, nr_events, event); 1357 if (ret) { 1358 DRM_ERROR("no free events\n"); 1359 pm_runtime_put_noidle(gpu->dev); 1360 return NULL; 1361 } 1362 1363 mutex_lock(&gpu->lock); 1364 1365 gpu_fence = etnaviv_gpu_fence_alloc(gpu); 1366 if (!gpu_fence) { 1367 for (i = 0; i < nr_events; i++) 1368 event_free(gpu, event[i]); 1369 1370 goto out_unlock; 1371 } 1372 1373 if (!gpu->mmu_context) { 1374 etnaviv_iommu_context_get(submit->mmu_context); 1375 gpu->mmu_context = submit->mmu_context; 1376 etnaviv_gpu_start_fe_idleloop(gpu); 1377 } else { 1378 etnaviv_iommu_context_get(gpu->mmu_context); 1379 submit->prev_mmu_context = gpu->mmu_context; 1380 } 1381 1382 if (submit->nr_pmrs) { 1383 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; 1384 kref_get(&submit->refcount); 1385 gpu->event[event[1]].submit = submit; 1386 etnaviv_sync_point_queue(gpu, event[1]); 1387 } 1388 1389 gpu->event[event[0]].fence = gpu_fence; 1390 submit->cmdbuf.user_size = submit->cmdbuf.size - 8; 1391 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, 1392 event[0], &submit->cmdbuf); 1393 1394 if (submit->nr_pmrs) { 1395 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; 1396 kref_get(&submit->refcount); 1397 gpu->event[event[2]].submit = submit; 1398 etnaviv_sync_point_queue(gpu, event[2]); 1399 } 1400 1401 out_unlock: 1402 mutex_unlock(&gpu->lock); 1403 1404 return gpu_fence; 1405 } 1406 1407 static void sync_point_worker(struct work_struct *work) 1408 { 1409 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, 1410 sync_point_work); 1411 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; 1412 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); 1413 1414 event->sync_point(gpu, event); 1415 etnaviv_submit_put(event->submit); 1416 event_free(gpu, gpu->sync_point_event); 1417 1418 /* restart FE last to avoid GPU and IRQ racing against this worker */ 1419 etnaviv_gpu_start_fe(gpu, addr + 2, 2); 1420 } 1421 1422 static void dump_mmu_fault(struct etnaviv_gpu *gpu) 1423 { 1424 u32 status_reg, status; 1425 int i; 1426 1427 if (gpu->sec_mode == ETNA_SEC_NONE) 1428 status_reg = VIVS_MMUv2_STATUS; 1429 else 1430 status_reg = VIVS_MMUv2_SEC_STATUS; 1431 1432 status = gpu_read(gpu, status_reg); 1433 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); 1434 1435 for (i = 0; i < 4; i++) { 1436 u32 address_reg; 1437 1438 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4)))) 1439 continue; 1440 1441 if (gpu->sec_mode == ETNA_SEC_NONE) 1442 address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i); 1443 else 1444 address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR; 1445 1446 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i, 1447 gpu_read(gpu, address_reg)); 1448 } 1449 } 1450 1451 static irqreturn_t irq_handler(int irq, void *data) 1452 { 1453 struct etnaviv_gpu *gpu = data; 1454 irqreturn_t ret = IRQ_NONE; 1455 1456 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); 1457 1458 if (intr != 0) { 1459 int event; 1460 1461 pm_runtime_mark_last_busy(gpu->dev); 1462 1463 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); 1464 1465 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) { 1466 dev_err(gpu->dev, "AXI bus error\n"); 1467 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; 1468 } 1469 1470 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { 1471 dump_mmu_fault(gpu); 1472 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; 1473 } 1474 1475 while ((event = ffs(intr)) != 0) { 1476 struct dma_fence *fence; 1477 1478 event -= 1; 1479 1480 intr &= ~(1 << event); 1481 1482 dev_dbg(gpu->dev, "event %u\n", event); 1483 1484 if (gpu->event[event].sync_point) { 1485 gpu->sync_point_event = event; 1486 queue_work(gpu->wq, &gpu->sync_point_work); 1487 } 1488 1489 fence = gpu->event[event].fence; 1490 if (!fence) 1491 continue; 1492 1493 gpu->event[event].fence = NULL; 1494 1495 /* 1496 * Events can be processed out of order. Eg, 1497 * - allocate and queue event 0 1498 * - allocate event 1 1499 * - event 0 completes, we process it 1500 * - allocate and queue event 0 1501 * - event 1 and event 0 complete 1502 * we can end up processing event 0 first, then 1. 1503 */ 1504 if (fence_after(fence->seqno, gpu->completed_fence)) 1505 gpu->completed_fence = fence->seqno; 1506 dma_fence_signal(fence); 1507 1508 event_free(gpu, event); 1509 } 1510 1511 ret = IRQ_HANDLED; 1512 } 1513 1514 return ret; 1515 } 1516 1517 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) 1518 { 1519 int ret; 1520 1521 ret = clk_prepare_enable(gpu->clk_reg); 1522 if (ret) 1523 return ret; 1524 1525 ret = clk_prepare_enable(gpu->clk_bus); 1526 if (ret) 1527 goto disable_clk_reg; 1528 1529 ret = clk_prepare_enable(gpu->clk_core); 1530 if (ret) 1531 goto disable_clk_bus; 1532 1533 ret = clk_prepare_enable(gpu->clk_shader); 1534 if (ret) 1535 goto disable_clk_core; 1536 1537 return 0; 1538 1539 disable_clk_core: 1540 clk_disable_unprepare(gpu->clk_core); 1541 disable_clk_bus: 1542 clk_disable_unprepare(gpu->clk_bus); 1543 disable_clk_reg: 1544 clk_disable_unprepare(gpu->clk_reg); 1545 1546 return ret; 1547 } 1548 1549 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) 1550 { 1551 clk_disable_unprepare(gpu->clk_shader); 1552 clk_disable_unprepare(gpu->clk_core); 1553 clk_disable_unprepare(gpu->clk_bus); 1554 clk_disable_unprepare(gpu->clk_reg); 1555 1556 return 0; 1557 } 1558 1559 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) 1560 { 1561 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 1562 1563 do { 1564 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); 1565 1566 if ((idle & gpu->idle_mask) == gpu->idle_mask) 1567 return 0; 1568 1569 if (time_is_before_jiffies(timeout)) { 1570 dev_warn(gpu->dev, 1571 "timed out waiting for idle: idle=0x%x\n", 1572 idle); 1573 return -ETIMEDOUT; 1574 } 1575 1576 udelay(5); 1577 } while (1); 1578 } 1579 1580 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) 1581 { 1582 if (gpu->initialized && gpu->mmu_context) { 1583 /* Replace the last WAIT with END */ 1584 mutex_lock(&gpu->lock); 1585 etnaviv_buffer_end(gpu); 1586 mutex_unlock(&gpu->lock); 1587 1588 /* 1589 * We know that only the FE is busy here, this should 1590 * happen quickly (as the WAIT is only 200 cycles). If 1591 * we fail, just warn and continue. 1592 */ 1593 etnaviv_gpu_wait_idle(gpu, 100); 1594 1595 etnaviv_iommu_context_put(gpu->mmu_context); 1596 gpu->mmu_context = NULL; 1597 } 1598 1599 gpu->exec_state = -1; 1600 1601 return etnaviv_gpu_clk_disable(gpu); 1602 } 1603 1604 #ifdef CONFIG_PM 1605 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) 1606 { 1607 int ret; 1608 1609 ret = mutex_lock_killable(&gpu->lock); 1610 if (ret) 1611 return ret; 1612 1613 etnaviv_gpu_update_clock(gpu); 1614 etnaviv_gpu_hw_init(gpu); 1615 1616 mutex_unlock(&gpu->lock); 1617 1618 return 0; 1619 } 1620 #endif 1621 1622 static int 1623 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev, 1624 unsigned long *state) 1625 { 1626 *state = 6; 1627 1628 return 0; 1629 } 1630 1631 static int 1632 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev, 1633 unsigned long *state) 1634 { 1635 struct etnaviv_gpu *gpu = cdev->devdata; 1636 1637 *state = gpu->freq_scale; 1638 1639 return 0; 1640 } 1641 1642 static int 1643 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev, 1644 unsigned long state) 1645 { 1646 struct etnaviv_gpu *gpu = cdev->devdata; 1647 1648 mutex_lock(&gpu->lock); 1649 gpu->freq_scale = state; 1650 if (!pm_runtime_suspended(gpu->dev)) 1651 etnaviv_gpu_update_clock(gpu); 1652 mutex_unlock(&gpu->lock); 1653 1654 return 0; 1655 } 1656 1657 static struct thermal_cooling_device_ops cooling_ops = { 1658 .get_max_state = etnaviv_gpu_cooling_get_max_state, 1659 .get_cur_state = etnaviv_gpu_cooling_get_cur_state, 1660 .set_cur_state = etnaviv_gpu_cooling_set_cur_state, 1661 }; 1662 1663 static int etnaviv_gpu_bind(struct device *dev, struct device *master, 1664 void *data) 1665 { 1666 struct drm_device *drm = data; 1667 struct etnaviv_drm_private *priv = drm->dev_private; 1668 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1669 int ret; 1670 1671 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) { 1672 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, 1673 (char *)dev_name(dev), gpu, &cooling_ops); 1674 if (IS_ERR(gpu->cooling)) 1675 return PTR_ERR(gpu->cooling); 1676 } 1677 1678 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); 1679 if (!gpu->wq) { 1680 ret = -ENOMEM; 1681 goto out_thermal; 1682 } 1683 1684 ret = etnaviv_sched_init(gpu); 1685 if (ret) 1686 goto out_workqueue; 1687 1688 #ifdef CONFIG_PM 1689 ret = pm_runtime_get_sync(gpu->dev); 1690 #else 1691 ret = etnaviv_gpu_clk_enable(gpu); 1692 #endif 1693 if (ret < 0) 1694 goto out_sched; 1695 1696 1697 gpu->drm = drm; 1698 gpu->fence_context = dma_fence_context_alloc(1); 1699 idr_init(&gpu->fence_idr); 1700 spin_lock_init(&gpu->fence_spinlock); 1701 1702 INIT_WORK(&gpu->sync_point_work, sync_point_worker); 1703 init_waitqueue_head(&gpu->fence_event); 1704 1705 priv->gpu[priv->num_gpus++] = gpu; 1706 1707 pm_runtime_mark_last_busy(gpu->dev); 1708 pm_runtime_put_autosuspend(gpu->dev); 1709 1710 return 0; 1711 1712 out_sched: 1713 etnaviv_sched_fini(gpu); 1714 1715 out_workqueue: 1716 destroy_workqueue(gpu->wq); 1717 1718 out_thermal: 1719 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1720 thermal_cooling_device_unregister(gpu->cooling); 1721 1722 return ret; 1723 } 1724 1725 static void etnaviv_gpu_unbind(struct device *dev, struct device *master, 1726 void *data) 1727 { 1728 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1729 1730 DBG("%s", dev_name(gpu->dev)); 1731 1732 flush_workqueue(gpu->wq); 1733 destroy_workqueue(gpu->wq); 1734 1735 etnaviv_sched_fini(gpu); 1736 1737 #ifdef CONFIG_PM 1738 pm_runtime_get_sync(gpu->dev); 1739 pm_runtime_put_sync_suspend(gpu->dev); 1740 #else 1741 etnaviv_gpu_hw_suspend(gpu); 1742 #endif 1743 1744 if (gpu->initialized) { 1745 etnaviv_cmdbuf_free(&gpu->buffer); 1746 etnaviv_iommu_global_fini(gpu); 1747 gpu->initialized = false; 1748 } 1749 1750 gpu->drm = NULL; 1751 idr_destroy(&gpu->fence_idr); 1752 1753 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) 1754 thermal_cooling_device_unregister(gpu->cooling); 1755 gpu->cooling = NULL; 1756 } 1757 1758 static const struct component_ops gpu_ops = { 1759 .bind = etnaviv_gpu_bind, 1760 .unbind = etnaviv_gpu_unbind, 1761 }; 1762 1763 static const struct of_device_id etnaviv_gpu_match[] = { 1764 { 1765 .compatible = "vivante,gc" 1766 }, 1767 { /* sentinel */ } 1768 }; 1769 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match); 1770 1771 static int etnaviv_gpu_platform_probe(struct platform_device *pdev) 1772 { 1773 struct device *dev = &pdev->dev; 1774 struct etnaviv_gpu *gpu; 1775 int err; 1776 1777 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); 1778 if (!gpu) 1779 return -ENOMEM; 1780 1781 gpu->dev = &pdev->dev; 1782 mutex_init(&gpu->lock); 1783 mutex_init(&gpu->fence_lock); 1784 1785 /* Map registers: */ 1786 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); 1787 if (IS_ERR(gpu->mmio)) 1788 return PTR_ERR(gpu->mmio); 1789 1790 /* Get Interrupt: */ 1791 gpu->irq = platform_get_irq(pdev, 0); 1792 if (gpu->irq < 0) 1793 return gpu->irq; 1794 1795 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0, 1796 dev_name(gpu->dev), gpu); 1797 if (err) { 1798 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); 1799 return err; 1800 } 1801 1802 /* Get Clocks: */ 1803 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); 1804 DBG("clk_reg: %p", gpu->clk_reg); 1805 if (IS_ERR(gpu->clk_reg)) 1806 return PTR_ERR(gpu->clk_reg); 1807 1808 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); 1809 DBG("clk_bus: %p", gpu->clk_bus); 1810 if (IS_ERR(gpu->clk_bus)) 1811 return PTR_ERR(gpu->clk_bus); 1812 1813 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); 1814 DBG("clk_core: %p", gpu->clk_core); 1815 if (IS_ERR(gpu->clk_core)) 1816 return PTR_ERR(gpu->clk_core); 1817 gpu->base_rate_core = clk_get_rate(gpu->clk_core); 1818 1819 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); 1820 DBG("clk_shader: %p", gpu->clk_shader); 1821 if (IS_ERR(gpu->clk_shader)) 1822 return PTR_ERR(gpu->clk_shader); 1823 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); 1824 1825 /* TODO: figure out max mapped size */ 1826 dev_set_drvdata(dev, gpu); 1827 1828 /* 1829 * We treat the device as initially suspended. The runtime PM 1830 * autosuspend delay is rather arbitary: no measurements have 1831 * yet been performed to determine an appropriate value. 1832 */ 1833 pm_runtime_use_autosuspend(gpu->dev); 1834 pm_runtime_set_autosuspend_delay(gpu->dev, 200); 1835 pm_runtime_enable(gpu->dev); 1836 1837 err = component_add(&pdev->dev, &gpu_ops); 1838 if (err < 0) { 1839 dev_err(&pdev->dev, "failed to register component: %d\n", err); 1840 return err; 1841 } 1842 1843 return 0; 1844 } 1845 1846 static int etnaviv_gpu_platform_remove(struct platform_device *pdev) 1847 { 1848 component_del(&pdev->dev, &gpu_ops); 1849 pm_runtime_disable(&pdev->dev); 1850 return 0; 1851 } 1852 1853 #ifdef CONFIG_PM 1854 static int etnaviv_gpu_rpm_suspend(struct device *dev) 1855 { 1856 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1857 u32 idle, mask; 1858 1859 /* If there are any jobs in the HW queue, we're not idle */ 1860 if (atomic_read(&gpu->sched.hw_rq_count)) 1861 return -EBUSY; 1862 1863 /* Check whether the hardware (except FE and MC) is idle */ 1864 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | 1865 VIVS_HI_IDLE_STATE_MC); 1866 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; 1867 if (idle != mask) { 1868 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", 1869 idle); 1870 return -EBUSY; 1871 } 1872 1873 return etnaviv_gpu_hw_suspend(gpu); 1874 } 1875 1876 static int etnaviv_gpu_rpm_resume(struct device *dev) 1877 { 1878 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); 1879 int ret; 1880 1881 ret = etnaviv_gpu_clk_enable(gpu); 1882 if (ret) 1883 return ret; 1884 1885 /* Re-initialise the basic hardware state */ 1886 if (gpu->drm && gpu->initialized) { 1887 ret = etnaviv_gpu_hw_resume(gpu); 1888 if (ret) { 1889 etnaviv_gpu_clk_disable(gpu); 1890 return ret; 1891 } 1892 } 1893 1894 return 0; 1895 } 1896 #endif 1897 1898 static const struct dev_pm_ops etnaviv_gpu_pm_ops = { 1899 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume, 1900 NULL) 1901 }; 1902 1903 struct platform_driver etnaviv_gpu_driver = { 1904 .driver = { 1905 .name = "etnaviv-gpu", 1906 .owner = THIS_MODULE, 1907 .pm = &etnaviv_gpu_pm_ops, 1908 .of_match_table = etnaviv_gpu_match, 1909 }, 1910 .probe = etnaviv_gpu_platform_probe, 1911 .remove = etnaviv_gpu_platform_remove, 1912 .id_table = gpu_ids, 1913 }; 1914